sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 #include "sim-base.h"
  40
  41
  42 /* Depreciated macros and types for manipulating 64bit values.  Use
  43    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  44
  45 typedef signed64 word64;
  46 typedef unsigned64 uword64;
  47
  48 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  49 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  50 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  51 #define SET64HI(t)      (((uword64)(t))<<32)
  52 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  53 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  54
  55 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  56    assume the HI32bits of the operand are zero, so we must perform a
  57    mask to ensure we can use the simple subtraction to sign-extend. */
  58 #define SIGNEXTEND(e,b) \
  59  ((unsigned_word) \
  60   (((e) & ((uword64) 1 << ((b) - 1))) \
  61    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  62    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  63
  64 /* Check if a value will fit within a halfword: */
  65 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  66
  67
  68
  69 /* Floating-point operations: */
  70
  71 #include "sim-fpu.h"
  72
  73 /* FPU registers must be one of the following types. All other values
  74    are reserved (and undefined). */
  75 typedef enum {
  76  fmt_single  = 0,
  77  fmt_double  = 1,
  78  fmt_word    = 4,
  79  fmt_long    = 5,
  80  /* The following are well outside the normal acceptable format
  81     range, and are used in the register status vector. */
  82  fmt_unknown       = 0x10000000,
  83  fmt_uninterpreted = 0x20000000,
  84  fmt_uninterpreted_32 = 0x40000000,
  85  fmt_uninterpreted_64 = 0x80000000U,
  86 } FP_formats;
  87
  88 unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
  89 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
  90
  91 void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
  92 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
  93
  94 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
  95 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
  96 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  97 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  98 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
  99 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 100 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 101 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 102 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 103 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 104 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 105 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 106 unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 107 unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 108 unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 109 #define Convert(rm,op,from,to) \
 110 convert (SD, CPU, cia, rm, op, from, to)
 111
 112 /* Macro to update FPSR condition-code field. This is complicated by
 113    the fact that there is a hole in the index range of the bits within
 114    the FCSR register. Also, the number of bits visible depends on the
 115    MIPS ISA version being supported. */
 116
 117 #define SETFCC(cc,v) {\
 118   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 119   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 120 }
 121 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
 122
 123 /* This should be the COC1 value at the start of the preceding
 124    instruction: */
 125 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 126
 127 #if 1
 128 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 129 #else
 130 /* They depend on the CPU being simulated */
 131 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 132 #endif
 133
 134 /* Standard FCRS bits: */
 135 #define IR (0) /* Inexact Result */
 136 #define UF (1) /* UnderFlow */
 137 #define OF (2) /* OverFlow */
 138 #define DZ (3) /* Division by Zero */
 139 #define IO (4) /* Invalid Operation */
 140 #define UO (5) /* Unimplemented Operation */
 141
 142 /* Get masks for individual flags: */
 143 #if 1 /* SAFE version */
 144 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 145 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 146 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 147 #else
 148 #define FP_FLAGS(b)  (1 << ((b) + 2))
 149 #define FP_ENABLE(b) (1 << ((b) + 7))
 150 #define FP_CAUSE(b)  (1 << ((b) + 12))
 151 #endif
 152
 153 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 154
 155 #define FP_MASK_RM    (0x3)
 156 #define FP_SH_RM      (0)
 157 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 158 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 159 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 160 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 161 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 162
 163 /* start-sanitize-sky */
 164 #ifdef TARGET_SKY
 165 #ifdef SKY_FUNIT
 166 #include <assert.h>
 167 #include "wf.h"
 168 #endif
 169 #endif
 170 /* end-sanitize-sky */
 171
 172
 173
 174
 175
 176 /* HI/LO register accesses */
 177
 178 /* For some MIPS targets, the HI/LO registers have certain timing
 179    restrictions in that, for instance, a read of a HI register must be
 180    separated by at least three instructions from a preceeding read.
 181
 182    The struct below is used to record the last access by each of A MT,
 183    MF or other OP instruction to a HI/LO register.  See mips.igen for
 184    more details. */
 185
 186 typedef struct _hilo_access {
 187   signed64 timestamp;
 188   address_word cia;
 189 } hilo_access;
 190
 191 typedef struct _hilo_history {
 192   hilo_access mt;
 193   hilo_access mf;
 194   hilo_access op;
 195 } hilo_history;
 196
 197
 198
 199
 200 /* Integer ALU operations: */
 201
 202 #include "sim-alu.h"
 203
 204 #define ALU32_END(ANS) \
 205   if (ALU32_HAD_OVERFLOW) \
 206     SignalExceptionIntegerOverflow (); \
 207   (ANS) = (signed32) ALU32_OVERFLOW_RESULT
 208
 209
 210 #define ALU64_END(ANS) \
 211   if (ALU64_HAD_OVERFLOW) \
 212     SignalExceptionIntegerOverflow (); \
 213   (ANS) = ALU64_OVERFLOW_RESULT;
 214
 215
 216 /* start-sanitize-r5900 */
 217
 218 /* Figure 10-5 FPU Control/Status Register.
 219    Note: some of these bits are different to what is found in a
 220    standard MIPS manual. */
 221 enum {
 222   R5900_FCSR_C = BIT (23), /* OK */
 223   R5900_FCSR_I = BIT (17),
 224   R5900_FCSR_D = BIT (16),
 225   R5900_FCSR_O = BIT (15),
 226   R5900_FCSR_U = BIT (14),
 227   R5900_FCSR_CAUSE = MASK (16,14),
 228   R5900_FCSR_SI = BIT (6),
 229   R5900_FCSR_SD = BIT (5),
 230   R5900_FCSR_SO = BIT (4),
 231   R5900_FCSR_SU = BIT (3),
 232 };
 233
 234 /* Table 10-1 FP format values.
 235    Note: some of these bits are different to what is found in a
 236    standard MIPS manual. */
 237 enum {
 238   R5900_EXPMAX = 128,
 239   R5900_EXPMIN = -127,
 240   R5900_EXPBIAS = 127,
 241 };
 242
 243 /* MAX and MIN FP values */
 244 enum {
 245   R5900_FPMAX = LSMASK32 (30, 0),
 246   R5900_FPMIN = LSMASK32 (31, 0),
 247 };
 248
 249 typedef struct _r4000_tlb_entry {
 250   unsigned32 mask;
 251   unsigned32 hi;
 252   unsigned32 lo0;
 253   unsigned32 lo1;
 254 } r4000_tlb_entry_t;
 255
 256 #define TLB_MASK_MASK_MASK 0x01ffe000
 257 #define TLB_HI_VPN2_MASK   0xffffe000
 258 #define TLB_HI_G_MASK      0x00001000
 259 #define TLB_HI_ASID_MASK   0x000000ff
 260
 261 #define TLB_LO_S_MASK      0x80000000
 262 #define TLB_LO_PFN_MASK    0x03ffffc0
 263 #define TLB_LO_C_MASK      0x00000038
 264 #define TLB_LO_D_MASK      0x00000004
 265 #define TLB_LO_V_MASK      0x00000002
 266
 267 #define TLB_SIZE 48
 268
 269 typedef struct _sim_r5900_cpu {
 270
 271   /* The R5900 has 32 x 128bit general purpose registers.
 272      Fortunatly, the high 64 bits are only touched by multimedia (MMI)
 273      instructions.  The normal mips instructions just use the lower 64
 274      bits.  To avoid changing the older parts of the simulator to
 275      handle this weirdness, the high 64 bits of each register are kept
 276      in a separate array (registers1).  The high 64 bits of any
 277      register are by convention refered by adding a '1' to the end of
 278      the normal register's name.  So LO still refers to the low 64
 279      bits of the LO register, LO1 refers to the high 64 bits of that
 280      same register.  */
 281   signed_word gpr1[32];
 282 #define GPR1     ((CPU)->r5900.gpr1)
 283 #define GPR1_SET(N,VAL) (GPR1[(N]) = (VAL))
 284   signed_word lo1;
 285   signed_word hi1;
 286 #define LO1      ((CPU)->r5900.lo1)
 287 #define HI1      ((CPU)->r5900.hi1)
 288
 289   /* The R5900 defines a shift amount register, that controls the
 290      amount of certain shift instructions */
 291   unsigned_word sa;        /* the shift amount register */
 292 #define REGISTER_SA     (124) /* GET RID IF THIS! */
 293 #define SA ((CPU)->r5900.sa)
 294
 295   /* The R5900, in addition to the (almost) standard floating point
 296      registers, defines a 32 bit accumulator.  This is used in
 297      multiply/accumulate style instructions */
 298   fp_word acc; /* floating-point accumulator */
 299 #define ACC ((CPU)->r5900.acc)
 300
 301   /* See comments below about needing to count cycles between updating
 302      and setting HI/LO registers */
 303   hilo_history hi1_history;
 304 #define HI1HISTORY (&(CPU)->r5900.hi1_history)
 305   hilo_history lo1_history;
 306 #define LO1HISTORY (&(CPU)->r5900.lo1_history)
 307
 308   r4000_tlb_entry_t tlb[TLB_SIZE];
 309 #define TLB ((CPU)->r5900.tlb)
 310
 311 } sim_r5900_cpu;
 312
 313 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 314 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 315 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 316 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 317
 318 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 319 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 320 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 321 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 322
 323 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 324    T  - type of the sub part
 325    TC - # of T's in the mips part of the "register"
 326    I  - index (from 0) of desired sub part
 327    A  - low part of "register"
 328    A1 - high part of register
 329 */
 330 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 331 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 332    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 333       ? ((TC) - 1 - (I) % (TC)) \
 334       : ((I) % (TC)) \
 335       ) \
 336    ) \
 337  )
 338
 339 /*
 340 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 341             where <type> has two letters:
 342                   1 is S=signed or U=unsigned
 343                   2 is B=byte H=halfword W=word D=doubleword
 344 */
 345
 346 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 347 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 348 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 349 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 350
 351 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 352 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 353 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 354 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 355
 356 #define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
 357 #define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
 358 #define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
 359 #define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
 360
 361 #define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
 362 #define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
 363 #define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
 364 #define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
 365
 366 #define TMP_DCL unsigned64 tmp_reg, tmp_reg1
 367
 368 #define TMP_SB(I) SUB_REG_SB(&tmp_reg, &tmp_reg1, I)
 369 #define TMP_SH(I) SUB_REG_SH(&tmp_reg, &tmp_reg1, I)
 370 #define TMP_SW(I) SUB_REG_SW(&tmp_reg, &tmp_reg1, I)
 371 #define TMP_SD(I) SUB_REG_SD(&tmp_reg, &tmp_reg1, I)
 372
 373 #define TMP_UB(I) SUB_REG_UB(&tmp_reg, &tmp_reg1, I)
 374 #define TMP_UH(I) SUB_REG_UH(&tmp_reg, &tmp_reg1, I)
 375 #define TMP_UW(I) SUB_REG_UW(&tmp_reg, &tmp_reg1, I)
 376 #define TMP_UD(I) SUB_REG_UD(&tmp_reg, &tmp_reg1, I)
 377
 378 #define TMP_WRT(R) do { GPR[R] = tmp_reg; GPR1[R] = tmp_reg1; } while(0)
 379
 380 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 381 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 382 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 383 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 384
 385 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 386 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 387 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 388 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 389
 390 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 391 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 392 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 393 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 394
 395 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 396 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 397 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 398 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 399
 400
 401
 402 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 403 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 404 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 405 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 406
 407 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 408 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 409 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 410 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 411
 412 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 413 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 414 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 415 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 416
 417 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 418 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 419 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 420 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 421
 422 /* end-sanitize-r5900 */
 423
 424
 425
 426 /* The following is probably not used for MIPS IV onwards: */
 427 /* Slots for delayed register updates. For the moment we just have a
 428    fixed number of slots (rather than a more generic, dynamic
 429    system). This keeps the simulator fast. However, we only allow
 430    for the register update to be delayed for a single instruction
 431    cycle. */
 432 #define PSLOTS (8) /* Maximum number of instruction cycles */
 433
 434 typedef struct _pending_write_queue {
 435   int in;
 436   int out;
 437   int total;
 438   int slot_delay[PSLOTS];
 439   int slot_size[PSLOTS];
 440   int slot_bit[PSLOTS];
 441   void *slot_dest[PSLOTS];
 442   unsigned64 slot_value[PSLOTS];
 443 } pending_write_queue;
 444
 445 #ifndef PENDING_TRACE
 446 #define PENDING_TRACE 0
 447 #endif
 448 #define PENDING_IN ((CPU)->pending.in)
 449 #define PENDING_OUT ((CPU)->pending.out)
 450 #define PENDING_TOTAL ((CPU)->pending.total)
 451 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 452 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
 453 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 454 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 455 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 456
 457 /* Invalidate the pending write queue, all pending writes are
 458    discarded. */
 459
 460 #define PENDING_INVALIDATE() \
 461 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 462
 463 /* Schedule a write to DEST for N cycles time.  For 64 bit
 464    destinations, schedule two writes.  For floating point registers,
 465    the caller should schedule a write to both the dest register and
 466    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 467    is updated. */
 468
 469 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 470   do {                                                                  \
 471     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 472       sim_engine_abort (SD, CPU, cia,                                   \
 473                         "PENDING_SCHED - buffer overflow\n");           \
 474     if (PENDING_TRACE)                                                  \
 475       sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",                  \
 476                       (unsigned long) cia, (unsigned long) &(DEST),     \
 477                       (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
 478                       PENDING_IN, PENDING_OUT, PENDING_TOTAL);          \
 479     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 480     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 481     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 482     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 483     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 484     PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
 485     PENDING_TOTAL += 1;                                                 \
 486   } while (0)
 487
 488 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 489 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 490
 491 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 492
 493 #define PENDING_FLUSH() abort () /* think about this one */
 494 #define PENDING_FP() abort () /* think about this one */
 495
 496 /* For backward compatibility */
 497 #define PENDING_FILL(R,VAL)                                             \
 498 do {                                                                    \
 499   if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR)                           \
 500     {                                                                   \
 501       PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1);                     \
 502       PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1); \
 503     }                                                                   \
 504   else                                                                  \
 505     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                                \
 506 } while (0)
 507
 508
 509
 510 struct _sim_cpu {
 511
 512
 513   /* The following are internal simulator state variables: */
 514 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 515 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 516   address_word dspc;  /* delay-slot PC */
 517 #define DSPC ((CPU)->dspc)
 518
 519 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 520 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 521
 522
 523   /* State of the simulator */
 524   unsigned int state;
 525   unsigned int dsstate;
 526 #define STATE ((CPU)->state)
 527 #define DSSTATE ((CPU)->dsstate)
 528
 529 /* Flags in the "state" variable: */
 530 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 531 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 532 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 533 #define simPCOC0        (1 << 17) /* COC[1] from current */
 534 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 535 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 536 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 537 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 538 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 539
 540 #define ENGINE_ISSUE_PREFIX_HOOK() \
 541   { \
 542     /* Perform any pending writes */ \
 543     PENDING_TICK(); \
 544     /* Set previous flag, depending on current: */ \
 545     if (STATE & simPCOC0) \
 546      STATE |= simPCOC1; \
 547     else \
 548      STATE &= ~simPCOC1; \
 549     /* and update the current value: */ \
 550     if (GETFCC(0)) \
 551      STATE |= simPCOC0; \
 552     else \
 553      STATE &= ~simPCOC0; \
 554   }
 555
 556
 557 /* This is nasty, since we have to rely on matching the register
 558    numbers used by GDB. Unfortunately, depending on the MIPS target
 559    GDB uses different register numbers. We cannot just include the
 560    relevant "gdb/tm.h" link, since GDB may not be configured before
 561    the sim world, and also the GDB header file requires too much other
 562    state. */
 563
 564 #ifndef TM_MIPS_H
 565 #define LAST_EMBED_REGNUM (89)
 566 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 567
 568 /* start-sanitize-r5900 */
 569 #define FIRST_COP0_REG 128
 570 #define NUM_COP0_REGS 22
 571 #undef NUM_REGS
 572 #define NUM_REGS (150)
 573 /* end-sanitize-r5900 */
 574
 575 #endif
 576
 577 /* start-sanitize-sky */
 578 #ifdef TARGET_SKY
 579 #ifndef TM_TXVU_H
 580 /* Number of machine registers */
 581 #define NUM_VU_REGS     160
 582
 583 #define NUM_VU_INTEGER_REGS 16
 584 #define FIRST_VEC_REG   32
 585
 586 #define NUM_VIF_REGS    26
 587
 588 #define NUM_CORE_REGS   150
 589
 590 #undef NUM_REGS
 591 #define NUM_REGS (NUM_CORE_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
 592 #endif /* no tm-txvu.h */
 593 #endif /* TARGET_SKY */
 594 /* end-sanitize-sky */
 595
 596 enum float_operation
 597 /* start-sanitize-sky */
 598 /* NOTE: THE VALUES of THESE CONSTANTS MUST BE IN SYNC WITH THOSE IN WF.H */
 599 /* end-sanitize-sky */
 600   {
 601     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 602     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 603     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 604   };
 605
 606 /* To keep this default simulator simple, and fast, we use a direct
 607    vector of registers. The internal simulator engine then uses
 608    manifests to access the correct slot. */
 609
 610   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 611   int register_widths[NUM_REGS];
 612 #define REGISTERS       ((CPU)->registers)
 613
 614 #define GPR     (&REGISTERS[0])
 615 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 616
 617   /* While space is allocated for the floating point registers in the
 618      main registers array, they are stored separatly.  This is because
 619      their size may not necessarily match the size of either the
 620      general-purpose or system specific registers */
 621 #define NR_FGR  (32)
 622 #define FGRIDX  (38)
 623   fp_word fgr[NR_FGR];
 624 #define FGR     ((CPU)->fgr)
 625
 626 #define LO      (REGISTERS[33])
 627 #define HI      (REGISTERS[34])
 628 #define PCIDX   37
 629 #define PC      (REGISTERS[PCIDX])
 630 #define CAUSE   (REGISTERS[36])
 631 #define SRIDX   (32)
 632 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 633 #define FCR0IDX  (71)
 634 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 635 #define FCR31IDX (70)
 636 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 637 #define FCSR    (FCR31)
 638 #define Debug   (REGISTERS[86])
 639 #define DEPC    (REGISTERS[87])
 640 #define EPC     (REGISTERS[88])
 641 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 642
 643   unsigned_word c0_config_reg;
 644 #define C0_CONFIG ((CPU)->c0_config_reg)
 645
 646 /* The following are pseudonyms for standard registers */
 647 #define ZERO    (REGISTERS[0])
 648 #define V0      (REGISTERS[2])
 649 #define A0      (REGISTERS[4])
 650 #define A1      (REGISTERS[5])
 651 #define A2      (REGISTERS[6])
 652 #define A3      (REGISTERS[7])
 653 #define T8IDX   24
 654 #define T8      (REGISTERS[T8IDX])
 655 #define SPIDX   29
 656 #define SP      (REGISTERS[SPIDX])
 657 #define RAIDX   31
 658 #define RA      (REGISTERS[RAIDX])
 659
 660   /* While space is allocated in the main registers arrray for some of
 661      the COP0 registers, that space isn't sufficient.  Unknown COP0
 662      registers overflow into the array below */
 663
 664 #define NR_COP0_GPR     32
 665   unsigned_word cop0_gpr[NR_COP0_GPR];
 666 #define COP0_GPR        ((CPU)->cop0_gpr)
 667   /* start-sanitize-r5900 */
 668 #define NR_COP0_BP      8
 669   unsigned_word cop0_bp[NR_COP0_BP];
 670 #define COP0_BP ((CPU)->cop0_bp)
 671 #define NR_COP0_P 64
 672   unsigned_word cop0_p[NR_COP0_P];
 673
 674 #define COP0_P  ((CPU)->cop0_p)
 675 #define COP0_INDEX    ((unsigned32)(COP0_GPR[0]))
 676 #define COP0_RANDOM   ((unsigned32)(COP0_GPR[1]))
 677 #define COP0_ENTRYLO0 ((unsigned32)(COP0_GPR[2]))
 678 #define COP0_ENTRYLO1 ((unsigned32)(COP0_GPR[3]))
 679 #define COP0_CONTEXT  ((unsigned32)(COP0_GPR[4]))
 680 #define COP0_PAGEMASK ((unsigned32)(COP0_GPR[5]))
 681 #define COP0_WIRED    ((unsigned32)(COP0_GPR[6]))
 682 #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
 683 #define COP0_COUNT    ((unsigned32)(COP0_GPR[9]))
 684 #define COP0_ENTRYHI  ((unsigned32)(COP0_GPR[10]))
 685 #define COP0_COMPARE  ((unsigned32)(COP0_GPR[11]))
 686 #define COP0_EPC      ((unsigned32)(EPC))       /* 14 */
 687 #define COP0_PRID     ((unsigned32)(COP0_GPR[15]))
 688 #define COP0_CONFIG   ((unsigned32)(C0_CONFIG)) /* 16 */
 689 #define COP0_TAGLO    ((unsigned32)(COP0_GPR[28]))
 690 #define COP0_TAGHI    ((unsigned32)(COP0_GPR[29]))
 691 #define COP0_ERROREPC ((unsigned32)(COP0_GPR[30]))
 692
 693 #define COP0_CONTEXT_BADVPN2_MASK 0x007ffff0
 694
 695 #define COP0_CONTEXT_set_BADVPN2(x) \
 696         (COP0_CONTEXT = ((COP0_CONTEXT & 0xff100000) | ((x << 4) & 0x007ffff0)))
 697   /* end-sanitize-r5900 */
 698
 699   /* Keep the current format state for each register: */
 700   FP_formats fpr_state[32];
 701 #define FPR_STATE ((CPU)->fpr_state)
 702
 703   pending_write_queue pending;
 704
 705   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 706      read-write instructions. It is set when a linked load occurs. It
 707      is tested and cleared by the conditional store. It is cleared
 708      (during other CPU operations) when a store to the location would
 709      no longer be atomic. In particular, it is cleared by exception
 710      return instructions. */
 711   int llbit;
 712 #define LLBIT ((CPU)->llbit)
 713
 714
 715 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 716    corruptions caused by using the HI or LO register too close to a
 717    following operation is spotted. See mips.igen for more details. */
 718
 719   hilo_history hi_history;
 720 #define HIHISTORY (&(CPU)->hi_history)
 721   hilo_history lo_history;
 722 #define LOHISTORY (&(CPU)->lo_history)
 723
 724   /* start-sanitize-branchbug4011 */
 725 #if 1
 726   int branchbug4011_option;
 727 #define BRANCHBUG4011_OPTION ((CPU)->branchbug4011_option)
 728   address_word branchbug4011_last_target;
 729 #define BRANCHBUG4011_LAST_TARGET ((CPU)->branchbug4011_last_target)
 730   address_word branchbug4011_last_cia;
 731 #define BRANCHBUG4011_LAST_CIA ((CPU)->branchbug4011_last_cia)
 732
 733 #define check_branch_bug() (check_4011_branch_bug (_SD))
 734 #define mark_branch_bug(TARGET) (mark_4011_branch_bug (_SD,TARGET))
 735 #else
 736   /* end-sanitize-branchbug4011 */
 737 #define check_branch_bug()
 738 #define mark_branch_bug(TARGET)
 739   /* start-sanitize-branchbug4011 */
 740 #endif
 741   /* end-sanitize-branchbug4011 */
 742   /* start-sanitize-r5900 */
 743   sim_r5900_cpu r5900;
 744   /* end-sanitize-r5900 */
 745
 746   /* start-sanitize-cygnus */
 747   /* The MDMX ISA has a very very large accumulator */
 748   unsigned8 acc[3 * 8];
 749   /* end-sanitize-cygnus */
 750
 751   /* start-sanitize-sky */
 752 #ifdef TARGET_SKY
 753   /* Device on which instruction issue last occured.  */
 754   char cur_device;
 755 #endif
 756   /* end-sanitize-sky */
 757
 758   sim_cpu_base base;
 759 };
 760
 761
 762 /* MIPS specific simulator watch config */
 763
 764 void watch_options_install PARAMS ((SIM_DESC sd));
 765
 766 struct swatch {
 767   sim_event *pc;
 768   sim_event *clock;
 769   sim_event *cycles;
 770 };
 771
 772
 773 /* FIXME: At present much of the simulator is still static */
 774 struct sim_state {
 775
 776   struct swatch watch;
 777
 778   sim_cpu cpu[MAX_NR_PROCESSORS];
 779 #if (WITH_SMP)
 780 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 781 #else
 782 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 783 #endif
 784
 785 /* start-sanitize-sky */
 786 #ifdef TARGET_SKY
 787
 788 #ifdef SKY_FUNIT
 789   /* Record of option for floating point implementation type. */
 790   int fp_type_opt;
 791 #define STATE_FP_TYPE_OPT(sd) ((sd)->fp_type_opt)
 792 #define STATE_FP_TYPE_OPT_ACCURATE 0x80000000
 793 #endif
 794
 795   /* Index of next unused name slot for multi-phase load list. */
 796   int next_mload_count;
 797 #define STATE_MLOAD_COUNT(sd) ((sd)->next_mload_count)
 798
 799 #define MAX_MLOAD_COUNT 2 /* limit for next_load_count and load_index */
 800
 801   /* Program names for multi-phase load. */
 802   char *next_mload_name[MAX_MLOAD_COUNT];
 803 #define STATE_MLOAD_NAME(sd) ((sd)->next_mload_name)
 804
 805   /* Index of next program for multi-phase load. */
 806   int mload_index;
 807 #define STATE_MLOAD_INDEX(sd) ((sd)->mload_index)
 808
 809 #endif
 810 /* end-sanitize-sky */
 811
 812   sim_state_base base;
 813 };
 814
 815
 816
 817 /* Status information: */
 818
 819 /* TODO : these should be the bitmasks for these bits within the
 820    status register. At the moment the following are VR4300
 821    bit-positions: */
 822 #define status_KSU_mask  (0x18)         /* mask for KSU bits */
 823 #define status_KSU_shift (3)            /* shift for field */
 824 #define ksu_kernel       (0x0)
 825 #define ksu_supervisor   (0x1)
 826 #define ksu_user         (0x2)
 827 #define ksu_unknown      (0x3)
 828
 829 #define SR_KSU           ((SR & status_KSU_mask) >> status_KSU_shift)
 830
 831 #define status_IE        (1 <<  0)      /* Interrupt enable */
 832 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 833 #define status_EXL       (1 <<  1)      /* Exception level */
 834 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 835 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 836 #define status_SR        (1 << 20)      /* soft reset or NMI */
 837 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 838 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 839 #define status_ERL       (1 <<  2)      /* Error level */
 840 #define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
 841 #define status_RP        (1 << 27)      /* Reduced Power mode */
 842 /* start-sanitize-r5900 */
 843 #define status_CU0       (1 << 28)      /* COP0 usable */
 844 #define status_CU1       (1 << 29)      /* COP1 usable */
 845 #define status_CU2       (1 << 30)      /* COP2 usable */
 846 /* end-sanitize-r5900 */
 847
 848 /* Specializations for TX39 family */
 849 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 850 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 851 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 852 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 853 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 854 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 855 #define status_IM_mask   (0xff)         /* Interrupt mask */
 856 #define status_IM_shift  (8)
 857 #define status_NMI       (1 << 20)      /* NMI */
 858 #define status_NMI       (1 << 20)      /* NMI */
 859
 860 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 861 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
 862 #define cause_CE_mask     0x30000000    /* Coprocessor exception */
 863 #define cause_CE_shift    28
 864 #define cause_EXC2_mask   0x00070000
 865 #define cause_EXC2_shift  16
 866 #define cause_IP7         (1 << 15)     /* Interrupt pending */
 867 #define cause_SIOP        (1 << 12)     /* SIO pending */
 868 #define cause_IP3         (1 << 11)     /* Int 0 pending */
 869 #define cause_IP2         (1 << 10)     /* Int 1 pending */
 870
 871 /* start-sanitize-sky */
 872 #ifdef TARGET_SKY
 873 #define cause_EXC_mask  (0x7c)          /* Exception code */
 874 #else
 875 /* end-sanitize-sky */
 876 #define cause_EXC_mask  (0x1c)          /* Exception code */
 877 /* start-sanitize-sky */
 878 #endif
 879 /* end-sanitize-sky */
 880 #define cause_EXC_shift (2)
 881
 882 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 883 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 884 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 885 #define cause_IP_shift  (10)
 886
 887 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 888 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 889
 890
 891 /* NOTE: We keep the following status flags as bit values (1 for true,
 892    0 for false). This allows them to be used in binary boolean
 893    operations without worrying about what exactly the non-zero true
 894    value is. */
 895
 896 /* UserMode */
 897 #ifdef SUBTARGET_R3900
 898 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 899 #else
 900 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 901 #endif /* SUBTARGET_R3900 */
 902
 903 /* BigEndianMem */
 904 /* Hardware configuration. Affects endianness of LoadMemory and
 905    StoreMemory and the endianness of Kernel and Supervisor mode
 906    execution. The value is 0 for little-endian; 1 for big-endian. */
 907 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 908 /*(state & simBE) ? 1 : 0)*/
 909
 910 /* ReverseEndian */
 911 /* This mode is selected if in User mode with the RE bit being set in
 912    SR (Status Register). It reverses the endianness of load and store
 913    instructions. */
 914 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 915
 916 /* BigEndianCPU */
 917 /* The endianness for load and store instructions (0=little;1=big). In
 918    User mode this endianness may be switched by setting the state_RE
 919    bit in the SR register. Thus, BigEndianCPU may be computed as
 920    (BigEndianMem EOR ReverseEndian). */
 921 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 922
 923
 924
 925 /* Exceptions: */
 926
 927 /* NOTE: These numbers depend on the processor architecture being
 928    simulated: */
 929 enum ExceptionCause {
 930   Interrupt               = 0,
 931   TLBModification         = 1,
 932   TLBLoad                 = 2,
 933   TLBStore                = 3,
 934   AddressLoad             = 4,
 935   AddressStore            = 5,
 936   InstructionFetch        = 6,
 937   DataReference           = 7,
 938   SystemCall              = 8,
 939   BreakPoint              = 9,
 940   ReservedInstruction     = 10,
 941   CoProcessorUnusable     = 11,
 942   IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 943   Trap                    = 13,
 944   FPE                     = 15,
 945   DebugBreakPoint         = 16,
 946   Watch                   = 23,
 947   NMIReset                = 31,
 948
 949
 950 /* The following exception code is actually private to the simulator
 951    world. It is *NOT* a processor feature, and is used to signal
 952    run-time errors in the simulator. */
 953   SimulatorFault          = 0xFFFFFFFF
 954 };
 955
 956 #define TLB_REFILL  (0)
 957 #define TLB_INVALID (1)
 958
 959 /* start-sanitize-r5900 */
 960 /* For the 5900, we have level 1 and level 2 exceptions.  The level 2 exceptions
 961    are ColdReset, NMI, Counter, and Debug/SIO.  Of these, we support only
 962    the NMIReset exception. */
 963
 964 #define is5900Level2Exception(x) (x == NMIReset)
 965 /* end-sanitize-r5900 */
 966
 967 /* The following break instructions are reserved for use by the
 968    simulator.  The first is used to halt the simulation.  The second
 969    is used by gdb for break-points.  NOTE: Care must be taken, since
 970    this value may be used in later revisions of the MIPS ISA. */
 971 #define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
 972
 973 #define HALT_INSTRUCTION        (0x03ff000d)
 974 #define HALT_INSTRUCTION2       (0x0000ffcd)
 975
 976 /* start-sanitize-sky */
 977 #define HALT_INSTRUCTION_PASS   (0x03fffc0d)    /* break 0xffff0 */
 978 #define HALT_INSTRUCTION_FAIL   (0x03ffffcd)    /* break 0xfffff */
 979 /* end-sanitize-sky */
 980
 981 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
 982 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
 983
 984 /* start-sanitize-sky */
 985 #define LOAD_INSTRUCTION        (0x03fffc4d)    /* break 0xffff1 */
 986 #define PRINTF_INSTRUCTION      (0x03fffc8d)    /* break 0xffff2 */
 987 /* end-sanitize-sky */
 988
 989
 990 void interrupt_event (SIM_DESC sd, void *data);
 991
 992 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 993 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 994 #define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
 995 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 996 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 997 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 998 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 999 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
1000 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
1001 #define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
1002 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
1003 #define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
1004 #define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
1005 #define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
1006 #define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
1007 #define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
1008
1009 /* Co-processor accesses */
1010
1011 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
1012 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
1013 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
1014 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
1015
1016 #define COP_LW(coproc_num,coproc_reg,memword) \
1017 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
1018 #define COP_LD(coproc_num,coproc_reg,memword) \
1019 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
1020 #define COP_SW(coproc_num,coproc_reg) \
1021 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
1022 #define COP_SD(coproc_num,coproc_reg) \
1023 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
1024
1025 /* start-sanitize-sky */
1026 #ifdef TARGET_SKY
1027 void cop_lq  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
1028                       int coproc_num, int coproc_reg, unsigned128 memword));
1029 unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
1030                             int coproc_num, int coproc_reg));
1031 #define COP_LQ(coproc_num,coproc_reg,memword) \
1032 cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
1033 #define COP_SQ(coproc_num,coproc_reg) \
1034 cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
1035 #endif /* TARGET_SKY */
1036 /* end-sanitize-sky */
1037
1038 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
1039 #define DecodeCoproc(instruction) \
1040 decode_coproc (SD, CPU, cia, (instruction))
1041
1042 void sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
1043
1044
1045
1046 /* Memory accesses */
1047
1048 /* The following are generic to all versions of the MIPS architecture
1049    to date: */
1050
1051 /* Memory Access Types (for CCA): */
1052 #define Uncached                (0)
1053 #define CachedNoncoherent       (1)
1054 #define CachedCoherent          (2)
1055 #define Cached                  (3)
1056
1057 #define isINSTRUCTION   (1 == 0) /* FALSE */
1058 #define isDATA          (1 == 1) /* TRUE */
1059 #define isLOAD          (1 == 0) /* FALSE */
1060 #define isSTORE         (1 == 1) /* TRUE */
1061 #define isREAL          (1 == 0) /* FALSE */
1062 #define isRAW           (1 == 1) /* TRUE */
1063 /* The parameter HOST (isTARGET / isHOST) is ignored */
1064 #define isTARGET        (1 == 0) /* FALSE */
1065 /* #define isHOST          (1 == 1) TRUE */
1066
1067 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
1068    is the number of bytes minus 1. */
1069 #define AccessLength_BYTE       (0)
1070 #define AccessLength_HALFWORD   (1)
1071 #define AccessLength_TRIPLEBYTE (2)
1072 #define AccessLength_WORD       (3)
1073 #define AccessLength_QUINTIBYTE (4)
1074 #define AccessLength_SEXTIBYTE  (5)
1075 #define AccessLength_SEPTIBYTE  (6)
1076 #define AccessLength_DOUBLEWORD (7)
1077 #define AccessLength_QUADWORD   (15)
1078
1079 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
1080                     ? AccessLength_DOUBLEWORD /*7*/ \
1081                     : AccessLength_WORD /*3*/)
1082 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
1083
1084
1085 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
1086 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
1087 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
1088
1089 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
1090 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
1091 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
1092
1093 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
1094 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
1095 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
1096
1097 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
1098 #define CacheOp(op,pAddr,vAddr,instruction) \
1099 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
1100
1101 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
1102 #define SyncOperation(stype) \
1103 sync_operation (SD, CPU, cia, (stype))
1104
1105 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
1106 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
1107 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
1108
1109 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
1110 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
1111 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
1112 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
1113 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
1114
1115 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
1116 extern FILE *tracefh;
1117
1118 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
1119
1120 char* pr_addr PARAMS ((SIM_ADDR addr));
1121 char* pr_uword64 PARAMS ((uword64 addr));
1122
1123 /* start-sanitize-sky */
1124 #ifdef TARGET_SKY
1125
1126 #ifdef SIM_ENGINE_HALT_HOOK
1127 #undef SIM_ENGINE_HALT_HOOK
1128 #endif
1129
1130 void sky_sim_engine_halt PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
1131 #define SIM_ENGINE_HALT_HOOK(sd, last, cia) sky_sim_engine_halt(sd, last, cia)
1132
1133 #ifdef SIM_ENGINE_RESTART_HOOK
1134 #undef SIM_ENGINE_RESTART_HOOK
1135 #endif
1136
1137 void sky_sim_engine_restart PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
1138 #define SIM_ENGINE_RESTART_HOOK(sd, L, pc) sky_sim_engine_restart(sd, L, pc)
1139
1140 /* for resume/suspend modules */
1141 SIM_RC sky_sim_module_install PARAMS ((SIM_DESC sd));
1142
1143 #define MODULE_LIST     sky_sim_module_install,
1144
1145 #ifndef TM_TXVU_H /* In case GDB hasn't been configured yet */
1146 enum txvu_cpu_context
1147 {
1148   TXVU_CPU_AUTO         = -1,   /* context-sensitive context */
1149   TXVU_CPU_MASTER       = 0,    /* R5900 core */
1150   TXVU_CPU_VU0          = 1,    /* Vector units */
1151   TXVU_CPU_VU1          = 2,
1152   TXVU_CPU_VIF0         = 3,    /* Vector interface units */
1153   TXVU_CPU_VIF1         = 4,
1154   TXVU_CPU_LAST                 /* Count of context types */
1155 };
1156
1157 /* memory segment for communication with GDB */
1158 #define VIO_BASE        0xa0000000
1159 #define GDB_COMM_AREA   0x19810000      /* Random choice */
1160 #define GDB_COMM_SIZE   0x4000
1161
1162 /* Memory address containing last device to execute */
1163 #define LAST_DEVICE     GDB_COMM_AREA
1164
1165 /* The FIFO breakpoint count and table */
1166 #define FIFO_BPT_CNT    (GDB_COMM_AREA + 4)
1167 #define FIFO_BPT_TBL    (GDB_COMM_AREA + 8)
1168
1169 /* Each element of the breakpoint table is three four-byte integers. */
1170 #define BPT_ELEM_SZ     4*3
1171
1172 #define TXVU_VU_BRK_MASK 0x02   /* Breakpoint bit is #57 for VU insns */
1173 #define TXVU_VIF_BRK_MASK 0x80  /* Use interrupt bit for VIF insns */
1174
1175 #endif /* !TM_TXVU_H */
1176 #endif /* TARGET_SKY */
1177 /* end-sanitize-sky */
1178
1179 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1180 #include "sim-main.c"
1181 #endif
1182
1183 #endif