f5356bd623bf2f986cfffa2574f7013f4e786d9d
1 /* MIPS Simulator definition.
2 Copyright (C) 1997 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* This simulator doesn't cache the Current Instruction Address */
25 #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA)
26 #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA)
28 #define SIM_HAVE_BIENDIAN
29 #define SIM_HAVE_FLATMEM
32 /* hobble some common features for moment */
33 #define WITH_PROFILE 0
35 #define WITH_WATCHPOINTS 1
37 #include "sim-basics.h"
39 /* dummy - not used */
46 /* Depreciated macros and types for manipulating 64bit values. Use
47 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
49 typedef signed64 word64
;
50 typedef unsigned64 uword64
;
52 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
53 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
54 #define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
55 #define SET64HI(t) (((uword64)(t))<<32)
56 #define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
57 #define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
59 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
60 assume the HI32bits of the operand are zero, so we must perform a
61 mask to ensure we can use the simple subtraction to sign-extend. */
62 #define SIGNEXTEND(e,b) \
63 (((e) & ((uword64) 1 << ((b) - 1))) \
64 ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
65 : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1)))
67 /* Check if a value will fit within a halfword: */
68 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
70 /* windows always looses */
73 #define SIGBUS SIGSEGV
81 /* FIXME: At present the CPU registers are static */
87 /* MIPS specific simulator watch config */
89 void watch_options_install
PARAMS ((SIM_DESC sd
));
98 /* FIXME: At present much of the simulator is still static */
105 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
107 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
116 /* NOTE: These numbers depend on the processor architecture being
118 #define Interrupt (0)
119 #define TLBModification (1)
122 #define AddressLoad (4)
123 #define AddressStore (5)
124 #define InstructionFetch (6)
125 #define DataReference (7)
126 #define SystemCall (8)
127 #define BreakPoint (9)
128 #define ReservedInstruction (10)
129 #define CoProcessorUnusable (11)
130 #define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
133 #define DebugBreakPoint (16)
136 /* The following exception code is actually private to the simulator
137 world. It is *NOT* a processor feature, and is used to signal
138 run-time errors in the simulator. */
139 #define SimulatorFault (0xFFFFFFFF)
141 void signal_exception (SIM_DESC sd
, int exception
, ...);
142 #define SignalException(exc,instruction) signal_exception (sd, (exc), (instruction))
143 #define SignalExceptionInterrupt() signal_exception (sd, Interrupt)
144 #define SignalExceptionInstructionFetch() signal_exception (sd, InstructionFetch)
145 #define SignalExceptionAddressStore() signal_exception (sd, AddressStore)
146 #define SignalExceptionAddressLoad() signal_exception (sd, AddressLoad)
147 #define SignalExceptionSimulatorFault(buf) signal_exception (sd, SimulatorFault, buf)
148 #define SignalExceptionFPE() signal_exception (sd, FPE)
149 #define SignalExceptionIntegerOverflow() signal_exception (sd, IntegerOverflow)
150 #define SignalExceptionCoProcessorUnusable() signal_exception (sd, CoProcessorUnusable)
153 /* Floating-point operations: */
155 /* FPU registers must be one of the following types. All other values
156 are reserved (and undefined). */
162 /* The following are well outside the normal acceptable format
163 range, and are used in the register status vector. */
164 fmt_unknown
= 0x10000000,
165 fmt_uninterpreted
= 0x20000000,
168 unsigned64 value_fpr
PARAMS ((SIM_DESC sd
, int fpr
, FP_formats
));
169 #define ValueFPR(FPR,FMT) value_fpr (sd, (FPR), (FMT))
171 void store_fpr
PARAMS ((SIM_DESC sd
, int fpr
, FP_formats fmt
, unsigned64 value
));
172 #define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, (FPR), (FMT), (VALUE))
174 int NaN
PARAMS ((unsigned64 op
, FP_formats fmt
));
175 int Infinity
PARAMS ((unsigned64 op
, FP_formats fmt
));
176 int Less
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
177 int Equal
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
178 unsigned64 AbsoluteValue
PARAMS ((unsigned64 op
, FP_formats fmt
));
179 unsigned64 Negate
PARAMS ((unsigned64 op
, FP_formats fmt
));
180 unsigned64 Add
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
181 unsigned64 Sub
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
182 unsigned64 Multiply
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
183 unsigned64 Divide
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
184 unsigned64 Recip
PARAMS ((unsigned64 op
, FP_formats fmt
));
185 unsigned64 SquareRoot
PARAMS ((unsigned64 op
, FP_formats fmt
));
186 unsigned64 convert
PARAMS ((SIM_DESC sd
, int rm
, unsigned64 op
, FP_formats from
, FP_formats to
));
187 #define Convert(rm,op,from,to) convert(sd,rm,op,from,to)
190 /* Co-processor accesses */
192 void cop_lw
PARAMS ((SIM_DESC sd
, int coproc_num
, int coproc_reg
, unsigned int memword
));
193 void cop_ld
PARAMS ((SIM_DESC sd
, int coproc_num
, int coproc_reg
, uword64 memword
));
194 unsigned int cop_sw
PARAMS ((SIM_DESC sd
, int coproc_num
, int coproc_reg
));
195 uword64 cop_sd
PARAMS ((SIM_DESC sd
, int coproc_num
, int coproc_reg
));
197 #define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,coproc_num,coproc_reg,memword)
198 #define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,coproc_num,coproc_reg,memword)
199 #define COP_SW(coproc_num,coproc_reg) cop_sw(sd,coproc_num,coproc_reg)
200 #define COP_SD(coproc_num,coproc_reg) cop_sd(sd,coproc_num,coproc_reg)
204 /* Memory accesses */
206 int address_translation
PARAMS ((SIM_DESC sd
, uword64 vAddr
, int IorD
, int LorS
, uword64
*pAddr
, int *CCA
, int host
, int raw
));
207 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
208 address_translation(sd, vAddr,IorD,LorS,pAddr,CCA,host,raw)
210 void load_memory
PARAMS ((SIM_DESC sd
, uword64
* memvalp
, uword64
* memval1p
, int CCA
, int AccessLength
, uword64 pAddr
, uword64 vAddr
, int IorD
, int raw
));
211 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
212 load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw)
214 void store_memory
PARAMS ((SIM_DESC sd
, int CCA
, int AccessLength
, uword64 MemElem
, uword64 MemElem1
, uword64 pAddr
, uword64 vAddr
, int raw
));
215 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
216 store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw)
218 void cache_op
PARAMS ((SIM_DESC sd
, int op
, uword64 pAddr
, uword64 vAddr
, unsigned int instruction
));
219 #define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,op,pAddr,vAddr,instruction)
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