sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 #if (WITH_IGEN)
  40 /* Get the number of instructions.  FIXME: must be a more elegant way
  41    of doing this.  */
  42 #include "itable.h"
  43 #define MAX_INSNS (nr_itable_entries)
  44 #define INSN_NAME(i) itable[(i)].name
  45 #endif
  46
  47 #include "sim-base.h"
  48
  49
  50 /* Depreciated macros and types for manipulating 64bit values.  Use
  51    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  52
  53 typedef signed64 word64;
  54 typedef unsigned64 uword64;
  55
  56 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  57 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  58 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  59 #define SET64HI(t)      (((uword64)(t))<<32)
  60 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  61 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  62
  63 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  64    assume the HI32bits of the operand are zero, so we must perform a
  65    mask to ensure we can use the simple subtraction to sign-extend. */
  66 #define SIGNEXTEND(e,b) \
  67  ((unsigned_word) \
  68   (((e) & ((uword64) 1 << ((b) - 1))) \
  69    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  70    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  71
  72 /* Check if a value will fit within a halfword: */
  73 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  74
  75
  76
  77 /* Floating-point operations: */
  78
  79 #include "sim-fpu.h"
  80
  81 /* FPU registers must be one of the following types. All other values
  82    are reserved (and undefined). */
  83 typedef enum {
  84  fmt_single  = 0,
  85  fmt_double  = 1,
  86  fmt_word    = 4,
  87  fmt_long    = 5,
  88  /* The following are well outside the normal acceptable format
  89     range, and are used in the register status vector. */
  90  fmt_unknown       = 0x10000000,
  91  fmt_uninterpreted = 0x20000000,
  92  fmt_uninterpreted_32 = 0x40000000,
  93  fmt_uninterpreted_64 = 0x80000000,
  94 } FP_formats;
  95
  96 unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
  97 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
  98
  99 void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
 100 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
 101
 102 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
 103 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 104 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 105 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 106 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 107 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 108 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 109 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 110 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 111 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 112 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 113 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 114 unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 115 #define Convert(rm,op,from,to) \
 116 convert (SD, CPU, cia, rm, op, from, to)
 117
 118 /* Macro to update FPSR condition-code field. This is complicated by
 119    the fact that there is a hole in the index range of the bits within
 120    the FCSR register. Also, the number of bits visible depends on the
 121    MIPS ISA version being supported. */
 122
 123 #define SETFCC(cc,v) {\
 124   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 125   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 126 }
 127 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
 128
 129 /* This should be the COC1 value at the start of the preceding
 130    instruction: */
 131 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 132
 133 #if 1
 134 #define SizeFGR() (WITH_TARGET_WORD_BITSIZE)
 135 #else
 136 /* They depend on the CPU being simulated */
 137 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 138 #endif
 139
 140 /* Standard FCRS bits: */
 141 #define IR (0) /* Inexact Result */
 142 #define UF (1) /* UnderFlow */
 143 #define OF (2) /* OverFlow */
 144 #define DZ (3) /* Division by Zero */
 145 #define IO (4) /* Invalid Operation */
 146 #define UO (5) /* Unimplemented Operation */
 147
 148 /* Get masks for individual flags: */
 149 #if 1 /* SAFE version */
 150 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 151 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 152 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 153 #else
 154 #define FP_FLAGS(b)  (1 << ((b) + 2))
 155 #define FP_ENABLE(b) (1 << ((b) + 7))
 156 #define FP_CAUSE(b)  (1 << ((b) + 12))
 157 #endif
 158
 159 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 160
 161 #define FP_MASK_RM    (0x3)
 162 #define FP_SH_RM      (0)
 163 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 164 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 165 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 166 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 167 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 168
 169
 170
 171 /* Integer ALU operations: */
 172
 173 #include "sim-alu.h"
 174
 175 #define ALU32_END(ANS) \
 176   if (ALU32_HAD_OVERFLOW) \
 177     SignalExceptionIntegerOverflow (); \
 178   (ANS) = ALU32_OVERFLOW_RESULT
 179
 180
 181 #define ALU64_END(ANS) \
 182   if (ALU64_HAD_OVERFLOW) \
 183     SignalExceptionIntegerOverflow (); \
 184   (ANS) = ALU64_OVERFLOW_RESULT;
 185
 186 /* start-sanitize-r5900 */
 187
 188 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 189 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 190 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 191 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 192
 193 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 194 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 195 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 196 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 197
 198 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 199    T  - type of the sub part
 200    TC - # of T's in the mips part of the "register"
 201    I  - index (from 0) of desired sub part
 202    A  - low part of "register"
 203    A1 - high part of register
 204 */
 205 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 206 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 207    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 208       ? ((TC) - 1 - (I) % (TC)) \
 209       : ((I) % (TC)) \
 210       ) \
 211    ) \
 212  )
 213
 214 /*
 215 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 216             where <type> has two letters:
 217                   1 is S=signed or U=unsigned
 218                   2 is B=byte H=halfword W=word D=doubleword
 219 */
 220
 221 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 222 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 223 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 224 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 225
 226 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 227 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 228 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 229 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 230
 231 #define GPR_SB(R,I) SUB_REG_SB(&REGISTERS[R], &REGISTERS1[R], I)
 232 #define GPR_SH(R,I) SUB_REG_SH(&REGISTERS[R], &REGISTERS1[R], I)
 233 #define GPR_SW(R,I) SUB_REG_SW(&REGISTERS[R], &REGISTERS1[R], I)
 234 #define GPR_SD(R,I) SUB_REG_SD(&REGISTERS[R], &REGISTERS1[R], I)
 235
 236 #define GPR_UB(R,I) SUB_REG_UB(&REGISTERS[R], &REGISTERS1[R], I)
 237 #define GPR_UH(R,I) SUB_REG_UH(&REGISTERS[R], &REGISTERS1[R], I)
 238 #define GPR_UW(R,I) SUB_REG_UW(&REGISTERS[R], &REGISTERS1[R], I)
 239 #define GPR_UD(R,I) SUB_REG_UD(&REGISTERS[R], &REGISTERS1[R], I)
 240
 241
 242 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 243 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 244 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 245 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 246
 247 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 248 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 249 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 250 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 251
 252 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 253 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 254 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 255 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 256
 257 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 258 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 259 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 260 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 261
 262
 263
 264 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 265 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 266 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 267 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 268
 269 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 270 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 271 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 272 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 273
 274 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 275 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 276 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 277 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 278
 279 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 280 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 281 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 282 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 283
 284 /* end-sanitize-r5900 */
 285
 286
 287
 288
 289 struct _sim_cpu {
 290
 291
 292   /* The following are internal simulator state variables: */
 293 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 294 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 295   address_word dspc;  /* delay-slot PC */
 296 #define DSPC ((CPU)->dspc)
 297
 298   /* Issue a delay slot instruction immediatly by re-calling
 299      idecode_issue */
 300 #define DELAY_SLOT(TARGET) \
 301   do { \
 302     address_word target = (TARGET); \
 303     instruction_word delay_insn; \
 304     sim_events_slip (SD, 1); \
 305     CIA = CIA + 4; \
 306     STATE |= simDELAYSLOT; \
 307     delay_insn = IMEM (CIA); \
 308     idecode_issue (CPU_, delay_insn, (CIA)); \
 309     STATE &= ~simDELAYSLOT; \
 310     NIA = target; \
 311   } while (0)
 312 #define NULLIFY_NEXT_INSTRUCTION() \
 313   do { \
 314     sim_events_slip (SD, 1); \
 315     dotrace (SD, CPU, tracefh, 2, NIA, 4, "load instruction"); \
 316     NIA = CIA + 8; \
 317   } while (0)
 318
 319
 320
 321   /* State of the simulator */
 322   unsigned int state;
 323   unsigned int dsstate;
 324 #define STATE ((CPU)->state)
 325 #define DSSTATE ((CPU)->dsstate)
 326
 327 /* Flags in the "state" variable: */
 328 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 329 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 330 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 331 #define simPCOC0        (1 << 17) /* COC[1] from current */
 332 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 333 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 334 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 335 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 336 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 337
 338 #define ENGINE_ISSUE_PREFIX_HOOK() \
 339   { \
 340     /* Set previous flag, depending on current: */ \
 341     if (STATE & simPCOC0) \
 342      STATE |= simPCOC1; \
 343     else \
 344      STATE &= ~simPCOC1; \
 345     /* and update the current value: */ \
 346     if (GETFCC(0)) \
 347      STATE |= simPCOC0; \
 348     else \
 349      STATE &= ~simPCOC0; \
 350   }
 351
 352
 353 /* This is nasty, since we have to rely on matching the register
 354    numbers used by GDB. Unfortunately, depending on the MIPS target
 355    GDB uses different register numbers. We cannot just include the
 356    relevant "gdb/tm.h" link, since GDB may not be configured before
 357    the sim world, and also the GDB header file requires too much other
 358    state. */
 359
 360 #ifndef TM_MIPS_H
 361 #define LAST_EMBED_REGNUM (89)
 362 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 363 /* start-sanitize-r5900 */
 364 #undef NUM_REGS
 365 #define NUM_REGS (128)
 366 /* end-sanitize-r5900 */
 367 #endif
 368
 369 /* To keep this default simulator simple, and fast, we use a direct
 370    vector of registers. The internal simulator engine then uses
 371    manifests to access the correct slot. */
 372
 373   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 374   int register_widths[NUM_REGS];
 375 #define REGISTERS       ((CPU)->registers)
 376
 377 #define GPR     (&REGISTERS[0])
 378 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 379 #define FGRIDX  (38)
 380 #define FGR     (&REGISTERS[FGRIDX])
 381 #define LO      (REGISTERS[33])
 382 #define HI      (REGISTERS[34])
 383 #define PCIDX   37
 384 #define PC      (REGISTERS[PCIDX])
 385 #define CAUSE   (REGISTERS[36])
 386 #define SRIDX   (32)
 387 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 388 #define FCR0IDX  (71)
 389 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 390 #define FCR31IDX (70)
 391 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 392 #define FCSR    (FCR31)
 393 #define Debug   (REGISTERS[86])
 394 #define DEPC    (REGISTERS[87])
 395 #define EPC     (REGISTERS[88])
 396 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 397
 398   unsigned_word c0_config_reg;
 399 #define C0_CONFIG ((CPU)->c0_config_reg)
 400
 401 /* The following are pseudonyms for standard registers */
 402 #define ZERO    (REGISTERS[0])
 403 #define V0      (REGISTERS[2])
 404 #define A0      (REGISTERS[4])
 405 #define A1      (REGISTERS[5])
 406 #define A2      (REGISTERS[6])
 407 #define A3      (REGISTERS[7])
 408 #define SP      (REGISTERS[29])
 409 #define RA      (REGISTERS[31])
 410
 411   /* Keep the current format state for each register: */
 412   FP_formats fpr_state[32];
 413 #define FPR_STATE ((CPU)->fpr_state)
 414
 415
 416   /* Slots for delayed register updates. For the moment we just have a
 417      fixed number of slots (rather than a more generic, dynamic
 418      system). This keeps the simulator fast. However, we only allow
 419      for the register update to be delayed for a single instruction
 420      cycle. */
 421 #define PSLOTS (5) /* Maximum number of instruction cycles */
 422   int pending_in;
 423   int pending_out;
 424   int pending_total;
 425   int pending_slot_count[PSLOTS];
 426   int pending_slot_reg[PSLOTS];
 427   unsigned_word pending_slot_value[PSLOTS];
 428 #define PENDING_IN ((CPU)->pending_in)
 429 #define PENDING_OUT ((CPU)->pending_out)
 430 #define PENDING_TOTAL ((CPU)->pending_total)
 431 #define PENDING_SLOT_COUNT ((CPU)->pending_slot_count)
 432 #define PENDING_SLOT_REG ((CPU)->pending_slot_reg)
 433 #define PENDING_SLOT_VALUE ((CPU)->pending_slot_value)
 434
 435   /* The following are not used for MIPS IV onwards: */
 436 #define PENDING_FILL(r,v) {\
 437 /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
 438                             if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
 439                              sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
 440                             PENDING_SLOT_COUNT[PENDING_IN] = 2;\
 441                             PENDING_SLOT_REG[PENDING_IN] = (r);\
 442                             PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
 443 /*printf("DBG: FILL        reg %d value = 0x%s\n",(r),pr_addr(v));*/\
 444                             PENDING_TOTAL++;\
 445                             PENDING_IN++;\
 446                             if (PENDING_IN == PSLOTS)\
 447                              PENDING_IN = 0;\
 448 /*printf("DBG: FILL AFTER  pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
 449                           }
 450
 451
 452   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 453      read-write instructions. It is set when a linked load occurs. It
 454      is tested and cleared by the conditional store. It is cleared
 455      (during other CPU operations) when a store to the location would
 456      no longer be atomic. In particular, it is cleared by exception
 457      return instructions. */
 458   int llbit;
 459 #define LLBIT ((CPU)->llbit)
 460
 461
 462 /* The HIACCESS and LOACCESS counts are used to ensure that
 463    corruptions caused by using the HI or LO register to close to a
 464    following operation are spotted. */
 465
 466   int hiaccess;
 467   int loaccess;
 468 #define HIACCESS ((CPU)->hiaccess)
 469 #define LOACCESS ((CPU)->loaccess)
 470   /* start-sanitize-r5900 */
 471   int hi1access;
 472   int lo1access;
 473 #define HI1ACCESS ((CPU)->hi1access)
 474 #define LO1ACCESS ((CPU)->lo1access)
 475   /* end-sanitize-r5900 */
 476 #if 1
 477   /* The 4300 and a few other processors have interlocks on hi/lo
 478      register reads, and hence do not have this problem.  To avoid
 479      spurious warnings, we just disable this always.  */
 480 #define CHECKHILO(s)
 481 #else
 482   unsigned_word HLPC;
 483   /* If either of the preceding two instructions have accessed the HI
 484      or LO registers, then the values they see should be
 485      undefined. However, to keep the simulator world simple, we just
 486      let them use the value read and raise a warning to notify the
 487      user: */
 488 #define CHECKHILO(s) {\
 489   if ((HIACCESS != 0) || (LOACCESS != 0)) \
 490     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 491 }
 492   /* start-sanitize-r5900 */
 493 #undef CHECKHILO
 494 #define CHECKHILO(s) {\
 495   if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
 496     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 497 }
 498   /* end-sanitize-r5900 */
 499 #endif
 500
 501
 502   /* start-sanitize-r5900 */
 503   /* The R5900 has 128 bit registers, but the hi 64 bits are only
 504      touched by multimedia (MMI) instructions.  The normal mips
 505      instructions just use the lower 64 bits.  To avoid changing the
 506      older parts of the simulator to handle this weirdness, the high
 507      64 bits of each register are kept in a separate array
 508      (registers1).  The high 64 bits of any register are by convention
 509      refered by adding a '1' to the end of the normal register's name.
 510      So LO still refers to the low 64 bits of the LO register, LO1
 511      refers to the high 64 bits of that same register.  */
 512
 513   signed_word registers1[LAST_EMBED_REGNUM + 1];
 514 #define REGISTERS1 ((CPU)->registers1)
 515 #define GPR1     (&REGISTERS1[0])
 516 #define LO1      (REGISTERS1[32])
 517 #define HI1      (REGISTERS1[33])
 518 #define REGISTER_SA     (124)
 519
 520   unsigned_word sa;        /* the shift amount register */
 521 #define SA ((CPU)->sa)
 522
 523   /* end-sanitize-r5900 */
 524   /* start-sanitize-vr5400 */
 525
 526   /* The MDMX ISA has a very very large accumulator */
 527   unsigned8 acc[3 * 8];
 528   /* end-sanitize-vr5400 */
 529
 530   sim_cpu_base base;
 531 };
 532
 533
 534 /* MIPS specific simulator watch config */
 535
 536 void watch_options_install PARAMS ((SIM_DESC sd));
 537
 538 struct swatch {
 539   sim_event *pc;
 540   sim_event *clock;
 541   sim_event *cycles;
 542 };
 543
 544
 545 /* FIXME: At present much of the simulator is still static */
 546 struct sim_state {
 547
 548   struct swatch watch;
 549
 550   sim_cpu cpu[MAX_NR_PROCESSORS];
 551 #if (WITH_SMP)
 552 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 553 #else
 554 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 555 #endif
 556
 557   sim_state_base base;
 558 };
 559
 560
 561
 562 /* Status information: */
 563
 564 /* TODO : these should be the bitmasks for these bits within the
 565    status register. At the moment the following are VR4300
 566    bit-positions: */
 567 #define status_KSU_mask  (0x3)          /* mask for KSU bits */
 568 #define status_KSU_shift (3)            /* shift for field */
 569 #define ksu_kernel       (0x0)
 570 #define ksu_supervisor   (0x1)
 571 #define ksu_user         (0x2)
 572 #define ksu_unknown      (0x3)
 573
 574 #define status_IE        (1 <<  0)      /* Interrupt enable */
 575 #define status_EXL       (1 <<  1)      /* Exception level */
 576 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 577 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 578 #define status_SR        (1 << 20)      /* soft reset or NMI */
 579 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 580 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 581 #define status_ERL       (1 <<  2)      /* Error level */
 582 #define status_RP        (1 << 27)      /* Reduced Power mode */
 583
 584 #define cause_BD        ((unsigned)1 << 31)     /* Exception in branch delay slot */
 585
 586 /* NOTE: We keep the following status flags as bit values (1 for true,
 587    0 for false). This allows them to be used in binary boolean
 588    operations without worrying about what exactly the non-zero true
 589    value is. */
 590
 591 /* UserMode */
 592 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 593
 594 /* BigEndianMem */
 595 /* Hardware configuration. Affects endianness of LoadMemory and
 596    StoreMemory and the endianness of Kernel and Supervisor mode
 597    execution. The value is 0 for little-endian; 1 for big-endian. */
 598 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 599 /*(state & simBE) ? 1 : 0)*/
 600
 601 /* ReverseEndian */
 602 /* This mode is selected if in User mode with the RE bit being set in
 603    SR (Status Register). It reverses the endianness of load and store
 604    instructions. */
 605 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 606
 607 /* BigEndianCPU */
 608 /* The endianness for load and store instructions (0=little;1=big). In
 609    User mode this endianness may be switched by setting the state_RE
 610    bit in the SR register. Thus, BigEndianCPU may be computed as
 611    (BigEndianMem EOR ReverseEndian). */
 612 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 613
 614
 615
 616 /* Exceptions: */
 617
 618 /* NOTE: These numbers depend on the processor architecture being
 619    simulated: */
 620 #define Interrupt               (0)
 621 #define TLBModification         (1)
 622 #define TLBLoad                 (2)
 623 #define TLBStore                (3)
 624 #define AddressLoad             (4)
 625 #define AddressStore            (5)
 626 #define InstructionFetch        (6)
 627 #define DataReference           (7)
 628 #define SystemCall              (8)
 629 #define BreakPoint              (9)
 630 #define ReservedInstruction     (10)
 631 #define CoProcessorUnusable     (11)
 632 #define IntegerOverflow         (12)    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 633 #define Trap                    (13)
 634 #define FPE                     (15)
 635 #define DebugBreakPoint         (16)
 636 #define Watch                   (23)
 637
 638 /* The following exception code is actually private to the simulator
 639    world. It is *NOT* a processor feature, and is used to signal
 640    run-time errors in the simulator. */
 641 #define SimulatorFault      (0xFFFFFFFF)
 642
 643 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 644 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 645 #define SignalExceptionInterrupt()           signal_exception (SD, CPU, NULL_CIA, Interrupt)
 646 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 647 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 648 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 649 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 650 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 651 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 652 #define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
 653
 654
 655 /* Co-processor accesses */
 656
 657 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 658 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 659 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 660 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 661
 662 #define COP_LW(coproc_num,coproc_reg,memword) \
 663 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 664 #define COP_LD(coproc_num,coproc_reg,memword) \
 665 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 666 #define COP_SW(coproc_num,coproc_reg) \
 667 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 668 #define COP_SD(coproc_num,coproc_reg) \
 669 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 670
 671 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
 672 #define DecodeCoproc(instruction) \
 673 decode_coproc (SD, CPU, cia, (instruction))
 674
 675
 676
 677 /* Memory accesses */
 678
 679 /* The following are generic to all versions of the MIPS architecture
 680    to date: */
 681
 682 /* Memory Access Types (for CCA): */
 683 #define Uncached                (0)
 684 #define CachedNoncoherent       (1)
 685 #define CachedCoherent          (2)
 686 #define Cached                  (3)
 687
 688 #define isINSTRUCTION   (1 == 0) /* FALSE */
 689 #define isDATA          (1 == 1) /* TRUE */
 690 #define isLOAD          (1 == 0) /* FALSE */
 691 #define isSTORE         (1 == 1) /* TRUE */
 692 #define isREAL          (1 == 0) /* FALSE */
 693 #define isRAW           (1 == 1) /* TRUE */
 694 /* The parameter HOST (isTARGET / isHOST) is ignored */
 695 #define isTARGET        (1 == 0) /* FALSE */
 696 /* #define isHOST          (1 == 1) TRUE */
 697
 698 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 699    is the number of bytes minus 1. */
 700 #define AccessLength_BYTE       (0)
 701 #define AccessLength_HALFWORD   (1)
 702 #define AccessLength_TRIPLEBYTE (2)
 703 #define AccessLength_WORD       (3)
 704 #define AccessLength_QUINTIBYTE (4)
 705 #define AccessLength_SEXTIBYTE  (5)
 706 #define AccessLength_SEPTIBYTE  (6)
 707 #define AccessLength_DOUBLEWORD (7)
 708 #define AccessLength_QUADWORD   (15)
 709
 710 int address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 711 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 712 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 713
 714 void load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 715 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 716 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 717
 718 void store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 719 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 720 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 721
 722 void cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 723 #define CacheOp(op,pAddr,vAddr,instruction) \
 724 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 725
 726 void sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
 727 #define SyncOperation(stype) \
 728 sync_operation (SD, CPU, cia, (stype))
 729
 730 void prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 731 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 732 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 733
 734 unsigned32 ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 735 #define IMEM(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 736
 737 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 738 FILE *tracefh;
 739
 740 #endif