sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 #if (WITH_IGEN)
  40 /* Get the number of instructions.  FIXME: must be a more elegant way
  41    of doing this.  */
  42 #include "itable.h"
  43 #define MAX_INSNS (nr_itable_entries)
  44 #define INSN_NAME(i) itable[(i)].name
  45 #endif
  46
  47 #include "sim-base.h"
  48
  49
  50 /* Depreciated macros and types for manipulating 64bit values.  Use
  51    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  52
  53 typedef signed64 word64;
  54 typedef unsigned64 uword64;
  55
  56 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  57 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  58 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  59 #define SET64HI(t)      (((uword64)(t))<<32)
  60 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  61 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  62
  63 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  64    assume the HI32bits of the operand are zero, so we must perform a
  65    mask to ensure we can use the simple subtraction to sign-extend. */
  66 #define SIGNEXTEND(e,b) \
  67  ((unsigned_word) \
  68   (((e) & ((uword64) 1 << ((b) - 1))) \
  69    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  70    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  71
  72 /* Check if a value will fit within a halfword: */
  73 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  74
  75
  76
  77 /* Floating-point operations: */
  78
  79 /* FPU registers must be one of the following types. All other values
  80    are reserved (and undefined). */
  81 typedef enum {
  82  fmt_single  = 0,
  83  fmt_double  = 1,
  84  fmt_word    = 4,
  85  fmt_long    = 5,
  86  /* The following are well outside the normal acceptable format
  87     range, and are used in the register status vector. */
  88  fmt_unknown       = 0x10000000,
  89  fmt_uninterpreted = 0x20000000,
  90  fmt_uninterpreted_32 = 0x40000000,
  91  fmt_uninterpreted_64 = 0x80000000,
  92 } FP_formats;
  93
  94 unsigned64 value_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats));
  95 #define ValueFPR(FPR,FMT) value_fpr (sd, cia, (FPR), (FMT))
  96
  97 void store_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
  98 #define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, cia, (FPR), (FMT), (VALUE))
  99
 100 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
 101 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 102 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 103 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 104 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 105 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 106 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 107 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 108 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 109 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 110 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 111 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 112 unsigned64 convert PARAMS ((SIM_DESC sd, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 113 #define Convert(rm,op,from,to) convert(sd,cia,rm,op,from,to)
 114
 115 /* Macro to update FPSR condition-code field. This is complicated by
 116    the fact that there is a hole in the index range of the bits within
 117    the FCSR register. Also, the number of bits visible depends on the
 118    MIPS ISA version being supported. */
 119
 120 #define SETFCC(cc,v) {\
 121   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 122   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 123 }
 124 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
 125
 126 /* This should be the COC1 value at the start of the preceding
 127    instruction: */
 128 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 129
 130 #if 1
 131 #define SizeFGR() (WITH_TARGET_WORD_BITSIZE)
 132 #else
 133 /* They depend on the CPU being simulated */
 134 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 135 #endif
 136
 137 /* Standard FCRS bits: */
 138 #define IR (0) /* Inexact Result */
 139 #define UF (1) /* UnderFlow */
 140 #define OF (2) /* OverFlow */
 141 #define DZ (3) /* Division by Zero */
 142 #define IO (4) /* Invalid Operation */
 143 #define UO (5) /* Unimplemented Operation */
 144
 145 /* Get masks for individual flags: */
 146 #if 1 /* SAFE version */
 147 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 148 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 149 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 150 #else
 151 #define FP_FLAGS(b)  (1 << ((b) + 2))
 152 #define FP_ENABLE(b) (1 << ((b) + 7))
 153 #define FP_CAUSE(b)  (1 << ((b) + 12))
 154 #endif
 155
 156 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 157
 158 #define FP_MASK_RM    (0x3)
 159 #define FP_SH_RM      (0)
 160 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 161 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 162 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 163 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 164 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 165
 166
 167
 168 /* Integer ALU operations: */
 169
 170 #include "sim-alu.h"
 171
 172 #define ALU32_END(ANS) \
 173   if (ALU32_HAD_OVERFLOW) \
 174     SignalExceptionIntegerOverflow (); \
 175   (ANS) = ALU32_OVERFLOW_RESULT
 176
 177
 178 #define ALU64_END(ANS) \
 179   if (ALU64_HAD_OVERFLOW) \
 180     SignalExceptionIntegerOverflow (); \
 181   (ANS) = ALU64_OVERFLOW_RESULT;
 182
 183 /* start-sanitize-r5900 */
 184
 185 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 186 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 187 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 188 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 189
 190 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 191 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 192 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 193 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 194
 195 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 196    T  - type of the sub part
 197    TC - # of T's in the mips part of the "register"
 198    I  - index (from 0) of desired sub part
 199    A  - low part of "register"
 200    A1 - high part of register
 201 */
 202 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 203 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 204    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 205       ? ((TC) - 1 - (I) % (TC)) \
 206       : ((I) % (TC)) \
 207       ) \
 208    ) \
 209  )
 210
 211 /*
 212 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 213             where <type> has two letters:
 214                   1 is S=signed or U=unsigned
 215                   2 is B=byte H=halfword W=word D=doubleword
 216 */
 217
 218 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 219 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 220 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 221 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 222
 223 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 224 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 225 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 226 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 227
 228 #define GPR_SB(R,I) SUB_REG_SB(&REGISTERS[R], &REGISTERS1[R], I)
 229 #define GPR_SH(R,I) SUB_REG_SH(&REGISTERS[R], &REGISTERS1[R], I)
 230 #define GPR_SW(R,I) SUB_REG_SW(&REGISTERS[R], &REGISTERS1[R], I)
 231 #define GPR_SD(R,I) SUB_REG_SD(&REGISTERS[R], &REGISTERS1[R], I)
 232
 233 #define GPR_UB(R,I) SUB_REG_UB(&REGISTERS[R], &REGISTERS1[R], I)
 234 #define GPR_UH(R,I) SUB_REG_UH(&REGISTERS[R], &REGISTERS1[R], I)
 235 #define GPR_UW(R,I) SUB_REG_UW(&REGISTERS[R], &REGISTERS1[R], I)
 236 #define GPR_UD(R,I) SUB_REG_UD(&REGISTERS[R], &REGISTERS1[R], I)
 237
 238
 239 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 240 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 241 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 242 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 243
 244 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 245 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 246 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 247 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 248
 249 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 250 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 251 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 252 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 253
 254 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 255 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 256 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 257 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 258
 259
 260
 261 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 262 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 263 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 264 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 265
 266 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 267 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 268 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 269 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 270
 271 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 272 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 273 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 274 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 275
 276 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 277 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 278 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 279 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 280
 281 /* end-sanitize-r5900 */
 282
 283
 284
 285
 286 struct _sim_cpu {
 287
 288
 289   /* The following are internal simulator state variables: */
 290 #define CPU_CIA(CPU) (PC)
 291   address_word dspc;  /* delay-slot PC */
 292 #define DSPC ((STATE_CPU (sd,0))->dspc)
 293
 294   /* Issue a delay slot instruction immediatly by re-calling
 295      idecode_issue */
 296 #define DELAY_SLOT(TARGET) \
 297   do { \
 298     address_word target = (TARGET); \
 299     instruction_word delay_insn; \
 300     sim_events_slip (sd, 1); \
 301     CIA = CIA + 4; \
 302     STATE |= simDELAYSLOT; \
 303     delay_insn = IMEM (CIA); \
 304     idecode_issue (sd, delay_insn, (CIA)); \
 305     STATE &= ~simDELAYSLOT; \
 306     NIA = target; \
 307   } while (0)
 308 #define NULLIFY_NEXT_INSTRUCTION() \
 309   do { \
 310     sim_events_slip (sd, 1); \
 311     dotrace (sd, tracefh, 2, NIA, 4, "load instruction"); \
 312     NIA = CIA + 8; \
 313   } while (0)
 314
 315
 316
 317   /* State of the simulator */
 318   unsigned int state;
 319   unsigned int dsstate;
 320 #define STATE ((STATE_CPU (sd,0))->state)
 321 #define DSSTATE ((STATE_CPU (sd,0))->dsstate)
 322
 323 /* Flags in the "state" variable: */
 324 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 325 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 326 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 327 #define simPCOC0        (1 << 17) /* COC[1] from current */
 328 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 329 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 330 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 331 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 332 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 333
 334 #define ENGINE_ISSUE_PREFIX_HOOK() \
 335   { \
 336     /* Set previous flag, depending on current: */ \
 337     if (STATE & simPCOC0) \
 338      STATE |= simPCOC1; \
 339     else \
 340      STATE &= ~simPCOC1; \
 341     /* and update the current value: */ \
 342     if (GETFCC(0)) \
 343      STATE |= simPCOC0; \
 344     else \
 345      STATE &= ~simPCOC0; \
 346   }
 347
 348
 349 /* This is nasty, since we have to rely on matching the register
 350    numbers used by GDB. Unfortunately, depending on the MIPS target
 351    GDB uses different register numbers. We cannot just include the
 352    relevant "gdb/tm.h" link, since GDB may not be configured before
 353    the sim world, and also the GDB header file requires too much other
 354    state. */
 355
 356 #ifndef TM_MIPS_H
 357 #define LAST_EMBED_REGNUM (89)
 358 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 359 /* start-sanitize-r5900 */
 360 #undef NUM_REGS
 361 #define NUM_REGS (128)
 362 /* end-sanitize-r5900 */
 363 #endif
 364
 365 /* To keep this default simulator simple, and fast, we use a direct
 366    vector of registers. The internal simulator engine then uses
 367    manifests to access the correct slot. */
 368
 369   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 370   int register_widths[NUM_REGS];
 371 #define REGISTERS       ((STATE_CPU (sd,0))->registers)
 372
 373 #define GPR     (&REGISTERS[0])
 374 #define FGRIDX  (38)
 375 #define FGR     (&REGISTERS[FGRIDX])
 376 #define LO      (REGISTERS[33])
 377 #define HI      (REGISTERS[34])
 378 #define PC      (REGISTERS[37])
 379 #define CAUSE   (REGISTERS[36])
 380 #define SRIDX   (32)
 381 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 382 #define FCR0IDX  (71)
 383 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 384 #define FCR31IDX (70)
 385 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 386 #define FCSR    (FCR31)
 387 #define Debug   (REGISTERS[86])
 388 #define DEPC    (REGISTERS[87])
 389 #define EPC     (REGISTERS[88])
 390 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 391
 392   unsigned_word c0_config_reg;
 393 #define C0_CONFIG ((STATE_CPU (sd,0))->c0_config_reg)
 394
 395 /* The following are pseudonyms for standard registers */
 396 #define ZERO    (REGISTERS[0])
 397 #define V0      (REGISTERS[2])
 398 #define A0      (REGISTERS[4])
 399 #define A1      (REGISTERS[5])
 400 #define A2      (REGISTERS[6])
 401 #define A3      (REGISTERS[7])
 402 #define SP      (REGISTERS[29])
 403 #define RA      (REGISTERS[31])
 404
 405   /* Keep the current format state for each register: */
 406   FP_formats fpr_state[32];
 407 #define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state)
 408
 409
 410   /* Slots for delayed register updates. For the moment we just have a
 411      fixed number of slots (rather than a more generic, dynamic
 412      system). This keeps the simulator fast. However, we only allow
 413      for the register update to be delayed for a single instruction
 414      cycle. */
 415 #define PSLOTS (5) /* Maximum number of instruction cycles */
 416   int pending_in;
 417   int pending_out;
 418   int pending_total;
 419   int pending_slot_count[PSLOTS];
 420   int pending_slot_reg[PSLOTS];
 421   unsigned_word pending_slot_value[PSLOTS];
 422 #define PENDING_IN ((STATE_CPU (sd, 0))->pending_in)
 423 #define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out)
 424 #define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total)
 425 #define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count)
 426 #define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg)
 427 #define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value)
 428
 429   /* The following are not used for MIPS IV onwards: */
 430 #define PENDING_FILL(r,v) {\
 431 /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
 432                             if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
 433                              sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
 434                             PENDING_SLOT_COUNT[PENDING_IN] = 2;\
 435                             PENDING_SLOT_REG[PENDING_IN] = (r);\
 436                             PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
 437 /*printf("DBG: FILL        reg %d value = 0x%s\n",(r),pr_addr(v));*/\
 438                             PENDING_TOTAL++;\
 439                             PENDING_IN++;\
 440                             if (PENDING_IN == PSLOTS)\
 441                              PENDING_IN = 0;\
 442 /*printf("DBG: FILL AFTER  pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
 443                           }
 444
 445
 446   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 447      read-write instructions. It is set when a linked load occurs. It
 448      is tested and cleared by the conditional store. It is cleared
 449      (during other CPU operations) when a store to the location would
 450      no longer be atomic. In particular, it is cleared by exception
 451      return instructions. */
 452   int llbit;
 453 #define LLBIT ((STATE_CPU (sd, 0))->llbit)
 454
 455
 456 /* The HIACCESS and LOACCESS counts are used to ensure that
 457    corruptions caused by using the HI or LO register to close to a
 458    following operation are spotted. */
 459
 460   int hiaccess;
 461   int loaccess;
 462 #define HIACCESS ((STATE_CPU (sd, 0))->hiaccess)
 463 #define LOACCESS ((STATE_CPU (sd, 0))->loaccess)
 464   /* start-sanitize-r5900 */
 465   int hi1access;
 466   int lo1access;
 467 #define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access)
 468 #define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access)
 469   /* end-sanitize-r5900 */
 470 #if 1
 471   /* The 4300 and a few other processors have interlocks on hi/lo
 472      register reads, and hence do not have this problem.  To avoid
 473      spurious warnings, we just disable this always.  */
 474 #define CHECKHILO(s)
 475 #else
 476   unsigned_word HLPC;
 477   /* If either of the preceding two instructions have accessed the HI
 478      or LO registers, then the values they see should be
 479      undefined. However, to keep the simulator world simple, we just
 480      let them use the value read and raise a warning to notify the
 481      user: */
 482 #define CHECKHILO(s) {\
 483   if ((HIACCESS != 0) || (LOACCESS != 0)) \
 484     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 485 }
 486   /* start-sanitize-r5900 */
 487 #undef CHECKHILO
 488 #define CHECKHILO(s) {\
 489   if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
 490     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 491 }
 492   /* end-sanitize-r5900 */
 493 #endif
 494
 495
 496   /* start-sanitize-r5900 */
 497   /* The R5900 has 128 bit registers, but the hi 64 bits are only
 498      touched by multimedia (MMI) instructions.  The normal mips
 499      instructions just use the lower 64 bits.  To avoid changing the
 500      older parts of the simulator to handle this weirdness, the high
 501      64 bits of each register are kept in a separate array
 502      (registers1).  The high 64 bits of any register are by convention
 503      refered by adding a '1' to the end of the normal register's name.
 504      So LO still refers to the low 64 bits of the LO register, LO1
 505      refers to the high 64 bits of that same register.  */
 506
 507   signed_word registers1[LAST_EMBED_REGNUM + 1];
 508 #define REGISTERS1 ((STATE_CPU (sd, 0))->registers1)
 509 #define GPR1     (&REGISTERS1[0])
 510 #define LO1      (REGISTERS1[32])
 511 #define HI1      (REGISTERS1[33])
 512 #define REGISTER_SA     (124)
 513
 514   unsigned_word sa;        /* the shift amount register */
 515 #define SA ((STATE_CPU (sd, 0))->sa)
 516
 517   /* end-sanitize-r5900 */
 518   /* start-sanitize-vr5400 */
 519
 520   /* end-sanitize-vr5400 */
 521
 522
 523
 524   sim_cpu_base base;
 525 };
 526
 527
 528 /* MIPS specific simulator watch config */
 529
 530 void watch_options_install PARAMS ((SIM_DESC sd));
 531
 532 struct swatch {
 533   sim_event *pc;
 534   sim_event *clock;
 535   sim_event *cycles;
 536 };
 537
 538
 539 /* FIXME: At present much of the simulator is still static */
 540 struct sim_state {
 541
 542   struct swatch watch;
 543
 544   sim_cpu cpu[1];
 545 #if (WITH_SMP)
 546 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 547 #else
 548 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 549 #endif
 550
 551   sim_state_base base;
 552 };
 553
 554
 555
 556 /* Status information: */
 557
 558 /* TODO : these should be the bitmasks for these bits within the
 559    status register. At the moment the following are VR4300
 560    bit-positions: */
 561 #define status_KSU_mask  (0x3)          /* mask for KSU bits */
 562 #define status_KSU_shift (3)            /* shift for field */
 563 #define ksu_kernel       (0x0)
 564 #define ksu_supervisor   (0x1)
 565 #define ksu_user         (0x2)
 566 #define ksu_unknown      (0x3)
 567
 568 #define status_IE        (1 <<  0)      /* Interrupt enable */
 569 #define status_EXL       (1 <<  1)      /* Exception level */
 570 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 571 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 572 #define status_SR        (1 << 20)      /* soft reset or NMI */
 573 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 574 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 575 #define status_ERL       (1 <<  2)      /* Error level */
 576 #define status_RP        (1 << 27)      /* Reduced Power mode */
 577
 578 #define cause_BD        ((unsigned)1 << 31)     /* Exception in branch delay slot */
 579
 580 /* NOTE: We keep the following status flags as bit values (1 for true,
 581    0 for false). This allows them to be used in binary boolean
 582    operations without worrying about what exactly the non-zero true
 583    value is. */
 584
 585 /* UserMode */
 586 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 587
 588 /* BigEndianMem */
 589 /* Hardware configuration. Affects endianness of LoadMemory and
 590    StoreMemory and the endianness of Kernel and Supervisor mode
 591    execution. The value is 0 for little-endian; 1 for big-endian. */
 592 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 593 /*(state & simBE) ? 1 : 0)*/
 594
 595 /* ReverseEndian */
 596 /* This mode is selected if in User mode with the RE bit being set in
 597    SR (Status Register). It reverses the endianness of load and store
 598    instructions. */
 599 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 600
 601 /* BigEndianCPU */
 602 /* The endianness for load and store instructions (0=little;1=big). In
 603    User mode this endianness may be switched by setting the state_RE
 604    bit in the SR register. Thus, BigEndianCPU may be computed as
 605    (BigEndianMem EOR ReverseEndian). */
 606 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 607
 608
 609
 610 /* Exceptions: */
 611
 612 /* NOTE: These numbers depend on the processor architecture being
 613    simulated: */
 614 #define Interrupt               (0)
 615 #define TLBModification         (1)
 616 #define TLBLoad                 (2)
 617 #define TLBStore                (3)
 618 #define AddressLoad             (4)
 619 #define AddressStore            (5)
 620 #define InstructionFetch        (6)
 621 #define DataReference           (7)
 622 #define SystemCall              (8)
 623 #define BreakPoint              (9)
 624 #define ReservedInstruction     (10)
 625 #define CoProcessorUnusable     (11)
 626 #define IntegerOverflow         (12)    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 627 #define Trap                    (13)
 628 #define FPE                     (15)
 629 #define DebugBreakPoint         (16)
 630 #define Watch                   (23)
 631
 632 /* The following exception code is actually private to the simulator
 633    world. It is *NOT* a processor feature, and is used to signal
 634    run-time errors in the simulator. */
 635 #define SimulatorFault      (0xFFFFFFFF)
 636
 637 void signal_exception (SIM_DESC sd, address_word cia, int exception, ...);
 638 #define SignalException(exc,instruction)     signal_exception (sd, cia, (exc), (instruction))
 639 #define SignalExceptionInterrupt()           signal_exception (sd, NULL_CIA, Interrupt)
 640 #define SignalExceptionInstructionFetch()    signal_exception (sd, cia, InstructionFetch)
 641 #define SignalExceptionAddressStore()        signal_exception (sd, cia, AddressStore)
 642 #define SignalExceptionAddressLoad()         signal_exception (sd, cia, AddressLoad)
 643 #define SignalExceptionSimulatorFault(buf)   signal_exception (sd, cia, SimulatorFault, buf)
 644 #define SignalExceptionFPE()                 signal_exception (sd, cia, FPE)
 645 #define SignalExceptionIntegerOverflow()     signal_exception (sd, cia, IntegerOverflow)
 646 #define SignalExceptionCoProcessorUnusable() signal_exception (sd, cia, CoProcessorUnusable)
 647
 648
 649 /* Co-processor accesses */
 650
 651 void cop_lw  PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 652 void cop_ld  PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 653 unsigned int cop_sw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
 654 uword64 cop_sd PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
 655
 656 #define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,cia,coproc_num,coproc_reg,memword)
 657 #define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,cia,coproc_num,coproc_reg,memword)
 658 #define COP_SW(coproc_num,coproc_reg) cop_sw(sd,cia,coproc_num,coproc_reg)
 659 #define COP_SD(coproc_num,coproc_reg) cop_sd(sd,cia,coproc_num,coproc_reg)
 660
 661 void decode_coproc PARAMS ((SIM_DESC sd, address_word cia, unsigned int instruction));
 662 #define DecodeCoproc(instruction) decode_coproc(sd, cia, (instruction))
 663
 664
 665
 666 /* Memory accesses */
 667
 668 /* The following are generic to all versions of the MIPS architecture
 669    to date: */
 670
 671 /* Memory Access Types (for CCA): */
 672 #define Uncached                (0)
 673 #define CachedNoncoherent       (1)
 674 #define CachedCoherent          (2)
 675 #define Cached                  (3)
 676
 677 #define isINSTRUCTION   (1 == 0) /* FALSE */
 678 #define isDATA          (1 == 1) /* TRUE */
 679 #define isLOAD          (1 == 0) /* FALSE */
 680 #define isSTORE         (1 == 1) /* TRUE */
 681 #define isREAL          (1 == 0) /* FALSE */
 682 #define isRAW           (1 == 1) /* TRUE */
 683 /* The parameter HOST (isTARGET / isHOST) is ignored */
 684 #define isTARGET        (1 == 0) /* FALSE */
 685 /* #define isHOST          (1 == 1) TRUE */
 686
 687 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 688    is the number of bytes minus 1. */
 689 #define AccessLength_BYTE       (0)
 690 #define AccessLength_HALFWORD   (1)
 691 #define AccessLength_TRIPLEBYTE (2)
 692 #define AccessLength_WORD       (3)
 693 #define AccessLength_QUINTIBYTE (4)
 694 #define AccessLength_SEXTIBYTE  (5)
 695 #define AccessLength_SEPTIBYTE  (6)
 696 #define AccessLength_DOUBLEWORD (7)
 697 #define AccessLength_QUADWORD   (15)
 698
 699 int address_translation PARAMS ((SIM_DESC sd, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 700 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 701 address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
 702
 703 void load_memory PARAMS ((SIM_DESC sd, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 704 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 705 load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
 706
 707 void store_memory PARAMS ((SIM_DESC sd, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 708 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 709 store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
 710
 711 void cache_op PARAMS ((SIM_DESC sd, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 712 #define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,cia,op,pAddr,vAddr,instruction)
 713
 714 void sync_operation PARAMS ((SIM_DESC sd, address_word cia, int stype));
 715 #define SyncOperation(stype) sync_operation (sd, cia, (stype))
 716
 717 void prefetch PARAMS ((SIM_DESC sd, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 718 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
 719
 720 unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia, address_word vaddr));
 721 #define IMEM(CIA) ifetch32 (SD, (CIA), (CIA))
 722
 723 void dotrace PARAMS ((SIM_DESC sd, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 724 FILE *tracefh;
 725
 726 #endif