sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35
  36 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  37 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  38
  39 #include "sim-basics.h"
  40
  41 typedef address_word sim_cia;
  42
  43 #include "sim-base.h"
  44
  45
  46 /* Deprecated macros and types for manipulating 64bit values.  Use
  47    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  48
  49 typedef signed64 word64;
  50 typedef unsigned64 uword64;
  51
  52 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  53 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  54 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  55 #define SET64HI(t)      (((uword64)(t))<<32)
  56 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  57 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  58
  59 /* Check if a value will fit within a halfword: */
  60 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  61
  62
  63
  64 /* Floating-point operations: */
  65
  66 #include "sim-fpu.h"
  67 #include "cp1.h"
  68
  69 /* FPU registers must be one of the following types. All other values
  70    are reserved (and undefined). */
  71 typedef enum {
  72  fmt_single  = 0,
  73  fmt_double  = 1,
  74  fmt_word    = 4,
  75  fmt_long    = 5,
  76  fmt_ps      = 6,
  77  /* The following are well outside the normal acceptable format
  78     range, and are used in the register status vector. */
  79  fmt_unknown       = 0x10000000,
  80  fmt_uninterpreted = 0x20000000,
  81  fmt_uninterpreted_32 = 0x40000000,
  82  fmt_uninterpreted_64 = 0x80000000U,
  83 } FP_formats;
  84
  85 /* For paired word (pw) operations, the opcode representation is fmt_word,
  86    but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long.  */
  87 #define fmt_pw fmt_long
  88
  89 /* This should be the COC1 value at the start of the preceding
  90    instruction: */
  91 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
  92
  93 #ifdef TARGET_ENABLE_FR
  94 /* FIXME: this should be enabled for all targets, but needs testing first. */
  95 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
  96    ? ((SR & status_FR) ? 64 : 32) \
  97    : (WITH_TARGET_FLOATING_POINT_BITSIZE))
  98 #else
  99 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 100 #endif
 101
 102
 103
 104
 105
 106 /* HI/LO register accesses */
 107
 108 /* For some MIPS targets, the HI/LO registers have certain timing
 109    restrictions in that, for instance, a read of a HI register must be
 110    separated by at least three instructions from a preceeding read.
 111
 112    The struct below is used to record the last access by each of A MT,
 113    MF or other OP instruction to a HI/LO register.  See mips.igen for
 114    more details. */
 115
 116 typedef struct _hilo_access {
 117   signed64 timestamp;
 118   address_word cia;
 119 } hilo_access;
 120
 121 typedef struct _hilo_history {
 122   hilo_access mt;
 123   hilo_access mf;
 124   hilo_access op;
 125 } hilo_history;
 126
 127
 128
 129
 130 /* Integer ALU operations: */
 131
 132 #include "sim-alu.h"
 133
 134 #define ALU32_END(ANS) \
 135   if (ALU32_HAD_OVERFLOW) \
 136     SignalExceptionIntegerOverflow (); \
 137   (ANS) = (signed32) ALU32_OVERFLOW_RESULT
 138
 139
 140 #define ALU64_END(ANS) \
 141   if (ALU64_HAD_OVERFLOW) \
 142     SignalExceptionIntegerOverflow (); \
 143   (ANS) = ALU64_OVERFLOW_RESULT;
 144
 145
 146
 147
 148
 149 /* The following is probably not used for MIPS IV onwards: */
 150 /* Slots for delayed register updates. For the moment we just have a
 151    fixed number of slots (rather than a more generic, dynamic
 152    system). This keeps the simulator fast. However, we only allow
 153    for the register update to be delayed for a single instruction
 154    cycle. */
 155 #define PSLOTS (8) /* Maximum number of instruction cycles */
 156
 157 typedef struct _pending_write_queue {
 158   int in;
 159   int out;
 160   int total;
 161   int slot_delay[PSLOTS];
 162   int slot_size[PSLOTS];
 163   int slot_bit[PSLOTS];
 164   void *slot_dest[PSLOTS];
 165   unsigned64 slot_value[PSLOTS];
 166 } pending_write_queue;
 167
 168 #ifndef PENDING_TRACE
 169 #define PENDING_TRACE 0
 170 #endif
 171 #define PENDING_IN ((CPU)->pending.in)
 172 #define PENDING_OUT ((CPU)->pending.out)
 173 #define PENDING_TOTAL ((CPU)->pending.total)
 174 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 175 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
 176 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 177 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 178 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 179
 180 /* Invalidate the pending write queue, all pending writes are
 181    discarded. */
 182
 183 #define PENDING_INVALIDATE() \
 184 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 185
 186 /* Schedule a write to DEST for N cycles time.  For 64 bit
 187    destinations, schedule two writes.  For floating point registers,
 188    the caller should schedule a write to both the dest register and
 189    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 190    is updated. */
 191
 192 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 193   do {                                                                  \
 194     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 195       sim_engine_abort (SD, CPU, cia,                                   \
 196                         "PENDING_SCHED - buffer overflow\n");           \
 197     if (PENDING_TRACE)                                                  \
 198       sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",                  \
 199                       (unsigned long) cia, (unsigned long) &(DEST),     \
 200                       (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
 201                       PENDING_IN, PENDING_OUT, PENDING_TOTAL);          \
 202     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 203     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 204     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 205     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 206     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 207     PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
 208     PENDING_TOTAL += 1;                                                 \
 209   } while (0)
 210
 211 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 212 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 213
 214 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 215
 216 #define PENDING_FLUSH() abort () /* think about this one */
 217 #define PENDING_FP() abort () /* think about this one */
 218
 219 /* For backward compatibility */
 220 #define PENDING_FILL(R,VAL)                                             \
 221 do {                                                                    \
 222   if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR)                       \
 223     {                                                                   \
 224       PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1);                   \
 225       PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
 226     }                                                                   \
 227   else                                                                  \
 228     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                                \
 229 } while (0)
 230
 231
 232 enum float_operation
 233   {
 234     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 235     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 236     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 237   };
 238
 239
 240 /* The internal representation of an MDMX accumulator.
 241    Note that 24 and 48 bit accumulator elements are represented in
 242    32 or 64 bits.  Since the accumulators are 2's complement with
 243    overflow suppressed, high-order bits can be ignored in most contexts.  */
 244
 245 typedef signed32 signed24;
 246 typedef signed64 signed48;
 247
 248 typedef union {
 249   signed24  ob[8];
 250   signed48  qh[4];
 251 } MDMX_accumulator;
 252
 253
 254 /* Conventional system arguments.  */
 255 #define SIM_STATE  sim_cpu *cpu, address_word cia
 256 #define SIM_ARGS   CPU, cia
 257
 258 struct _sim_cpu {
 259
 260
 261   /* The following are internal simulator state variables: */
 262 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 263 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 264   address_word dspc;  /* delay-slot PC */
 265 #define DSPC ((CPU)->dspc)
 266
 267 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 268 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 269
 270
 271   /* State of the simulator */
 272   unsigned int state;
 273   unsigned int dsstate;
 274 #define STATE ((CPU)->state)
 275 #define DSSTATE ((CPU)->dsstate)
 276
 277 /* Flags in the "state" variable: */
 278 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 279 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 280 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 281 #define simPCOC0        (1 << 17) /* COC[1] from current */
 282 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 283 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 284 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 285 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 286 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 287
 288 #ifndef ENGINE_ISSUE_PREFIX_HOOK
 289 #define ENGINE_ISSUE_PREFIX_HOOK() \
 290   { \
 291     /* Perform any pending writes */ \
 292     PENDING_TICK(); \
 293     /* Set previous flag, depending on current: */ \
 294     if (STATE & simPCOC0) \
 295      STATE |= simPCOC1; \
 296     else \
 297      STATE &= ~simPCOC1; \
 298     /* and update the current value: */ \
 299     if (GETFCC(0)) \
 300      STATE |= simPCOC0; \
 301     else \
 302      STATE &= ~simPCOC0; \
 303   }
 304 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
 305
 306
 307 /* This is nasty, since we have to rely on matching the register
 308    numbers used by GDB. Unfortunately, depending on the MIPS target
 309    GDB uses different register numbers. We cannot just include the
 310    relevant "gdb/tm.h" link, since GDB may not be configured before
 311    the sim world, and also the GDB header file requires too much other
 312    state. */
 313
 314 #ifndef TM_MIPS_H
 315 #define LAST_EMBED_REGNUM (89)
 316 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 317
 318 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 319 #define FCRCS_REGNUM 70         /* FP control/status */
 320 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 321 #endif
 322
 323
 324 /* To keep this default simulator simple, and fast, we use a direct
 325    vector of registers. The internal simulator engine then uses
 326    manifests to access the correct slot. */
 327
 328   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 329
 330   int register_widths[NUM_REGS];
 331 #define REGISTERS       ((CPU)->registers)
 332
 333 #define GPR     (&REGISTERS[0])
 334 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 335
 336 #define LO      (REGISTERS[33])
 337 #define HI      (REGISTERS[34])
 338 #define PCIDX   37
 339 #define PC      (REGISTERS[PCIDX])
 340 #define CAUSE   (REGISTERS[36])
 341 #define SRIDX   (32)
 342 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 343 #define FCR0IDX  (71)
 344 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 345 #define FCR31IDX (70)
 346 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 347 #define FCSR    (FCR31)
 348 #define Debug   (REGISTERS[86])
 349 #define DEPC    (REGISTERS[87])
 350 #define EPC     (REGISTERS[88])
 351
 352   /* All internal state modified by signal_exception() that may need to be
 353      rolled back for passing moment-of-exception image back to gdb. */
 354   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
 355   unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
 356   int exc_suspended;
 357
 358 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
 359 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
 360 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
 361
 362   unsigned_word c0_config_reg;
 363 #define C0_CONFIG ((CPU)->c0_config_reg)
 364
 365 /* The following are pseudonyms for standard registers */
 366 #define ZERO    (REGISTERS[0])
 367 #define V0      (REGISTERS[2])
 368 #define A0      (REGISTERS[4])
 369 #define A1      (REGISTERS[5])
 370 #define A2      (REGISTERS[6])
 371 #define A3      (REGISTERS[7])
 372 #define T8IDX   24
 373 #define T8      (REGISTERS[T8IDX])
 374 #define SPIDX   29
 375 #define SP      (REGISTERS[SPIDX])
 376 #define RAIDX   31
 377 #define RA      (REGISTERS[RAIDX])
 378
 379   /* While space is allocated in the main registers arrray for some of
 380      the COP0 registers, that space isn't sufficient.  Unknown COP0
 381      registers overflow into the array below */
 382
 383 #define NR_COP0_GPR     32
 384   unsigned_word cop0_gpr[NR_COP0_GPR];
 385 #define COP0_GPR        ((CPU)->cop0_gpr)
 386 #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
 387
 388   /* While space is allocated for the floating point registers in the
 389      main registers array, they are stored separatly.  This is because
 390      their size may not necessarily match the size of either the
 391      general-purpose or system specific registers.  */
 392 #define NR_FGR    (32)
 393 #define FGR_BASE  FP0_REGNUM
 394   fp_word fgr[NR_FGR];
 395 #define FGR       ((CPU)->fgr)
 396
 397   /* Keep the current format state for each register: */
 398   FP_formats fpr_state[32];
 399 #define FPR_STATE ((CPU)->fpr_state)
 400
 401   pending_write_queue pending;
 402
 403   /* The MDMX accumulator (used only for MDMX ASE).  */
 404   MDMX_accumulator acc;
 405 #define ACC             ((CPU)->acc)
 406
 407   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 408      read-write instructions. It is set when a linked load occurs. It
 409      is tested and cleared by the conditional store. It is cleared
 410      (during other CPU operations) when a store to the location would
 411      no longer be atomic. In particular, it is cleared by exception
 412      return instructions. */
 413   int llbit;
 414 #define LLBIT ((CPU)->llbit)
 415
 416
 417 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 418    corruptions caused by using the HI or LO register too close to a
 419    following operation is spotted. See mips.igen for more details. */
 420
 421   hilo_history hi_history;
 422 #define HIHISTORY (&(CPU)->hi_history)
 423   hilo_history lo_history;
 424 #define LOHISTORY (&(CPU)->lo_history)
 425
 426 #define check_branch_bug()
 427 #define mark_branch_bug(TARGET)
 428
 429
 430
 431   sim_cpu_base base;
 432 };
 433
 434
 435 /* MIPS specific simulator watch config */
 436
 437 void watch_options_install PARAMS ((SIM_DESC sd));
 438
 439 struct swatch {
 440   sim_event *pc;
 441   sim_event *clock;
 442   sim_event *cycles;
 443 };
 444
 445
 446 /* FIXME: At present much of the simulator is still static */
 447 struct sim_state {
 448
 449   struct swatch watch;
 450
 451   sim_cpu cpu[MAX_NR_PROCESSORS];
 452 #if (WITH_SMP)
 453 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 454 #else
 455 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 456 #endif
 457
 458
 459   sim_state_base base;
 460 };
 461
 462
 463
 464 /* Status information: */
 465
 466 /* TODO : these should be the bitmasks for these bits within the
 467    status register. At the moment the following are VR4300
 468    bit-positions: */
 469 #define status_KSU_mask  (0x18)         /* mask for KSU bits */
 470 #define status_KSU_shift (3)            /* shift for field */
 471 #define ksu_kernel       (0x0)
 472 #define ksu_supervisor   (0x1)
 473 #define ksu_user         (0x2)
 474 #define ksu_unknown      (0x3)
 475
 476 #define SR_KSU           ((SR & status_KSU_mask) >> status_KSU_shift)
 477
 478 #define status_IE        (1 <<  0)      /* Interrupt enable */
 479 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 480 #define status_EXL       (1 <<  1)      /* Exception level */
 481 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 482 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 483 #define status_SR        (1 << 20)      /* soft reset or NMI */
 484 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 485 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 486 #define status_ERL       (1 <<  2)      /* Error level */
 487 #define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
 488 #define status_RP        (1 << 27)      /* Reduced Power mode */
 489
 490 /* Specializations for TX39 family */
 491 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 492 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 493 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 494 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 495 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 496 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 497 #define status_IM_mask   (0xff)         /* Interrupt mask */
 498 #define status_IM_shift  (8)
 499 #define status_NMI       (1 << 20)      /* NMI */
 500 #define status_NMI       (1 << 20)      /* NMI */
 501
 502 /* Status bits used by MIPS32/MIPS64.  */
 503 #define status_UX        (1 <<  5)      /* 64-bit user addrs */
 504 #define status_SX        (1 <<  6)      /* 64-bit supervisor addrs */
 505 #define status_KX        (1 <<  7)      /* 64-bit kernel addrs */
 506 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 507 #define status_PX        (1 << 23)      /* Enable 64 bit operations */
 508 #define status_MX        (1 << 24)      /* Enable MDMX resources */
 509 #define status_CU0       (1 << 28)      /* Coprocessor 0 usable */
 510 #define status_CU1       (1 << 29)      /* Coprocessor 1 usable */
 511 #define status_CU2       (1 << 30)      /* Coprocessor 2 usable */
 512 #define status_CU3       (1 << 31)      /* Coprocessor 3 usable */
 513 /* Bits reserved for implementations:  */
 514 #define status_SBX       (1 << 16)      /* Enable SiByte SB-1 extensions.  */
 515
 516 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 517 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
 518 #define cause_CE_mask     0x30000000    /* Coprocessor exception */
 519 #define cause_CE_shift    28
 520 #define cause_EXC2_mask   0x00070000
 521 #define cause_EXC2_shift  16
 522 #define cause_IP7         (1 << 15)     /* Interrupt pending */
 523 #define cause_SIOP        (1 << 12)     /* SIO pending */
 524 #define cause_IP3         (1 << 11)     /* Int 0 pending */
 525 #define cause_IP2         (1 << 10)     /* Int 1 pending */
 526
 527 #define cause_EXC_mask  (0x1c)          /* Exception code */
 528 #define cause_EXC_shift (2)
 529
 530 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 531 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 532 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 533 #define cause_IP_shift  (10)
 534
 535 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 536 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 537
 538
 539 /* NOTE: We keep the following status flags as bit values (1 for true,
 540    0 for false). This allows them to be used in binary boolean
 541    operations without worrying about what exactly the non-zero true
 542    value is. */
 543
 544 /* UserMode */
 545 #ifdef SUBTARGET_R3900
 546 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 547 #else
 548 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 549 #endif /* SUBTARGET_R3900 */
 550
 551 /* BigEndianMem */
 552 /* Hardware configuration. Affects endianness of LoadMemory and
 553    StoreMemory and the endianness of Kernel and Supervisor mode
 554    execution. The value is 0 for little-endian; 1 for big-endian. */
 555 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 556 /*(state & simBE) ? 1 : 0)*/
 557
 558 /* ReverseEndian */
 559 /* This mode is selected if in User mode with the RE bit being set in
 560    SR (Status Register). It reverses the endianness of load and store
 561    instructions. */
 562 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 563
 564 /* BigEndianCPU */
 565 /* The endianness for load and store instructions (0=little;1=big). In
 566    User mode this endianness may be switched by setting the state_RE
 567    bit in the SR register. Thus, BigEndianCPU may be computed as
 568    (BigEndianMem EOR ReverseEndian). */
 569 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 570
 571
 572
 573 /* Exceptions: */
 574
 575 /* NOTE: These numbers depend on the processor architecture being
 576    simulated: */
 577 enum ExceptionCause {
 578   Interrupt               = 0,
 579   TLBModification         = 1,
 580   TLBLoad                 = 2,
 581   TLBStore                = 3,
 582   AddressLoad             = 4,
 583   AddressStore            = 5,
 584   InstructionFetch        = 6,
 585   DataReference           = 7,
 586   SystemCall              = 8,
 587   BreakPoint              = 9,
 588   ReservedInstruction     = 10,
 589   CoProcessorUnusable     = 11,
 590   IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 591   Trap                    = 13,
 592   FPE                     = 15,
 593   DebugBreakPoint         = 16,    /* Impl. dep. in MIPS32/MIPS64.  */
 594   MDMX                    = 22,
 595   Watch                   = 23,
 596   MCheck                  = 24,
 597   CacheErr                = 30,
 598   NMIReset                = 31,    /* Reserved in MIPS32/MIPS64.  */
 599
 600
 601 /* The following exception code is actually private to the simulator
 602    world. It is *NOT* a processor feature, and is used to signal
 603    run-time errors in the simulator. */
 604   SimulatorFault          = 0xFFFFFFFF
 605 };
 606
 607 #define TLB_REFILL  (0)
 608 #define TLB_INVALID (1)
 609
 610
 611 /* The following break instructions are reserved for use by the
 612    simulator.  The first is used to halt the simulation.  The second
 613    is used by gdb for break-points.  NOTE: Care must be taken, since
 614    this value may be used in later revisions of the MIPS ISA. */
 615 #define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
 616
 617 #define HALT_INSTRUCTION        (0x03ff000d)
 618 #define HALT_INSTRUCTION2       (0x0000ffcd)
 619
 620
 621 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
 622 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
 623
 624
 625
 626 void interrupt_event (SIM_DESC sd, void *data);
 627
 628 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 629 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 630 #define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
 631 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 632 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 633 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 634 #define SignalExceptionDataReference()       signal_exception (SD, CPU, cia, DataReference)
 635 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 636 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 637 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 638 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
 639 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
 640 #define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
 641 #define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
 642 #define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
 643 #define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
 644 #define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
 645 #define SignalExceptionMDMX()                signal_exception (SD, CPU, cia, MDMX)
 646 #define SignalExceptionWatch()               signal_exception (SD, CPU, cia, Watch)
 647 #define SignalExceptionMCheck()              signal_exception (SD, CPU, cia, MCheck)
 648 #define SignalExceptionCacheErr()            signal_exception (SD, CPU, cia, CacheErr)
 649
 650 /* Co-processor accesses */
 651
 652 /* XXX FIXME: For now, assume that FPU (cp1) is always usable.  */
 653 #define COP_Usable(coproc_num)          (coproc_num == 1)
 654
 655 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 656 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 657 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 658 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 659
 660 #define COP_LW(coproc_num,coproc_reg,memword) \
 661 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 662 #define COP_LD(coproc_num,coproc_reg,memword) \
 663 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 664 #define COP_SW(coproc_num,coproc_reg) \
 665 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 666 #define COP_SD(coproc_num,coproc_reg) \
 667 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 668
 669
 670 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
 671 #define DecodeCoproc(instruction) \
 672 decode_coproc (SD, CPU, cia, (instruction))
 673
 674 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
 675
 676
 677 /* FPR access.  */
 678 unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
 679 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
 680 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
 681 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
 682 unsigned64 ps_lower (SIM_STATE, unsigned64 op);
 683 #define PSLower(op) ps_lower (SIM_ARGS, op)
 684 unsigned64 ps_upper (SIM_STATE, unsigned64 op);
 685 #define PSUpper(op) ps_upper (SIM_ARGS, op)
 686 unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
 687 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
 688
 689
 690 /* FCR access.  */
 691 unsigned_word value_fcr (SIM_STATE, int fcr);
 692 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
 693 void store_fcr (SIM_STATE, int fcr, unsigned_word value);
 694 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
 695 void test_fcsr (SIM_STATE);
 696 #define TestFCSR() test_fcsr (SIM_ARGS)
 697
 698
 699 /* FPU operations.  */
 700 void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
 701 #define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
 702 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
 703 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
 704 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
 705 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
 706 unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 707 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
 708 unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 709 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
 710 unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 711 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
 712 unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 713 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
 714 unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
 715 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
 716 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
 717 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
 718 unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
 719 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
 720 unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
 721                     unsigned64 op3, FP_formats fmt);
 722 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
 723 unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
 724                     unsigned64 op3, FP_formats fmt);
 725 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
 726 unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
 727                      unsigned64 op3, FP_formats fmt);
 728 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
 729 unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
 730                      unsigned64 op3, FP_formats fmt);
 731 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
 732 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
 733 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
 734 unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
 735                        FP_formats to);
 736 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
 737
 738
 739 /* MIPS-3D ASE operations.  */
 740 #define CompareAbs(op1,op2,fmt,cond,cc) \
 741 fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
 742 unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 743 #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
 744 unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 745 #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
 746 unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
 747 #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
 748 unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 749 #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
 750 unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
 751 #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
 752 unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 753 #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
 754
 755
 756 /* MDMX access.  */
 757
 758 typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */
 759 #define ob_fmtsel(sel) (((sel)<<1)|0x0)
 760 #define qh_fmtsel(sel) (((sel)<<2)|0x1)
 761
 762 #define fmt_mdmx fmt_uninterpreted
 763
 764 #define MX_VECT_AND  (0)
 765 #define MX_VECT_NOR  (1)
 766 #define MX_VECT_OR   (2)
 767 #define MX_VECT_XOR  (3)
 768 #define MX_VECT_SLL  (4)
 769 #define MX_VECT_SRL  (5)
 770 #define MX_VECT_ADD  (6)
 771 #define MX_VECT_SUB  (7)
 772 #define MX_VECT_MIN  (8)
 773 #define MX_VECT_MAX  (9)
 774 #define MX_VECT_MUL  (10)
 775 #define MX_VECT_MSGN (11)
 776 #define MX_VECT_SRA  (12)
 777 #define MX_VECT_ABSD (13)               /* SB-1 only.  */
 778 #define MX_VECT_AVG  (14)               /* SB-1 only.  */
 779
 780 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 781 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
 782 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
 783 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
 784 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
 785 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
 786 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
 787 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
 788 #define MX_Or(op1,vt,fmtsel)  mdmx_cpr_op(SIM_ARGS, MX_VECT_OR,  op1, vt, fmtsel)
 789 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
 790 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
 791 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
 792 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
 793 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
 794 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
 795 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
 796
 797 #define MX_C_EQ  0x1
 798 #define MX_C_LT  0x4
 799
 800 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 801 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
 802
 803 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 804 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
 805
 806 #define MX_VECT_ADDA  (0)
 807 #define MX_VECT_ADDL  (1)
 808 #define MX_VECT_MULA  (2)
 809 #define MX_VECT_MULL  (3)
 810 #define MX_VECT_MULS  (4)
 811 #define MX_VECT_MULSL (5)
 812 #define MX_VECT_SUBA  (6)
 813 #define MX_VECT_SUBL  (7)
 814 #define MX_VECT_ABSDA (8)               /* SB-1 only.  */
 815
 816 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 817 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
 818 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
 819 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
 820 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
 821 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
 822 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
 823 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
 824 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
 825 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
 826
 827 #define MX_FMT_OB   (0)
 828 #define MX_FMT_QH   (1)
 829
 830 /* The following codes chosen to indicate the units of shift.  */
 831 #define MX_RAC_L    (0)
 832 #define MX_RAC_M    (1)
 833 #define MX_RAC_H    (2)
 834
 835 unsigned64 mdmx_rac_op (SIM_STATE, int, int);
 836 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
 837
 838 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
 839 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
 840 void mdmx_wach (SIM_STATE, int, unsigned64);
 841 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
 842
 843 #define MX_RND_AS   (0)
 844 #define MX_RND_AU   (1)
 845 #define MX_RND_ES   (2)
 846 #define MX_RND_EU   (3)
 847 #define MX_RND_ZS   (4)
 848 #define MX_RND_ZU   (5)
 849
 850 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
 851 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
 852 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
 853 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
 854 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
 855 #define MX_RZS(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
 856 #define MX_RZU(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
 857
 858 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
 859 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
 860
 861
 862
 863 /* Memory accesses */
 864
 865 /* The following are generic to all versions of the MIPS architecture
 866    to date: */
 867
 868 /* Memory Access Types (for CCA): */
 869 #define Uncached                (0)
 870 #define CachedNoncoherent       (1)
 871 #define CachedCoherent          (2)
 872 #define Cached                  (3)
 873
 874 #define isINSTRUCTION   (1 == 0) /* FALSE */
 875 #define isDATA          (1 == 1) /* TRUE */
 876 #define isLOAD          (1 == 0) /* FALSE */
 877 #define isSTORE         (1 == 1) /* TRUE */
 878 #define isREAL          (1 == 0) /* FALSE */
 879 #define isRAW           (1 == 1) /* TRUE */
 880 /* The parameter HOST (isTARGET / isHOST) is ignored */
 881 #define isTARGET        (1 == 0) /* FALSE */
 882 /* #define isHOST          (1 == 1) TRUE */
 883
 884 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 885    is the number of bytes minus 1. */
 886 #define AccessLength_BYTE       (0)
 887 #define AccessLength_HALFWORD   (1)
 888 #define AccessLength_TRIPLEBYTE (2)
 889 #define AccessLength_WORD       (3)
 890 #define AccessLength_QUINTIBYTE (4)
 891 #define AccessLength_SEXTIBYTE  (5)
 892 #define AccessLength_SEPTIBYTE  (6)
 893 #define AccessLength_DOUBLEWORD (7)
 894 #define AccessLength_QUADWORD   (15)
 895
 896 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 897                     ? AccessLength_DOUBLEWORD /*7*/ \
 898                     : AccessLength_WORD /*3*/)
 899 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 900
 901
 902 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 903 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 904 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 905
 906 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 907 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 908 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 909
 910 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 911 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 912 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 913
 914 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 915 #define CacheOp(op,pAddr,vAddr,instruction) \
 916 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 917
 918 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
 919 #define SyncOperation(stype) \
 920 sync_operation (SD, CPU, cia, (stype))
 921
 922 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 923 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 924 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 925
 926 void unpredictable_action (sim_cpu *cpu, address_word cia);
 927 #define NotWordValue(val)       not_word_value (SD_, (val))
 928 #define Unpredictable()         unpredictable (SD_)
 929 #define UnpredictableResult()   /* For now, do nothing.  */
 930
 931 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 932 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 933 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 934 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
 935 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
 936
 937 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 938 extern FILE *tracefh;
 939
 940 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 941 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 942
 943 char* pr_addr PARAMS ((SIM_ADDR addr));
 944 char* pr_uword64 PARAMS ((uword64 addr));
 945
 946
 947 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
 948
 949 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 950 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 951 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 952
 953
 954 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 955 #include "sim-main.c"
 956 #endif
 957
 958 #endif