sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 #if (WITH_IGEN)
  40 /* Get the number of instructions.  FIXME: must be a more elegant way
  41    of doing this.  */
  42 #include "itable.h"
  43 #define MAX_INSNS (nr_itable_entries)
  44 #define INSN_NAME(i) itable[(i)].name
  45 #endif
  46
  47 #include "sim-base.h"
  48
  49
  50 /* Depreciated macros and types for manipulating 64bit values.  Use
  51    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  52
  53 typedef signed64 word64;
  54 typedef unsigned64 uword64;
  55
  56 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  57 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  58 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  59 #define SET64HI(t)      (((uword64)(t))<<32)
  60 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  61 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  62
  63 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  64    assume the HI32bits of the operand are zero, so we must perform a
  65    mask to ensure we can use the simple subtraction to sign-extend. */
  66 #define SIGNEXTEND(e,b) \
  67  ((unsigned_word) \
  68   (((e) & ((uword64) 1 << ((b) - 1))) \
  69    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  70    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  71
  72 /* Check if a value will fit within a halfword: */
  73 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  74
  75 /* windows always looses */
  76 #include <signal.h>
  77 #ifndef SIGBUS
  78 #define SIGBUS SIGSEGV
  79 #endif
  80 #ifdef _WIN32
  81 #define SIGTRAP 5
  82 #define SIGQUIT 3
  83 #endif
  84
  85
  86
  87 /* Floating-point operations: */
  88
  89 /* FPU registers must be one of the following types. All other values
  90    are reserved (and undefined). */
  91 typedef enum {
  92  fmt_single  = 0,
  93  fmt_double  = 1,
  94  fmt_word    = 4,
  95  fmt_long    = 5,
  96  /* The following are well outside the normal acceptable format
  97     range, and are used in the register status vector. */
  98  fmt_unknown       = 0x10000000,
  99  fmt_uninterpreted = 0x20000000,
 100 } FP_formats;
 101
 102 unsigned64 value_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats));
 103 #define ValueFPR(FPR,FMT) value_fpr (sd, cia, (FPR), (FMT))
 104
 105 void store_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
 106 #define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, cia, (FPR), (FMT), (VALUE))
 107
 108 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
 109 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 110 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 111 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 112 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 113 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 114 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 115 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 116 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 117 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 118 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 119 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 120 unsigned64 convert PARAMS ((SIM_DESC sd, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 121 #define Convert(rm,op,from,to) convert(sd,cia,rm,op,from,to)
 122
 123 /* Macro to update FPSR condition-code field. This is complicated by
 124    the fact that there is a hole in the index range of the bits within
 125    the FCSR register. Also, the number of bits visible depends on the
 126    MIPS ISA version being supported. */
 127
 128 #define SETFCC(cc,v) {\
 129   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 130   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 131 }
 132 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
 133
 134 /* This should be the COC1 value at the start of the preceding
 135    instruction: */
 136 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 137
 138 #if 1
 139 #define SizeFGR() (WITH_TARGET_WORD_BITSIZE)
 140 #else
 141 /* They depend on the CPU being simulated */
 142 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 143 #endif
 144
 145 /* Standard FCRS bits: */
 146 #define IR (0) /* Inexact Result */
 147 #define UF (1) /* UnderFlow */
 148 #define OF (2) /* OverFlow */
 149 #define DZ (3) /* Division by Zero */
 150 #define IO (4) /* Invalid Operation */
 151 #define UO (5) /* Unimplemented Operation */
 152
 153 /* Get masks for individual flags: */
 154 #if 1 /* SAFE version */
 155 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 156 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 157 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 158 #else
 159 #define FP_FLAGS(b)  (1 << ((b) + 2))
 160 #define FP_ENABLE(b) (1 << ((b) + 7))
 161 #define FP_CAUSE(b)  (1 << ((b) + 12))
 162 #endif
 163
 164 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 165
 166 #define FP_MASK_RM    (0x3)
 167 #define FP_SH_RM      (0)
 168 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 169 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 170 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 171 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 172 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 173
 174
 175
 176 /* Integer ALU operations: */
 177
 178 #include "sim-alu.h"
 179
 180 #define ALU32_END(ANS) \
 181   if (ALU32_HAD_OVERFLOW) \
 182     SignalExceptionIntegerOverflow (); \
 183   (ANS) = ALU32_OVERFLOW_RESULT
 184
 185
 186 #define ALU64_END(ANS) \
 187   if (ALU64_HAD_OVERFLOW) \
 188     SignalExceptionIntegerOverflow (); \
 189   (ANS) = ALU64_OVERFLOW_RESULT;
 190
 191 /* start-sanitize-r5900 */
 192
 193 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 194 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 195 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 196 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 197
 198 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 199 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 200 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 201 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 202
 203 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 204    T  - type of the sub part
 205    TC - # of T's in the mips part of the "register"
 206    I  - index (from 0) of desired sub part
 207    A  - low part of "register"
 208    A1 - high part of register
 209 */
 210 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 211 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 212    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 213       ? ((TC) - 1 - (I) % (TC)) \
 214       : ((I) % (TC)) \
 215       ) \
 216    ) \
 217  )
 218
 219 /*
 220 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 221             where <type> has two letters:
 222                   1 is S=signed or U=unsigned
 223                   2 is B=byte H=halfword W=word D=doubleword
 224 */
 225
 226 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 227 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 228 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 229 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 230
 231 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 232 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 233 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 234 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 235
 236 #define GPR_SB(R,I) SUB_REG_SB(&REGISTERS[R], &REGISTERS1[R], I)
 237 #define GPR_SH(R,I) SUB_REG_SH(&REGISTERS[R], &REGISTERS1[R], I)
 238 #define GPR_SW(R,I) SUB_REG_SW(&REGISTERS[R], &REGISTERS1[R], I)
 239 #define GPR_SD(R,I) SUB_REG_SD(&REGISTERS[R], &REGISTERS1[R], I)
 240
 241 #define GPR_UB(R,I) SUB_REG_UB(&REGISTERS[R], &REGISTERS1[R], I)
 242 #define GPR_UH(R,I) SUB_REG_UH(&REGISTERS[R], &REGISTERS1[R], I)
 243 #define GPR_UW(R,I) SUB_REG_UW(&REGISTERS[R], &REGISTERS1[R], I)
 244 #define GPR_UD(R,I) SUB_REG_UD(&REGISTERS[R], &REGISTERS1[R], I)
 245
 246
 247 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 248 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 249 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 250 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 251
 252 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 253 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 254 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 255 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 256
 257 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 258 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 259 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 260 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 261
 262 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 263 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 264 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 265 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 266
 267
 268
 269 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 270 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 271 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 272 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 273
 274 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 275 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 276 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 277 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 278
 279 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 280 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 281 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 282 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 283
 284 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 285 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 286 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 287 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 288
 289 /* end-sanitize-r5900 */
 290
 291
 292
 293
 294 struct _sim_cpu {
 295
 296
 297   /* The following are internal simulator state variables: */
 298 #define CPU_CIA(CPU) (PC)
 299   address_word ipc; /* internal Instruction PC */
 300   address_word dspc;  /* delay-slot PC */
 301 #define IPC ((STATE_CPU (sd,0))->ipc)
 302 #define DSPC ((STATE_CPU (sd,0))->dspc)
 303
 304   /* Issue a delay slot instruction immediatly by re-calling
 305      idecode_issue */
 306 #define DELAY_SLOT(TARGET) \
 307   do { \
 308     address_word target = (TARGET); \
 309     instruction_word delay_insn; \
 310     sim_events_slip (sd, 1); \
 311     CIA = CIA + 4; \
 312     STATE |= simDELAYSLOT; \
 313     delay_insn = IMEM (CIA); \
 314     idecode_issue (sd, delay_insn, (CIA)); \
 315     STATE &= ~simDELAYSLOT; \
 316     NIA = target; \
 317   } while (0)
 318 #define NULLIFY_NEXT_INSTRUCTION() \
 319   do { \
 320     sim_events_slip (sd, 1); \
 321     NIA = CIA + 8; \
 322   } while (0)
 323
 324
 325
 326   /* State of the simulator */
 327   unsigned int state;
 328   unsigned int dsstate;
 329 #define STATE ((STATE_CPU (sd,0))->state)
 330 #define DSSTATE ((STATE_CPU (sd,0))->dsstate)
 331
 332 /* Flags in the "state" variable: */
 333 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 334 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 335 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 336 #define simPCOC0        (1 << 17) /* COC[1] from current */
 337 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 338 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 339 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 340 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 341 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 342
 343
 344
 345
 346 /* This is nasty, since we have to rely on matching the register
 347    numbers used by GDB. Unfortunately, depending on the MIPS target
 348    GDB uses different register numbers. We cannot just include the
 349    relevant "gdb/tm.h" link, since GDB may not be configured before
 350    the sim world, and also the GDB header file requires too much other
 351    state. */
 352
 353 #ifndef TM_MIPS_H
 354 #define LAST_EMBED_REGNUM (89)
 355 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 356 /* start-sanitize-r5900 */
 357 #undef NUM_REGS
 358 #define NUM_REGS (128)
 359 /* end-sanitize-r5900 */
 360 #endif
 361
 362 /* To keep this default simulator simple, and fast, we use a direct
 363    vector of registers. The internal simulator engine then uses
 364    manifests to access the correct slot. */
 365
 366   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 367   int register_widths[NUM_REGS];
 368 #define REGISTERS       ((STATE_CPU (sd,0))->registers)
 369
 370 #define GPR     (&REGISTERS[0])
 371 #define FGRIDX  (38)
 372 #define FGR     (&REGISTERS[FGRIDX])
 373 #define LO      (REGISTERS[33])
 374 #define HI      (REGISTERS[34])
 375 #define PC      (REGISTERS[37])
 376 #define CAUSE   (REGISTERS[36])
 377 #define SRIDX   (32)
 378 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 379 #define FCR0IDX  (71)
 380 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 381 #define FCR31IDX (70)
 382 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 383 #define FCSR    (FCR31)
 384 #define Debug   (REGISTERS[86])
 385 #define DEPC    (REGISTERS[87])
 386 #define EPC     (REGISTERS[88])
 387 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 388
 389 /* The following are pseudonyms for standard registers */
 390 #define ZERO    (REGISTERS[0])
 391 #define V0      (REGISTERS[2])
 392 #define A0      (REGISTERS[4])
 393 #define A1      (REGISTERS[5])
 394 #define A2      (REGISTERS[6])
 395 #define A3      (REGISTERS[7])
 396 #define SP      (REGISTERS[29])
 397 #define RA      (REGISTERS[31])
 398
 399   /* Keep the current format state for each register: */
 400   FP_formats fpr_state[32];
 401 #define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state)
 402
 403
 404   /* Slots for delayed register updates. For the moment we just have a
 405      fixed number of slots (rather than a more generic, dynamic
 406      system). This keeps the simulator fast. However, we only allow
 407      for the register update to be delayed for a single instruction
 408      cycle. */
 409 #define PSLOTS (5) /* Maximum number of instruction cycles */
 410   int pending_in;
 411   int pending_out;
 412   int pending_total;
 413   int pending_slot_count[PSLOTS];
 414   int pending_slot_reg[PSLOTS];
 415   unsigned_word pending_slot_value[PSLOTS];
 416 #define PENDING_IN ((STATE_CPU (sd, 0))->pending_in)
 417 #define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out)
 418 #define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total)
 419 #define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count)
 420 #define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg)
 421 #define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value)
 422
 423   /* The following are not used for MIPS IV onwards: */
 424 #define PENDING_FILL(r,v) {\
 425 /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
 426                             if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
 427                              sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
 428                             PENDING_SLOT_COUNT[PENDING_IN] = 2;\
 429                             PENDING_SLOT_REG[PENDING_IN] = (r);\
 430                             PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
 431 /*printf("DBG: FILL        reg %d value = 0x%s\n",(r),pr_addr(v));*/\
 432                             PENDING_TOTAL++;\
 433                             PENDING_IN++;\
 434                             if (PENDING_IN == PSLOTS)\
 435                              PENDING_IN = 0;\
 436 /*printf("DBG: FILL AFTER  pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
 437                           }
 438
 439
 440   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 441      read-write instructions. It is set when a linked load occurs. It
 442      is tested and cleared by the conditional store. It is cleared
 443      (during other CPU operations) when a store to the location would
 444      no longer be atomic. In particular, it is cleared by exception
 445      return instructions. */
 446   int llbit;
 447 #define LLBIT ((STATE_CPU (sd, 0))->llbit)
 448
 449
 450 /* The HIACCESS and LOACCESS counts are used to ensure that
 451    corruptions caused by using the HI or LO register to close to a
 452    following operation are spotted. */
 453
 454   int hiaccess;
 455   int loaccess;
 456 #define HIACCESS ((STATE_CPU (sd, 0))->hiaccess)
 457 #define LOACCESS ((STATE_CPU (sd, 0))->loaccess)
 458   /* start-sanitize-r5900 */
 459   int hi1access;
 460   int lo1access;
 461 #define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access)
 462 #define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access)
 463   /* end-sanitize-r5900 */
 464 #if 1
 465   /* The 4300 and a few other processors have interlocks on hi/lo
 466      register reads, and hence do not have this problem.  To avoid
 467      spurious warnings, we just disable this always.  */
 468 #define CHECKHILO(s)
 469 #else
 470   unsigned_word HLPC;
 471   /* If either of the preceding two instructions have accessed the HI
 472      or LO registers, then the values they see should be
 473      undefined. However, to keep the simulator world simple, we just
 474      let them use the value read and raise a warning to notify the
 475      user: */
 476 #define CHECKHILO(s) {\
 477   if ((HIACCESS != 0) || (LOACCESS != 0)) \
 478     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 479 }
 480   /* start-sanitize-r5900 */
 481 #undef CHECKHILO
 482 #define CHECKHILO(s) {\
 483   if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
 484     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 485 }
 486   /* end-sanitize-r5900 */
 487 #endif
 488
 489
 490   /* start-sanitize-r5900 */
 491   /* The R5900 has 128 bit registers, but the hi 64 bits are only
 492      touched by multimedia (MMI) instructions.  The normal mips
 493      instructions just use the lower 64 bits.  To avoid changing the
 494      older parts of the simulator to handle this weirdness, the high
 495      64 bits of each register are kept in a separate array
 496      (registers1).  The high 64 bits of any register are by convention
 497      refered by adding a '1' to the end of the normal register's name.
 498      So LO still refers to the low 64 bits of the LO register, LO1
 499      refers to the high 64 bits of that same register.  */
 500
 501   signed_word registers1[LAST_EMBED_REGNUM + 1];
 502 #define REGISTERS1 ((STATE_CPU (sd, 0))->registers1)
 503 #define GPR1     (&REGISTERS1[0])
 504 #define LO1      (REGISTERS1[32])
 505 #define HI1      (REGISTERS1[33])
 506 #define REGISTER_SA     (124)
 507
 508   unsigned_word sa;        /* the shift amount register */
 509 #define SA ((STATE_CPU (sd, 0))->sa)
 510
 511   /* end-sanitize-r5900 */
 512   /* start-sanitize-vr5400 */
 513
 514   /* end-sanitize-vr5400 */
 515
 516
 517
 518   sim_cpu_base base;
 519 };
 520
 521
 522 /* MIPS specific simulator watch config */
 523
 524 void watch_options_install PARAMS ((SIM_DESC sd));
 525
 526 struct swatch {
 527   sim_event *pc;
 528   sim_event *clock;
 529   sim_event *cycles;
 530 };
 531
 532
 533 /* FIXME: At present much of the simulator is still static */
 534 struct sim_state {
 535
 536   struct swatch watch;
 537
 538   sim_cpu cpu[1];
 539 #if (WITH_SMP)
 540 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 541 #else
 542 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 543 #endif
 544
 545   sim_state_base base;
 546 };
 547
 548
 549
 550 /* Status information: */
 551
 552 /* TODO : these should be the bitmasks for these bits within the
 553    status register. At the moment the following are VR4300
 554    bit-positions: */
 555 #define status_KSU_mask  (0x3)          /* mask for KSU bits */
 556 #define status_KSU_shift (3)            /* shift for field */
 557 #define ksu_kernel       (0x0)
 558 #define ksu_supervisor   (0x1)
 559 #define ksu_user         (0x2)
 560 #define ksu_unknown      (0x3)
 561
 562 #define status_IE        (1 <<  0)      /* Interrupt enable */
 563 #define status_EXL       (1 <<  1)      /* Exception level */
 564 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 565 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 566 #define status_SR        (1 << 20)      /* soft reset or NMI */
 567 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 568 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 569 #define status_ERL       (1 <<  2)      /* Error level */
 570 #define status_RP        (1 << 27)      /* Reduced Power mode */
 571
 572 #define cause_BD        ((unsigned)1 << 31)     /* Exception in branch delay slot */
 573
 574 /* NOTE: We keep the following status flags as bit values (1 for true,
 575    0 for false). This allows them to be used in binary boolean
 576    operations without worrying about what exactly the non-zero true
 577    value is. */
 578
 579 /* UserMode */
 580 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 581
 582 /* BigEndianMem */
 583 /* Hardware configuration. Affects endianness of LoadMemory and
 584    StoreMemory and the endianness of Kernel and Supervisor mode
 585    execution. The value is 0 for little-endian; 1 for big-endian. */
 586 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 587 /*(state & simBE) ? 1 : 0)*/
 588
 589 /* ReverseEndian */
 590 /* This mode is selected if in User mode with the RE bit being set in
 591    SR (Status Register). It reverses the endianness of load and store
 592    instructions. */
 593 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 594
 595 /* BigEndianCPU */
 596 /* The endianness for load and store instructions (0=little;1=big). In
 597    User mode this endianness may be switched by setting the state_RE
 598    bit in the SR register. Thus, BigEndianCPU may be computed as
 599    (BigEndianMem EOR ReverseEndian). */
 600 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 601
 602
 603
 604 /* Exceptions: */
 605
 606 /* NOTE: These numbers depend on the processor architecture being
 607    simulated: */
 608 #define Interrupt               (0)
 609 #define TLBModification         (1)
 610 #define TLBLoad                 (2)
 611 #define TLBStore                (3)
 612 #define AddressLoad             (4)
 613 #define AddressStore            (5)
 614 #define InstructionFetch        (6)
 615 #define DataReference           (7)
 616 #define SystemCall              (8)
 617 #define BreakPoint              (9)
 618 #define ReservedInstruction     (10)
 619 #define CoProcessorUnusable     (11)
 620 #define IntegerOverflow         (12)    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 621 #define Trap                    (13)
 622 #define FPE                     (15)
 623 #define DebugBreakPoint         (16)
 624 #define Watch                   (23)
 625
 626 /* The following exception code is actually private to the simulator
 627    world. It is *NOT* a processor feature, and is used to signal
 628    run-time errors in the simulator. */
 629 #define SimulatorFault      (0xFFFFFFFF)
 630
 631 void signal_exception (SIM_DESC sd, address_word cia, int exception, ...);
 632 #define SignalException(exc,instruction)     signal_exception (sd, cia, (exc), (instruction))
 633 #define SignalExceptionInterrupt()           signal_exception (sd, NULL_CIA, Interrupt)
 634 #define SignalExceptionInstructionFetch()    signal_exception (sd, cia, InstructionFetch)
 635 #define SignalExceptionAddressStore()        signal_exception (sd, cia, AddressStore)
 636 #define SignalExceptionAddressLoad()         signal_exception (sd, cia, AddressLoad)
 637 #define SignalExceptionSimulatorFault(buf)   signal_exception (sd, cia, SimulatorFault, buf)
 638 #define SignalExceptionFPE()                 signal_exception (sd, cia, FPE)
 639 #define SignalExceptionIntegerOverflow()     signal_exception (sd, cia, IntegerOverflow)
 640 #define SignalExceptionCoProcessorUnusable() signal_exception (sd, cia, CoProcessorUnusable)
 641
 642
 643 /* Co-processor accesses */
 644
 645 void cop_lw  PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 646 void cop_ld  PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 647 unsigned int cop_sw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
 648 uword64 cop_sd PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
 649
 650 #define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,cia,coproc_num,coproc_reg,memword)
 651 #define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,cia,coproc_num,coproc_reg,memword)
 652 #define COP_SW(coproc_num,coproc_reg) cop_sw(sd,cia,coproc_num,coproc_reg)
 653 #define COP_SD(coproc_num,coproc_reg) cop_sd(sd,cia,coproc_num,coproc_reg)
 654
 655 void decode_coproc PARAMS ((SIM_DESC sd, address_word cia, unsigned int instruction));
 656 #define DecodeCoproc(instruction) decode_coproc(sd, cia, (instruction))
 657
 658
 659
 660 /* Memory accesses */
 661
 662 /* The following are generic to all versions of the MIPS architecture
 663    to date: */
 664
 665 /* Memory Access Types (for CCA): */
 666 #define Uncached                (0)
 667 #define CachedNoncoherent       (1)
 668 #define CachedCoherent          (2)
 669 #define Cached                  (3)
 670
 671 #define isINSTRUCTION   (1 == 0) /* FALSE */
 672 #define isDATA          (1 == 1) /* TRUE */
 673 #define isLOAD          (1 == 0) /* FALSE */
 674 #define isSTORE         (1 == 1) /* TRUE */
 675 #define isREAL          (1 == 0) /* FALSE */
 676 #define isRAW           (1 == 1) /* TRUE */
 677 /* The parameter HOST (isTARGET / isHOST) is ignored */
 678 #define isTARGET        (1 == 0) /* FALSE */
 679 /* #define isHOST          (1 == 1) TRUE */
 680
 681 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 682    is the number of bytes minus 1. */
 683 #define AccessLength_BYTE       (0)
 684 #define AccessLength_HALFWORD   (1)
 685 #define AccessLength_TRIPLEBYTE (2)
 686 #define AccessLength_WORD       (3)
 687 #define AccessLength_QUINTIBYTE (4)
 688 #define AccessLength_SEXTIBYTE  (5)
 689 #define AccessLength_SEPTIBYTE  (6)
 690 #define AccessLength_DOUBLEWORD (7)
 691 #define AccessLength_QUADWORD   (15)
 692
 693 int address_translation PARAMS ((SIM_DESC sd, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 694 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 695 address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
 696
 697 void load_memory PARAMS ((SIM_DESC sd, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 698 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 699 load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
 700
 701 void store_memory PARAMS ((SIM_DESC sd, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 702 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 703 store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
 704
 705 void cache_op PARAMS ((SIM_DESC sd, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 706 #define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,cia,op,pAddr,vAddr,instruction)
 707
 708 void sync_operation PARAMS ((SIM_DESC sd, address_word cia, int stype));
 709 #define SyncOperation(stype) sync_operation (sd, cia, (stype))
 710
 711 void prefetch PARAMS ((SIM_DESC sd, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 712 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
 713
 714 unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia, address_word vaddr));
 715 #define IMEM(CIA) ifetch32 (SD, (CIA), (CIA))
 716
 717
 718 #endif