sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 #if (WITH_IGEN)
  40 /* Get the number of instructions.  FIXME: must be a more elegant way
  41    of doing this.  */
  42 #include "itable.h"
  43 #define MAX_INSNS (nr_itable_entries)
  44 #define INSN_NAME(i) itable[(i)].name
  45 #endif
  46
  47 #include "sim-base.h"
  48
  49
  50 /* Depreciated macros and types for manipulating 64bit values.  Use
  51    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  52
  53 typedef signed64 word64;
  54 typedef unsigned64 uword64;
  55
  56 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  57 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  58 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  59 #define SET64HI(t)      (((uword64)(t))<<32)
  60 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  61 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  62
  63 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  64    assume the HI32bits of the operand are zero, so we must perform a
  65    mask to ensure we can use the simple subtraction to sign-extend. */
  66 #define SIGNEXTEND(e,b) \
  67  ((unsigned_word) \
  68   (((e) & ((uword64) 1 << ((b) - 1))) \
  69    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  70    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  71
  72 /* Check if a value will fit within a halfword: */
  73 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  74
  75
  76
  77 /* Floating-point operations: */
  78
  79 #include "sim-fpu.h"
  80
  81 /* FPU registers must be one of the following types. All other values
  82    are reserved (and undefined). */
  83 typedef enum {
  84  fmt_single  = 0,
  85  fmt_double  = 1,
  86  fmt_word    = 4,
  87  fmt_long    = 5,
  88  /* The following are well outside the normal acceptable format
  89     range, and are used in the register status vector. */
  90  fmt_unknown       = 0x10000000,
  91  fmt_uninterpreted = 0x20000000,
  92  fmt_uninterpreted_32 = 0x40000000,
  93  fmt_uninterpreted_64 = 0x80000000,
  94 } FP_formats;
  95
  96 unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
  97 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
  98
  99 void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
 100 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
 101
 102 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
 103 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 104 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 105 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 106 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 107 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 108 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 109 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 110 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 111 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 112 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 113 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 114 unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 115 unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 116 unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 117 #define Convert(rm,op,from,to) \
 118 convert (SD, CPU, cia, rm, op, from, to)
 119
 120 /* Macro to update FPSR condition-code field. This is complicated by
 121    the fact that there is a hole in the index range of the bits within
 122    the FCSR register. Also, the number of bits visible depends on the
 123    MIPS ISA version being supported. */
 124
 125 #define SETFCC(cc,v) {\
 126   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 127   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 128 }
 129 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
 130
 131 /* This should be the COC1 value at the start of the preceding
 132    instruction: */
 133 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 134
 135 #if 1
 136 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 137 #else
 138 /* They depend on the CPU being simulated */
 139 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 140 #endif
 141
 142 /* Standard FCRS bits: */
 143 #define IR (0) /* Inexact Result */
 144 #define UF (1) /* UnderFlow */
 145 #define OF (2) /* OverFlow */
 146 #define DZ (3) /* Division by Zero */
 147 #define IO (4) /* Invalid Operation */
 148 #define UO (5) /* Unimplemented Operation */
 149
 150 /* Get masks for individual flags: */
 151 #if 1 /* SAFE version */
 152 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 153 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 154 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 155 #else
 156 #define FP_FLAGS(b)  (1 << ((b) + 2))
 157 #define FP_ENABLE(b) (1 << ((b) + 7))
 158 #define FP_CAUSE(b)  (1 << ((b) + 12))
 159 #endif
 160
 161 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 162
 163 #define FP_MASK_RM    (0x3)
 164 #define FP_SH_RM      (0)
 165 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 166 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 167 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 168 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 169 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 170
 171
 172
 173 /* HI/LO register accesses */
 174
 175 /* For some MIPS targets, the HI/LO registers have certain timing
 176    restrictions in that, for instance, a read of a HI register must be
 177    separated by at least three instructions from a preceeding read.
 178
 179    The struct below is used to record the last access by each of A MT,
 180    MF or other OP instruction to a HI/LO register.  See mips.igen for
 181    more details. */
 182
 183 typedef struct _hilo_access {
 184   signed64 timestamp;
 185   address_word cia;
 186 } hilo_access;
 187
 188 typedef struct _hilo_history {
 189   hilo_access mt;
 190   hilo_access mf;
 191   hilo_access op;
 192 } hilo_history;
 193
 194
 195
 196
 197 /* Integer ALU operations: */
 198
 199 #include "sim-alu.h"
 200
 201 #define ALU32_END(ANS) \
 202   if (ALU32_HAD_OVERFLOW) \
 203     SignalExceptionIntegerOverflow (); \
 204   (ANS) = ALU32_OVERFLOW_RESULT
 205
 206
 207 #define ALU64_END(ANS) \
 208   if (ALU64_HAD_OVERFLOW) \
 209     SignalExceptionIntegerOverflow (); \
 210   (ANS) = ALU64_OVERFLOW_RESULT;
 211
 212
 213 /* start-sanitize-r5900 */
 214
 215 /* Figure 10-5 FPU Control/Status Register.
 216    Note: some of these bits are different to what is found in a
 217    standard MIPS manual. */
 218 enum {
 219   R5900_FCSR_C = BIT (23), /* OK */
 220   R5900_FCSR_I = BIT (17),
 221   R5900_FCSR_D = BIT (16),
 222   R5900_FCSR_O = BIT (15),
 223   R5900_FCSR_U = BIT (14),
 224   R5900_FCSR_CAUSE = MASK (16,14),
 225   R5900_FCSR_SI = BIT (6),
 226   R5900_FCSR_SD = BIT (5),
 227   R5900_FCSR_SO = BIT (4),
 228   R5900_FCSR_SU = BIT (3),
 229 };
 230
 231 /* Table 10-1 FP format values.
 232    Note: some of these bits are different to what is found in a
 233    standard MIPS manual. */
 234 enum {
 235   R5900_EXPMAX = 128,
 236   R5900_EXPMIN = -127,
 237   R5900_EXPBIAS = 127,
 238 };
 239
 240
 241
 242 typedef struct _sim_r5900_cpu {
 243
 244   /* The R5900 has 32 x 128bit general purpose registers.
 245      Fortunatly, the high 64 bits are only touched by multimedia (MMI)
 246      instructions.  The normal mips instructions just use the lower 64
 247      bits.  To avoid changing the older parts of the simulator to
 248      handle this weirdness, the high 64 bits of each register are kept
 249      in a separate array (registers1).  The high 64 bits of any
 250      register are by convention refered by adding a '1' to the end of
 251      the normal register's name.  So LO still refers to the low 64
 252      bits of the LO register, LO1 refers to the high 64 bits of that
 253      same register.  */
 254   signed_word gpr1[32];
 255 #define GPR1     ((CPU)->r5900.gpr1)
 256   signed_word lo1;
 257   signed_word hi1;
 258 #define LO1      ((CPU)->r5900.lo1)
 259 #define HI1      ((CPU)->r5900.hi1)
 260
 261   /* The R5900 defines a shift amount register, that controls the
 262      amount of certain shift instructions */
 263   unsigned_word sa;        /* the shift amount register */
 264 #define REGISTER_SA     (124) /* GET RID IF THIS! */
 265 #define SA ((CPU)->r5900.sa)
 266
 267   /* The R5900, in addition to the (almost) standard floating point
 268      registers, defines a 32 bit accumulator.  This is used in
 269      multiply/accumulate style instructions */
 270   fp_word acc; /* floating-point accumulator */
 271 #define ACC ((CPU)->r5900.acc)
 272
 273   /* See comments below about needing to count cycles between updating
 274      and setting HI/LO registers */
 275   hilo_history hi1_history;
 276 #define HI1HISTORY (&(CPU)->r5900.hi1_history)
 277   hilo_history lo1_history;
 278 #define LO1HISTORY (&(CPU)->r5900.lo1_history)
 279
 280 } sim_r5900_cpu;
 281
 282 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 283 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 284 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 285 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 286
 287 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 288 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 289 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 290 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 291
 292 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 293    T  - type of the sub part
 294    TC - # of T's in the mips part of the "register"
 295    I  - index (from 0) of desired sub part
 296    A  - low part of "register"
 297    A1 - high part of register
 298 */
 299 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 300 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 301    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 302       ? ((TC) - 1 - (I) % (TC)) \
 303       : ((I) % (TC)) \
 304       ) \
 305    ) \
 306  )
 307
 308 /*
 309 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 310             where <type> has two letters:
 311                   1 is S=signed or U=unsigned
 312                   2 is B=byte H=halfword W=word D=doubleword
 313 */
 314
 315 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 316 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 317 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 318 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 319
 320 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 321 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 322 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 323 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 324
 325 #define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
 326 #define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
 327 #define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
 328 #define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
 329
 330 #define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
 331 #define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
 332 #define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
 333 #define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
 334
 335
 336 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 337 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 338 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 339 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 340
 341 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 342 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 343 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 344 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 345
 346 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 347 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 348 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 349 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 350
 351 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 352 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 353 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 354 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 355
 356
 357
 358 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 359 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 360 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 361 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 362
 363 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 364 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 365 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 366 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 367
 368 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 369 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 370 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 371 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 372
 373 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 374 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 375 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 376 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 377
 378 /* end-sanitize-r5900 */
 379
 380
 381
 382 /* The following is probably not used for MIPS IV onwards: */
 383 /* Slots for delayed register updates. For the moment we just have a
 384    fixed number of slots (rather than a more generic, dynamic
 385    system). This keeps the simulator fast. However, we only allow
 386    for the register update to be delayed for a single instruction
 387    cycle. */
 388 #define PSLOTS (8) /* Maximum number of instruction cycles */
 389
 390 typedef struct _pending_write_queue {
 391   int in;
 392   int out;
 393   int total;
 394   int slot_delay[PSLOTS];
 395   int slot_size[PSLOTS];
 396   int slot_bit[PSLOTS];
 397   void *slot_dest[PSLOTS];
 398   unsigned64 slot_value[PSLOTS];
 399 } pending_write_queue;
 400
 401 #ifndef PENDING_TRACE
 402 #define PENDING_TRACE 0
 403 #endif
 404 #define PENDING_IN ((CPU)->pending.in)
 405 #define PENDING_OUT ((CPU)->pending.out)
 406 #define PENDING_TOTAL ((CPU)->pending.total)
 407 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 408 #define PENDING_SLOT_BIT ((CPU)->pending.slot_size)
 409 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 410 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 411 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 412
 413 /* Invalidate the pending write queue, all pending writes are
 414    discarded. */
 415
 416 #define PENDING_INVALIDATE() \
 417 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 418
 419 /* Schedule a write to DEST for N cycles time.  For 64 bit
 420    destinations, schedule two writes.  For floating point registers,
 421    the caller should schedule a write to both the dest register and
 422    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 423    is updated. */
 424
 425 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 426   do {                                                                  \
 427     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 428       sim_engine_abort (SD, CPU, cia,                                   \
 429                         "PENDING_SCHED - buffer overflow\n");           \
 430     if (PENDING_TRACE)                                                  \
 431       sim_io_printf (SD, "PENDING_SCHED - dest 0x%lx, val 0x%lx, pending_in %d, pending_out %d, pending_total %d\n", (unsigned long) (DEST), (unsigned long) (VAL), PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
 432     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 433     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 434     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 435     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 436     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 437   } while (0)
 438
 439 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 440 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 441
 442 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 443
 444 #define PENDING_FLUSH() abort () /* think about this one */
 445 #define PENDING_FP() abort () /* think about this one */
 446
 447 /* For backward compatibility */
 448 #define PENDING_FILL(R,VAL)                                             \
 449 {                                                                       \
 450   if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR)                           \
 451     PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 2, -1);                       \
 452   else                                                                  \
 453     PENDING_SCHED(GPR[(R)], VAL, 2, -1);                                \
 454 }
 455
 456
 457
 458 struct _sim_cpu {
 459
 460
 461   /* The following are internal simulator state variables: */
 462 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 463 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 464   address_word dspc;  /* delay-slot PC */
 465 #define DSPC ((CPU)->dspc)
 466
 467 #if !WITH_IGEN
 468   /* Issue a delay slot instruction immediatly by re-calling
 469      idecode_issue */
 470 #define DELAY_SLOT(TARGET) \
 471   do { \
 472     address_word target = (TARGET); \
 473     instruction_word delay_insn; \
 474     sim_events_slip (SD, 1); \
 475     CIA = CIA + 4; /* NOTE not mips16 */ \
 476     STATE |= simDELAYSLOT; \
 477     delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ \
 478     idecode_issue (CPU_, delay_insn, (CIA)); \
 479     STATE &= ~simDELAYSLOT; \
 480     NIA = target; \
 481   } while (0)
 482 #define NULLIFY_NEXT_INSTRUCTION() \
 483   do { \
 484     sim_events_slip (SD, 1); \
 485     dotrace (SD, CPU, tracefh, 2, NIA, 4, "load instruction"); \
 486     NIA = CIA + 8; \
 487   } while (0)
 488 #else
 489 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 490 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 491 #endif
 492
 493
 494   /* State of the simulator */
 495   unsigned int state;
 496   unsigned int dsstate;
 497 #define STATE ((CPU)->state)
 498 #define DSSTATE ((CPU)->dsstate)
 499
 500 /* Flags in the "state" variable: */
 501 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 502 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 503 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 504 #define simPCOC0        (1 << 17) /* COC[1] from current */
 505 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 506 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 507 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 508 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 509 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 510
 511 #define ENGINE_ISSUE_PREFIX_HOOK() \
 512   { \
 513     /* Perform any pending writes */ \
 514     PENDING_TICK(); \
 515     /* Set previous flag, depending on current: */ \
 516     if (STATE & simPCOC0) \
 517      STATE |= simPCOC1; \
 518     else \
 519      STATE &= ~simPCOC1; \
 520     /* and update the current value: */ \
 521     if (GETFCC(0)) \
 522      STATE |= simPCOC0; \
 523     else \
 524      STATE &= ~simPCOC0; \
 525   }
 526
 527
 528 /* This is nasty, since we have to rely on matching the register
 529    numbers used by GDB. Unfortunately, depending on the MIPS target
 530    GDB uses different register numbers. We cannot just include the
 531    relevant "gdb/tm.h" link, since GDB may not be configured before
 532    the sim world, and also the GDB header file requires too much other
 533    state. */
 534
 535 #ifndef TM_MIPS_H
 536 #define LAST_EMBED_REGNUM (89)
 537 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 538 /* start-sanitize-r5900 */
 539 #undef NUM_REGS
 540 #define NUM_REGS (128)
 541 /* end-sanitize-r5900 */
 542 #endif
 543
 544 /* start-sanitize-sky */
 545 #ifdef TARGET_SKY
 546 #ifndef TM_TXVU_H
 547
 548 /* Number of machine registers */
 549 #define NUM_VU_REGS     153
 550 #define NUM_VU_INTEGER_REGS 16
 551
 552 #define NUM_VIF_REGS    25
 553
 554 #define FIRST_VEC_REG   25
 555 #define NUM_R5900_REGS  128
 556
 557 #undef NUM_REGS
 558 #define NUM_REGS (NUM_R5900_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
 559 #endif /* no tm-txvu.h */
 560 #endif
 561 /* end-sanitize-sky */
 562
 563 /* To keep this default simulator simple, and fast, we use a direct
 564    vector of registers. The internal simulator engine then uses
 565    manifests to access the correct slot. */
 566
 567   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 568   int register_widths[NUM_REGS];
 569 #define REGISTERS       ((CPU)->registers)
 570
 571 #define GPR     (&REGISTERS[0])
 572 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 573
 574   /* While space is allocated for the floating point registers in the
 575      main registers array, they are stored separatly.  This is because
 576      their size may not necessarily match the size of either the
 577      general-purpose or system specific registers */
 578 #define NR_FGR  (32)
 579 #define FGRIDX  (38)
 580   fp_word fgr[NR_FGR];
 581 #define FGR     ((CPU)->fgr)
 582
 583 #define LO      (REGISTERS[33])
 584 #define HI      (REGISTERS[34])
 585 #define PCIDX   37
 586 #define PC      (REGISTERS[PCIDX])
 587 #define CAUSE   (REGISTERS[36])
 588 #define SRIDX   (32)
 589 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 590 #define FCR0IDX  (71)
 591 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 592 #define FCR31IDX (70)
 593 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 594 #define FCSR    (FCR31)
 595 #define Debug   (REGISTERS[86])
 596 #define DEPC    (REGISTERS[87])
 597 #define EPC     (REGISTERS[88])
 598 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 599
 600   unsigned_word c0_config_reg;
 601 #define C0_CONFIG ((CPU)->c0_config_reg)
 602
 603 /* The following are pseudonyms for standard registers */
 604 #define ZERO    (REGISTERS[0])
 605 #define V0      (REGISTERS[2])
 606 #define A0      (REGISTERS[4])
 607 #define A1      (REGISTERS[5])
 608 #define A2      (REGISTERS[6])
 609 #define A3      (REGISTERS[7])
 610 #define T8IDX   24
 611 #define T8      (REGISTERS[T8IDX])
 612 #define SPIDX   29
 613 #define SP      (REGISTERS[SPIDX])
 614 #define RAIDX   31
 615 #define RA      (REGISTERS[RAIDX])
 616
 617   /* Keep the current format state for each register: */
 618   FP_formats fpr_state[32];
 619 #define FPR_STATE ((CPU)->fpr_state)
 620
 621   pending_write_queue pending;
 622
 623   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 624      read-write instructions. It is set when a linked load occurs. It
 625      is tested and cleared by the conditional store. It is cleared
 626      (during other CPU operations) when a store to the location would
 627      no longer be atomic. In particular, it is cleared by exception
 628      return instructions. */
 629   int llbit;
 630 #define LLBIT ((CPU)->llbit)
 631
 632
 633 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 634    corruptions caused by using the HI or LO register too close to a
 635    following operation is spotted. See mips.igen for more details. */
 636
 637   hilo_history hi_history;
 638 #define HIHISTORY (&(CPU)->hi_history)
 639   hilo_history lo_history;
 640 #define LOHISTORY (&(CPU)->lo_history)
 641
 642
 643   /* start-sanitize-r5900 */
 644   sim_r5900_cpu r5900;
 645
 646   /* end-sanitize-r5900 */
 647   /* start-sanitize-vr5400 */
 648
 649   /* The MDMX ISA has a very very large accumulator */
 650   unsigned8 acc[3 * 8];
 651   /* end-sanitize-vr5400 */
 652
 653   sim_cpu_base base;
 654 };
 655
 656
 657 /* MIPS specific simulator watch config */
 658
 659 void watch_options_install PARAMS ((SIM_DESC sd));
 660
 661 struct swatch {
 662   sim_event *pc;
 663   sim_event *clock;
 664   sim_event *cycles;
 665 };
 666
 667
 668 /* FIXME: At present much of the simulator is still static */
 669 struct sim_state {
 670
 671   struct swatch watch;
 672
 673   sim_cpu cpu[MAX_NR_PROCESSORS];
 674 #if (WITH_SMP)
 675 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 676 #else
 677 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 678 #endif
 679
 680   sim_state_base base;
 681 };
 682
 683
 684
 685 /* Status information: */
 686
 687 /* TODO : these should be the bitmasks for these bits within the
 688    status register. At the moment the following are VR4300
 689    bit-positions: */
 690 #define status_KSU_mask  (0x3)          /* mask for KSU bits */
 691 #define status_KSU_shift (3)            /* shift for field */
 692 #define ksu_kernel       (0x0)
 693 #define ksu_supervisor   (0x1)
 694 #define ksu_user         (0x2)
 695 #define ksu_unknown      (0x3)
 696
 697 #define status_IE        (1 <<  0)      /* Interrupt enable */
 698 #define status_EXL       (1 <<  1)      /* Exception level */
 699 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 700 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 701 #define status_SR        (1 << 20)      /* soft reset or NMI */
 702 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 703 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 704 #define status_ERL       (1 <<  2)      /* Error level */
 705 #define status_RP        (1 << 27)      /* Reduced Power mode */
 706 /* begin-sanitize-r5900 */
 707 #define status_CU0       (1 << 28)      /* COP0 usable */
 708 #define status_CU1       (1 << 29)      /* COP1 usable */
 709 #define status_CU2       (1 << 30)      /* COP2 usable */
 710 /* begin-sanitize-r5900 */
 711
 712 #define cause_BD        ((unsigned)1 << 31)     /* Exception in branch delay slot */
 713
 714 /* NOTE: We keep the following status flags as bit values (1 for true,
 715    0 for false). This allows them to be used in binary boolean
 716    operations without worrying about what exactly the non-zero true
 717    value is. */
 718
 719 /* UserMode */
 720 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 721
 722 /* BigEndianMem */
 723 /* Hardware configuration. Affects endianness of LoadMemory and
 724    StoreMemory and the endianness of Kernel and Supervisor mode
 725    execution. The value is 0 for little-endian; 1 for big-endian. */
 726 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 727 /*(state & simBE) ? 1 : 0)*/
 728
 729 /* ReverseEndian */
 730 /* This mode is selected if in User mode with the RE bit being set in
 731    SR (Status Register). It reverses the endianness of load and store
 732    instructions. */
 733 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 734
 735 /* BigEndianCPU */
 736 /* The endianness for load and store instructions (0=little;1=big). In
 737    User mode this endianness may be switched by setting the state_RE
 738    bit in the SR register. Thus, BigEndianCPU may be computed as
 739    (BigEndianMem EOR ReverseEndian). */
 740 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 741
 742
 743
 744 /* Exceptions: */
 745
 746 /* NOTE: These numbers depend on the processor architecture being
 747    simulated: */
 748 #define Interrupt               (0)
 749 #define TLBModification         (1)
 750 #define TLBLoad                 (2)
 751 #define TLBStore                (3)
 752 #define AddressLoad             (4)
 753 #define AddressStore            (5)
 754 #define InstructionFetch        (6)
 755 #define DataReference           (7)
 756 #define SystemCall              (8)
 757 #define BreakPoint              (9)
 758 #define ReservedInstruction     (10)
 759 #define CoProcessorUnusable     (11)
 760 #define IntegerOverflow         (12)    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 761 #define Trap                    (13)
 762 #define FPE                     (15)
 763 #define DebugBreakPoint         (16)
 764 #define Watch                   (23)
 765
 766 /* The following exception code is actually private to the simulator
 767    world. It is *NOT* a processor feature, and is used to signal
 768    run-time errors in the simulator. */
 769 #define SimulatorFault      (0xFFFFFFFF)
 770
 771 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 772 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 773 #define SignalExceptionInterrupt()           signal_exception (SD, CPU, NULL_CIA, Interrupt)
 774 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 775 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 776 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 777 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 778 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 779 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 780 #define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
 781
 782
 783 /* Co-processor accesses */
 784
 785 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 786 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 787 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 788 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 789
 790 #define COP_LW(coproc_num,coproc_reg,memword) \
 791 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 792 #define COP_LD(coproc_num,coproc_reg,memword) \
 793 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 794 #define COP_SW(coproc_num,coproc_reg) \
 795 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 796 #define COP_SD(coproc_num,coproc_reg) \
 797 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 798
 799 /* start-sanitize-sky */
 800 #ifdef TARGET_SKY
 801 void cop_lq  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
 802                       int coproc_num, int coproc_reg, unsigned128 memword));
 803 unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
 804                             int coproc_num, int coproc_reg));
 805 #define COP_LQ(coproc_num,coproc_reg,memword) \
 806 cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
 807 #define COP_SQ(coproc_num,coproc_reg) \
 808 cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
 809 #endif /* TARGET_SKY */
 810 /* end-sanitize-sky */
 811
 812 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
 813 #define DecodeCoproc(instruction) \
 814 decode_coproc (SD, CPU, cia, (instruction))
 815
 816
 817
 818 /* Memory accesses */
 819
 820 /* The following are generic to all versions of the MIPS architecture
 821    to date: */
 822
 823 /* Memory Access Types (for CCA): */
 824 #define Uncached                (0)
 825 #define CachedNoncoherent       (1)
 826 #define CachedCoherent          (2)
 827 #define Cached                  (3)
 828
 829 #define isINSTRUCTION   (1 == 0) /* FALSE */
 830 #define isDATA          (1 == 1) /* TRUE */
 831 #define isLOAD          (1 == 0) /* FALSE */
 832 #define isSTORE         (1 == 1) /* TRUE */
 833 #define isREAL          (1 == 0) /* FALSE */
 834 #define isRAW           (1 == 1) /* TRUE */
 835 /* The parameter HOST (isTARGET / isHOST) is ignored */
 836 #define isTARGET        (1 == 0) /* FALSE */
 837 /* #define isHOST          (1 == 1) TRUE */
 838
 839 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 840    is the number of bytes minus 1. */
 841 #define AccessLength_BYTE       (0)
 842 #define AccessLength_HALFWORD   (1)
 843 #define AccessLength_TRIPLEBYTE (2)
 844 #define AccessLength_WORD       (3)
 845 #define AccessLength_QUINTIBYTE (4)
 846 #define AccessLength_SEXTIBYTE  (5)
 847 #define AccessLength_SEPTIBYTE  (6)
 848 #define AccessLength_DOUBLEWORD (7)
 849 #define AccessLength_QUADWORD   (15)
 850
 851 #if (WITH_IGEN)
 852 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 853                     ? AccessLength_DOUBLEWORD /*7*/ \
 854                     : AccessLength_WORD /*3*/)
 855 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 856 #endif
 857
 858
 859 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 860 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 861 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 862
 863 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 864 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 865 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 866
 867 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 868 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 869 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 870
 871 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 872 #define CacheOp(op,pAddr,vAddr,instruction) \
 873 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 874
 875 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
 876 #define SyncOperation(stype) \
 877 sync_operation (SD, CPU, cia, (stype))
 878
 879 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 880 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 881 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 882
 883 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 884 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 885 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 886 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
 887 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
 888
 889 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 890 FILE *tracefh;
 891
 892 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 893
 894 char* pr_addr PARAMS ((SIM_ADDR addr));
 895 char* pr_uword64 PARAMS ((uword64 addr));
 896
 897
 898 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 899 #include "sim-main.c"
 900 #endif
 901
 902 #endif