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sim: unify sim_cia definition
[deliverable/binutils-gdb.git] / sim / mips / sim-main.h
1 /* MIPS Simulator definition.
2 Copyright (C) 1997-2015 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #ifndef SIM_MAIN_H
21 #define SIM_MAIN_H
22
23 /* This simulator doesn't cache the Current Instruction Address */
24 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
25 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
26
27 /* hobble some common features for moment */
28 #define WITH_WATCHPOINTS 1
29 #define WITH_MODULO_MEMORY 1
30
31
32 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
33 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
34
35 #include "sim-basics.h"
36
37 typedef struct _sim_cpu SIM_CPU;
38
39 #include "sim-base.h"
40 #include "bfd.h"
41
42 /* Deprecated macros and types for manipulating 64bit values. Use
43 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
44
45 typedef signed64 word64;
46 typedef unsigned64 uword64;
47
48 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
49 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
50 #define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
51 #define SET64HI(t) (((uword64)(t))<<32)
52 #define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
53 #define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
54
55 /* Check if a value will fit within a halfword: */
56 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
57
58
59
60 /* Floating-point operations: */
61
62 #include "sim-fpu.h"
63 #include "cp1.h"
64
65 /* FPU registers must be one of the following types. All other values
66 are reserved (and undefined). */
67 typedef enum {
68 fmt_single = 0,
69 fmt_double = 1,
70 fmt_word = 4,
71 fmt_long = 5,
72 fmt_ps = 6,
73 /* The following are well outside the normal acceptable format
74 range, and are used in the register status vector. */
75 fmt_unknown = 0x10000000,
76 fmt_uninterpreted = 0x20000000,
77 fmt_uninterpreted_32 = 0x40000000,
78 fmt_uninterpreted_64 = 0x80000000U,
79 } FP_formats;
80
81 /* For paired word (pw) operations, the opcode representation is fmt_word,
82 but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */
83 #define fmt_pw fmt_long
84
85 /* This should be the COC1 value at the start of the preceding
86 instruction: */
87 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
88
89 #ifdef TARGET_ENABLE_FR
90 /* FIXME: this should be enabled for all targets, but needs testing first. */
91 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
92 ? ((SR & status_FR) ? 64 : 32) \
93 : (WITH_TARGET_FLOATING_POINT_BITSIZE))
94 #else
95 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
96 #endif
97
98
99
100
101
102 /* HI/LO register accesses */
103
104 /* For some MIPS targets, the HI/LO registers have certain timing
105 restrictions in that, for instance, a read of a HI register must be
106 separated by at least three instructions from a preceeding read.
107
108 The struct below is used to record the last access by each of A MT,
109 MF or other OP instruction to a HI/LO register. See mips.igen for
110 more details. */
111
112 typedef struct _hilo_access {
113 signed64 timestamp;
114 address_word cia;
115 } hilo_access;
116
117 typedef struct _hilo_history {
118 hilo_access mt;
119 hilo_access mf;
120 hilo_access op;
121 } hilo_history;
122
123
124
125
126 /* Integer ALU operations: */
127
128 #include "sim-alu.h"
129
130 #define ALU32_END(ANS) \
131 if (ALU32_HAD_OVERFLOW) \
132 SignalExceptionIntegerOverflow (); \
133 (ANS) = (signed32) ALU32_OVERFLOW_RESULT
134
135
136 #define ALU64_END(ANS) \
137 if (ALU64_HAD_OVERFLOW) \
138 SignalExceptionIntegerOverflow (); \
139 (ANS) = ALU64_OVERFLOW_RESULT;
140
141
142
143
144
145 /* The following is probably not used for MIPS IV onwards: */
146 /* Slots for delayed register updates. For the moment we just have a
147 fixed number of slots (rather than a more generic, dynamic
148 system). This keeps the simulator fast. However, we only allow
149 for the register update to be delayed for a single instruction
150 cycle. */
151 #define PSLOTS (8) /* Maximum number of instruction cycles */
152
153 typedef struct _pending_write_queue {
154 int in;
155 int out;
156 int total;
157 int slot_delay[PSLOTS];
158 int slot_size[PSLOTS];
159 int slot_bit[PSLOTS];
160 void *slot_dest[PSLOTS];
161 unsigned64 slot_value[PSLOTS];
162 } pending_write_queue;
163
164 #ifndef PENDING_TRACE
165 #define PENDING_TRACE 0
166 #endif
167 #define PENDING_IN ((CPU)->pending.in)
168 #define PENDING_OUT ((CPU)->pending.out)
169 #define PENDING_TOTAL ((CPU)->pending.total)
170 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
171 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
172 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
173 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
174 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
175
176 /* Invalidate the pending write queue, all pending writes are
177 discarded. */
178
179 #define PENDING_INVALIDATE() \
180 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
181
182 /* Schedule a write to DEST for N cycles time. For 64 bit
183 destinations, schedule two writes. For floating point registers,
184 the caller should schedule a write to both the dest register and
185 the FPR_STATE register. When BIT is non-negative, only BIT of DEST
186 is updated. */
187
188 #define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
189 do { \
190 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
191 sim_engine_abort (SD, CPU, cia, \
192 "PENDING_SCHED - buffer overflow\n"); \
193 if (PENDING_TRACE) \
194 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \
195 (unsigned long) cia, (unsigned long) &(DEST), \
196 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
197 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
198 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
199 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
200 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
201 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
202 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
203 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \
204 PENDING_TOTAL += 1; \
205 } while (0)
206
207 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
208 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
209
210 #define PENDING_TICK() pending_tick (SD, CPU, cia)
211
212 #define PENDING_FLUSH() abort () /* think about this one */
213 #define PENDING_FP() abort () /* think about this one */
214
215 /* For backward compatibility */
216 #define PENDING_FILL(R,VAL) \
217 do { \
218 if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \
219 { \
220 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \
221 PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
222 } \
223 else \
224 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
225 } while (0)
226
227
228 enum float_operation
229 {
230 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
231 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
232 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
233 };
234
235
236 /* The internal representation of an MDMX accumulator.
237 Note that 24 and 48 bit accumulator elements are represented in
238 32 or 64 bits. Since the accumulators are 2's complement with
239 overflow suppressed, high-order bits can be ignored in most contexts. */
240
241 typedef signed32 signed24;
242 typedef signed64 signed48;
243
244 typedef union {
245 signed24 ob[8];
246 signed48 qh[4];
247 } MDMX_accumulator;
248
249
250 /* Conventional system arguments. */
251 #define SIM_STATE sim_cpu *cpu, address_word cia
252 #define SIM_ARGS CPU, cia
253
254 struct _sim_cpu {
255
256
257 /* The following are internal simulator state variables: */
258 address_word dspc; /* delay-slot PC */
259 #define DSPC ((CPU)->dspc)
260
261 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
262 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
263
264
265 /* State of the simulator */
266 unsigned int state;
267 unsigned int dsstate;
268 #define STATE ((CPU)->state)
269 #define DSSTATE ((CPU)->dsstate)
270
271 /* Flags in the "state" variable: */
272 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
273 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
274 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
275 #define simPCOC0 (1 << 17) /* COC[1] from current */
276 #define simPCOC1 (1 << 18) /* COC[1] from previous */
277 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
278 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
279 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
280 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
281
282 #ifndef ENGINE_ISSUE_PREFIX_HOOK
283 #define ENGINE_ISSUE_PREFIX_HOOK() \
284 { \
285 /* Perform any pending writes */ \
286 PENDING_TICK(); \
287 /* Set previous flag, depending on current: */ \
288 if (STATE & simPCOC0) \
289 STATE |= simPCOC1; \
290 else \
291 STATE &= ~simPCOC1; \
292 /* and update the current value: */ \
293 if (GETFCC(0)) \
294 STATE |= simPCOC0; \
295 else \
296 STATE &= ~simPCOC0; \
297 }
298 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
299
300
301 /* This is nasty, since we have to rely on matching the register
302 numbers used by GDB. Unfortunately, depending on the MIPS target
303 GDB uses different register numbers. We cannot just include the
304 relevant "gdb/tm.h" link, since GDB may not be configured before
305 the sim world, and also the GDB header file requires too much other
306 state. */
307
308 #ifndef TM_MIPS_H
309 #define LAST_EMBED_REGNUM (96)
310 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
311
312 #define FP0_REGNUM 38 /* Floating point register 0 (single float) */
313 #define FCRCS_REGNUM 70 /* FP control/status */
314 #define FCRIR_REGNUM 71 /* FP implementation/revision */
315 #endif
316
317
318 /* To keep this default simulator simple, and fast, we use a direct
319 vector of registers. The internal simulator engine then uses
320 manifests to access the correct slot. */
321
322 unsigned_word registers[LAST_EMBED_REGNUM + 1];
323
324 int register_widths[NUM_REGS];
325 #define REGISTERS ((CPU)->registers)
326
327 #define GPR (&REGISTERS[0])
328 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
329
330 #define LO (REGISTERS[33])
331 #define HI (REGISTERS[34])
332 #define PCIDX 37
333 #define PC (REGISTERS[PCIDX])
334 #define CAUSE (REGISTERS[36])
335 #define SRIDX (32)
336 #define SR (REGISTERS[SRIDX]) /* CPU status register */
337 #define FCR0IDX (71)
338 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
339 #define FCR31IDX (70)
340 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
341 #define FCSR (FCR31)
342 #define Debug (REGISTERS[86])
343 #define DEPC (REGISTERS[87])
344 #define EPC (REGISTERS[88])
345 #define ACX (REGISTERS[89])
346
347 #define AC0LOIDX (33) /* Must be the same register as LO */
348 #define AC0HIIDX (34) /* Must be the same register as HI */
349 #define AC1LOIDX (90)
350 #define AC1HIIDX (91)
351 #define AC2LOIDX (92)
352 #define AC2HIIDX (93)
353 #define AC3LOIDX (94)
354 #define AC3HIIDX (95)
355
356 #define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]])
357 #define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]])
358
359 #define DSPCRIDX (96) /* DSP control register */
360 #define DSPCR (REGISTERS[DSPCRIDX])
361
362 #define DSPCR_POS_SHIFT (0)
363 #define DSPCR_POS_MASK (0x3f)
364 #define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
365
366 #define DSPCR_SCOUNT_SHIFT (7)
367 #define DSPCR_SCOUNT_MASK (0x3f)
368 #define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
369
370 #define DSPCR_CARRY_SHIFT (13)
371 #define DSPCR_CARRY_MASK (1)
372 #define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
373 #define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT)
374
375 #define DSPCR_EFI_SHIFT (14)
376 #define DSPCR_EFI_MASK (1)
377 #define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
378 #define DSPCR_EFI (1 << DSPCR_EFI_MASK)
379
380 #define DSPCR_OUFLAG_SHIFT (16)
381 #define DSPCR_OUFLAG_MASK (0xff)
382 #define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
383 #define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4))
384 #define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5))
385 #define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6))
386 #define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7))
387
388 #define DSPCR_CCOND_SHIFT (24)
389 #define DSPCR_CCOND_MASK (0xf)
390 #define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
391
392 /* All internal state modified by signal_exception() that may need to be
393 rolled back for passing moment-of-exception image back to gdb. */
394 unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
395 unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
396 int exc_suspended;
397
398 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
399 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
400 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
401
402 unsigned_word c0_config_reg;
403 #define C0_CONFIG ((CPU)->c0_config_reg)
404
405 /* The following are pseudonyms for standard registers */
406 #define ZERO (REGISTERS[0])
407 #define V0 (REGISTERS[2])
408 #define A0 (REGISTERS[4])
409 #define A1 (REGISTERS[5])
410 #define A2 (REGISTERS[6])
411 #define A3 (REGISTERS[7])
412 #define T8IDX 24
413 #define T8 (REGISTERS[T8IDX])
414 #define SPIDX 29
415 #define SP (REGISTERS[SPIDX])
416 #define RAIDX 31
417 #define RA (REGISTERS[RAIDX])
418
419 /* While space is allocated in the main registers arrray for some of
420 the COP0 registers, that space isn't sufficient. Unknown COP0
421 registers overflow into the array below */
422
423 #define NR_COP0_GPR 32
424 unsigned_word cop0_gpr[NR_COP0_GPR];
425 #define COP0_GPR ((CPU)->cop0_gpr)
426 #define COP0_BADVADDR (COP0_GPR[8])
427
428 /* While space is allocated for the floating point registers in the
429 main registers array, they are stored separatly. This is because
430 their size may not necessarily match the size of either the
431 general-purpose or system specific registers. */
432 #define NR_FGR (32)
433 #define FGR_BASE FP0_REGNUM
434 fp_word fgr[NR_FGR];
435 #define FGR ((CPU)->fgr)
436
437 /* Keep the current format state for each register: */
438 FP_formats fpr_state[32];
439 #define FPR_STATE ((CPU)->fpr_state)
440
441 pending_write_queue pending;
442
443 /* The MDMX accumulator (used only for MDMX ASE). */
444 MDMX_accumulator acc;
445 #define ACC ((CPU)->acc)
446
447 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
448 read-write instructions. It is set when a linked load occurs. It
449 is tested and cleared by the conditional store. It is cleared
450 (during other CPU operations) when a store to the location would
451 no longer be atomic. In particular, it is cleared by exception
452 return instructions. */
453 int llbit;
454 #define LLBIT ((CPU)->llbit)
455
456
457 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
458 corruptions caused by using the HI or LO register too close to a
459 following operation is spotted. See mips.igen for more details. */
460
461 hilo_history hi_history;
462 #define HIHISTORY (&(CPU)->hi_history)
463 hilo_history lo_history;
464 #define LOHISTORY (&(CPU)->lo_history)
465
466
467 sim_cpu_base base;
468 };
469
470
471 /* MIPS specific simulator watch config */
472
473 void watch_options_install (SIM_DESC sd);
474
475 struct swatch {
476 sim_event *pc;
477 sim_event *clock;
478 sim_event *cycles;
479 };
480
481
482 /* FIXME: At present much of the simulator is still static */
483 struct sim_state {
484
485 struct swatch watch;
486
487 sim_cpu *cpu[MAX_NR_PROCESSORS];
488
489 sim_state_base base;
490 };
491
492
493
494 /* Status information: */
495
496 /* TODO : these should be the bitmasks for these bits within the
497 status register. At the moment the following are VR4300
498 bit-positions: */
499 #define status_KSU_mask (0x18) /* mask for KSU bits */
500 #define status_KSU_shift (3) /* shift for field */
501 #define ksu_kernel (0x0)
502 #define ksu_supervisor (0x1)
503 #define ksu_user (0x2)
504 #define ksu_unknown (0x3)
505
506 #define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift)
507
508 #define status_IE (1 << 0) /* Interrupt enable */
509 #define status_EIE (1 << 16) /* Enable Interrupt Enable */
510 #define status_EXL (1 << 1) /* Exception level */
511 #define status_RE (1 << 25) /* Reverse Endian in user mode */
512 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */
513 #define status_SR (1 << 20) /* soft reset or NMI */
514 #define status_BEV (1 << 22) /* Location of general exception vectors */
515 #define status_TS (1 << 21) /* TLB shutdown has occurred */
516 #define status_ERL (1 << 2) /* Error level */
517 #define status_IM7 (1 << 15) /* Timer Interrupt Mask */
518 #define status_RP (1 << 27) /* Reduced Power mode */
519
520 /* Specializations for TX39 family */
521 #define status_IEc (1 << 0) /* Interrupt enable (current) */
522 #define status_KUc (1 << 1) /* Kernel/User mode */
523 #define status_IEp (1 << 2) /* Interrupt enable (previous) */
524 #define status_KUp (1 << 3) /* Kernel/User mode */
525 #define status_IEo (1 << 4) /* Interrupt enable (old) */
526 #define status_KUo (1 << 5) /* Kernel/User mode */
527 #define status_IM_mask (0xff) /* Interrupt mask */
528 #define status_IM_shift (8)
529 #define status_NMI (1 << 20) /* NMI */
530 #define status_NMI (1 << 20) /* NMI */
531
532 /* Status bits used by MIPS32/MIPS64. */
533 #define status_UX (1 << 5) /* 64-bit user addrs */
534 #define status_SX (1 << 6) /* 64-bit supervisor addrs */
535 #define status_KX (1 << 7) /* 64-bit kernel addrs */
536 #define status_TS (1 << 21) /* TLB shutdown has occurred */
537 #define status_PX (1 << 23) /* Enable 64 bit operations */
538 #define status_MX (1 << 24) /* Enable MDMX resources */
539 #define status_CU0 (1 << 28) /* Coprocessor 0 usable */
540 #define status_CU1 (1 << 29) /* Coprocessor 1 usable */
541 #define status_CU2 (1 << 30) /* Coprocessor 2 usable */
542 #define status_CU3 (1 << 31) /* Coprocessor 3 usable */
543 /* Bits reserved for implementations: */
544 #define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */
545
546 #define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
547 #define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
548 #define cause_CE_mask 0x30000000 /* Coprocessor exception */
549 #define cause_CE_shift 28
550 #define cause_EXC2_mask 0x00070000
551 #define cause_EXC2_shift 16
552 #define cause_IP7 (1 << 15) /* Interrupt pending */
553 #define cause_SIOP (1 << 12) /* SIO pending */
554 #define cause_IP3 (1 << 11) /* Int 0 pending */
555 #define cause_IP2 (1 << 10) /* Int 1 pending */
556
557 #define cause_EXC_mask (0x1c) /* Exception code */
558 #define cause_EXC_shift (2)
559
560 #define cause_SW0 (1 << 8) /* Software interrupt 0 */
561 #define cause_SW1 (1 << 9) /* Software interrupt 1 */
562 #define cause_IP_mask (0x3f) /* Interrupt pending field */
563 #define cause_IP_shift (10)
564
565 #define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask)
566 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
567
568
569 /* NOTE: We keep the following status flags as bit values (1 for true,
570 0 for false). This allows them to be used in binary boolean
571 operations without worrying about what exactly the non-zero true
572 value is. */
573
574 /* UserMode */
575 #ifdef SUBTARGET_R3900
576 #define UserMode ((SR & status_KUc) ? 1 : 0)
577 #else
578 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
579 #endif /* SUBTARGET_R3900 */
580
581 /* BigEndianMem */
582 /* Hardware configuration. Affects endianness of LoadMemory and
583 StoreMemory and the endianness of Kernel and Supervisor mode
584 execution. The value is 0 for little-endian; 1 for big-endian. */
585 #define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
586 /*(state & simBE) ? 1 : 0)*/
587
588 /* ReverseEndian */
589 /* This mode is selected if in User mode with the RE bit being set in
590 SR (Status Register). It reverses the endianness of load and store
591 instructions. */
592 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
593
594 /* BigEndianCPU */
595 /* The endianness for load and store instructions (0=little;1=big). In
596 User mode this endianness may be switched by setting the state_RE
597 bit in the SR register. Thus, BigEndianCPU may be computed as
598 (BigEndianMem EOR ReverseEndian). */
599 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
600
601
602
603 /* Exceptions: */
604
605 /* NOTE: These numbers depend on the processor architecture being
606 simulated: */
607 enum ExceptionCause {
608 Interrupt = 0,
609 TLBModification = 1,
610 TLBLoad = 2,
611 TLBStore = 3,
612 AddressLoad = 4,
613 AddressStore = 5,
614 InstructionFetch = 6,
615 DataReference = 7,
616 SystemCall = 8,
617 BreakPoint = 9,
618 ReservedInstruction = 10,
619 CoProcessorUnusable = 11,
620 IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */
621 Trap = 13,
622 FPE = 15,
623 DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */
624 MDMX = 22,
625 Watch = 23,
626 MCheck = 24,
627 CacheErr = 30,
628 NMIReset = 31, /* Reserved in MIPS32/MIPS64. */
629
630
631 /* The following exception code is actually private to the simulator
632 world. It is *NOT* a processor feature, and is used to signal
633 run-time errors in the simulator. */
634 SimulatorFault = 0xFFFFFFFF
635 };
636
637 #define TLB_REFILL (0)
638 #define TLB_INVALID (1)
639
640
641 /* The following break instructions are reserved for use by the
642 simulator. The first is used to halt the simulation. The second
643 is used by gdb for break-points. NOTE: Care must be taken, since
644 this value may be used in later revisions of the MIPS ISA. */
645 #define HALT_INSTRUCTION_MASK (0x03FFFFC0)
646
647 #define HALT_INSTRUCTION (0x03ff000d)
648 #define HALT_INSTRUCTION2 (0x0000ffcd)
649
650
651 #define BREAKPOINT_INSTRUCTION (0x0005000d)
652 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
653
654
655
656 void interrupt_event (SIM_DESC sd, void *data);
657
658 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
659 #define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
660 #define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level)
661 #define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
662 #define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
663 #define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
664 #define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference)
665 #define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
666 #define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
667 #define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
668 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
669 #define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
670 #define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
671 #define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
672 #define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
673 #define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
674 #define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification)
675 #define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX)
676 #define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch)
677 #define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck)
678 #define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr)
679
680 /* Co-processor accesses */
681
682 /* XXX FIXME: For now, assume that FPU (cp1) is always usable. */
683 #define COP_Usable(coproc_num) (coproc_num == 1)
684
685 void cop_lw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword);
686 void cop_ld (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword);
687 unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
688 uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
689
690 #define COP_LW(coproc_num,coproc_reg,memword) \
691 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
692 #define COP_LD(coproc_num,coproc_reg,memword) \
693 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
694 #define COP_SW(coproc_num,coproc_reg) \
695 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
696 #define COP_SD(coproc_num,coproc_reg) \
697 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
698
699
700 void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction);
701 #define DecodeCoproc(instruction) \
702 decode_coproc (SD, CPU, cia, (instruction))
703
704 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
705
706
707 /* FPR access. */
708 unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
709 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
710 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
711 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
712 unsigned64 ps_lower (SIM_STATE, unsigned64 op);
713 #define PSLower(op) ps_lower (SIM_ARGS, op)
714 unsigned64 ps_upper (SIM_STATE, unsigned64 op);
715 #define PSUpper(op) ps_upper (SIM_ARGS, op)
716 unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
717 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
718
719
720 /* FCR access. */
721 unsigned_word value_fcr (SIM_STATE, int fcr);
722 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
723 void store_fcr (SIM_STATE, int fcr, unsigned_word value);
724 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
725 void test_fcsr (SIM_STATE);
726 #define TestFCSR() test_fcsr (SIM_ARGS)
727
728
729 /* FPU operations. */
730 void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
731 #define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
732 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
733 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
734 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
735 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
736 unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
737 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
738 unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
739 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
740 unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
741 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
742 unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
743 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
744 unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
745 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
746 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
747 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
748 unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
749 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
750 unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
751 unsigned64 op3, FP_formats fmt);
752 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
753 unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
754 unsigned64 op3, FP_formats fmt);
755 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
756 unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
757 unsigned64 op3, FP_formats fmt);
758 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
759 unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
760 unsigned64 op3, FP_formats fmt);
761 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
762 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
763 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
764 unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
765 FP_formats to);
766 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
767
768
769 /* MIPS-3D ASE operations. */
770 #define CompareAbs(op1,op2,fmt,cond,cc) \
771 fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
772 unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
773 #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
774 unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
775 #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
776 unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
777 #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
778 unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
779 #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
780 unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
781 #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
782 unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
783 #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
784
785
786 /* MDMX access. */
787
788 typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
789 #define ob_fmtsel(sel) (((sel)<<1)|0x0)
790 #define qh_fmtsel(sel) (((sel)<<2)|0x1)
791
792 #define fmt_mdmx fmt_uninterpreted
793
794 #define MX_VECT_AND (0)
795 #define MX_VECT_NOR (1)
796 #define MX_VECT_OR (2)
797 #define MX_VECT_XOR (3)
798 #define MX_VECT_SLL (4)
799 #define MX_VECT_SRL (5)
800 #define MX_VECT_ADD (6)
801 #define MX_VECT_SUB (7)
802 #define MX_VECT_MIN (8)
803 #define MX_VECT_MAX (9)
804 #define MX_VECT_MUL (10)
805 #define MX_VECT_MSGN (11)
806 #define MX_VECT_SRA (12)
807 #define MX_VECT_ABSD (13) /* SB-1 only. */
808 #define MX_VECT_AVG (14) /* SB-1 only. */
809
810 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
811 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
812 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
813 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
814 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
815 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
816 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
817 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
818 #define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel)
819 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
820 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
821 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
822 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
823 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
824 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
825 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
826
827 #define MX_C_EQ 0x1
828 #define MX_C_LT 0x4
829
830 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
831 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
832
833 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
834 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
835
836 #define MX_VECT_ADDA (0)
837 #define MX_VECT_ADDL (1)
838 #define MX_VECT_MULA (2)
839 #define MX_VECT_MULL (3)
840 #define MX_VECT_MULS (4)
841 #define MX_VECT_MULSL (5)
842 #define MX_VECT_SUBA (6)
843 #define MX_VECT_SUBL (7)
844 #define MX_VECT_ABSDA (8) /* SB-1 only. */
845
846 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
847 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
848 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
849 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
850 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
851 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
852 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
853 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
854 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
855 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
856
857 #define MX_FMT_OB (0)
858 #define MX_FMT_QH (1)
859
860 /* The following codes chosen to indicate the units of shift. */
861 #define MX_RAC_L (0)
862 #define MX_RAC_M (1)
863 #define MX_RAC_H (2)
864
865 unsigned64 mdmx_rac_op (SIM_STATE, int, int);
866 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
867
868 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
869 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
870 void mdmx_wach (SIM_STATE, int, unsigned64);
871 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
872
873 #define MX_RND_AS (0)
874 #define MX_RND_AU (1)
875 #define MX_RND_ES (2)
876 #define MX_RND_EU (3)
877 #define MX_RND_ZS (4)
878 #define MX_RND_ZU (5)
879
880 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
881 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
882 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
883 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
884 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
885 #define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
886 #define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
887
888 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
889 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
890
891
892
893 /* Memory accesses */
894
895 /* The following are generic to all versions of the MIPS architecture
896 to date: */
897
898 /* Memory Access Types (for CCA): */
899 #define Uncached (0)
900 #define CachedNoncoherent (1)
901 #define CachedCoherent (2)
902 #define Cached (3)
903
904 #define isINSTRUCTION (1 == 0) /* FALSE */
905 #define isDATA (1 == 1) /* TRUE */
906 #define isLOAD (1 == 0) /* FALSE */
907 #define isSTORE (1 == 1) /* TRUE */
908 #define isREAL (1 == 0) /* FALSE */
909 #define isRAW (1 == 1) /* TRUE */
910 /* The parameter HOST (isTARGET / isHOST) is ignored */
911 #define isTARGET (1 == 0) /* FALSE */
912 /* #define isHOST (1 == 1) TRUE */
913
914 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
915 is the number of bytes minus 1. */
916 #define AccessLength_BYTE (0)
917 #define AccessLength_HALFWORD (1)
918 #define AccessLength_TRIPLEBYTE (2)
919 #define AccessLength_WORD (3)
920 #define AccessLength_QUINTIBYTE (4)
921 #define AccessLength_SEXTIBYTE (5)
922 #define AccessLength_SEPTIBYTE (6)
923 #define AccessLength_DOUBLEWORD (7)
924 #define AccessLength_QUADWORD (15)
925
926 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
927 ? AccessLength_DOUBLEWORD /*7*/ \
928 : AccessLength_WORD /*3*/)
929 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
930
931
932 INLINE_SIM_MAIN (int) address_translation (SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw);
933 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
934 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
935
936 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
937 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
938 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
939
940 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
941 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
942 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
943
944 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
945 #define CacheOp(op,pAddr,vAddr,instruction) \
946 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
947
948 INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype);
949 #define SyncOperation(stype) \
950 sync_operation (SD, CPU, cia, (stype))
951
952 INLINE_SIM_MAIN (void) prefetch (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint);
953 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
954 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
955
956 void unpredictable_action (sim_cpu *cpu, address_word cia);
957 #define NotWordValue(val) not_word_value (SD_, (val))
958 #define Unpredictable() unpredictable (SD_)
959 #define UnpredictableResult() /* For now, do nothing. */
960
961 INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
962 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
963 INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
964 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
965 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
966
967 void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...);
968 extern FILE *tracefh;
969
970 extern int DSPLO_REGNUM[4];
971 extern int DSPHI_REGNUM[4];
972
973 INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia);
974 extern SIM_CORE_SIGNAL_FN mips_core_signal;
975
976 char* pr_addr (SIM_ADDR addr);
977 char* pr_uword64 (uword64 addr);
978
979
980 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
981
982 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
983 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
984 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
985
986 #ifdef MIPS_MACH_MULTI
987 extern int mips_mach_multi(SIM_DESC sd);
988 #define MIPS_MACH(SD) mips_mach_multi(SD)
989 #else
990 #define MIPS_MACH(SD) MIPS_MACH_DEFAULT
991 #endif
992
993 /* Macros for determining whether a MIPS IV or MIPS V part is subject
994 to the hi/lo restrictions described in mips.igen. */
995
996 #define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
997 (MIPS_MACH (SD) != bfd_mach_mips5500)
998
999 #define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
1000 (MIPS_MACH (SD) != bfd_mach_mips5500)
1001
1002 #define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
1003 (MIPS_MACH (SD) != bfd_mach_mips5500)
1004
1005 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1006 #include "sim-main.c"
1007 #endif
1008
1009 #endif
GDB Binutils - Deliverables
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