sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 #if (WITH_IGEN)
  40 /* Get the number of instructions.  FIXME: must be a more elegant way
  41    of doing this.  */
  42 #include "itable.h"
  43 #define MAX_INSNS (nr_itable_entries)
  44 #define INSN_NAME(cpu,i) itable[(i)].name
  45 #endif
  46
  47 #include "sim-base.h"
  48
  49
  50 /* Depreciated macros and types for manipulating 64bit values.  Use
  51    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  52
  53 typedef signed64 word64;
  54 typedef unsigned64 uword64;
  55
  56 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  57 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  58 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  59 #define SET64HI(t)      (((uword64)(t))<<32)
  60 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  61 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  62
  63 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  64    assume the HI32bits of the operand are zero, so we must perform a
  65    mask to ensure we can use the simple subtraction to sign-extend. */
  66 #define SIGNEXTEND(e,b) \
  67  ((unsigned_word) \
  68   (((e) & ((uword64) 1 << ((b) - 1))) \
  69    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  70    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  71
  72 /* Check if a value will fit within a halfword: */
  73 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  74
  75
  76
  77 /* Floating-point operations: */
  78
  79 #include "sim-fpu.h"
  80
  81 /* FPU registers must be one of the following types. All other values
  82    are reserved (and undefined). */
  83 typedef enum {
  84  fmt_single  = 0,
  85  fmt_double  = 1,
  86  fmt_word    = 4,
  87  fmt_long    = 5,
  88  /* The following are well outside the normal acceptable format
  89     range, and are used in the register status vector. */
  90  fmt_unknown       = 0x10000000,
  91  fmt_uninterpreted = 0x20000000,
  92  fmt_uninterpreted_32 = 0x40000000,
  93  fmt_uninterpreted_64 = 0x80000000U,
  94 } FP_formats;
  95
  96 unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
  97 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
  98
  99 void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
 100 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
 101
 102 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
 103 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 104 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 105 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 106 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 107 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 108 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 109 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 110 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 111 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 112 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 113 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 114 unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 115 unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 116 unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 117 #define Convert(rm,op,from,to) \
 118 convert (SD, CPU, cia, rm, op, from, to)
 119
 120 /* Macro to update FPSR condition-code field. This is complicated by
 121    the fact that there is a hole in the index range of the bits within
 122    the FCSR register. Also, the number of bits visible depends on the
 123    MIPS ISA version being supported. */
 124
 125 #define SETFCC(cc,v) {\
 126   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 127   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 128 }
 129 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
 130
 131 /* This should be the COC1 value at the start of the preceding
 132    instruction: */
 133 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 134
 135 #if 1
 136 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 137 #else
 138 /* They depend on the CPU being simulated */
 139 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 140 #endif
 141
 142 /* Standard FCRS bits: */
 143 #define IR (0) /* Inexact Result */
 144 #define UF (1) /* UnderFlow */
 145 #define OF (2) /* OverFlow */
 146 #define DZ (3) /* Division by Zero */
 147 #define IO (4) /* Invalid Operation */
 148 #define UO (5) /* Unimplemented Operation */
 149
 150 /* Get masks for individual flags: */
 151 #if 1 /* SAFE version */
 152 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 153 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 154 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 155 #else
 156 #define FP_FLAGS(b)  (1 << ((b) + 2))
 157 #define FP_ENABLE(b) (1 << ((b) + 7))
 158 #define FP_CAUSE(b)  (1 << ((b) + 12))
 159 #endif
 160
 161 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 162
 163 #define FP_MASK_RM    (0x3)
 164 #define FP_SH_RM      (0)
 165 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 166 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 167 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 168 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 169 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 170
 171 /* start-sanitize-sky */
 172 #ifdef TARGET_SKY
 173 #ifdef SKY_FUNIT
 174 #include <assert.h>
 175 #include "wf.h"
 176 #endif
 177 #endif
 178 /* end-sanitize-sky */
 179
 180
 181
 182
 183
 184 /* HI/LO register accesses */
 185
 186 /* For some MIPS targets, the HI/LO registers have certain timing
 187    restrictions in that, for instance, a read of a HI register must be
 188    separated by at least three instructions from a preceeding read.
 189
 190    The struct below is used to record the last access by each of A MT,
 191    MF or other OP instruction to a HI/LO register.  See mips.igen for
 192    more details. */
 193
 194 typedef struct _hilo_access {
 195   signed64 timestamp;
 196   address_word cia;
 197 } hilo_access;
 198
 199 typedef struct _hilo_history {
 200   hilo_access mt;
 201   hilo_access mf;
 202   hilo_access op;
 203 } hilo_history;
 204
 205
 206
 207
 208 /* Integer ALU operations: */
 209
 210 #include "sim-alu.h"
 211
 212 #define ALU32_END(ANS) \
 213   if (ALU32_HAD_OVERFLOW) \
 214     SignalExceptionIntegerOverflow (); \
 215   (ANS) = (signed32) ALU32_OVERFLOW_RESULT
 216
 217
 218 #define ALU64_END(ANS) \
 219   if (ALU64_HAD_OVERFLOW) \
 220     SignalExceptionIntegerOverflow (); \
 221   (ANS) = ALU64_OVERFLOW_RESULT;
 222
 223
 224 /* start-sanitize-r5900 */
 225
 226 /* Figure 10-5 FPU Control/Status Register.
 227    Note: some of these bits are different to what is found in a
 228    standard MIPS manual. */
 229 enum {
 230   R5900_FCSR_C = BIT (23), /* OK */
 231   R5900_FCSR_I = BIT (17),
 232   R5900_FCSR_D = BIT (16),
 233   R5900_FCSR_O = BIT (15),
 234   R5900_FCSR_U = BIT (14),
 235   R5900_FCSR_CAUSE = MASK (16,14),
 236   R5900_FCSR_SI = BIT (6),
 237   R5900_FCSR_SD = BIT (5),
 238   R5900_FCSR_SO = BIT (4),
 239   R5900_FCSR_SU = BIT (3),
 240 };
 241
 242 /* Table 10-1 FP format values.
 243    Note: some of these bits are different to what is found in a
 244    standard MIPS manual. */
 245 enum {
 246   R5900_EXPMAX = 128,
 247   R5900_EXPMIN = -127,
 248   R5900_EXPBIAS = 127,
 249 };
 250
 251 /* MAX and MIN FP values */
 252 enum {
 253   R5900_FPMAX = LSMASK32 (30, 0),
 254   R5900_FPMIN = LSMASK32 (31, 0),
 255 };
 256
 257
 258
 259 typedef struct _sim_r5900_cpu {
 260
 261   /* The R5900 has 32 x 128bit general purpose registers.
 262      Fortunatly, the high 64 bits are only touched by multimedia (MMI)
 263      instructions.  The normal mips instructions just use the lower 64
 264      bits.  To avoid changing the older parts of the simulator to
 265      handle this weirdness, the high 64 bits of each register are kept
 266      in a separate array (registers1).  The high 64 bits of any
 267      register are by convention refered by adding a '1' to the end of
 268      the normal register's name.  So LO still refers to the low 64
 269      bits of the LO register, LO1 refers to the high 64 bits of that
 270      same register.  */
 271   signed_word gpr1[32];
 272 #define GPR1     ((CPU)->r5900.gpr1)
 273   signed_word lo1;
 274   signed_word hi1;
 275 #define LO1      ((CPU)->r5900.lo1)
 276 #define HI1      ((CPU)->r5900.hi1)
 277
 278   /* The R5900 defines a shift amount register, that controls the
 279      amount of certain shift instructions */
 280   unsigned_word sa;        /* the shift amount register */
 281 #define REGISTER_SA     (124) /* GET RID IF THIS! */
 282 #define SA ((CPU)->r5900.sa)
 283
 284   /* The R5900, in addition to the (almost) standard floating point
 285      registers, defines a 32 bit accumulator.  This is used in
 286      multiply/accumulate style instructions */
 287   fp_word acc; /* floating-point accumulator */
 288 #define ACC ((CPU)->r5900.acc)
 289
 290   /* See comments below about needing to count cycles between updating
 291      and setting HI/LO registers */
 292   hilo_history hi1_history;
 293 #define HI1HISTORY (&(CPU)->r5900.hi1_history)
 294   hilo_history lo1_history;
 295 #define LO1HISTORY (&(CPU)->r5900.lo1_history)
 296
 297 } sim_r5900_cpu;
 298
 299 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 300 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 301 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 302 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 303
 304 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 305 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 306 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 307 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 308
 309 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 310    T  - type of the sub part
 311    TC - # of T's in the mips part of the "register"
 312    I  - index (from 0) of desired sub part
 313    A  - low part of "register"
 314    A1 - high part of register
 315 */
 316 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 317 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 318    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 319       ? ((TC) - 1 - (I) % (TC)) \
 320       : ((I) % (TC)) \
 321       ) \
 322    ) \
 323  )
 324
 325 /*
 326 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 327             where <type> has two letters:
 328                   1 is S=signed or U=unsigned
 329                   2 is B=byte H=halfword W=word D=doubleword
 330 */
 331
 332 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 333 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 334 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 335 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 336
 337 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 338 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 339 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 340 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 341
 342 #define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
 343 #define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
 344 #define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
 345 #define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
 346
 347 #define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
 348 #define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
 349 #define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
 350 #define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
 351
 352 #define TMP_DCL unsigned64 tmp_reg, tmp_reg1
 353
 354 #define TMP_SB(I) SUB_REG_SB(&tmp_reg, &tmp_reg1, I)
 355 #define TMP_SH(I) SUB_REG_SH(&tmp_reg, &tmp_reg1, I)
 356 #define TMP_SW(I) SUB_REG_SW(&tmp_reg, &tmp_reg1, I)
 357 #define TMP_SD(I) SUB_REG_SD(&tmp_reg, &tmp_reg1, I)
 358
 359 #define TMP_UB(I) SUB_REG_UB(&tmp_reg, &tmp_reg1, I)
 360 #define TMP_UH(I) SUB_REG_UH(&tmp_reg, &tmp_reg1, I)
 361 #define TMP_UW(I) SUB_REG_UW(&tmp_reg, &tmp_reg1, I)
 362 #define TMP_UD(I) SUB_REG_UD(&tmp_reg, &tmp_reg1, I)
 363
 364 #define TMP_WRT(R) do { GPR[R] = tmp_reg; GPR1[R] = tmp_reg1; } while(0)
 365
 366 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 367 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 368 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 369 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 370
 371 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 372 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 373 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 374 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 375
 376 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 377 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 378 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 379 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 380
 381 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 382 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 383 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 384 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 385
 386
 387
 388 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 389 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 390 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 391 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 392
 393 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 394 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 395 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 396 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 397
 398 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 399 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 400 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 401 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 402
 403 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 404 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 405 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 406 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 407
 408 /* end-sanitize-r5900 */
 409
 410
 411
 412 /* The following is probably not used for MIPS IV onwards: */
 413 /* Slots for delayed register updates. For the moment we just have a
 414    fixed number of slots (rather than a more generic, dynamic
 415    system). This keeps the simulator fast. However, we only allow
 416    for the register update to be delayed for a single instruction
 417    cycle. */
 418 #define PSLOTS (8) /* Maximum number of instruction cycles */
 419
 420 typedef struct _pending_write_queue {
 421   int in;
 422   int out;
 423   int total;
 424   int slot_delay[PSLOTS];
 425   int slot_size[PSLOTS];
 426   int slot_bit[PSLOTS];
 427   void *slot_dest[PSLOTS];
 428   unsigned64 slot_value[PSLOTS];
 429 } pending_write_queue;
 430
 431 #ifndef PENDING_TRACE
 432 #define PENDING_TRACE 0
 433 #endif
 434 #define PENDING_IN ((CPU)->pending.in)
 435 #define PENDING_OUT ((CPU)->pending.out)
 436 #define PENDING_TOTAL ((CPU)->pending.total)
 437 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 438 #define PENDING_SLOT_BIT ((CPU)->pending.slot_size)
 439 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 440 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 441 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 442
 443 /* Invalidate the pending write queue, all pending writes are
 444    discarded. */
 445
 446 #define PENDING_INVALIDATE() \
 447 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 448
 449 /* Schedule a write to DEST for N cycles time.  For 64 bit
 450    destinations, schedule two writes.  For floating point registers,
 451    the caller should schedule a write to both the dest register and
 452    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 453    is updated. */
 454
 455 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 456   do {                                                                  \
 457     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 458       sim_engine_abort (SD, CPU, cia,                                   \
 459                         "PENDING_SCHED - buffer overflow\n");           \
 460     if (PENDING_TRACE)                                                  \
 461       sim_io_printf (SD, "PENDING_SCHED - dest 0x%lx, val 0x%lx, pending_in %d, pending_out %d, pending_total %d\n", (unsigned long) (DEST), (unsigned long) (VAL), PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
 462     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 463     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 464     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 465     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 466     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 467   } while (0)
 468
 469 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 470 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 471
 472 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 473
 474 #define PENDING_FLUSH() abort () /* think about this one */
 475 #define PENDING_FP() abort () /* think about this one */
 476
 477 /* For backward compatibility */
 478 #define PENDING_FILL(R,VAL)                                             \
 479 {                                                                       \
 480   if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR)                           \
 481     PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 2, -1);                       \
 482   else                                                                  \
 483     PENDING_SCHED(GPR[(R)], VAL, 2, -1);                                \
 484 }
 485
 486
 487
 488 struct _sim_cpu {
 489
 490
 491   /* The following are internal simulator state variables: */
 492 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 493 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 494   address_word dspc;  /* delay-slot PC */
 495 #define DSPC ((CPU)->dspc)
 496
 497 #if !WITH_IGEN
 498   /* Issue a delay slot instruction immediatly by re-calling
 499      idecode_issue */
 500 #define DELAY_SLOT(TARGET) \
 501   do { \
 502     address_word target = (TARGET); \
 503     instruction_word delay_insn; \
 504     sim_events_slip (SD, 1); \
 505     CIA = CIA + 4; /* NOTE not mips16 */ \
 506     STATE |= simDELAYSLOT; \
 507     delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ \
 508     idecode_issue (CPU_, delay_insn, (CIA)); \
 509     STATE &= ~simDELAYSLOT; \
 510     NIA = target; \
 511   } while (0)
 512 #define NULLIFY_NEXT_INSTRUCTION() \
 513   do { \
 514     sim_events_slip (SD, 1); \
 515     dotrace (SD, CPU, tracefh, 2, NIA, 4, "load instruction"); \
 516     NIA = CIA + 8; \
 517   } while (0)
 518 #else
 519 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 520 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 521 #endif
 522
 523
 524   /* State of the simulator */
 525   unsigned int state;
 526   unsigned int dsstate;
 527 #define STATE ((CPU)->state)
 528 #define DSSTATE ((CPU)->dsstate)
 529
 530 /* Flags in the "state" variable: */
 531 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 532 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 533 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 534 #define simPCOC0        (1 << 17) /* COC[1] from current */
 535 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 536 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 537 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 538 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 539 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 540
 541 #define ENGINE_ISSUE_PREFIX_HOOK() \
 542   { \
 543     /* Perform any pending writes */ \
 544     PENDING_TICK(); \
 545     /* Set previous flag, depending on current: */ \
 546     if (STATE & simPCOC0) \
 547      STATE |= simPCOC1; \
 548     else \
 549      STATE &= ~simPCOC1; \
 550     /* and update the current value: */ \
 551     if (GETFCC(0)) \
 552      STATE |= simPCOC0; \
 553     else \
 554      STATE &= ~simPCOC0; \
 555   }
 556
 557
 558 /* This is nasty, since we have to rely on matching the register
 559    numbers used by GDB. Unfortunately, depending on the MIPS target
 560    GDB uses different register numbers. We cannot just include the
 561    relevant "gdb/tm.h" link, since GDB may not be configured before
 562    the sim world, and also the GDB header file requires too much other
 563    state. */
 564
 565 #ifndef TM_MIPS_H
 566 #define LAST_EMBED_REGNUM (89)
 567 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 568 /* start-sanitize-r5900 */
 569 #undef NUM_REGS
 570 #define NUM_REGS (128)
 571 /* end-sanitize-r5900 */
 572 #endif
 573
 574 /* start-sanitize-sky */
 575 #ifdef TARGET_SKY
 576 #ifndef TM_TXVU_H
 577 /* Number of machine registers */
 578 #define NUM_VU_REGS     160
 579
 580 #define NUM_VU_INTEGER_REGS 16
 581 #define FIRST_VEC_REG   32
 582
 583 #define NUM_VIF_REGS    26
 584
 585 #define NUM_CORE_REGS   128
 586
 587 #undef NUM_REGS
 588 #define NUM_REGS (NUM_CORE_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
 589 #endif /* no tm-txvu.h */
 590 #endif /* TARGET_SKY */
 591 /* end-sanitize-sky */
 592
 593 enum float_operation
 594 /* start-sanitize-sky */
 595 /* NOTE: THE VALUES of THESE CONSTANTS MUST BE IN SYNC WITH THOSE IN WF.H */
 596 /* end-sanitize-sky */
 597   {
 598     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 599     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 600     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 601   };
 602
 603 /* To keep this default simulator simple, and fast, we use a direct
 604    vector of registers. The internal simulator engine then uses
 605    manifests to access the correct slot. */
 606
 607   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 608   int register_widths[NUM_REGS];
 609 #define REGISTERS       ((CPU)->registers)
 610
 611 #define GPR     (&REGISTERS[0])
 612 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 613
 614   /* While space is allocated for the floating point registers in the
 615      main registers array, they are stored separatly.  This is because
 616      their size may not necessarily match the size of either the
 617      general-purpose or system specific registers */
 618 #define NR_FGR  (32)
 619 #define FGRIDX  (38)
 620   fp_word fgr[NR_FGR];
 621 #define FGR     ((CPU)->fgr)
 622
 623 #define LO      (REGISTERS[33])
 624 #define HI      (REGISTERS[34])
 625 #define PCIDX   37
 626 #define PC      (REGISTERS[PCIDX])
 627 #define CAUSE   (REGISTERS[36])
 628 #define SRIDX   (32)
 629 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 630 #define FCR0IDX  (71)
 631 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 632 #define FCR31IDX (70)
 633 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 634 #define FCSR    (FCR31)
 635 #define Debug   (REGISTERS[86])
 636 #define DEPC    (REGISTERS[87])
 637 #define EPC     (REGISTERS[88])
 638 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 639
 640   unsigned_word c0_config_reg;
 641 #define C0_CONFIG ((CPU)->c0_config_reg)
 642
 643 /* The following are pseudonyms for standard registers */
 644 #define ZERO    (REGISTERS[0])
 645 #define V0      (REGISTERS[2])
 646 #define A0      (REGISTERS[4])
 647 #define A1      (REGISTERS[5])
 648 #define A2      (REGISTERS[6])
 649 #define A3      (REGISTERS[7])
 650 #define T8IDX   24
 651 #define T8      (REGISTERS[T8IDX])
 652 #define SPIDX   29
 653 #define SP      (REGISTERS[SPIDX])
 654 #define RAIDX   31
 655 #define RA      (REGISTERS[RAIDX])
 656
 657   /* While space is allocated in the main registers arrray for some of
 658      the COP0 registers, that space isn't sufficient.  Unknown COP0
 659      registers overflow into the array below */
 660
 661 #define NR_COP0_GPR     32
 662   unsigned_word cop0_gpr[NR_COP0_GPR];
 663 #define COP0_GPR        ((CPU)->cop0_gpr)
 664   /* start-sanitize-r5900 */
 665 #define NR_COP0_BP      8
 666   unsigned_word cop0_bp[NR_COP0_BP];
 667 #define COP0_BP ((CPU)->cop0_bp)
 668 #define NR_COP0_P 64
 669   unsigned_word cop0_p[NR_COP0_P];
 670 #define COP0_P  ((CPU)->cop0_p)
 671   /* end-sanitize-r5900 */
 672
 673
 674   /* Keep the current format state for each register: */
 675   FP_formats fpr_state[32];
 676 #define FPR_STATE ((CPU)->fpr_state)
 677
 678   pending_write_queue pending;
 679
 680   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 681      read-write instructions. It is set when a linked load occurs. It
 682      is tested and cleared by the conditional store. It is cleared
 683      (during other CPU operations) when a store to the location would
 684      no longer be atomic. In particular, it is cleared by exception
 685      return instructions. */
 686   int llbit;
 687 #define LLBIT ((CPU)->llbit)
 688
 689
 690 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 691    corruptions caused by using the HI or LO register too close to a
 692    following operation is spotted. See mips.igen for more details. */
 693
 694   hilo_history hi_history;
 695 #define HIHISTORY (&(CPU)->hi_history)
 696   hilo_history lo_history;
 697 #define LOHISTORY (&(CPU)->lo_history)
 698
 699   /* start-sanitize-branchbug4011 */
 700 #if 1
 701   int branchbug4011_option;
 702 #define BRANCHBUG4011_OPTION ((CPU)->branchbug4011_option)
 703   address_word branchbug4011_last_target;
 704 #define BRANCHBUG4011_LAST_TARGET ((CPU)->branchbug4011_last_target)
 705   address_word branchbug4011_last_cia;
 706 #define BRANCHBUG4011_LAST_CIA ((CPU)->branchbug4011_last_cia)
 707
 708 #define check_branch_bug() (check_4011_branch_bug (_SD))
 709 #define mark_branch_bug(TARGET) (mark_4011_branch_bug (_SD,TARGET))
 710 #else
 711   /* end-sanitize-branchbug4011 */
 712 #define check_branch_bug()
 713 #define mark_branch_bug(TARGET)
 714   /* start-sanitize-branchbug4011 */
 715 #endif
 716   /* end-sanitize-branchbug4011 */
 717   /* start-sanitize-r5900 */
 718   sim_r5900_cpu r5900;
 719
 720   /* end-sanitize-r5900 */
 721   /* start-sanitize-cygnus */
 722
 723   /* The MDMX ISA has a very very large accumulator */
 724   unsigned8 acc[3 * 8];
 725   /* end-sanitize-cygnus */
 726   /* start-sanitize-sky */
 727
 728 #ifdef TARGET_SKY
 729   /* Device on which instruction issue last occured.  */
 730   char cur_device;
 731 #endif
 732   /* end-sanitize-sky */
 733   sim_cpu_base base;
 734 };
 735
 736
 737 /* MIPS specific simulator watch config */
 738
 739 void watch_options_install PARAMS ((SIM_DESC sd));
 740
 741 struct swatch {
 742   sim_event *pc;
 743   sim_event *clock;
 744   sim_event *cycles;
 745 };
 746
 747
 748 /* FIXME: At present much of the simulator is still static */
 749 struct sim_state {
 750
 751   struct swatch watch;
 752
 753   sim_cpu cpu[MAX_NR_PROCESSORS];
 754 #if (WITH_SMP)
 755 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 756 #else
 757 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 758 #endif
 759
 760 /* start-sanitize-sky */
 761 #ifdef TARGET_SKY
 762 #ifdef SKY_FUNIT
 763   /* Record of option for floating point implementation type. */
 764   int fp_type_opt;
 765 #define STATE_FP_TYPE_OPT(sd) ((sd)->fp_type_opt)
 766 #define STATE_FP_TYPE_OPT_ACCURATE 0x80000000
 767 #endif
 768 #endif
 769 /* end-sanitize-sky */
 770
 771   sim_state_base base;
 772 };
 773
 774
 775
 776 /* Status information: */
 777
 778 /* TODO : these should be the bitmasks for these bits within the
 779    status register. At the moment the following are VR4300
 780    bit-positions: */
 781 #define status_KSU_mask  (0x3)          /* mask for KSU bits */
 782 #define status_KSU_shift (3)            /* shift for field */
 783 #define ksu_kernel       (0x0)
 784 #define ksu_supervisor   (0x1)
 785 #define ksu_user         (0x2)
 786 #define ksu_unknown      (0x3)
 787
 788 #define status_IE        (1 <<  0)      /* Interrupt enable */
 789 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 790 #define status_EXL       (1 <<  1)      /* Exception level */
 791 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 792 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 793 #define status_SR        (1 << 20)      /* soft reset or NMI */
 794 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 795 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 796 #define status_ERL       (1 <<  2)      /* Error level */
 797 #define status_RP        (1 << 27)      /* Reduced Power mode */
 798 /* start-sanitize-r5900 */
 799 #define status_CU0       (1 << 28)      /* COP0 usable */
 800 #define status_CU1       (1 << 29)      /* COP1 usable */
 801 #define status_CU2       (1 << 30)      /* COP2 usable */
 802 /* end-sanitize-r5900 */
 803
 804 /* Specializations for TX39 family */
 805 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 806 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 807 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 808 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 809 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 810 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 811 #define status_IM_mask   (0xff)         /* Interrupt mask */
 812 #define status_IM_shift  (8)
 813 #define status_NMI       (1 << 20)      /* NMI */
 814 #define status_NMI       (1 << 20)      /* NMI */
 815
 816 #define cause_EXC_mask  (0x1f)          /* Exception code */
 817 #define cause_EXC_shift (2)
 818 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 819 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 820 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 821 #define cause_IP_shift  (10)
 822 #define cause_CE_mask   (0x3)           /* Coprocessor error */
 823 #define cause_CE_shift  (28)
 824
 825 #define cause_BD  ((unsigned)1 << 31)   /* Exception in branch delay slot */
 826
 827
 828 /* NOTE: We keep the following status flags as bit values (1 for true,
 829    0 for false). This allows them to be used in binary boolean
 830    operations without worrying about what exactly the non-zero true
 831    value is. */
 832
 833 /* UserMode */
 834 #ifdef SUBTARGET_R3900
 835 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 836 #else
 837 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 838 #endif /* SUBTARGET_R3900 */
 839
 840 /* BigEndianMem */
 841 /* Hardware configuration. Affects endianness of LoadMemory and
 842    StoreMemory and the endianness of Kernel and Supervisor mode
 843    execution. The value is 0 for little-endian; 1 for big-endian. */
 844 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 845 /*(state & simBE) ? 1 : 0)*/
 846
 847 /* ReverseEndian */
 848 /* This mode is selected if in User mode with the RE bit being set in
 849    SR (Status Register). It reverses the endianness of load and store
 850    instructions. */
 851 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 852
 853 /* BigEndianCPU */
 854 /* The endianness for load and store instructions (0=little;1=big). In
 855    User mode this endianness may be switched by setting the state_RE
 856    bit in the SR register. Thus, BigEndianCPU may be computed as
 857    (BigEndianMem EOR ReverseEndian). */
 858 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 859
 860
 861
 862 /* Exceptions: */
 863
 864 /* NOTE: These numbers depend on the processor architecture being
 865    simulated: */
 866 #define Interrupt               (0)
 867 #define TLBModification         (1)
 868 #define TLBLoad                 (2)
 869 #define TLBStore                (3)
 870 #define AddressLoad             (4)
 871 #define AddressStore            (5)
 872 #define InstructionFetch        (6)
 873 #define DataReference           (7)
 874 #define SystemCall              (8)
 875 #define BreakPoint              (9)
 876 #define ReservedInstruction     (10)
 877 #define CoProcessorUnusable     (11)
 878 #define IntegerOverflow         (12)    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 879 #define Trap                    (13)
 880 #define FPE                     (15)
 881 #define DebugBreakPoint         (16)
 882 #define Watch                   (23)
 883 #define NMIReset                (31)
 884
 885
 886 /* The following exception code is actually private to the simulator
 887    world. It is *NOT* a processor feature, and is used to signal
 888    run-time errors in the simulator. */
 889 #define SimulatorFault      (0xFFFFFFFF)
 890
 891 /* The following break instructions are reserved for use by the
 892    simulator.  The first is used to halt the simulation.  The second
 893    is used by gdb for break-points.  NOTE: Care must be taken, since
 894    this value may be used in later revisions of the MIPS ISA. */
 895 #define HALT_INSTRUCTION_MASK  (0x03FFFFC0)
 896
 897 #define HALT_INSTRUCTION       (0x03ff000d)
 898 #define HALT_INSTRUCTION2      (0x0000ffcd)
 899
 900 /* start-sanitize-sky */
 901 #define HALT_INSTRUCTION_PASS    (0x03fffc0d)
 902 #define HALT_INSTRUCTION_FAIL    (0x03ffffcd)
 903 /* end-sanitize-sky */
 904
 905 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
 906 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
 907
 908
 909 void interrupt_event (SIM_DESC sd, void *data);
 910
 911 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 912 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 913 #define SignalExceptionInterrupt()           signal_exception (SD, CPU, cia, Interrupt)
 914 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 915 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 916 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 917 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 918 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 919 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 920 #define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
 921 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
 922
 923 /* Co-processor accesses */
 924
 925 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 926 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 927 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 928 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 929
 930 #define COP_LW(coproc_num,coproc_reg,memword) \
 931 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 932 #define COP_LD(coproc_num,coproc_reg,memword) \
 933 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 934 #define COP_SW(coproc_num,coproc_reg) \
 935 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 936 #define COP_SD(coproc_num,coproc_reg) \
 937 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 938
 939 /* start-sanitize-sky */
 940 #ifdef TARGET_SKY
 941 void cop_lq  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
 942                       int coproc_num, int coproc_reg, unsigned128 memword));
 943 unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
 944                             int coproc_num, int coproc_reg));
 945 #define COP_LQ(coproc_num,coproc_reg,memword) \
 946 cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
 947 #define COP_SQ(coproc_num,coproc_reg) \
 948 cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
 949 #endif /* TARGET_SKY */
 950 /* end-sanitize-sky */
 951
 952 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
 953 #define DecodeCoproc(instruction) \
 954 decode_coproc (SD, CPU, cia, (instruction))
 955
 956
 957
 958 /* Memory accesses */
 959
 960 /* The following are generic to all versions of the MIPS architecture
 961    to date: */
 962
 963 /* Memory Access Types (for CCA): */
 964 #define Uncached                (0)
 965 #define CachedNoncoherent       (1)
 966 #define CachedCoherent          (2)
 967 #define Cached                  (3)
 968
 969 #define isINSTRUCTION   (1 == 0) /* FALSE */
 970 #define isDATA          (1 == 1) /* TRUE */
 971 #define isLOAD          (1 == 0) /* FALSE */
 972 #define isSTORE         (1 == 1) /* TRUE */
 973 #define isREAL          (1 == 0) /* FALSE */
 974 #define isRAW           (1 == 1) /* TRUE */
 975 /* The parameter HOST (isTARGET / isHOST) is ignored */
 976 #define isTARGET        (1 == 0) /* FALSE */
 977 /* #define isHOST          (1 == 1) TRUE */
 978
 979 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 980    is the number of bytes minus 1. */
 981 #define AccessLength_BYTE       (0)
 982 #define AccessLength_HALFWORD   (1)
 983 #define AccessLength_TRIPLEBYTE (2)
 984 #define AccessLength_WORD       (3)
 985 #define AccessLength_QUINTIBYTE (4)
 986 #define AccessLength_SEXTIBYTE  (5)
 987 #define AccessLength_SEPTIBYTE  (6)
 988 #define AccessLength_DOUBLEWORD (7)
 989 #define AccessLength_QUADWORD   (15)
 990
 991 #if (WITH_IGEN)
 992 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 993                     ? AccessLength_DOUBLEWORD /*7*/ \
 994                     : AccessLength_WORD /*3*/)
 995 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 996 #endif
 997
 998
 999 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
1000 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
1001 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
1002
1003 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
1004 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
1005 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
1006
1007 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
1008 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
1009 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
1010
1011 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
1012 #define CacheOp(op,pAddr,vAddr,instruction) \
1013 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
1014
1015 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
1016 #define SyncOperation(stype) \
1017 sync_operation (SD, CPU, cia, (stype))
1018
1019 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
1020 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
1021 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
1022
1023 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
1024 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
1025 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
1026 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
1027 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
1028
1029 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
1030 extern FILE *tracefh;
1031
1032 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
1033
1034 char* pr_addr PARAMS ((SIM_ADDR addr));
1035 char* pr_uword64 PARAMS ((uword64 addr));
1036
1037 /* start-sanitize-sky */
1038 #ifdef TARGET_SKY
1039 #ifdef SIM_ENGINE_HALT_HOOK
1040 #undef SIM_ENGINE_HALT_HOOK
1041 #endif
1042
1043 void sky_sim_engine_halt PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
1044 #define SIM_ENGINE_HALT_HOOK(sd, last, cia) sky_sim_engine_halt(sd, last, cia)
1045
1046 #ifdef SIM_ENGINE_RESTART_HOOK
1047 #undef SIM_ENGINE_RESTART_HOOK
1048 #endif
1049
1050 void sky_sim_engine_restart PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
1051 #define SIM_ENGINE_RESTART_HOOK(sd, L, pc) sky_sim_engine_restart(sd, L, pc)
1052
1053 /* for resume/suspend modules */
1054 SIM_RC sky_sim_module_install PARAMS ((SIM_DESC sd));
1055
1056 #define MODULE_LIST     sky_sim_module_install,
1057
1058 #ifndef TM_TXVU_H /* In case GDB hasn't been configured yet */
1059 enum txvu_cpu_context
1060 {
1061   TXVU_CPU_AUTO         = -1,   /* context-sensitive context */
1062   TXVU_CPU_MASTER       = 0,    /* R5900 core */
1063   TXVU_CPU_VU0          = 1,    /* Vector units */
1064   TXVU_CPU_VU1          = 2,
1065   TXVU_CPU_VIF0         = 3,    /* FIFO's */
1066   TXVU_CPU_VIF1         = 4,
1067   TXVU_CPU_LAST                 /* Count of context types */
1068 };
1069
1070 /* memory segment for communication with GDB */
1071 #define VIO_BASE        0xa0000000
1072 #define GDB_COMM_AREA   0x19810000      /* Random choice */
1073 #define GDB_COMM_SIZE   0x4000
1074
1075 /* Memory address containing last device to execute */
1076 #define LAST_DEVICE     GDB_COMM_AREA
1077
1078 /* The FIFO breakpoint count and table */
1079 #define FIFO_BPT_CNT    (GDB_COMM_AREA + 4)
1080 #define FIFO_BPT_TBL    (GDB_COMM_AREA + 8)
1081
1082 /* Each element of the breakpoint table is three four-byte integers. */
1083 #define BPT_ELEM_SZ     4*3
1084
1085 #define TXVU_VU_BRK_MASK 0x02   /* Breakpoint bit is #57 for VU insns */
1086 #define TXVU_VIF_BRK_MASK 0x80  /* Use interrupt bit for VIF insns */
1087
1088 #endif /* !TM_TXVU_H */
1089 #endif /* TARGET_SKY */
1090 /* end-sanitize-sky */
1091
1092 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1093 #include "sim-main.c"
1094 #endif
1095
1096 #endif