sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA)
  26 #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA)
  27
  28 #define SIM_HAVE_BIENDIAN
  29 #define SIM_HAVE_FLATMEM
  30
  31
  32 /* hobble some common features for moment */
  33 #define WITH_PROFILE 0
  34 #define WITH_TRACE 0
  35 #define WITH_WATCHPOINTS 1
  36
  37 #include "sim-basics.h"
  38
  39
  40 #if 0
  41 /* These are generated files.  */
  42 #include "itable.h"
  43 #include "idecode.h"
  44 #include "idecode.h"
  45
  46 /* dummy - not used */
  47 typedef instruction_address sim_cia;
  48 static const sim_cia null_cia = {0}; /* dummy */
  49 #define NULL_CIA null_cia
  50 #else
  51 typedef int sim_cia;
  52 #endif
  53
  54
  55 #include "sim-base.h"
  56
  57
  58 /* Depreciated macros and types for manipulating 64bit values.  Use
  59    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  60
  61 typedef signed64 word64;
  62 typedef unsigned64 uword64;
  63
  64 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  65 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  66 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  67 #define SET64HI(t)      (((uword64)(t))<<32)
  68 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  69 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  70
  71 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  72    assume the HI32bits of the operand are zero, so we must perform a
  73    mask to ensure we can use the simple subtraction to sign-extend. */
  74 #define SIGNEXTEND(e,b) \
  75  ((unsigned_word) \
  76   (((e) & ((uword64) 1 << ((b) - 1))) \
  77    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  78    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  79
  80 /* Check if a value will fit within a halfword: */
  81 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  82
  83 /* windows always looses */
  84 #include <signal.h>
  85 #ifndef SIGBUS
  86 #define SIGBUS SIGSEGV
  87 #endif
  88 #ifdef _WIN32
  89 #define SIGTRAP 5
  90 #define SIGQUIT 3
  91 #endif
  92
  93
  94
  95 /* Floating-point operations: */
  96
  97 /* FPU registers must be one of the following types. All other values
  98    are reserved (and undefined). */
  99 typedef enum {
 100  fmt_single  = 0,
 101  fmt_double  = 1,
 102  fmt_word    = 4,
 103  fmt_long    = 5,
 104  /* The following are well outside the normal acceptable format
 105     range, and are used in the register status vector. */
 106  fmt_unknown       = 0x10000000,
 107  fmt_uninterpreted = 0x20000000,
 108 } FP_formats;
 109
 110 unsigned64 value_fpr PARAMS ((SIM_DESC sd, int fpr, FP_formats));
 111 #define ValueFPR(FPR,FMT) value_fpr (sd, (FPR), (FMT))
 112
 113 void store_fpr PARAMS ((SIM_DESC sd, int fpr, FP_formats fmt, unsigned64 value));
 114 #define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, (FPR), (FMT), (VALUE))
 115
 116 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
 117 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 118 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 119 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 120 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 121 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 122 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 123 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 124 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 125 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 126 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 127 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 128 unsigned64 convert PARAMS ((SIM_DESC sd, int rm, unsigned64 op, FP_formats from, FP_formats to));
 129 #define Convert(rm,op,from,to) convert(sd,rm,op,from,to)
 130
 131 /* Macro to update FPSR condition-code field. This is complicated by
 132    the fact that there is a hole in the index range of the bits within
 133    the FCSR register. Also, the number of bits visible depends on the
 134    MIPS ISA version being supported. */
 135
 136 #define SETFCC(cc,v) {\
 137   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 138   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 139 }
 140 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
 141
 142 /* This should be the COC1 value at the start of the preceding
 143    instruction: */
 144 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 145
 146 #if 1
 147 #define SizeFGR() (WITH_TARGET_WORD_BITSIZE)
 148 #else
 149 /* They depend on the CPU being simulated */
 150 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 151 #endif
 152
 153 /* Standard FCRS bits: */
 154 #define IR (0) /* Inexact Result */
 155 #define UF (1) /* UnderFlow */
 156 #define OF (2) /* OverFlow */
 157 #define DZ (3) /* Division by Zero */
 158 #define IO (4) /* Invalid Operation */
 159 #define UO (5) /* Unimplemented Operation */
 160
 161 /* Get masks for individual flags: */
 162 #if 1 /* SAFE version */
 163 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 164 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 165 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 166 #else
 167 #define FP_FLAGS(b)  (1 << ((b) + 2))
 168 #define FP_ENABLE(b) (1 << ((b) + 7))
 169 #define FP_CAUSE(b)  (1 << ((b) + 12))
 170 #endif
 171
 172 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 173
 174 #define FP_MASK_RM    (0x3)
 175 #define FP_SH_RM      (0)
 176 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 177 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 178 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 179 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 180 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 181
 182
 183
 184 /* Integer ALU operations: */
 185
 186 #include "sim-alu.h"
 187
 188 #define ALU32_END(ANS) \
 189   if (ALU32_HAD_OVERFLOW) \
 190     SignalExceptionIntegerOverflow (); \
 191   (ANS) = alu_overflow_val;
 192
 193
 194 #define ALU64_END(ANS) \
 195   if (ALU64_HAD_OVERFLOW) \
 196     SignalExceptionIntegerOverflow (); \
 197   (ANS) = alu_val;
 198
 199 /* start-sanitize-r5900 */
 200
 201 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 202 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 203 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 204 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 205
 206 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 207 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 208 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 209 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 210
 211 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 212    T  - type of the sub part
 213    TC - # of T's in the mips part of the "register"
 214    I  - index (from 0) of desired sub part
 215    A  - low part of "register"
 216    A1 - high part of register
 217 */
 218 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 219 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 220    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 221       ? ((TC) - 1 - (I) % (TC)) \
 222       : ((I) % (TC)) \
 223       ) \
 224    ) \
 225  )
 226
 227 /*
 228 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 229             where <type> has two letters:
 230                   1 is S=signed or U=unsigned
 231                   2 is B=byte H=halfword W=word D=doubleword
 232 */
 233
 234 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 235 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 236 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 237 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 238
 239 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 240 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 241 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 242 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 243
 244 #define GPR_SB(R,I) SUB_REG_SB(&REGISTERS[R], &REGISTERS1[R], I)
 245 #define GPR_SH(R,I) SUB_REG_SH(&REGISTERS[R], &REGISTERS1[R], I)
 246 #define GPR_SW(R,I) SUB_REG_SW(&REGISTERS[R], &REGISTERS1[R], I)
 247 #define GPR_SD(R,I) SUB_REG_SD(&REGISTERS[R], &REGISTERS1[R], I)
 248
 249 #define GPR_UB(R,I) SUB_REG_UB(&REGISTERS[R], &REGISTERS1[R], I)
 250 #define GPR_UH(R,I) SUB_REG_UH(&REGISTERS[R], &REGISTERS1[R], I)
 251 #define GPR_UW(R,I) SUB_REG_UW(&REGISTERS[R], &REGISTERS1[R], I)
 252 #define GPR_UD(R,I) SUB_REG_UD(&REGISTERS[R], &REGISTERS1[R], I)
 253
 254
 255 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 256 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 257 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 258 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 259
 260 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 261 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 262 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 263 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 264
 265 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 266 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 267 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 268 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 269
 270 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 271 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 272 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 273 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 274
 275
 276
 277 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 278 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 279 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 280 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 281
 282 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 283 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 284 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 285 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 286
 287 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 288 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 289 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 290 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 291
 292 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 293 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 294 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 295 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 296
 297 /* end-sanitize-r5900 */
 298
 299
 300
 301
 302 struct _sim_cpu {
 303
 304
 305   /* The following are internal simulator state variables: */
 306   sim_cia cia;
 307 #define CPU_CIA(CPU) ((CPU)->cia)
 308   address_word ipc; /* internal Instruction PC */
 309   address_word dspc;  /* delay-slot PC */
 310 #define IPC ((STATE_CPU (sd,0))->ipc)
 311 #define DSPC ((STATE_CPU (sd,0))->dspc)
 312
 313 #define NULLIFY_NIA() { nia.ip = cia.dp + 4; nia.dp = nia.ip += 4; }
 314
 315
 316
 317   /* State of the simulator */
 318   unsigned int state;
 319   unsigned int dsstate;
 320 #define STATE ((STATE_CPU (sd,0))->state)
 321 #define DSSTATE ((STATE_CPU (sd,0))->dsstate)
 322
 323 /* Flags in the "state" variable: */
 324 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 325 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 326 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 327 #define simPROFILE      (1 << 9)  /* 0 = do nothing; 1 = gather profiling samples */
 328 #define simPCOC0        (1 << 17) /* COC[1] from current */
 329 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 330 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 331 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 332 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 333 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 334
 335
 336
 337
 338 /* This is nasty, since we have to rely on matching the register
 339    numbers used by GDB. Unfortunately, depending on the MIPS target
 340    GDB uses different register numbers. We cannot just include the
 341    relevant "gdb/tm.h" link, since GDB may not be configured before
 342    the sim world, and also the GDB header file requires too much other
 343    state. */
 344
 345 #ifndef TM_MIPS_H
 346 #define LAST_EMBED_REGNUM (89)
 347 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 348 /* start-sanitize-r5900 */
 349 #undef NUM_REGS
 350 #define NUM_REGS (128)
 351 /* end-sanitize-r5900 */
 352 #endif
 353
 354 /* To keep this default simulator simple, and fast, we use a direct
 355    vector of registers. The internal simulator engine then uses
 356    manifests to access the correct slot. */
 357
 358   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 359   int register_widths[NUM_REGS];
 360 #define REGISTERS       ((STATE_CPU (sd,0))->registers)
 361
 362 #define GPR     (&REGISTERS[0])
 363 #define FGRIDX  (38)
 364 #define FGR     (&REGISTERS[FGRIDX])
 365 #define LO      (REGISTERS[33])
 366 #define HI      (REGISTERS[34])
 367 #define PC      (REGISTERS[37])
 368 #define CAUSE   (REGISTERS[36])
 369 #define SRIDX   (32)
 370 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 371 #define FCR0IDX  (71)
 372 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 373 #define FCR31IDX (70)
 374 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 375 #define FCSR    (FCR31)
 376 #define Debug   (REGISTERS[86])
 377 #define DEPC    (REGISTERS[87])
 378 #define EPC     (REGISTERS[88])
 379 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 380
 381 /* The following are pseudonyms for standard registers */
 382 #define ZERO    (REGISTERS[0])
 383 #define V0      (REGISTERS[2])
 384 #define A0      (REGISTERS[4])
 385 #define A1      (REGISTERS[5])
 386 #define A2      (REGISTERS[6])
 387 #define A3      (REGISTERS[7])
 388 #define SP      (REGISTERS[29])
 389 #define RA      (REGISTERS[31])
 390
 391   /* Keep the current format state for each register: */
 392   FP_formats fpr_state[32];
 393 #define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state)
 394
 395
 396   /* Slots for delayed register updates. For the moment we just have a
 397      fixed number of slots (rather than a more generic, dynamic
 398      system). This keeps the simulator fast. However, we only allow
 399      for the register update to be delayed for a single instruction
 400      cycle. */
 401 #define PSLOTS (5) /* Maximum number of instruction cycles */
 402   int pending_in;
 403   int pending_out;
 404   int pending_total;
 405   int pending_slot_count[PSLOTS];
 406   int pending_slot_reg[PSLOTS];
 407   unsigned_word pending_slot_value[PSLOTS];
 408 #define PENDING_IN ((STATE_CPU (sd, 0))->pending_in)
 409 #define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out)
 410 #define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total)
 411 #define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count)
 412 #define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg)
 413 #define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value)
 414
 415   /* The following are not used for MIPS IV onwards: */
 416 #define PENDING_FILL(r,v) {\
 417 /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
 418                             if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
 419                              sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
 420                             PENDING_SLOT_COUNT[PENDING_IN] = 2;\
 421                             PENDING_SLOT_REG[PENDING_IN] = (r);\
 422                             PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
 423 /*printf("DBG: FILL        reg %d value = 0x%s\n",(r),pr_addr(v));*/\
 424                             PENDING_TOTAL++;\
 425                             PENDING_IN++;\
 426                             if (PENDING_IN == PSLOTS)\
 427                              PENDING_IN = 0;\
 428 /*printf("DBG: FILL AFTER  pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
 429                           }
 430
 431
 432   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 433      read-write instructions. It is set when a linked load occurs. It
 434      is tested and cleared by the conditional store. It is cleared
 435      (during other CPU operations) when a store to the location would
 436      no longer be atomic. In particular, it is cleared by exception
 437      return instructions. */
 438   int llbit;
 439 #define LLBIT ((STATE_CPU (sd, 0))->llbit)
 440
 441
 442 /* The HIACCESS and LOACCESS counts are used to ensure that
 443    corruptions caused by using the HI or LO register to close to a
 444    following operation are spotted. */
 445
 446   int hiaccess;
 447   int loaccess;
 448 #define HIACCESS ((STATE_CPU (sd, 0))->hiaccess)
 449 #define LOACCESS ((STATE_CPU (sd, 0))->loaccess)
 450   /* start-sanitize-r5900 */
 451   int hi1access;
 452   int lo1access;
 453 #define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access)
 454 #define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access)
 455   /* end-sanitize-r5900 */
 456 #if 1
 457   /* The 4300 and a few other processors have interlocks on hi/lo
 458      register reads, and hence do not have this problem.  To avoid
 459      spurious warnings, we just disable this always.  */
 460 #define CHECKHILO(s)
 461 #else
 462   unsigned_word HLPC;
 463   /* If either of the preceding two instructions have accessed the HI
 464      or LO registers, then the values they see should be
 465      undefined. However, to keep the simulator world simple, we just
 466      let them use the value read and raise a warning to notify the
 467      user: */
 468 #define CHECKHILO(s) {\
 469   if ((HIACCESS != 0) || (LOACCESS != 0)) \
 470     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 471 }
 472   /* end-sanitize-r5900 */
 473 #undef CHECKHILO
 474 #define CHECKHILO(s) {\
 475   if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
 476     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 477 }
 478   /* end-sanitize-r5900 */
 479 #endif
 480
 481
 482   /* start-sanitize-r5900 */
 483   /* The R5900 has 128 bit registers, but the hi 64 bits are only
 484      touched by multimedia (MMI) instructions.  The normal mips
 485      instructions just use the lower 64 bits.  To avoid changing the
 486      older parts of the simulator to handle this weirdness, the high
 487      64 bits of each register are kept in a separate array
 488      (registers1).  The high 64 bits of any register are by convention
 489      refered by adding a '1' to the end of the normal register's name.
 490      So LO still refers to the low 64 bits of the LO register, LO1
 491      refers to the high 64 bits of that same register.  */
 492
 493   signed_word registers1[LAST_EMBED_REGNUM + 1];
 494 #define REGISTERS1 ((STATE_CPU (sd, 0))->registers1)
 495 #define GPR1     (&REGISTERS1[0])
 496 #define LO1      (REGISTERS1[32])
 497 #define HI1      (REGISTERS1[33])
 498 #define REGISTER_SA     (124)
 499
 500   unsigned_word sa;        /* the shift amount register */
 501 #define SA ((STATE_CPU (sd, 0))->sa)
 502
 503   /* end-sanitize-r5900 */
 504
 505
 506
 507   sim_cpu_base base;
 508 };
 509
 510
 511 /* MIPS specific simulator watch config */
 512
 513 void watch_options_install PARAMS ((SIM_DESC sd));
 514
 515 struct swatch {
 516   sim_event *pc;
 517   sim_event *clock;
 518   sim_event *cycles;
 519 };
 520
 521
 522 /* FIXME: At present much of the simulator is still static */
 523 struct sim_state {
 524
 525   struct swatch watch;
 526
 527   sim_cpu cpu[1];
 528 #if (WITH_SMP)
 529 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 530 #else
 531 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 532 #endif
 533
 534   sim_state_base base;
 535 };
 536
 537
 538
 539 /* Status information: */
 540
 541 /* TODO : these should be the bitmasks for these bits within the
 542    status register. At the moment the following are VR4300
 543    bit-positions: */
 544 #define status_KSU_mask  (0x3)          /* mask for KSU bits */
 545 #define status_KSU_shift (3)            /* shift for field */
 546 #define ksu_kernel       (0x0)
 547 #define ksu_supervisor   (0x1)
 548 #define ksu_user         (0x2)
 549 #define ksu_unknown      (0x3)
 550
 551 #define status_IE        (1 <<  0)      /* Interrupt enable */
 552 #define status_EXL       (1 <<  1)      /* Exception level */
 553 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 554 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 555 #define status_SR        (1 << 20)      /* soft reset or NMI */
 556 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 557 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 558 #define status_ERL       (1 <<  2)      /* Error level */
 559 #define status_RP        (1 << 27)      /* Reduced Power mode */
 560
 561 #define cause_BD        ((unsigned)1 << 31)     /* Exception in branch delay slot */
 562
 563 /* NOTE: We keep the following status flags as bit values (1 for true,
 564    0 for false). This allows them to be used in binary boolean
 565    operations without worrying about what exactly the non-zero true
 566    value is. */
 567
 568 /* UserMode */
 569 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 570
 571 /* BigEndianMem */
 572 /* Hardware configuration. Affects endianness of LoadMemory and
 573    StoreMemory and the endianness of Kernel and Supervisor mode
 574    execution. The value is 0 for little-endian; 1 for big-endian. */
 575 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 576 /*(state & simBE) ? 1 : 0)*/
 577
 578 /* ByteSwapMem */
 579 /* This is true if the host and target have different endianness.  */
 580 #define ByteSwapMem (CURRENT_TARGET_BYTE_ORDER != CURRENT_HOST_BYTE_ORDER)
 581
 582 /* ReverseEndian */
 583 /* This mode is selected if in User mode with the RE bit being set in
 584    SR (Status Register). It reverses the endianness of load and store
 585    instructions. */
 586 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 587
 588 /* BigEndianCPU */
 589 /* The endianness for load and store instructions (0=little;1=big). In
 590    User mode this endianness may be switched by setting the state_RE
 591    bit in the SR register. Thus, BigEndianCPU may be computed as
 592    (BigEndianMem EOR ReverseEndian). */
 593 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 594
 595
 596
 597 /* Exceptions: */
 598
 599 /* NOTE: These numbers depend on the processor architecture being
 600    simulated: */
 601 #define Interrupt               (0)
 602 #define TLBModification         (1)
 603 #define TLBLoad                 (2)
 604 #define TLBStore                (3)
 605 #define AddressLoad             (4)
 606 #define AddressStore            (5)
 607 #define InstructionFetch        (6)
 608 #define DataReference           (7)
 609 #define SystemCall              (8)
 610 #define BreakPoint              (9)
 611 #define ReservedInstruction     (10)
 612 #define CoProcessorUnusable     (11)
 613 #define IntegerOverflow         (12)    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 614 #define Trap                    (13)
 615 #define FPE                     (15)
 616 #define DebugBreakPoint         (16)
 617 #define Watch                   (23)
 618
 619 /* The following exception code is actually private to the simulator
 620    world. It is *NOT* a processor feature, and is used to signal
 621    run-time errors in the simulator. */
 622 #define SimulatorFault      (0xFFFFFFFF)
 623
 624 void signal_exception (SIM_DESC sd, int exception, ...);
 625 #define SignalException(exc,instruction) signal_exception (sd, (exc), (instruction))
 626 #define SignalExceptionInterrupt() signal_exception (sd, Interrupt)
 627 #define SignalExceptionInstructionFetch() signal_exception (sd, InstructionFetch)
 628 #define SignalExceptionAddressStore() signal_exception (sd, AddressStore)
 629 #define SignalExceptionAddressLoad() signal_exception (sd, AddressLoad)
 630 #define SignalExceptionSimulatorFault(buf) signal_exception (sd, SimulatorFault, buf)
 631 #define SignalExceptionFPE() signal_exception (sd, FPE)
 632 #define SignalExceptionIntegerOverflow() signal_exception (sd, IntegerOverflow)
 633 #define SignalExceptionCoProcessorUnusable() signal_exception (sd, CoProcessorUnusable)
 634
 635
 636 /* Co-processor accesses */
 637
 638 void cop_lw  PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg, unsigned int memword));
 639 void cop_ld  PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg, uword64 memword));
 640 unsigned int cop_sw PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg));
 641 uword64 cop_sd PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg));
 642
 643 #define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,coproc_num,coproc_reg,memword)
 644 #define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,coproc_num,coproc_reg,memword)
 645 #define COP_SW(coproc_num,coproc_reg) cop_sw(sd,coproc_num,coproc_reg)
 646 #define COP_SD(coproc_num,coproc_reg) cop_sd(sd,coproc_num,coproc_reg)
 647
 648 void decode_coproc PARAMS ((SIM_DESC sd,unsigned int instruction));
 649 #define DecodeCoproc(instruction) decode_coproc(sd, (instruction))
 650
 651
 652
 653 /* Memory accesses */
 654
 655 /* The following are generic to all versions of the MIPS architecture
 656    to date: */
 657
 658 /* Memory Access Types (for CCA): */
 659 #define Uncached                (0)
 660 #define CachedNoncoherent       (1)
 661 #define CachedCoherent          (2)
 662 #define Cached                  (3)
 663
 664 #define isINSTRUCTION   (1 == 0) /* FALSE */
 665 #define isDATA          (1 == 1) /* TRUE */
 666 #define isLOAD          (1 == 0) /* FALSE */
 667 #define isSTORE         (1 == 1) /* TRUE */
 668 #define isREAL          (1 == 0) /* FALSE */
 669 #define isRAW           (1 == 1) /* TRUE */
 670 #define isTARGET        (1 == 0) /* FALSE */
 671 #define isHOST          (1 == 1) /* TRUE */
 672
 673 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 674    is the number of bytes minus 1. */
 675 #define AccessLength_BYTE       (0)
 676 #define AccessLength_HALFWORD   (1)
 677 #define AccessLength_TRIPLEBYTE (2)
 678 #define AccessLength_WORD       (3)
 679 #define AccessLength_QUINTIBYTE (4)
 680 #define AccessLength_SEXTIBYTE  (5)
 681 #define AccessLength_SEPTIBYTE  (6)
 682 #define AccessLength_DOUBLEWORD (7)
 683 #define AccessLength_QUADWORD   (15)
 684
 685 int address_translation PARAMS ((SIM_DESC sd, uword64 vAddr, int IorD, int LorS, uword64 *pAddr, int *CCA, int host, int raw));
 686 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 687 address_translation(sd, vAddr,IorD,LorS,pAddr,CCA,host,raw)
 688
 689 void load_memory PARAMS ((SIM_DESC sd, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, uword64 pAddr, uword64 vAddr, int IorD, int raw));
 690 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 691 load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw)
 692
 693 void store_memory PARAMS ((SIM_DESC sd, int CCA, int AccessLength, uword64 MemElem,     uword64 MemElem1, uword64 pAddr, uword64 vAddr, int raw));
 694 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 695 store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw)
 696
 697 void cache_op PARAMS ((SIM_DESC sd, int op, uword64 pAddr, uword64 vAddr, unsigned int instruction));
 698 #define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,op,pAddr,vAddr,instruction)
 699
 700 void sync_operation PARAMS ((SIM_DESC sd, int stype));
 701 #define SyncOperation(stype) sync_operation (sd, (stype))
 702
 703 void prefetch PARAMS ((SIM_DESC sd, int CCA, uword64 pAddr, uword64 vAddr, int DATA, int hint));
 704 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,CCA,pAddr,vAddr,DATA,hint)
 705
 706 #define IMEM(CIA) 0 /* FIXME */
 707
 708
 709 #endif