1 /* Copyright (C) 1998, Cygnus Solutions */
10 #include "sim-assert.h"
13 #include "sky-gpuif.h"
14 #include "sky-device.h"
25 /* Internal function declarations */
27 static int pke_io_read_buffer(device
*, void*, int, address_word
,
28 unsigned, sim_cpu
*, sim_cia
);
29 static int pke_io_write_buffer(device
*, const void*, int, address_word
,
30 unsigned, sim_cpu
*, sim_cia
);
31 static void pke_reset(struct pke_device
*);
32 static void pke_issue(SIM_DESC
, struct pke_device
*);
33 static void pke_pc_advance(struct pke_device
*, int num_words
);
34 static struct fifo_quadword
* pke_pcrel_fifo(struct pke_device
*, int operand_num
,
35 unsigned_4
** operand
);
36 static unsigned_4
* pke_pcrel_operand(struct pke_device
*, int operand_num
);
37 static unsigned_4
pke_pcrel_operand_bits(struct pke_device
*, int bit_offset
,
38 int bit_width
, unsigned_4
* sourceaddr
);
39 static void pke_attach(SIM_DESC sd
, struct pke_device
* me
);
40 enum pke_check_target
{ chk_vu
, chk_path1
, chk_path2
, chk_path3
};
41 static int pke_check_stall(struct pke_device
* me
, enum pke_check_target what
);
42 static void pke_flip_dbf(struct pke_device
* me
);
43 static void pke_begin_interrupt_stall(struct pke_device
* me
);
44 /* PKEcode handlers */
45 static void pke_code_nop(struct pke_device
* me
, unsigned_4 pkecode
);
46 static void pke_code_stcycl(struct pke_device
* me
, unsigned_4 pkecode
);
47 static void pke_code_offset(struct pke_device
* me
, unsigned_4 pkecode
);
48 static void pke_code_base(struct pke_device
* me
, unsigned_4 pkecode
);
49 static void pke_code_itop(struct pke_device
* me
, unsigned_4 pkecode
);
50 static void pke_code_stmod(struct pke_device
* me
, unsigned_4 pkecode
);
51 static void pke_code_mskpath3(struct pke_device
* me
, unsigned_4 pkecode
);
52 static void pke_code_pkemark(struct pke_device
* me
, unsigned_4 pkecode
);
53 static void pke_code_flushe(struct pke_device
* me
, unsigned_4 pkecode
);
54 static void pke_code_flush(struct pke_device
* me
, unsigned_4 pkecode
);
55 static void pke_code_flusha(struct pke_device
* me
, unsigned_4 pkecode
);
56 static void pke_code_pkemscal(struct pke_device
* me
, unsigned_4 pkecode
);
57 static void pke_code_pkemscnt(struct pke_device
* me
, unsigned_4 pkecode
);
58 static void pke_code_pkemscalf(struct pke_device
* me
, unsigned_4 pkecode
);
59 static void pke_code_stmask(struct pke_device
* me
, unsigned_4 pkecode
);
60 static void pke_code_strow(struct pke_device
* me
, unsigned_4 pkecode
);
61 static void pke_code_stcol(struct pke_device
* me
, unsigned_4 pkecode
);
62 static void pke_code_mpg(struct pke_device
* me
, unsigned_4 pkecode
);
63 static void pke_code_direct(struct pke_device
* me
, unsigned_4 pkecode
);
64 static void pke_code_directhl(struct pke_device
* me
, unsigned_4 pkecode
);
65 static void pke_code_unpack(struct pke_device
* me
, unsigned_4 pkecode
);
66 static void pke_code_error(struct pke_device
* me
, unsigned_4 pkecode
);
72 struct pke_device pke0_device
=
74 { "pke0", &pke_io_read_buffer
, &pke_io_write_buffer
}, /* device */
77 {}, 0, /* FIFO write buffer */
78 { NULL
, 0, 0, 0 }, /* FIFO */
79 NULL
, /* FIFO trace file */
80 -1, -1, 0, 0, 0, /* invalid FIFO cache */
85 struct pke_device pke1_device
=
87 { "pke1", &pke_io_read_buffer
, &pke_io_write_buffer
}, /* device */
90 {}, 0, /* FIFO write buffer */
91 { NULL
, 0, 0, 0 }, /* FIFO */
92 NULL
, /* FIFO trace file */
93 -1, -1, 0, 0, 0, /* invalid FIFO cache */
99 /* External functions */
102 /* Attach PKE addresses to main memory */
105 pke0_attach(SIM_DESC sd
)
107 pke_attach(sd
, & pke0_device
);
108 pke_reset(& pke0_device
);
112 pke1_attach(SIM_DESC sd
)
114 pke_attach(sd
, & pke1_device
);
115 pke_reset(& pke1_device
);
120 /* Issue a PKE instruction if possible */
123 pke0_issue(SIM_DESC sd
)
125 pke_issue(sd
, & pke0_device
);
129 pke1_issue(SIM_DESC sd
)
131 pke_issue(sd
, & pke1_device
);
136 /* Internal functions */
139 /* Attach PKE memory regions to simulator */
142 pke_attach(SIM_DESC sd
, struct pke_device
* me
)
145 sim_core_attach (sd
, NULL
, 0, access_read_write
, 0,
146 (me
->pke_number
== 0) ? PKE0_REGISTER_WINDOW_START
: PKE1_REGISTER_WINDOW_START
,
147 PKE_REGISTER_WINDOW_SIZE
/*nr_bytes*/,
153 sim_core_attach (sd
, NULL
, 0, access_read_write
, 0,
154 (me
->pke_number
== 0) ? PKE0_FIFO_ADDR
: PKE1_FIFO_ADDR
,
155 sizeof(quadword
) /*nr_bytes*/,
160 /* VU MEM0 tracking table */
161 sim_core_attach (sd
, NULL
, 0, access_read_write
, 0,
162 ((me
->pke_number
== 0) ? VU0_MEM0_SRCADDR_START
: VU1_MEM0_SRCADDR_START
),
163 ((me
->pke_number
== 0) ? VU0_MEM0_SIZE
: VU1_MEM0_SIZE
) / 2,
168 /* VU MEM1 tracking table */
169 sim_core_attach (sd
, NULL
, 0, access_read_write
, 0,
170 ((me
->pke_number
== 0) ? VU0_MEM1_SRCADDR_START
: VU1_MEM1_SRCADDR_START
),
171 ((me
->pke_number
== 0) ? VU0_MEM1_SIZE
: VU1_MEM1_SIZE
) / 4,
177 /* attach to trace file if appropriate */
179 char trace_envvar
[80];
180 char* trace_filename
= NULL
;
181 sprintf(trace_envvar
, "VIF%d_TRACE_FILE", me
->pke_number
);
182 trace_filename
= getenv(trace_envvar
);
183 if(trace_filename
!= NULL
)
185 me
->fifo_trace_file
= fopen(trace_filename
, "w");
186 if(me
->fifo_trace_file
== NULL
)
187 perror("VIF FIFO trace error on fopen");
189 setvbuf(me
->fifo_trace_file
, NULL
, _IOLBF
, 0);
196 /* Handle a PKE read; return no. of bytes read */
199 pke_io_read_buffer(device
*me_
,
207 /* downcast to gather embedding pke_device struct */
208 struct pke_device
* me
= (struct pke_device
*) me_
;
210 /* find my address ranges */
211 address_word my_reg_start
=
212 (me
->pke_number
== 0) ? PKE0_REGISTER_WINDOW_START
: PKE1_REGISTER_WINDOW_START
;
213 address_word my_fifo_addr
=
214 (me
->pke_number
== 0) ? PKE0_FIFO_ADDR
: PKE1_FIFO_ADDR
;
216 /* enforce that an access does not span more than one quadword */
217 address_word low
= ADDR_TRUNC_QW(addr
);
218 address_word high
= ADDR_TRUNC_QW(addr
+ nr_bytes
- 1);
222 /* classify address & handle */
223 if((addr
>= my_reg_start
) && (addr
< my_reg_start
+ PKE_REGISTER_WINDOW_SIZE
))
226 int reg_num
= ADDR_TRUNC_QW(addr
- my_reg_start
) >> 4;
227 int reg_byte
= ADDR_OFFSET_QW(addr
); /* find byte-offset inside register bank */
232 result
[0] = result
[1] = result
[2] = result
[3] = 0;
234 /* handle reads to individual registers; clear `readable' on error */
237 /* handle common case of register reading, side-effect free */
238 /* PKE1-only registers*/
244 if(me
->pke_number
== 0)
247 /* PKE0 & PKE1 common registers*/
266 result
[0] = H2T_4(me
->regs
[reg_num
][0]);
269 /* handle common case of write-only registers */
275 ASSERT(0); /* test above should prevent this possibility */
278 /* perform transfer & return */
282 memcpy(dest
, ((unsigned_1
*) &result
) + reg_byte
, nr_bytes
);
287 /* return zero bits */
288 memset(dest
, 0, nr_bytes
);
294 else if(addr
>= my_fifo_addr
&&
295 addr
< my_fifo_addr
+ sizeof(quadword
))
299 /* FIFO is not readable: return a word of zeroes */
300 memset(dest
, 0, nr_bytes
);
309 /* Handle a PKE read; return no. of bytes written */
312 pke_io_write_buffer(device
*me_
,
320 /* downcast to gather embedding pke_device struct */
321 struct pke_device
* me
= (struct pke_device
*) me_
;
323 /* find my address ranges */
324 address_word my_reg_start
=
325 (me
->pke_number
== 0) ? PKE0_REGISTER_WINDOW_START
: PKE1_REGISTER_WINDOW_START
;
326 address_word my_fifo_addr
=
327 (me
->pke_number
== 0) ? PKE0_FIFO_ADDR
: PKE1_FIFO_ADDR
;
329 /* enforce that an access does not span more than one quadword */
330 address_word low
= ADDR_TRUNC_QW(addr
);
331 address_word high
= ADDR_TRUNC_QW(addr
+ nr_bytes
- 1);
335 /* classify address & handle */
336 if((addr
>= my_reg_start
) && (addr
< my_reg_start
+ PKE_REGISTER_WINDOW_SIZE
))
339 int reg_num
= ADDR_TRUNC_QW(addr
- my_reg_start
) >> 4;
340 int reg_byte
= ADDR_OFFSET_QW(addr
); /* find byte-offset inside register bank */
345 input
[0] = input
[1] = input
[2] = input
[3] = 0;
347 /* write user-given bytes into input */
348 memcpy(((unsigned_1
*) &input
) + reg_byte
, src
, nr_bytes
);
350 /* make words host-endian */
351 input
[0] = T2H_4(input
[0]);
352 /* we may ignore other words */
354 /* handle writes to individual registers; clear `writeable' on error */
358 /* Order these tests from least to most overriding, in case
359 multiple bits are set. */
360 if(BIT_MASK_GET(input
[0], PKE_REG_FBRST_STC_B
, PKE_REG_FBRST_STC_E
))
362 /* clear a bunch of status bits */
363 PKE_REG_MASK_SET(me
, STAT
, PSS
, 0);
364 PKE_REG_MASK_SET(me
, STAT
, PFS
, 0);
365 PKE_REG_MASK_SET(me
, STAT
, PIS
, 0);
366 PKE_REG_MASK_SET(me
, STAT
, INT
, 0);
367 PKE_REG_MASK_SET(me
, STAT
, ER0
, 0);
368 PKE_REG_MASK_SET(me
, STAT
, ER1
, 0);
369 me
->flags
&= ~PKE_FLAG_PENDING_PSS
;
370 /* will allow resumption of possible stalled instruction */
372 if(BIT_MASK_GET(input
[0], PKE_REG_FBRST_STP_B
, PKE_REG_FBRST_STP_E
))
374 me
->flags
|= PKE_FLAG_PENDING_PSS
;
376 if(BIT_MASK_GET(input
[0], PKE_REG_FBRST_FBK_B
, PKE_REG_FBRST_FBK_E
))
378 PKE_REG_MASK_SET(me
, STAT
, PFS
, 1);
380 if(BIT_MASK_GET(input
[0], PKE_REG_FBRST_RST_B
, PKE_REG_FBRST_RST_E
))
387 /* copy bottom three bits */
388 BIT_MASK_SET(me
->regs
[PKE_REG_ERR
][0], 0, 2, BIT_MASK_GET(input
[0], 0, 2));
392 /* copy bottom sixteen bits */
393 PKE_REG_MASK_SET(me
, MARK
, MARK
, BIT_MASK_GET(input
[0], 0, 15));
394 /* reset MRK bit in STAT */
395 PKE_REG_MASK_SET(me
, STAT
, MRK
, 0);
398 /* handle common case of read-only registers */
399 /* PKE1-only registers - not really necessary to handle separately */
405 if(me
->pke_number
== 0)
408 /* PKE0 & PKE1 common registers*/
410 /* ignore FDR bit for PKE1_STAT -- simulator does not implement PKE->RAM transfers */
430 ASSERT(0); /* test above should prevent this possibility */
443 else if(addr
>= my_fifo_addr
&&
444 addr
< my_fifo_addr
+ sizeof(quadword
))
447 struct fifo_quadword
* fqw
;
448 int fifo_byte
= ADDR_OFFSET_QW(addr
); /* find byte-offset inside fifo quadword */
449 unsigned_4 dma_tag_present
= 0;
452 /* collect potentially-partial quadword in write buffer; LE byte order */
453 memcpy(((unsigned_1
*)& me
->fifo_qw_in_progress
) + fifo_byte
, src
, nr_bytes
);
454 /* mark bytes written */
455 for(i
= fifo_byte
; i
< fifo_byte
+ nr_bytes
; i
++)
456 BIT_MASK_SET(me
->fifo_qw_done
, i
, i
, 1);
458 /* return if quadword not quite written yet */
459 if(BIT_MASK_GET(me
->fifo_qw_done
, 0, sizeof(quadword
)-1) !=
460 BIT_MASK_BTW(0, sizeof(quadword
)-1))
463 /* all done - process quadword after clearing flag */
464 BIT_MASK_SET(me
->fifo_qw_done
, 0, sizeof(quadword
)-1, 0);
466 /* allocate required address in FIFO */
467 fqw
= pke_fifo_fit(& me
->fifo
);
470 /* fill in unclassified FIFO quadword data in host byte order */
471 fqw
->word_class
[0] = fqw
->word_class
[1] =
472 fqw
->word_class
[2] = fqw
->word_class
[3] = wc_unknown
;
473 fqw
->data
[0] = T2H_4(me
->fifo_qw_in_progress
[0]);
474 fqw
->data
[1] = T2H_4(me
->fifo_qw_in_progress
[1]);
475 fqw
->data
[2] = T2H_4(me
->fifo_qw_in_progress
[2]);
476 fqw
->data
[3] = T2H_4(me
->fifo_qw_in_progress
[3]);
478 /* read DMAC-supplied indicators */
479 ASSERT(sizeof(unsigned_4
) == 4);
480 PKE_MEM_READ(me
, (me
->pke_number
== 0 ? DMA_D0_MADR
: DMA_D1_MADR
),
481 & fqw
->source_address
, /* converted to host-endian */
483 PKE_MEM_READ(me
, (me
->pke_number
== 0 ? DMA_D0_PKTFLAG
: DMA_D1_PKTFLAG
),
489 /* lower two words are DMA tags */
490 fqw
->word_class
[0] = fqw
->word_class
[1] = wc_dma
;
493 /* set FQC to "1" as FIFO is now not empty */
494 PKE_REG_MASK_SET(me
, STAT
, FQC
, 1);
508 pke_reset(struct pke_device
* me
)
510 /* advance PC over last quadword in FIFO; keep previous FIFO history */
511 me
->fifo_pc
= pke_fifo_flush(& me
->fifo
);
513 /* clear registers, flag, other state */
514 memset(me
->regs
, 0, sizeof(me
->regs
));
515 me
->fifo_qw_done
= 0;
521 /* Issue & swallow next PKE opcode if possible/available */
524 pke_issue(SIM_DESC sd
, struct pke_device
* me
)
526 struct fifo_quadword
* fqw
;
528 unsigned_4 cmd
, intr
;
530 /* 1 -- fetch PKE instruction */
532 /* confirm availability of new quadword of PKE instructions */
533 fqw
= pke_fifo_access(& me
->fifo
, me
->fifo_pc
);
537 /* skip over DMA tag, if present */
538 pke_pc_advance(me
, 0);
539 /* note: this can only change qw_pc from 0 to 2 and will not
542 /* "fetch" instruction quadword and word */
543 fw
= fqw
->data
[me
->qw_pc
];
545 /* store word in PKECODE register */
546 me
->regs
[PKE_REG_CODE
][0] = fw
;
549 /* 2 -- test go / no-go for PKE execution */
551 /* switch on STAT:PSS if PSS-pending and in idle state */
552 if((PKE_REG_MASK_GET(me
, STAT
, PPS
) == PKE_REG_STAT_PPS_IDLE
) &&
553 (me
->flags
& PKE_FLAG_PENDING_PSS
) != 0)
555 me
->flags
&= ~PKE_FLAG_PENDING_PSS
;
556 PKE_REG_MASK_SET(me
, STAT
, PSS
, 1);
559 /* check for stall/halt control bits */
560 if(PKE_REG_MASK_GET(me
, STAT
, PFS
) ||
561 PKE_REG_MASK_GET(me
, STAT
, PSS
) || /* note special treatment below */
562 /* PEW bit not a reason to keep stalling - it's just an indication, re-computed below */
563 /* PGW bit not a reason to keep stalling - it's just an indication, re-computed below */
564 /* ER0/ER1 not a reason to keep stalling - it's just an indication */
565 PKE_REG_MASK_GET(me
, STAT
, PIS
))
567 /* (still) stalled */
568 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_STALL
);
569 /* try again next cycle */
574 /* 3 -- decode PKE instruction */
577 if(PKE_REG_MASK_GET(me
, STAT
, PPS
) == PKE_REG_STAT_PPS_IDLE
)
578 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_DECODE
);
580 /* Extract relevant bits from PKEcode */
581 intr
= BIT_MASK_GET(fw
, PKE_OPCODE_I_B
, PKE_OPCODE_I_E
);
582 cmd
= BIT_MASK_GET(fw
, PKE_OPCODE_CMD_B
, PKE_OPCODE_CMD_E
);
584 /* handle interrupts */
587 /* are we resuming an interrupt-stalled instruction? */
588 if(me
->flags
& PKE_FLAG_INT_NOLOOP
)
590 /* clear loop-prevention flag */
591 me
->flags
&= ~PKE_FLAG_INT_NOLOOP
;
593 /* fall through to decode & execute */
594 /* The pke_code_* functions should not check the MSB in the
597 else /* new interrupt-flagged instruction */
599 /* set INT flag in STAT register */
600 PKE_REG_MASK_SET(me
, STAT
, INT
, 1);
601 /* set loop-prevention flag */
602 me
->flags
|= PKE_FLAG_INT_NOLOOP
;
604 /* set PIS if stall not masked */
605 if(!PKE_REG_MASK_GET(me
, ERR
, MII
))
606 pke_begin_interrupt_stall(me
);
608 /* suspend this instruction unless it's PKEMARK */
609 if(!IS_PKE_CMD(cmd
, PKEMARK
))
611 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_STALL
);
616 ; /* fall through to decode & execute */
622 /* decode & execute */
623 if(IS_PKE_CMD(cmd
, PKENOP
))
624 pke_code_nop(me
, fw
);
625 else if(IS_PKE_CMD(cmd
, STCYCL
))
626 pke_code_stcycl(me
, fw
);
627 else if(me
->pke_number
== 1 && IS_PKE_CMD(cmd
, OFFSET
))
628 pke_code_offset(me
, fw
);
629 else if(me
->pke_number
== 1 && IS_PKE_CMD(cmd
, BASE
))
630 pke_code_base(me
, fw
);
631 else if(IS_PKE_CMD(cmd
, ITOP
))
632 pke_code_itop(me
, fw
);
633 else if(IS_PKE_CMD(cmd
, STMOD
))
634 pke_code_stmod(me
, fw
);
635 else if(me
->pke_number
== 1 && IS_PKE_CMD(cmd
, MSKPATH3
))
636 pke_code_mskpath3(me
, fw
);
637 else if(IS_PKE_CMD(cmd
, PKEMARK
))
638 pke_code_pkemark(me
, fw
);
639 else if(IS_PKE_CMD(cmd
, FLUSHE
))
640 pke_code_flushe(me
, fw
);
641 else if(me
->pke_number
== 1 && IS_PKE_CMD(cmd
, FLUSH
))
642 pke_code_flush(me
, fw
);
643 else if(me
->pke_number
== 1 && IS_PKE_CMD(cmd
, FLUSHA
))
644 pke_code_flusha(me
, fw
);
645 else if(IS_PKE_CMD(cmd
, PKEMSCAL
))
646 pke_code_pkemscal(me
, fw
);
647 else if(IS_PKE_CMD(cmd
, PKEMSCNT
))
648 pke_code_pkemscnt(me
, fw
);
649 else if(me
->pke_number
== 1 && IS_PKE_CMD(cmd
, PKEMSCALF
))
650 pke_code_pkemscalf(me
, fw
);
651 else if(IS_PKE_CMD(cmd
, STMASK
))
652 pke_code_stmask(me
, fw
);
653 else if(IS_PKE_CMD(cmd
, STROW
))
654 pke_code_strow(me
, fw
);
655 else if(IS_PKE_CMD(cmd
, STCOL
))
656 pke_code_stcol(me
, fw
);
657 else if(IS_PKE_CMD(cmd
, MPG
))
658 pke_code_mpg(me
, fw
);
659 else if(IS_PKE_CMD(cmd
, DIRECT
))
660 pke_code_direct(me
, fw
);
661 else if(IS_PKE_CMD(cmd
, DIRECTHL
))
662 pke_code_directhl(me
, fw
);
663 else if(IS_PKE_CMD(cmd
, UNPACK
))
664 pke_code_unpack(me
, fw
);
665 /* ... no other commands ... */
667 pke_code_error(me
, fw
);
672 /* Clear out contents of FIFO; act as if it was empty. Return PC
673 pointing to one-past-last word. */
676 pke_fifo_flush(struct pke_fifo
* fifo
)
678 /* don't modify any state! */
679 return fifo
->origin
+ fifo
->next
;
684 /* Clear out contents of FIFO; make it really empty. */
687 pke_fifo_reset(struct pke_fifo
* fifo
)
691 /* clear fifo quadwords */
692 for(i
=0; i
<fifo
->next
; i
++)
694 zfree(fifo
->quadwords
[i
]);
695 fifo
->quadwords
[i
] = NULL
;
705 /* Make space for the next quadword in the FIFO. Allocate/enlarge
706 FIFO pointer block if necessary. Return a pointer to it. */
708 struct fifo_quadword
*
709 pke_fifo_fit(struct pke_fifo
* fifo
)
711 struct fifo_quadword
* fqw
;
713 /* out of space on quadword pointer array? */
714 if(fifo
->next
== fifo
->length
) /* also triggered before fifo->quadwords allocated */
716 struct fifo_quadword
** new_qw
;
717 unsigned_4 new_length
= fifo
->length
+ PKE_FIFO_GROW_SIZE
;
719 /* allocate new pointer block */
720 new_qw
= zalloc(new_length
* sizeof(struct fifo_quadword
*));
721 ASSERT(new_qw
!= NULL
);
723 /* copy over old contents, if any */
724 if(fifo
->quadwords
!= NULL
)
726 /* copy over old pointers to beginning of new block */
727 memcpy(new_qw
, fifo
->quadwords
,
728 fifo
->length
* sizeof(struct fifo_quadword
*));
731 zfree(fifo
->quadwords
);
734 /* replace pointers & counts */
735 fifo
->quadwords
= new_qw
;
736 fifo
->length
= new_length
;
740 ASSERT(fifo
->quadwords
!= NULL
);
742 /* allocate new quadword from heap */
743 fqw
= zalloc(sizeof(struct fifo_quadword
));
746 /* push quadword onto fifo */
747 fifo
->quadwords
[fifo
->next
] = fqw
;
754 /* Return a pointer to the FIFO quadword with given absolute index, or
755 NULL if it is out of range */
757 struct fifo_quadword
*
758 pke_fifo_access(struct pke_fifo
* fifo
, unsigned_4 qwnum
)
760 struct fifo_quadword
* fqw
;
762 if((qwnum
< fifo
->origin
) || /* before history */
763 (qwnum
>= fifo
->origin
+ fifo
->next
)) /* after last available quadword */
767 ASSERT(fifo
->quadwords
!= NULL
); /* must be allocated already */
768 fqw
= fifo
->quadwords
[qwnum
- fifo
->origin
]; /* pull out pointer from array */
769 ASSERT(fqw
!= NULL
); /* must be allocated already */
776 /* Authorize release of any FIFO entries older than given absolute quadword. */
778 pke_fifo_old(struct pke_fifo
* fifo
, unsigned_4 qwnum
)
780 /* do we have any too-old FIFO elements? */
781 if(fifo
->origin
+ PKE_FIFO_ARCHEOLOGY
< qwnum
)
783 /* count quadwords to forget */
784 int horizon
= qwnum
- (fifo
->origin
+ PKE_FIFO_ARCHEOLOGY
);
787 /* free quadwords at indices below horizon */
788 for(i
=0; i
< horizon
; i
++)
789 zfree(fifo
->quadwords
[i
]);
791 /* move surviving quadword pointers down to beginning of array */
792 for(i
=horizon
; i
< fifo
->next
; i
++)
793 fifo
->quadwords
[i
-horizon
] = fifo
->quadwords
[i
];
795 /* clear duplicate pointers */
796 for(i
=fifo
->next
- horizon
; i
< fifo
->next
; i
++)
797 fifo
->quadwords
[i
] = NULL
;
799 /* adjust FIFO pointers */
800 fifo
->origin
= fifo
->origin
+ horizon
;
801 fifo
->next
= fifo
->next
- horizon
;
808 /* advance the PC by given number of data words; update STAT/FQC
809 field; assume FIFO is filled enough; classify passed-over words;
810 write FIFO trace line */
813 pke_pc_advance(struct pke_device
* me
, int num_words
)
816 struct fifo_quadword
* fq
= NULL
;
817 unsigned_4 old_fifo_pc
= me
->fifo_pc
;
819 ASSERT(num_words
>= 0);
821 /* printf("pke %d pc_advance num_words %d\n", me->pke_number, num_words); */
825 /* find next quadword, if any */
826 fq
= pke_fifo_access(& me
->fifo
, me
->fifo_pc
);
828 /* skip over DMA tag words if present in word 0 or 1 */
829 if(fq
!= NULL
&& fq
->word_class
[me
->qw_pc
] == wc_dma
)
831 /* skip by going around loop an extra time */
835 /* nothing left to skip / no DMA tag here */
839 /* we are supposed to skip existing words */
842 /* one word skipped */
845 /* point to next word */
852 /* trace the consumption of the FIFO quadword we just skipped over */
853 /* fq still points to it */
854 if(me
->fifo_trace_file
!= NULL
)
856 /* assert complete classification */
857 ASSERT(fq
->word_class
[3] != wc_unknown
);
858 ASSERT(fq
->word_class
[2] != wc_unknown
);
859 ASSERT(fq
->word_class
[1] != wc_unknown
);
860 ASSERT(fq
->word_class
[0] != wc_unknown
);
862 /* print trace record */
863 fprintf(me
->fifo_trace_file
,
864 "%d 0x%08x_%08x_%08x_%08x 0x%08x %c%c%c%c\n",
865 (me
->pke_number
== 0 ? 0 : 1),
866 (unsigned) fq
->data
[3], (unsigned) fq
->data
[2],
867 (unsigned) fq
->data
[1], (unsigned) fq
->data
[0],
868 (unsigned) fq
->source_address
,
869 fq
->word_class
[3], fq
->word_class
[2],
870 fq
->word_class
[1], fq
->word_class
[0]);
872 } /* next quadword */
875 /* age old entries before PC */
876 if(me
->fifo_pc
!= old_fifo_pc
)
878 /* we advanced the fifo-pc; authorize disposal of anything
879 before previous PKEcode */
880 pke_fifo_old(& me
->fifo
, old_fifo_pc
);
883 /* clear FQC if FIFO is now empty */
884 fq
= pke_fifo_access(& me
->fifo
, me
->fifo_pc
);
887 PKE_REG_MASK_SET(me
, STAT
, FQC
, 0);
889 else /* annote the word where the PC lands as an PKEcode */
891 ASSERT(fq
->word_class
[me
->qw_pc
] == wc_pkecode
|| fq
->word_class
[me
->qw_pc
] == wc_unknown
);
892 fq
->word_class
[me
->qw_pc
] = wc_pkecode
;
900 /* Return pointer to FIFO quadword containing given operand# in FIFO.
901 `operand_num' starts at 1. Return pointer to operand word in last
902 argument, if non-NULL. If FIFO is not full enough, return 0.
903 Signal an ER0 indication upon skipping a DMA tag. */
905 struct fifo_quadword
*
906 pke_pcrel_fifo(struct pke_device
* me
, int operand_num
, unsigned_4
** operand
)
909 int new_qw_pc
, new_fifo_pc
;
910 struct fifo_quadword
* fq
= NULL
;
912 /* check for validity of last search results in cache */
913 if(me
->last_fifo_pc
== me
->fifo_pc
&&
914 me
->last_qw_pc
== me
->qw_pc
&&
915 operand_num
> me
->last_num
)
917 /* continue search from last stop */
918 new_fifo_pc
= me
->last_new_fifo_pc
;
919 new_qw_pc
= me
->last_new_qw_pc
;
920 num
= operand_num
- me
->last_num
;
924 /* start search from scratch */
925 new_fifo_pc
= me
->fifo_pc
;
926 new_qw_pc
= me
->qw_pc
;
932 /* printf("pke %d pcrel_fifo operand_num %d\n", me->pke_number, operand_num); */
936 /* one word skipped */
939 /* point to next word */
947 fq
= pke_fifo_access(& me
->fifo
, new_fifo_pc
);
949 /* check for FIFO underflow */
953 /* skip over DMA tag words if present in word 0 or 1 */
954 if(fq
->word_class
[new_qw_pc
] == wc_dma
)
957 PKE_REG_MASK_SET(me
, STAT
, ER0
, 1);
959 /* mismatch error! */
960 if(! PKE_REG_MASK_GET(me
, ERR
, ME0
))
962 pke_begin_interrupt_stall(me
);
963 /* don't stall just yet -- finish this instruction */
964 /* the PPS_STALL state will be entered by pke_issue() next time */
966 /* skip by going around loop an extra time */
972 /* return pointer to operand word itself */
975 *operand
= & fq
->data
[new_qw_pc
];
977 /* annote the word where the pseudo-PC lands as an PKE operand */
978 ASSERT(fq
->word_class
[new_qw_pc
] == wc_pkedata
|| fq
->word_class
[new_qw_pc
] == wc_unknown
);
979 fq
->word_class
[new_qw_pc
] = wc_pkedata
;
981 /* store search results in cache */
983 me
->last_fifo_pc
= me
->fifo_pc
;
984 me
->last_qw_pc
= me
->qw_pc
;
986 me
->last_num
= operand_num
;
987 me
->last_new_fifo_pc
= new_fifo_pc
;
988 me
->last_new_qw_pc
= new_qw_pc
;
995 /* Return pointer to given operand# in FIFO. `operand_num' starts at 1.
996 If FIFO is not full enough, return 0. Skip over DMA tags, but mark
997 them as an error (ER0). */
1000 pke_pcrel_operand(struct pke_device
* me
, int operand_num
)
1002 unsigned_4
* operand
= NULL
;
1003 struct fifo_quadword
* fifo_operand
;
1005 fifo_operand
= pke_pcrel_fifo(me
, operand_num
, & operand
);
1007 if(fifo_operand
== NULL
)
1008 ASSERT(operand
== NULL
); /* pke_pcrel_fifo() ought leave it untouched */
1014 /* Return a bit-field extract of given operand# in FIFO, and its
1015 source-addr. `bit_offset' starts at 0, referring to LSB after PKE
1016 instruction word. Width must be >0, <=32. Assume FIFO is full
1017 enough. Skip over DMA tags, but mark them as an error (ER0). */
1020 pke_pcrel_operand_bits(struct pke_device
* me
, int bit_offset
, int bit_width
, unsigned_4
* source_addr
)
1022 unsigned_4
* word
= NULL
;
1024 struct fifo_quadword
* fifo_operand
;
1025 int wordnumber
, bitnumber
;
1027 wordnumber
= bit_offset
/32;
1028 bitnumber
= bit_offset
%32;
1030 /* find operand word with bitfield */
1031 fifo_operand
= pke_pcrel_fifo(me
, wordnumber
+ 1, &word
);
1032 ASSERT(word
!= NULL
);
1034 /* extract bitfield from word */
1035 value
= BIT_MASK_GET(*word
, bitnumber
, bitnumber
+ bit_width
- 1);
1037 /* extract source addr from fifo word */
1038 *source_addr
= fifo_operand
->source_address
;
1045 /* check for stall conditions on indicated devices (path* only on
1046 PKE1), do not change status; return 0 iff no stall */
1048 pke_check_stall(struct pke_device
* me
, enum pke_check_target what
)
1051 unsigned_4 cop2_stat
, gpuif_stat
;
1053 /* read status words */
1054 ASSERT(sizeof(unsigned_4
) == 4);
1055 PKE_MEM_READ(me
, (GIF_REG_STAT
),
1058 PKE_MEM_READ(me
, (COP2_REG_STAT_ADDR
),
1062 /* perform checks */
1065 if(me
->pke_number
== 0)
1066 any_stall
= BIT_MASK_GET(cop2_stat
, COP2_REG_STAT_VBS0_B
, COP2_REG_STAT_VBS0_E
);
1067 else /* if(me->pke_number == 1) */
1068 any_stall
= BIT_MASK_GET(cop2_stat
, COP2_REG_STAT_VBS1_B
, COP2_REG_STAT_VBS1_E
);
1070 else if(what
== chk_path1
) /* VU -> GPUIF */
1072 if(BIT_MASK_GET(gpuif_stat
, GPUIF_REG_STAT_APATH_B
, GPUIF_REG_STAT_APATH_E
) == 1)
1075 else if(what
== chk_path2
) /* PKE -> GPUIF */
1077 if(BIT_MASK_GET(gpuif_stat
, GPUIF_REG_STAT_APATH_B
, GPUIF_REG_STAT_APATH_E
) == 2)
1080 else if(what
== chk_path3
) /* DMA -> GPUIF */
1082 if(BIT_MASK_GET(gpuif_stat
, GPUIF_REG_STAT_APATH_B
, GPUIF_REG_STAT_APATH_E
) == 3)
1091 /* any stall reasons? */
1096 /* PKE1 only: flip the DBF bit; recompute TOPS, TOP */
1098 pke_flip_dbf(struct pke_device
* me
)
1101 /* compute new TOP */
1102 PKE_REG_MASK_SET(me
, TOP
, TOP
,
1103 PKE_REG_MASK_GET(me
, TOPS
, TOPS
));
1105 newdf
= PKE_REG_MASK_GET(me
, DBF
, DF
) ? 0 : 1;
1106 PKE_REG_MASK_SET(me
, DBF
, DF
, newdf
);
1107 PKE_REG_MASK_SET(me
, STAT
, DBF
, newdf
);
1108 /* compute new TOPS */
1109 PKE_REG_MASK_SET(me
, TOPS
, TOPS
,
1110 (PKE_REG_MASK_GET(me
, BASE
, BASE
) +
1111 newdf
* PKE_REG_MASK_GET(me
, OFST
, OFFSET
)));
1113 /* this is equivalent to last word from okadaa (98-02-25):
1115 2) TOPS=BASE + !DBF*OFFSET
1120 /* set the STAT:PIS bit and send an interrupt to the 5900 */
1122 pke_begin_interrupt_stall(struct pke_device
* me
)
1125 PKE_REG_MASK_SET(me
, STAT
, PIS
, 1);
1127 /* XXX: send interrupt to 5900? */
1133 /* PKEcode handler functions -- responsible for checking and
1134 confirming old stall conditions, executing pkecode, updating PC and
1135 status registers -- may assume being run on correct PKE unit */
1138 pke_code_nop(struct pke_device
* me
, unsigned_4 pkecode
)
1141 pke_pc_advance(me
, 1);
1142 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1147 pke_code_stcycl(struct pke_device
* me
, unsigned_4 pkecode
)
1149 int imm
= BIT_MASK_GET(pkecode
, PKE_OPCODE_IMM_B
, PKE_OPCODE_IMM_E
);
1151 /* copy immediate value into CYCLE reg */
1152 PKE_REG_MASK_SET(me
, CYCLE
, WL
, BIT_MASK_GET(imm
, 8, 15));
1153 PKE_REG_MASK_SET(me
, CYCLE
, CL
, BIT_MASK_GET(imm
, 0, 7));
1155 pke_pc_advance(me
, 1);
1156 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1161 pke_code_offset(struct pke_device
* me
, unsigned_4 pkecode
)
1163 int imm
= BIT_MASK_GET(pkecode
, PKE_OPCODE_IMM_B
, PKE_OPCODE_IMM_E
);
1165 /* copy 10 bits to OFFSET field */
1166 PKE_REG_MASK_SET(me
, OFST
, OFFSET
, BIT_MASK_GET(imm
, 0, 9));
1168 PKE_REG_MASK_SET(me
, DBF
, DF
, 0);
1169 /* clear other DBF bit */
1170 PKE_REG_MASK_SET(me
, STAT
, DBF
, 0);
1171 /* set TOPS = BASE */
1172 PKE_REG_MASK_SET(me
, TOPS
, TOPS
, PKE_REG_MASK_GET(me
, BASE
, BASE
));
1174 pke_pc_advance(me
, 1);
1175 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1180 pke_code_base(struct pke_device
* me
, unsigned_4 pkecode
)
1182 int imm
= BIT_MASK_GET(pkecode
, PKE_OPCODE_IMM_B
, PKE_OPCODE_IMM_E
);
1184 /* copy 10 bits to BASE field */
1185 PKE_REG_MASK_SET(me
, BASE
, BASE
, BIT_MASK_GET(imm
, 0, 9));
1187 pke_pc_advance(me
, 1);
1188 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1193 pke_code_itop(struct pke_device
* me
, unsigned_4 pkecode
)
1195 int imm
= BIT_MASK_GET(pkecode
, PKE_OPCODE_IMM_B
, PKE_OPCODE_IMM_E
);
1197 /* copy 10 bits to ITOPS field */
1198 PKE_REG_MASK_SET(me
, ITOPS
, ITOPS
, BIT_MASK_GET(imm
, 0, 9));
1200 pke_pc_advance(me
, 1);
1201 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1206 pke_code_stmod(struct pke_device
* me
, unsigned_4 pkecode
)
1208 int imm
= BIT_MASK_GET(pkecode
, PKE_OPCODE_IMM_B
, PKE_OPCODE_IMM_E
);
1210 /* copy 2 bits to MODE register */
1211 PKE_REG_MASK_SET(me
, MODE
, MDE
, BIT_MASK_GET(imm
, 0, 2));
1213 pke_pc_advance(me
, 1);
1214 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1219 pke_code_mskpath3(struct pke_device
* me
, unsigned_4 pkecode
)
1221 int imm
= BIT_MASK_GET(pkecode
, PKE_OPCODE_IMM_B
, PKE_OPCODE_IMM_E
);
1222 unsigned_4 gif_mode
;
1224 /* set appropriate bit */
1225 if(BIT_MASK_GET(imm
, PKE_REG_MSKPATH3_B
, PKE_REG_MSKPATH3_E
) != 0)
1226 gif_mode
= GIF_REG_MODE_M3R_MASK
;
1230 /* write register; patrickm code will look at M3R bit only */
1231 PKE_MEM_WRITE(me
, GIF_REG_MODE
, & gif_mode
, 4);
1234 pke_pc_advance(me
, 1);
1235 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1240 pke_code_pkemark(struct pke_device
* me
, unsigned_4 pkecode
)
1242 int imm
= BIT_MASK_GET(pkecode
, PKE_OPCODE_IMM_B
, PKE_OPCODE_IMM_E
);
1243 /* copy 16 bits to MARK register */
1244 PKE_REG_MASK_SET(me
, MARK
, MARK
, BIT_MASK_GET(imm
, 0, 15));
1245 /* set MRK bit in STAT register - CPU2 v2.1 docs incorrect */
1246 PKE_REG_MASK_SET(me
, STAT
, MRK
, 1);
1248 pke_pc_advance(me
, 1);
1249 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1254 pke_code_flushe(struct pke_device
* me
, unsigned_4 pkecode
)
1256 /* compute next PEW bit */
1257 if(pke_check_stall(me
, chk_vu
))
1260 PKE_REG_MASK_SET(me
, STAT
, PEW
, 1);
1261 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_STALL
);
1262 /* try again next cycle */
1267 PKE_REG_MASK_SET(me
, STAT
, PEW
, 0);
1268 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1269 pke_pc_advance(me
, 1);
1275 pke_code_flush(struct pke_device
* me
, unsigned_4 pkecode
)
1277 int something_busy
= 0;
1279 /* compute next PEW, PGW bits */
1280 if(pke_check_stall(me
, chk_vu
))
1283 PKE_REG_MASK_SET(me
, STAT
, PEW
, 1);
1286 PKE_REG_MASK_SET(me
, STAT
, PEW
, 0);
1289 if(pke_check_stall(me
, chk_path1
) ||
1290 pke_check_stall(me
, chk_path2
))
1293 PKE_REG_MASK_SET(me
, STAT
, PGW
, 1);
1296 PKE_REG_MASK_SET(me
, STAT
, PGW
, 0);
1301 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_WAIT
);
1302 /* try again next cycle */
1307 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1308 pke_pc_advance(me
, 1);
1314 pke_code_flusha(struct pke_device
* me
, unsigned_4 pkecode
)
1316 int something_busy
= 0;
1318 /* compute next PEW, PGW bits */
1319 if(pke_check_stall(me
, chk_vu
))
1322 PKE_REG_MASK_SET(me
, STAT
, PEW
, 1);
1325 PKE_REG_MASK_SET(me
, STAT
, PEW
, 0);
1328 if(pke_check_stall(me
, chk_path1
) ||
1329 pke_check_stall(me
, chk_path2
) ||
1330 pke_check_stall(me
, chk_path3
))
1333 PKE_REG_MASK_SET(me
, STAT
, PGW
, 1);
1336 PKE_REG_MASK_SET(me
, STAT
, PGW
, 0);
1340 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_WAIT
);
1341 /* try again next cycle */
1346 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1347 pke_pc_advance(me
, 1);
1353 pke_code_pkemscal(struct pke_device
* me
, unsigned_4 pkecode
)
1355 /* compute next PEW bit */
1356 if(pke_check_stall(me
, chk_vu
))
1359 PKE_REG_MASK_SET(me
, STAT
, PEW
, 1);
1360 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_STALL
);
1361 /* try again next cycle */
1366 int imm
= BIT_MASK_GET(pkecode
, PKE_OPCODE_IMM_B
, PKE_OPCODE_IMM_E
);
1369 PKE_REG_MASK_SET(me
, STAT
, PEW
, 0);
1371 /* flip DBF on PKE1 */
1372 if(me
->pke_number
== 1)
1375 /* compute new PC for VU (host byte-order) */
1376 vu_pc
= BIT_MASK_GET(imm
, 0, 15);
1377 vu_pc
= T2H_4(vu_pc
);
1379 /* write new PC; callback function gets VU running */
1380 ASSERT(sizeof(unsigned_4
) == 4);
1381 PKE_MEM_WRITE(me
, (me
->pke_number
== 0 ? VU0_CIA
: VU1_CIA
),
1385 /* copy ITOPS field to ITOP */
1386 PKE_REG_MASK_SET(me
, ITOP
, ITOP
, PKE_REG_MASK_GET(me
, ITOPS
, ITOPS
));
1389 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1390 pke_pc_advance(me
, 1);
1397 pke_code_pkemscnt(struct pke_device
* me
, unsigned_4 pkecode
)
1399 /* compute next PEW bit */
1400 if(pke_check_stall(me
, chk_vu
))
1403 PKE_REG_MASK_SET(me
, STAT
, PEW
, 1);
1404 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_STALL
);
1405 /* try again next cycle */
1412 PKE_REG_MASK_SET(me
, STAT
, PEW
, 0);
1414 /* flip DBF on PKE1 */
1415 if(me
->pke_number
== 1)
1419 ASSERT(sizeof(unsigned_4
) == 4);
1420 PKE_MEM_READ(me
, (me
->pke_number
== 0 ? VU0_CIA
: VU1_CIA
),
1424 /* rewrite new PC; callback function gets VU running */
1425 ASSERT(sizeof(unsigned_4
) == 4);
1426 PKE_MEM_WRITE(me
, (me
->pke_number
== 0 ? VU0_CIA
: VU1_CIA
),
1430 /* copy ITOPS field to ITOP */
1431 PKE_REG_MASK_SET(me
, ITOP
, ITOP
, PKE_REG_MASK_GET(me
, ITOPS
, ITOPS
));
1434 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1435 pke_pc_advance(me
, 1);
1441 pke_code_pkemscalf(struct pke_device
* me
, unsigned_4 pkecode
)
1443 int something_busy
= 0;
1445 /* compute next PEW, PGW bits */
1446 if(pke_check_stall(me
, chk_vu
))
1449 PKE_REG_MASK_SET(me
, STAT
, PEW
, 1);
1452 PKE_REG_MASK_SET(me
, STAT
, PEW
, 0);
1455 if(pke_check_stall(me
, chk_path1
) ||
1456 pke_check_stall(me
, chk_path2
) ||
1457 pke_check_stall(me
, chk_path3
))
1460 PKE_REG_MASK_SET(me
, STAT
, PGW
, 1);
1463 PKE_REG_MASK_SET(me
, STAT
, PGW
, 0);
1468 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_WAIT
);
1469 /* try again next cycle */
1474 int imm
= BIT_MASK_GET(pkecode
, PKE_OPCODE_IMM_B
, PKE_OPCODE_IMM_E
);
1476 /* flip DBF on PKE1 */
1477 if(me
->pke_number
== 1)
1480 /* compute new PC for VU (host byte-order) */
1481 vu_pc
= BIT_MASK_GET(imm
, 0, 15);
1482 vu_pc
= T2H_4(vu_pc
);
1484 /* rewrite new PC; callback function gets VU running */
1485 ASSERT(sizeof(unsigned_4
) == 4);
1486 PKE_MEM_WRITE(me
, (me
->pke_number
== 0 ? VU0_CIA
: VU1_CIA
),
1490 /* copy ITOPS field to ITOP */
1491 PKE_REG_MASK_SET(me
, ITOP
, ITOP
, PKE_REG_MASK_GET(me
, ITOPS
, ITOPS
));
1494 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1495 pke_pc_advance(me
, 1);
1501 pke_code_stmask(struct pke_device
* me
, unsigned_4 pkecode
)
1505 /* check that FIFO has one more word for STMASK operand */
1506 mask
= pke_pcrel_operand(me
, 1);
1509 /* "transferring" operand */
1510 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_XFER
);
1513 PKE_REG_MASK_SET(me
, NUM
, NUM
, 1);
1515 /* fill the register */
1516 PKE_REG_MASK_SET(me
, MASK
, MASK
, *mask
);
1519 PKE_REG_MASK_SET(me
, NUM
, NUM
, 0);
1522 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1523 pke_pc_advance(me
, 2);
1527 /* need to wait for another word */
1528 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_WAIT
);
1529 /* try again next cycle */
1535 pke_code_strow(struct pke_device
* me
, unsigned_4 pkecode
)
1537 /* check that FIFO has four more words for STROW operand */
1538 unsigned_4
* last_op
;
1540 last_op
= pke_pcrel_operand(me
, 4);
1543 /* "transferring" operand */
1544 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_XFER
);
1547 PKE_REG_MASK_SET(me
, NUM
, NUM
, 1);
1549 /* copy ROW registers: must all exist if 4th operand exists */
1550 me
->regs
[PKE_REG_R0
][0] = * pke_pcrel_operand(me
, 1);
1551 me
->regs
[PKE_REG_R1
][0] = * pke_pcrel_operand(me
, 2);
1552 me
->regs
[PKE_REG_R2
][0] = * pke_pcrel_operand(me
, 3);
1553 me
->regs
[PKE_REG_R3
][0] = * pke_pcrel_operand(me
, 4);
1556 PKE_REG_MASK_SET(me
, NUM
, NUM
, 0);
1559 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1560 pke_pc_advance(me
, 5);
1564 /* need to wait for another word */
1565 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_WAIT
);
1566 /* try again next cycle */
1572 pke_code_stcol(struct pke_device
* me
, unsigned_4 pkecode
)
1574 /* check that FIFO has four more words for STCOL operand */
1575 unsigned_4
* last_op
;
1577 last_op
= pke_pcrel_operand(me
, 4);
1580 /* "transferring" operand */
1581 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_XFER
);
1584 PKE_REG_MASK_SET(me
, NUM
, NUM
, 1);
1586 /* copy COL registers: must all exist if 4th operand exists */
1587 me
->regs
[PKE_REG_C0
][0] = * pke_pcrel_operand(me
, 1);
1588 me
->regs
[PKE_REG_C1
][0] = * pke_pcrel_operand(me
, 2);
1589 me
->regs
[PKE_REG_C2
][0] = * pke_pcrel_operand(me
, 3);
1590 me
->regs
[PKE_REG_C3
][0] = * pke_pcrel_operand(me
, 4);
1593 PKE_REG_MASK_SET(me
, NUM
, NUM
, 0);
1596 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1597 pke_pc_advance(me
, 5);
1601 /* need to wait for another word */
1602 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_WAIT
);
1603 /* try again next cycle */
1609 pke_code_mpg(struct pke_device
* me
, unsigned_4 pkecode
)
1611 unsigned_4
* last_mpg_word
;
1612 int num
= BIT_MASK_GET(pkecode
, PKE_OPCODE_NUM_B
, PKE_OPCODE_NUM_E
);
1613 int imm
= BIT_MASK_GET(pkecode
, PKE_OPCODE_IMM_B
, PKE_OPCODE_IMM_E
);
1615 /* assert 64-bit alignment of MPG operand */
1616 if(me
->qw_pc
!= 3 && me
->qw_pc
!= 1)
1617 return pke_code_error(me
, pkecode
);
1619 /* map zero to max+1 */
1620 if(num
==0) num
=0x100;
1622 /* check that FIFO has a few more words for MPG operand */
1623 last_mpg_word
= pke_pcrel_operand(me
, num
*2); /* num: number of 64-bit words */
1624 if(last_mpg_word
!= NULL
)
1626 /* perform implied FLUSHE */
1627 if(pke_check_stall(me
, chk_vu
))
1630 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_STALL
);
1631 /* retry this instruction next clock */
1638 /* "transferring" operand */
1639 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_XFER
);
1642 PKE_REG_MASK_SET(me
, NUM
, NUM
, num
);
1644 /* transfer VU instructions, one word-pair per iteration */
1645 for(i
=0; i
<num
; i
++)
1647 address_word vu_addr_base
, vu_addr
;
1648 address_word vutrack_addr_base
, vutrack_addr
;
1649 address_word vu_addr_max_size
;
1650 unsigned_4 vu_lower_opcode
, vu_upper_opcode
;
1651 unsigned_4
* operand
;
1652 struct fifo_quadword
* fq
;
1656 next_num
= PKE_REG_MASK_GET(me
, NUM
, NUM
) - 1;
1657 PKE_REG_MASK_SET(me
, NUM
, NUM
, next_num
);
1659 /* imm: in 64-bit units for MPG instruction */
1660 /* VU*_MEM0 : instruction memory */
1661 vu_addr_base
= (me
->pke_number
== 0) ?
1662 VU0_MEM0_WINDOW_START
: VU1_MEM0_WINDOW_START
;
1663 vu_addr_max_size
= (me
->pke_number
== 0) ?
1664 VU0_MEM0_SIZE
: VU1_MEM0_SIZE
;
1665 vutrack_addr_base
= (me
->pke_number
== 0) ?
1666 VU0_MEM0_SRCADDR_START
: VU1_MEM0_SRCADDR_START
;
1668 /* compute VU address for this word-pair */
1669 vu_addr
= vu_addr_base
+ (imm
+ i
) * 8;
1670 /* check for vu_addr overflow */
1671 while(vu_addr
>= vu_addr_base
+ vu_addr_max_size
)
1672 vu_addr
-= vu_addr_max_size
;
1674 /* compute VU tracking address */
1675 vutrack_addr
= vutrack_addr_base
+ ((signed_8
)vu_addr
- (signed_8
)vu_addr_base
) / 2;
1677 /* Fetch operand words; assume they are already little-endian for VU imem */
1678 fq
= pke_pcrel_fifo(me
, i
*2 + 1, & operand
);
1679 vu_lower_opcode
= *operand
;
1680 vu_upper_opcode
= *pke_pcrel_operand(me
, i
*2 + 2);
1682 /* write data into VU memory */
1683 /* lower (scalar) opcode comes in first word ; macro performs H2T! */
1684 PKE_MEM_WRITE(me
, vu_addr
,
1687 /* upper (vector) opcode comes in second word ; H2T */
1688 ASSERT(sizeof(unsigned_4
) == 4);
1689 PKE_MEM_WRITE(me
, vu_addr
+ 4,
1693 /* write tracking address in target byte-order */
1694 ASSERT(sizeof(unsigned_4
) == 4);
1695 PKE_MEM_WRITE(me
, vutrack_addr
,
1696 & fq
->source_address
,
1698 } /* VU xfer loop */
1701 ASSERT(PKE_REG_MASK_GET(me
, NUM
, NUM
) == 0);
1704 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1705 pke_pc_advance(me
, 1 + num
*2);
1707 } /* if FIFO full enough */
1710 /* need to wait for another word */
1711 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_WAIT
);
1712 /* retry this instruction next clock */
1718 pke_code_direct(struct pke_device
* me
, unsigned_4 pkecode
)
1720 /* check that FIFO has a few more words for DIRECT operand */
1721 unsigned_4
* last_direct_word
;
1722 int imm
= BIT_MASK_GET(pkecode
, PKE_OPCODE_IMM_B
, PKE_OPCODE_IMM_E
);
1724 /* assert 128-bit alignment of DIRECT operand */
1726 return pke_code_error(me
, pkecode
);
1728 /* map zero to max+1 */
1729 if(imm
==0) imm
=0x10000;
1731 last_direct_word
= pke_pcrel_operand(me
, imm
*4); /* imm: number of 128-bit words */
1732 if(last_direct_word
!= NULL
)
1736 unsigned_16 fifo_data
;
1738 /* "transferring" operand */
1739 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_XFER
);
1741 /* transfer GPUIF quadwords, one word per iteration */
1742 for(i
=0; i
<imm
*4; i
++)
1744 unsigned_4
* operand
= pke_pcrel_operand(me
, 1+i
);
1746 /* collect word into quadword */
1747 *A4_16(&fifo_data
, 3 - (i
% 4)) = *operand
;
1749 /* write to GPUIF FIFO only with full quadword */
1752 ASSERT(sizeof(fifo_data
) == 16);
1753 PKE_MEM_WRITE(me
, GIF_PATH2_FIFO_ADDR
,
1756 } /* write collected quadword */
1757 } /* GPUIF xfer loop */
1760 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
1761 pke_pc_advance(me
, 1 + imm
*4);
1762 } /* if FIFO full enough */
1765 /* need to wait for another word */
1766 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_WAIT
);
1767 /* retry this instruction next clock */
1773 pke_code_directhl(struct pke_device
* me
, unsigned_4 pkecode
)
1775 /* treat the same as DIRECTH */
1776 pke_code_direct(me
, pkecode
);
1781 pke_code_unpack(struct pke_device
* me
, unsigned_4 pkecode
)
1783 int imm
= BIT_MASK_GET(pkecode
, PKE_OPCODE_IMM_B
, PKE_OPCODE_IMM_E
);
1784 int cmd
= BIT_MASK_GET(pkecode
, PKE_OPCODE_CMD_B
, PKE_OPCODE_CMD_E
);
1785 int num
= BIT_MASK_GET(pkecode
, PKE_OPCODE_NUM_B
, PKE_OPCODE_NUM_E
);
1786 int nummx
= (num
== 0) ? 0x0100 : num
;
1787 short vn
= BIT_MASK_GET(cmd
, 2, 3); /* unpack shape controls */
1788 short vl
= BIT_MASK_GET(cmd
, 0, 1);
1789 int m
= BIT_MASK_GET(cmd
, 4, 4);
1790 short cl
= PKE_REG_MASK_GET(me
, CYCLE
, CL
); /* cycle controls */
1791 short wl
= PKE_REG_MASK_GET(me
, CYCLE
, WL
);
1792 short addrwl
= (wl
== 0) ? 0x0100 : wl
;
1793 int r
= BIT_MASK_GET(imm
, 15, 15); /* indicator bits in imm value */
1794 int usn
= BIT_MASK_GET(imm
, 14, 14);
1796 int n
, num_operands
;
1797 unsigned_4
* last_operand_word
= NULL
;
1799 /* catch all illegal UNPACK variants */
1800 if(vl
== 3 && vn
< 3)
1802 pke_code_error(me
, pkecode
);
1806 /* compute PKEcode length, as given in CPU2 spec, v2.1 pg. 11 */
1810 n
= cl
* (nummx
/ addrwl
) + PKE_LIMIT(nummx
% addrwl
, cl
);
1811 num_operands
= (31 + (32 >> vl
) * (vn
+1) * n
)/32; /* round up to next word */
1813 /* confirm that FIFO has enough words in it */
1814 if(num_operands
> 0)
1815 last_operand_word
= pke_pcrel_operand(me
, num_operands
);
1816 if(last_operand_word
!= NULL
|| num_operands
== 0)
1818 address_word vu_addr_base
, vutrack_addr_base
;
1819 address_word vu_addr_max_size
;
1820 int vector_num_out
, vector_num_in
;
1822 /* "transferring" operand */
1823 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_XFER
);
1825 /* don't check whether VU is idle */
1827 /* compute VU address base */
1828 if(me
->pke_number
== 0)
1830 vu_addr_base
= VU0_MEM1_WINDOW_START
;
1831 vu_addr_max_size
= VU0_MEM1_SIZE
;
1832 vutrack_addr_base
= VU0_MEM1_SRCADDR_START
;
1837 vu_addr_base
= VU1_MEM1_WINDOW_START
;
1838 vu_addr_max_size
= VU1_MEM1_SIZE
;
1839 vutrack_addr_base
= VU1_MEM1_SRCADDR_START
;
1843 PKE_REG_MASK_SET(me
, NUM
, NUM
, nummx
);
1845 /* transfer given number of vectors */
1846 vector_num_out
= 0; /* output vector number being processed */
1847 vector_num_in
= 0; /* argument vector number being processed */
1850 quadword vu_old_data
;
1851 quadword vu_new_data
;
1852 quadword unpacked_data
;
1853 address_word vu_addr
;
1854 address_word vutrack_addr
;
1855 unsigned_4 source_addr
= 0;
1860 next_num
= PKE_REG_MASK_GET(me
, NUM
, NUM
) - 1;
1861 PKE_REG_MASK_SET(me
, NUM
, NUM
, next_num
);
1863 /* compute VU destination address, as bytes in R5900 memory */
1866 /* map zero to max+1 */
1867 vu_addr
= vu_addr_base
+ 16 * (BIT_MASK_GET(imm
, 0, 9) +
1868 (vector_num_out
/ addrwl
) * cl
+
1869 (vector_num_out
% addrwl
));
1872 vu_addr
= vu_addr_base
+ 16 * (BIT_MASK_GET(imm
, 0, 9) +
1875 /* handle "R" double-buffering bit */
1877 vu_addr
+= 16 * PKE_REG_MASK_GET(me
, TOPS
, TOPS
);
1879 /* check for vu_addr overflow */
1880 while(vu_addr
>= vu_addr_base
+ vu_addr_max_size
)
1881 vu_addr
-= vu_addr_max_size
;
1883 /* compute address of tracking table entry */
1884 vutrack_addr
= vutrack_addr_base
+ ((signed_8
)vu_addr
- (signed_8
)vu_addr_base
) / 4;
1886 /* read old VU data word at address; reverse words if needed */
1888 unsigned_16 vu_old_badwords
;
1889 ASSERT(sizeof(vu_old_badwords
) == 16);
1890 PKE_MEM_READ(me
, vu_addr
,
1891 &vu_old_badwords
, 16);
1892 vu_old_data
[0] = * A4_16(& vu_old_badwords
, 3);
1893 vu_old_data
[1] = * A4_16(& vu_old_badwords
, 2);
1894 vu_old_data
[2] = * A4_16(& vu_old_badwords
, 1);
1895 vu_old_data
[3] = * A4_16(& vu_old_badwords
, 0);
1898 /* For cyclic unpack, next operand quadword may come from instruction stream
1901 (vector_num_out
% addrwl
) >= cl
)
1903 /* clear operand - used only in a "indeterminate" state */
1904 for(i
= 0; i
< 4; i
++)
1905 unpacked_data
[i
] = 0;
1909 /* compute packed vector dimensions */
1910 int vectorbits
= 0, unitbits
= 0;
1912 if(vl
< 3) /* PKE_UNPACK_*_{32,16,8} */
1914 unitbits
= (32 >> vl
);
1915 vectorbits
= unitbits
* (vn
+1);
1917 else if(vl
== 3 && vn
== 3) /* PKE_UNPACK_V4_5 */
1922 else /* illegal unpack variant */
1924 /* should have been caught at top of function */
1928 /* loop over columns */
1929 for(i
=0; i
<=vn
; i
++)
1933 /* offset in bits in current operand word */
1935 (vector_num_in
* vectorbits
) + (i
* unitbits
); /* # of bits from PKEcode */
1937 /* last unit of V4_5 is only one bit wide */
1938 if(vl
== 3 && vn
== 3 && i
== 3) /* PKE_UNPACK_V4_5 */
1941 /* confirm we're not reading more than we said we needed */
1942 if(vector_num_in
* vectorbits
>= num_operands
* 32)
1944 /* this condition may be triggered by illegal
1945 PKEcode / CYCLE combinations. */
1946 pke_code_error(me
, pkecode
);
1947 /* XXX: this case needs to be better understood,
1948 and detected at a better time. */
1952 /* fetch bitfield operand */
1953 operand
= pke_pcrel_operand_bits(me
, bitoffset
, unitbits
, & source_addr
);
1955 /* selectively sign-extend; not for V4_5 1-bit value */
1956 if(usn
|| unitbits
== 1)
1957 unpacked_data
[i
] = operand
;
1959 unpacked_data
[i
] = SEXT32(operand
, unitbits
-1);
1962 /* set remaining top words in vector */
1963 for(i
=vn
+1; i
<4; i
++)
1965 if(vn
== 0) /* S_{32,16,8}: copy lowest element */
1966 unpacked_data
[i
] = unpacked_data
[0];
1968 unpacked_data
[i
] = 0;
1971 /* consumed a vector from the PKE instruction stream */
1973 } /* unpack word from instruction operand */
1975 /* process STMOD register for accumulation operations */
1976 switch(PKE_REG_MASK_GET(me
, MODE
, MDE
))
1978 case PKE_MODE_ADDROW
: /* add row registers to output data */
1980 /* exploit R0..R3 contiguity */
1981 unpacked_data
[i
] += me
->regs
[PKE_REG_R0
+ i
][0];
1984 case PKE_MODE_ACCROW
: /* add row registers to output data; accumulate */
1987 /* exploit R0..R3 contiguity */
1988 unpacked_data
[i
] += me
->regs
[PKE_REG_R0
+ i
][0];
1989 me
->regs
[PKE_REG_R0
+ i
][0] = unpacked_data
[i
];
1993 case PKE_MODE_INPUT
: /* pass data through */
1994 default: /* specified as undefined */
1998 /* compute replacement word */
1999 if(m
) /* use mask register? */
2001 /* compute index into mask register for this word */
2002 int mask_index
= PKE_LIMIT(vector_num_out
% addrwl
, 3);
2004 for(i
=0; i
<4; i
++) /* loop over columns */
2006 int mask_op
= PKE_MASKREG_GET(me
, mask_index
, i
);
2007 unsigned_4
* masked_value
= NULL
;
2011 case PKE_MASKREG_INPUT
:
2012 masked_value
= & unpacked_data
[i
];
2015 case PKE_MASKREG_ROW
: /* exploit R0..R3 contiguity */
2016 masked_value
= & me
->regs
[PKE_REG_R0
+ i
][0];
2019 case PKE_MASKREG_COLUMN
: /* exploit C0..C3 contiguity */
2020 masked_value
= & me
->regs
[PKE_REG_C0
+ mask_index
][0];
2023 case PKE_MASKREG_NOTHING
:
2024 /* "write inhibit" by re-copying old data */
2025 masked_value
= & vu_old_data
[i
];
2030 /* no other cases possible */
2033 /* copy masked value for column */
2034 vu_new_data
[i
] = *masked_value
;
2035 } /* loop over columns */
2039 /* no mask - just copy over entire unpacked quadword */
2040 memcpy(vu_new_data
, unpacked_data
, sizeof(unpacked_data
));
2043 /* write new VU data word at address; reverse words if needed */
2045 unsigned_16 vu_new_badwords
;
2046 * A4_16(& vu_new_badwords
, 3) = vu_new_data
[0];
2047 * A4_16(& vu_new_badwords
, 2) = vu_new_data
[1];
2048 * A4_16(& vu_new_badwords
, 1) = vu_new_data
[2];
2049 * A4_16(& vu_new_badwords
, 0) = vu_new_data
[3];
2050 ASSERT(sizeof(vu_new_badwords
) == 16);
2051 PKE_MEM_WRITE(me
, vu_addr
,
2052 &vu_new_badwords
, 16);
2055 /* write tracking address */
2056 ASSERT(sizeof(unsigned_4
) == 4);
2057 PKE_MEM_WRITE(me
, vutrack_addr
,
2061 /* next vector please */
2063 } /* vector transfer loop */
2064 while(PKE_REG_MASK_GET(me
, NUM
, NUM
) > 0);
2066 /* confirm we've written as many vectors as told */
2067 ASSERT(nummx
== vector_num_out
);
2070 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
2071 pke_pc_advance(me
, 1 + num_operands
);
2072 } /* PKE FIFO full enough */
2075 /* need to wait for another word */
2076 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_WAIT
);
2077 /* retry this instruction next clock */
2083 pke_code_error(struct pke_device
* me
, unsigned_4 pkecode
)
2085 /* set ER1 flag in STAT register */
2086 PKE_REG_MASK_SET(me
, STAT
, ER1
, 1);
2088 if(! PKE_REG_MASK_GET(me
, ERR
, ME1
))
2090 pke_begin_interrupt_stall(me
);
2091 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_STALL
);
2095 PKE_REG_MASK_SET(me
, STAT
, PPS
, PKE_REG_STAT_PPS_IDLE
);
2098 /* advance over faulty word */
2099 pke_pc_advance(me
, 1);