sim/mips/sky-pke.h

   1 /* Copyright (C) 1998, Cygnus Solutions */
   2
   3 #ifndef H_PKE_H
   4 #define H_PKE_H
   5
   6 #include "sim-main.h"
   7 #include "sky-device.h"
   8
   9
  10 /* External functions */
  11
  12 struct pke_fifo;
  13 struct fifo_quadword;
  14 struct pke_device;
  15
  16 void pke0_attach(SIM_DESC sd);
  17 void pke0_issue(SIM_DESC sd);
  18 void pke1_attach(SIM_DESC sd);
  19 void pke1_issue(SIM_DESC sd);
  20
  21 void pke_options(struct pke_device *device, unsigned_4 option, char *option_string);
  22 int read_pke_reg (struct pke_device *device, int regno, void *buf);
  23 int write_pke_reg (struct pke_device *device, int regno, const void *buf);
  24 int read_pke_pc (struct pke_device *device, void *buf);
  25 int read_pke_pcx (struct pke_device *device, void *buf);
  26 struct fifo_quadword* pke_fifo_access(struct pke_fifo*, unsigned_4 qwnum);
  27
  28
  29 /* Quadword data type */
  30
  31 typedef unsigned_4 quadword[4];
  32
  33 /* truncate address to quadword */
  34 #define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f)
  35 /* extract offset in quadword */
  36 #define ADDR_OFFSET_QW(addr) ((addr) & 0x0f)
  37
  38
  39 /* SCEI memory mapping information */
  40
  41 #define PKE0_REGISTER_WINDOW_START 0x10003800
  42 #define PKE1_REGISTER_WINDOW_START 0x10003C00
  43 #define PKE0_FIFO_ADDR             0x10004000
  44 #define PKE1_FIFO_ADDR             0x10005000
  45
  46
  47 /* VU source-addr tracking tables */ /* changed from 1998-01-22 e-mail plans */
  48 #define VU0_MEM0_SRCADDR_START 0x21000000
  49 #define VU0_MEM1_SRCADDR_START 0x21004000
  50 #define VU1_MEM0_SRCADDR_START 0x21008000
  51 #define VU1_MEM1_SRCADDR_START 0x2100C000
  52
  53 #define VU0_CIA (VU0_REGISTER_WINDOW_START + VU_REG_CIA)
  54 #define VU1_CIA (VU1_REGISTER_WINDOW_START + VU_REG_CIA)
  55
  56 /* GPUIF STAT register */
  57 #define GPUIF_REG_STAT_APATH_E 11
  58 #define GPUIF_REG_STAT_APATH_B 10
  59
  60 /* COP2 STAT register */
  61 #define COP2_REG_STAT_ADDR VPU_STAT_ADDR
  62 #define COP2_REG_STAT_VBS1_E 8
  63 #define COP2_REG_STAT_VBS1_B 8
  64 #define COP2_REG_STAT_VBS0_E 0
  65 #define COP2_REG_STAT_VBS0_B 0
  66
  67
  68 /* Quadword indices of PKE registers.  Actual registers sit at bottom
  69    32 bits of each quadword. */
  70 #define PKE_REG_STAT    0x00
  71 #define PKE_REG_FBRST   0x01
  72 #define PKE_REG_ERR     0x02
  73 #define PKE_REG_MARK    0x03
  74 #define PKE_REG_CYCLE   0x04
  75 #define PKE_REG_MODE    0x05
  76 #define PKE_REG_NUM     0x06
  77 #define PKE_REG_MASK    0x07
  78 #define PKE_REG_CODE    0x08
  79 #define PKE_REG_ITOPS   0x09
  80 #define PKE_REG_BASE    0x0a /* pke1 only */
  81 #define PKE_REG_OFST    0x0b /* pke1 only */
  82 #define PKE_REG_TOPS    0x0c /* pke1 only */
  83 #define PKE_REG_ITOP    0x0d
  84 #define PKE_REG_TOP     0x0e /* pke1 only */
  85 #define PKE_REG_DBF     0x0f /* pke1 only */
  86 #define PKE_REG_R0      0x10 /* R0 .. R3 must be contiguous */
  87 #define PKE_REG_R1      0x11
  88 #define PKE_REG_R2      0x12
  89 #define PKE_REG_R3      0x13
  90 #define PKE_REG_C0      0x14 /* C0 .. C3 must be contiguous */
  91 #define PKE_REG_C1      0x15
  92 #define PKE_REG_C2      0x16
  93 #define PKE_REG_C3      0x17
  94 /* one plus last index */
  95 #define PKE_NUM_REGS    0x18
  96
  97 #define PKE_REGISTER_WINDOW_SIZE  (sizeof(quadword) * PKE_NUM_REGS)
  98
  99
 100
 101 /* PKE commands */
 102
 103 #define PKE_CMD_PKENOP_MASK 0x7F
 104 #define PKE_CMD_PKENOP_BITS 0x00
 105 #define PKE_CMD_STCYCL_MASK 0x7F
 106 #define PKE_CMD_STCYCL_BITS 0x01
 107 #define PKE_CMD_OFFSET_MASK 0x7F
 108 #define PKE_CMD_OFFSET_BITS 0x02
 109 #define PKE_CMD_BASE_MASK 0x7F
 110 #define PKE_CMD_BASE_BITS 0x03
 111 #define PKE_CMD_ITOP_MASK 0x7F
 112 #define PKE_CMD_ITOP_BITS 0x04
 113 #define PKE_CMD_STMOD_MASK 0x7F
 114 #define PKE_CMD_STMOD_BITS 0x05
 115 #define PKE_CMD_MSKPATH3_MASK 0x7F
 116 #define PKE_CMD_MSKPATH3_BITS 0x06
 117 #define PKE_CMD_PKEMARK_MASK 0x7F
 118 #define PKE_CMD_PKEMARK_BITS 0x07
 119 #define PKE_CMD_FLUSHE_MASK 0x7F
 120 #define PKE_CMD_FLUSHE_BITS 0x10
 121 #define PKE_CMD_FLUSH_MASK 0x7F
 122 #define PKE_CMD_FLUSH_BITS 0x11
 123 #define PKE_CMD_FLUSHA_MASK 0x7F
 124 #define PKE_CMD_FLUSHA_BITS 0x13
 125 #define PKE_CMD_PKEMSCAL_MASK 0x7F  /* CAL == "call" */
 126 #define PKE_CMD_PKEMSCAL_BITS 0x14
 127 #define PKE_CMD_PKEMSCNT_MASK 0x7F  /* CNT == "continue" */
 128 #define PKE_CMD_PKEMSCNT_BITS 0x17
 129 #define PKE_CMD_PKEMSCALF_MASK 0x7F /* CALF == "call after flush" */
 130 #define PKE_CMD_PKEMSCALF_BITS 0x15
 131 #define PKE_CMD_STMASK_MASK 0x7F
 132 #define PKE_CMD_STMASK_BITS 0x20
 133 #define PKE_CMD_STROW_MASK 0x7F
 134 #define PKE_CMD_STROW_BITS 0x30
 135 #define PKE_CMD_STCOL_MASK 0x7F
 136 #define PKE_CMD_STCOL_BITS 0x31
 137 #define PKE_CMD_MPG_MASK 0x7F
 138 #define PKE_CMD_MPG_BITS 0x4A
 139 #define PKE_CMD_DIRECT_MASK 0x7F
 140 #define PKE_CMD_DIRECT_BITS 0x50
 141 #define PKE_CMD_DIRECTHL_MASK 0x7F
 142 #define PKE_CMD_DIRECTHL_BITS 0x51
 143 #define PKE_CMD_UNPACK_MASK 0x60
 144 #define PKE_CMD_UNPACK_BITS 0x60
 145
 146 /* test given word for particular PKE command bit pattern */
 147 #define IS_PKE_CMD(word,cmd) (((word) & PKE_CMD_##cmd##_MASK) == PKE_CMD_##cmd##_BITS)
 148
 149
 150 /* register bitmasks: bit numbers for end and beginning of fields */
 151
 152 /* PKE opcode */
 153 #define PKE_OPCODE_I_E 31
 154 #define PKE_OPCODE_I_B 31
 155 #define PKE_OPCODE_CMD_E 30
 156 #define PKE_OPCODE_CMD_B 24
 157 #define PKE_OPCODE_NUM_E 23
 158 #define PKE_OPCODE_NUM_B 16
 159 #define PKE_OPCODE_IMM_E 15
 160 #define PKE_OPCODE_IMM_B 0
 161
 162 /* STAT register */
 163 #define PKE_REG_STAT_FQC_E 28
 164 #define PKE_REG_STAT_FQC_B 24
 165 #define PKE_REG_STAT_FDR_E 23
 166 #define PKE_REG_STAT_FDR_B 23
 167 #define PKE_REG_STAT_ER1_E 13
 168 #define PKE_REG_STAT_ER1_B 13
 169 #define PKE_REG_STAT_ER0_E 12
 170 #define PKE_REG_STAT_ER0_B 12
 171 #define PKE_REG_STAT_INT_E 11
 172 #define PKE_REG_STAT_INT_B 11
 173 #define PKE_REG_STAT_PIS_E 10
 174 #define PKE_REG_STAT_PIS_B 10
 175 #define PKE_REG_STAT_PFS_E 9
 176 #define PKE_REG_STAT_PFS_B 9
 177 #define PKE_REG_STAT_PSS_E 8
 178 #define PKE_REG_STAT_PSS_B 8
 179 #define PKE_REG_STAT_DBF_E 7
 180 #define PKE_REG_STAT_DBF_B 7
 181 #define PKE_REG_STAT_MRK_E 6
 182 #define PKE_REG_STAT_MRK_B 6
 183 #define PKE_REG_STAT_PGW_E 3
 184 #define PKE_REG_STAT_PGW_B 3
 185 #define PKE_REG_STAT_PEW_E 2
 186 #define PKE_REG_STAT_PEW_B 2
 187 #define PKE_REG_STAT_PPS_E 1
 188 #define PKE_REG_STAT_PPS_B 0
 189
 190 #define PKE_REG_STAT_PPS_IDLE 0x00 /* ready to execute next instruction */
 191 #define PKE_REG_STAT_PPS_WAIT 0x01 /* not enough words in FIFO */
 192 #define PKE_REG_STAT_PPS_DECODE 0x02 /* decoding instruction */
 193 #define PKE_REG_STAT_PPS_STALL 0x02 /* alias state for stall (e.g., FLUSHE) */
 194 #define PKE_REG_STAT_PPS_XFER 0x03 /* transferring instruction operands */
 195
 196 /* DBF register */
 197 #define PKE_REG_DBF_DF_E 0
 198 #define PKE_REG_DBF_DF_B 0
 199
 200 /* OFST register */
 201 #define PKE_REG_OFST_OFFSET_E 9
 202 #define PKE_REG_OFST_OFFSET_B 0
 203
 204 /* OFST register */
 205 #define PKE_REG_TOPS_TOPS_E 9
 206 #define PKE_REG_TOPS_TOPS_B 0
 207
 208 /* BASE register */
 209 #define PKE_REG_BASE_BASE_E 9
 210 #define PKE_REG_BASE_BASE_B 0
 211
 212 /* ITOPS register */
 213 #define PKE_REG_ITOPS_ITOPS_E 9
 214 #define PKE_REG_ITOPS_ITOPS_B 0
 215
 216 /* MODE register */
 217 #define PKE_REG_MODE_MDE_E 1
 218 #define PKE_REG_MODE_MDE_B 0
 219
 220 /* NUM register */
 221 #define PKE_REG_NUM_NUM_E 9
 222 #define PKE_REG_NUM_NUM_B 0
 223
 224 /* MARK register */
 225 #define PKE_REG_MARK_MARK_E 15
 226 #define PKE_REG_MARK_MARK_B 0
 227
 228 /* ITOP register */
 229 #define PKE_REG_ITOP_ITOP_E 9
 230 #define PKE_REG_ITOP_ITOP_B 0
 231
 232 /* TOP register */
 233 #define PKE_REG_TOP_TOP_E 9
 234 #define PKE_REG_TOP_TOP_B 0
 235
 236 /* MASK register */
 237 #define PKE_REG_MASK_MASK_E 31
 238 #define PKE_REG_MASK_MASK_B 0
 239
 240 /* CYCLE register */
 241 #define PKE_REG_CYCLE_WL_E 15
 242 #define PKE_REG_CYCLE_WL_B 8
 243 #define PKE_REG_CYCLE_CL_E 7
 244 #define PKE_REG_CYCLE_CL_B 0
 245
 246 /* ERR register */
 247 #define PKE_REG_ERR_ME1_E 2
 248 #define PKE_REG_ERR_ME1_B 2
 249 #define PKE_REG_ERR_ME0_E 1
 250 #define PKE_REG_ERR_ME0_B 1
 251 #define PKE_REG_ERR_MII_E 0
 252 #define PKE_REG_ERR_MII_B 0
 253
 254 /* FBRST command bitfields */
 255 #define PKE_REG_FBRST_STC_E 3
 256 #define PKE_REG_FBRST_STC_B 3
 257 #define PKE_REG_FBRST_STP_E 2
 258 #define PKE_REG_FBRST_STP_B 2
 259 #define PKE_REG_FBRST_FBK_E 1
 260 #define PKE_REG_FBRST_FBK_B 1
 261 #define PKE_REG_FBRST_RST_E 0
 262 #define PKE_REG_FBRST_RST_B 0
 263
 264 /* MSKPATH3 command bitfields */
 265 #define PKE_REG_MSKPATH3_E 15
 266 #define PKE_REG_MSKPATH3_B 15
 267
 268
 269 /* UNPACK opcodes */
 270 #define PKE_UNPACK(vn,vl) ((vn) << 2 | (vl))
 271 #define PKE_UNPACK_S_32  PKE_UNPACK(0, 0)
 272 #define PKE_UNPACK_S_16  PKE_UNPACK(0, 1)
 273 #define PKE_UNPACK_S_8   PKE_UNPACK(0, 2)
 274 #define PKE_UNPACK_V2_32 PKE_UNPACK(1, 0)
 275 #define PKE_UNPACK_V2_16 PKE_UNPACK(1, 1)
 276 #define PKE_UNPACK_V2_8  PKE_UNPACK(1, 2)
 277 #define PKE_UNPACK_V3_32 PKE_UNPACK(2, 0)
 278 #define PKE_UNPACK_V3_16 PKE_UNPACK(2, 1)
 279 #define PKE_UNPACK_V3_8  PKE_UNPACK(2, 2)
 280 #define PKE_UNPACK_V4_32 PKE_UNPACK(3, 0)
 281 #define PKE_UNPACK_V4_16 PKE_UNPACK(3, 1)
 282 #define PKE_UNPACK_V4_8  PKE_UNPACK(3, 2)
 283 #define PKE_UNPACK_V4_5  PKE_UNPACK(3, 3)
 284
 285
 286 /* MASK register sub-field definitions */
 287 #define PKE_MASKREG_INPUT 0
 288 #define PKE_MASKREG_ROW 1
 289 #define PKE_MASKREG_COLUMN 2
 290 #define PKE_MASKREG_NOTHING 3
 291
 292
 293 /* STMOD register field definitions */
 294 #define PKE_MODE_INPUT 0
 295 #define PKE_MODE_ADDROW 1
 296 #define PKE_MODE_ACCROW 2
 297
 298
 299 /* extract a MASK register sub-field for row [0..3] and column [0..3] */
 300 /* MASK register is laid out of 2-bit values in this r-c order */
 301 /* m33 m32 m31 m30 m23 m22 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 */
 302 #define PKE_MASKREG_GET(me,row,col) \
 303 ((((me)->regs[PKE_REG_MASK][0]) >> (8*(row) + 2*(col))) & 0x03)
 304
 305
 306 /* operations - replace with those in sim-bits.h when convenient */
 307
 308 /* unsigned 32-bit mask of given width */
 309 #define BIT_MASK(width) ((width) == 31 ? 0xffffffff : (((unsigned_4)1) << (width+1)) - 1)
 310 /* e.g.: BIT_MASK(4) = 00011111 */
 311
 312 /* mask between given given bits numbers (MSB) */
 313 #define BIT_MASK_BTW(begin,end) ((BIT_MASK(end) & ~((begin) == 0 ? 0 : BIT_MASK((begin)-1))))
 314 /* e.g.: BIT_MASK_BTW(4,11) = 0000111111110000 */
 315
 316 /* set bitfield value */
 317 #define BIT_MASK_SET(lvalue,begin,end,value) \
 318 do { \
 319   ASSERT((begin) <= (end)); \
 320   (lvalue) &= ~BIT_MASK_BTW((begin),(end)); \
 321   (lvalue) |= ((value) << (begin)) & BIT_MASK_BTW((begin),(end)); \
 322 } while(0)
 323
 324 /* get bitfield value */
 325 #define BIT_MASK_GET(rvalue,begin,end) \
 326   (((rvalue) & BIT_MASK_BTW(begin,end)) >> (begin))
 327 /* e.g., BIT_MASK_GET(0000111100001111, 2, 8) = 0000000100001100 */
 328
 329 /* These ugly macro hacks allow succinct bitfield accesses */
 330 /* set a bitfield in a register by "name" */
 331 #define PKE_REG_MASK_SET(me,reg,flag,value) \
 332      do { \
 333        unsigned_4 old = BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
 334                     PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E); \
 335        BIT_MASK_SET(((me)->regs[PKE_REG_##reg][0]), \
 336                     PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E, \
 337                     (value)); \
 338        if( indebug ((me)->dev.name)) \
 339          { \
 340            if (old != (value)) \
 341            { \
 342              if (((me)->fifo_trace_file == NULL ) &&  \
 343                  ((me)->fifo_trace_file_name != NULL )) \
 344                sky_open_file (&((me)->fifo_trace_file), \
 345                               (me)->fifo_trace_file_name, \
 346                               (char *) NULL, _IOLBF ); \
 347              fprintf (((me)->fifo_trace_file != NULL) ? \
 348                       (me)->fifo_trace_file : stdout, \
 349                       "# Reg %s:%s = 0x%x\n", #reg, #flag, (unsigned)(value)); \
 350            } \
 351          } \
 352      } while(0)
 353
 354 /* get a bitfield from a register by "name" */
 355 #define PKE_REG_MASK_GET(me,reg,flag) \
 356      BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
 357                   PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E)
 358
 359
 360 #define PKE_LIMIT(value,max) ((value) > (max) ? (max) : (value))
 361
 362
 363 /* Classify words in a FIFO quadword */
 364 enum wordclass
 365 {
 366   wc_dma = 'D',
 367   wc_pkecode = 'P',
 368   wc_unknown = '?',
 369   wc_pkedata = '.',
 370   wc_gpuiftag = 'g'
 371 };
 372
 373
 374 /* One row in the FIFO */
 375 struct fifo_quadword
 376 {
 377   /* 128 bits of data */
 378   quadword data;
 379   /* source main memory address (or 0: unknown) */
 380   unsigned_4 source_address;
 381   /* classification of words in quadword; wc_dma set on DMA tags at FIFO write */
 382   enum wordclass word_class[4];
 383 };
 384
 385
 386 /* quadword FIFO structure for PKE */
 387 typedef struct pke_fifo
 388 {
 389   struct fifo_quadword** quadwords; /* pointer to fifo quadwords */
 390   unsigned_4 origin; /* quadword serial number of quadwords[0] */
 391   unsigned_4 length; /* length of quadword pointer array: 0..N */
 392   unsigned_4 next;   /* relative index of first unfilled quadword: 0..length-1 */
 393 } pke_fifo;
 394
 395 #define PKE_FIFO_GROW_SIZE 1000 /* number of quadword pointers to allocate */
 396 #define PKE_FIFO_ARCHEOLOGY 1000 /* number of old quadwords to keep as history */
 397
 398
 399
 400 /* PKE internal state: FIFOs, registers, handle to VU friend */
 401 struct pke_device
 402 {
 403   /* common device info */
 404   device dev;
 405
 406   /* identity: 0=PKE0, 1=PKE1 */
 407   int pke_number;
 408   int flags;
 409
 410   /* quadword registers: data in [0] word only */
 411   quadword regs[PKE_NUM_REGS];
 412
 413   /* write buffer for FIFO address */
 414   quadword fifo_qw_in_progress;
 415   int fifo_qw_done; /* bitfield */
 416
 417   /* FIFO - private: use only pke_fifo_* routines to access */
 418   struct pke_fifo fifo;  /* array of FIFO quadword pointers */
 419   FILE* fifo_trace_file; /* stdio stream open in append mode, or 0 for no trace */
 420   char* fifo_trace_file_name; /* user defined debug trace file name  */
 421
 422   /* FIFO cache -- curry last search pke_pcrel_fifo results */
 423   unsigned_4 last_fifo_pc;
 424   unsigned_4 last_qw_pc;
 425   unsigned_4 last_num;
 426   unsigned_4 last_new_fifo_pc;
 427   unsigned_4 last_new_qw_pc;
 428
 429   /* PC */
 430   int fifo_pc;  /* 0 .. (fifo_num_elements-1): quadword index of next instruction */
 431   int qw_pc;    /* 0 .. 3:                     word index of next instruction */
 432
 433   /* Disassembly state */
 434   FILE *trace_file;
 435   char *trace_file_name;
 436 };
 437
 438
 439 extern struct pke_device pke0_device;
 440 extern struct pke_device pke1_device;
 441
 442
 443
 444 /* Flags for PKE.flags */
 445
 446 #define PKE_FLAG_NONE        0x00
 447 #define PKE_FLAG_PENDING_PSS 0x01 /* PSS bit written-to; set STAT:PSS after current instruction */
 448 #define PKE_FLAG_INT_NOLOOP  0x02 /* INT PKEcode received; INT/PIS set; suppress loop after resumption */
 449 #define PKE_FLAG_TRACE_ON    0x04 /* Trace file request from command line  */
 450
 451 /* Kludge alert */
 452
 453 #define PKE_MEM_READ(me,addr,data,size) \
 454     do { \
 455       sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
 456       unsigned_##size value = \
 457         sim_core_read_aligned_##size(cpu, CIA_GET(cpu), read_map, \
 458                                      (SIM_ADDR)(addr)); \
 459       memcpy((unsigned_##size*) (data), (void*) & value, size); \
 460      } while(0)
 461
 462 #define PKE_MEM_WRITE(me,addr,data,size) \
 463     do { sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
 464          unsigned_##size value; \
 465          memcpy((void*) & value, (unsigned_##size*)(data), size); \
 466          sim_core_write_aligned_##size(cpu, CIA_GET(cpu), write_map, \
 467                                        (SIM_ADDR)(addr), value); \
 468          if (indebug ((me)->dev.name)) \
 469            { \
 470              int i; \
 471              unsigned_##size value_te; \
 472              value_te = H2T_##size(value); \
 473              if (((me)->fifo_trace_file == NULL ) && \
 474                  ((me)->fifo_trace_file_name != NULL )) \
 475                sky_open_file (&((me)->fifo_trace_file), \
 476                               (me)->fifo_trace_file_name, \
 477                               (char *) NULL, _IOLBF ); \
 478              fprintf (((me)->fifo_trace_file != NULL) ? \
 479                       (me)->fifo_trace_file : stdout, \
 480                       "# Write %2d bytes  to  ", size); \
 481              fprintf (((me)->fifo_trace_file != NULL) ? \
 482                       (me)->fifo_trace_file : stdout, \
 483                      "0x%08lx: ", (unsigned long)(addr)); \
 484              for(i=0; i<size; i++) \
 485                fprintf (((me)->fifo_trace_file != NULL) ? \
 486                         (me)->fifo_trace_file : stdout, \
 487                         " %02x", ((unsigned_1*)(& value_te))[i]); \
 488              fprintf (((me)->fifo_trace_file != NULL) ? \
 489                       (me)->fifo_trace_file : stdout, \
 490                       "\n"); \
 491            } \
 492         } while(0)
 493
 494
 495 #endif /* H_PKE_H */