sim/mips/sky-pke.h

   1 /* Copyright (C) 1998, Cygnus Solutions */
   2
   3 #ifndef H_PKE_H
   4 #define H_PKE_H
   5
   6 #include "sim-main.h"
   7 #include "sky-device.h"
   8
   9
  10
  11 /* External functions */
  12
  13 void pke0_attach(SIM_DESC sd);
  14 void pke0_issue(void);
  15 void pke1_attach(SIM_DESC sd);
  16 void pke1_issue(void);
  17
  18 /* Quadword data type */
  19
  20 typedef unsigned_4 quadword[4];
  21
  22 /* truncate address to quadword */
  23 #define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f)
  24 /* extract offset in quadword */
  25 #define ADDR_OFFSET_QW(addr) ((addr) & 0x0f)
  26
  27
  28 /* SCEI memory mapping information */
  29
  30 #define PKE0_REGISTER_WINDOW_START 0x10000800
  31 #define PKE1_REGISTER_WINDOW_START 0x10000A00
  32 #define PKE0_FIFO_ADDR             0x10008000
  33 #define PKE1_FIFO_ADDR             0x10008010
  34
  35
  36 /* Quadword indices of PKE registers.  Actual registers sit at bottom
  37    32 bits of each quadword. */
  38 #define PKE_REG_STAT    0x00
  39 #define PKE_REG_FBRST   0x01
  40 #define PKE_REG_ERR     0x02
  41 #define PKE_REG_MARK    0x03
  42 #define PKE_REG_CYCLE   0x04
  43 #define PKE_REG_MODE    0x05
  44 #define PKE_REG_NUM     0x06
  45 #define PKE_REG_MASK    0x07
  46 #define PKE_REG_CODE    0x08
  47 #define PKE_REG_ITOPS   0x09
  48 #define PKE_REG_BASE    0x0a /* pke1 only */
  49 #define PKE_REG_OFST    0x0b /* pke1 only */
  50 #define PKE_REG_TOPS    0x0c /* pke1 only */
  51 #define PKE_REG_ITOP    0x0d
  52 #define PKE_REG_TOP     0x0e /* pke1 only */
  53 #define PKE_REG_DBF     0x0f /* pke1 only */
  54 #define PKE_REG_R0      0x10 /* R0 .. R3 must be contiguous */
  55 #define PKE_REG_R1      0x11
  56 #define PKE_REG_R2      0x12
  57 #define PKE_REG_R3      0x13
  58 #define PKE_REG_C0      0x14 /* C0 .. C3 must be contiguous */
  59 #define PKE_REG_C1      0x15
  60 #define PKE_REG_C2      0x16
  61 #define PKE_REG_C3      0x17
  62 /* one plus last index */
  63 #define PKE_NUM_REGS    0x18
  64
  65 #define PKE_REGISTER_WINDOW_SIZE  (sizeof(quadword) * PKE_NUM_REGS)
  66
  67
  68 /* virtual addresses for source-addr tracking */
  69 #define PKE0_SRCADDR    0x20000020
  70 #define PKE1_SRCADDR    0x20000024
  71
  72
  73 /* PKE commands */
  74
  75 #define PKE_CMD_PKENOP_MASK 0x7F
  76 #define PKE_CMD_PKENOP_BITS 0x00
  77 #define PKE_CMD_STCYCL_MASK 0x7F
  78 #define PKE_CMD_STCYCL_BITS 0x01
  79 #define PKE_CMD_OFFSET_MASK 0x7F
  80 #define PKE_CMD_OFFSET_BITS 0x02
  81 #define PKE_CMD_BASE_MASK 0x7F
  82 #define PKE_CMD_BASE_BITS 0x03
  83 #define PKE_CMD_ITOP_MASK 0x7F
  84 #define PKE_CMD_ITOP_BITS 0x04
  85 #define PKE_CMD_STMOD_MASK 0x7F
  86 #define PKE_CMD_STMOD_BITS 0x05
  87 #define PKE_CMD_MSKPATH3_MASK 0x7F
  88 #define PKE_CMD_MSKPATH3_BITS 0x06
  89 #define PKE_CMD_PKEMARK_MASK 0x7F
  90 #define PKE_CMD_PKEMARK_BITS 0x07
  91 #define PKE_CMD_FLUSHE_MASK 0x7F
  92 #define PKE_CMD_FLUSHE_BITS 0x10
  93 #define PKE_CMD_FLUSH_MASK 0x7F
  94 #define PKE_CMD_FLUSH_BITS 0x11
  95 #define PKE_CMD_FLUSHA_MASK 0x7F
  96 #define PKE_CMD_FLUSHA_BITS 0x13
  97 #define PKE_CMD_PKEMSCAL_MASK 0x7F  /* CAL == "call" */
  98 #define PKE_CMD_PKEMSCAL_BITS 0x14
  99 #define PKE_CMD_PKEMSCNT_MASK 0x7F  /* CNT == "continue" */
 100 #define PKE_CMD_PKEMSCNT_BITS 0x17
 101 #define PKE_CMD_PKEMSCALF_MASK 0x7F /* CALF == "call after flush" */
 102 #define PKE_CMD_PKEMSCALF_BITS 0x15
 103 #define PKE_CMD_STMASK_MASK 0x7F
 104 #define PKE_CMD_STMASK_BITS 0x20
 105 #define PKE_CMD_STROW_MASK 0x7F
 106 #define PKE_CMD_STROW_BITS 0x30
 107 #define PKE_CMD_STCOL_MASK 0x7F
 108 #define PKE_CMD_STCOL_BITS 0x31
 109 #define PKE_CMD_MPG_MASK 0x7F
 110 #define PKE_CMD_MPG_BITS 0x4A
 111 #define PKE_CMD_DIRECT_MASK 0x7F
 112 #define PKE_CMD_DIRECT_BITS 0x50
 113 #define PKE_CMD_DIRECTHL_MASK 0x7F
 114 #define PKE_CMD_DIRECTHL_BITS 0x51
 115 #define PKE_CMD_UNPACK_MASK 0x60
 116 #define PKE_CMD_UNPACK_BITS 0x60
 117
 118 /* test given word for particular PKE command bit pattern */
 119 #define IS_PKE_CMD(word,cmd) (((word) & PKE_CMD_##cmd##_MASK) == PKE_CMD_##cmd##_BITS)
 120
 121
 122 /* register bitmasks: bit numbers for end and beginning of fields */
 123
 124 /* PKE opcode */
 125 #define PKE_OPCODE_I_E 31
 126 #define PKE_OPCODE_I_B 31
 127 #define PKE_OPCODE_CMD_E 30
 128 #define PKE_OPCODE_CMD_B 24
 129 #define PKE_OPCODE_NUM_E 23
 130 #define PKE_OPCODE_NUM_B 16
 131 #define PKE_OPCODE_IMM_E 15
 132 #define PKE_OPCODE_IMM_B 0
 133
 134 /* STAT register */
 135 #define PKE_REG_STAT_FQC_E 28
 136 #define PKE_REG_STAT_FQC_B 24
 137 #define PKE_REG_STAT_FDR_E 23
 138 #define PKE_REG_STAT_FDR_B 23
 139 #define PKE_REG_STAT_ER1_E 13
 140 #define PKE_REG_STAT_ER1_B 13
 141 #define PKE_REG_STAT_ER0_E 12
 142 #define PKE_REG_STAT_ER0_B 12
 143 #define PKE_REG_STAT_INT_E 11
 144 #define PKE_REG_STAT_INT_B 11
 145 #define PKE_REG_STAT_PIS_E 10
 146 #define PKE_REG_STAT_PIS_B 10
 147 #define PKE_REG_STAT_PFS_E 9
 148 #define PKE_REG_STAT_PFS_B 9
 149 #define PKE_REG_STAT_PSS_E 8
 150 #define PKE_REG_STAT_PSS_B 8
 151 #define PKE_REG_STAT_DBF_E 7
 152 #define PKE_REG_STAT_DBF_B 7
 153 #define PKE_REG_STAT_MRK_E 6
 154 #define PKE_REG_STAT_MRK_B 6
 155 #define PKE_REG_STAT_PGW_E 3
 156 #define PKE_REG_STAT_PGW_B 3
 157 #define PKE_REG_STAT_PEW_E 2
 158 #define PKE_REG_STAT_PEW_B 2
 159 #define PKE_REG_STAT_PPS_E 1
 160 #define PKE_REG_STAT_PPS_B 0
 161
 162 #define PKE_REG_STAT_PPS_IDLE 0x00 /* ready to execute next instruction */
 163 #define PKE_REG_STAT_PPS_WAIT 0x01 /* not enough words in FIFO */
 164 #define PKE_REG_STAT_PPS_DECODE 0x02 /* decoding instruction */
 165 #define PKE_REG_STAT_PPS_STALL 0x02 /* alias state for FLUSHE stall */
 166 #define PKE_REG_STAT_PPS_XFER 0x03 /* transferring instruction operands */
 167
 168 /* DBF register */
 169 #define PKE_REG_DBF_DF_E 0
 170 #define PKE_REG_DBF_DF_B 0
 171
 172 /* OFST register */
 173 #define PKE_REG_OFST_OFFSET_E 9
 174 #define PKE_REG_OFST_OFFSET_B 0
 175
 176 /* OFST register */
 177 #define PKE_REG_TOPS_TOPS_E 9
 178 #define PKE_REG_TOPS_TOPS_B 0
 179
 180 /* BASE register */
 181 #define PKE_REG_BASE_BASE_E 9
 182 #define PKE_REG_BASE_BASE_B 0
 183
 184 /* ITOPS register */
 185 #define PKE_REG_ITOPS_ITOPS_E 9
 186 #define PKE_REG_ITOPS_ITOPS_B 0
 187
 188 /* MODE register */
 189 #define PKE_REG_MODE_MDE_E 1
 190 #define PKE_REG_MODE_MDE_B 0
 191
 192 /* MARK register */
 193 #define PKE_REG_MARK_MARK_E 15
 194 #define PKE_REG_MARK_MARK_B 0
 195
 196 /* ITOP register */
 197 #define PKE_REG_ITOP_ITOP_E 9
 198 #define PKE_REG_ITOP_ITOP_B 0
 199
 200 /* TOP register */
 201 #define PKE_REG_TOP_TOP_E 9
 202 #define PKE_REG_TOP_TOP_B 0
 203
 204 /* MASK register */
 205 #define PKE_REG_MASK_MASK_E 31
 206 #define PKE_REG_MASK_MASK_B 0
 207
 208 /* CYCLE register */
 209 #define PKE_REG_CYCLE_WL_E 15
 210 #define PKE_REG_CYCLE_WL_B 8
 211 #define PKE_REG_CYCLE_CL_E 7
 212 #define PKE_REG_CYCLE_CL_B 0
 213
 214 /* ERR register */
 215 #define PKE_REG_ERR_ME1_E 2
 216 #define PKE_REG_ERR_ME1_B 2
 217 #define PKE_REG_ERR_ME0_E 1
 218 #define PKE_REG_ERR_ME0_B 1
 219 #define PKE_REG_ERR_MII_E 0
 220 #define PKE_REG_ERR_MII_B 0
 221
 222
 223 /* source-addr for words written to VU/GPUIF ports */
 224 #define PKE0_SRCADDR 0x20000020 /* from 1998-01-22 e-mail plans */
 225 #define PKE1_SRCADDR 0x20000024 /* from 1998-01-22 e-mail plans */
 226
 227
 228 /* UNPACK opcodes */
 229 #define PKE_UNPACK(vn,vl) ((vn) << 2 | (vl))
 230 #define PKE_UNPACK_S_32  PKE_UNPACK(0, 0)
 231 #define PKE_UNPACK_S_16  PKE_UNPACK(0, 1)
 232 #define PKE_UNPACK_S_8   PKE_UNPACK(0, 2)
 233 #define PKE_UNPACK_V2_32 PKE_UNPACK(1, 0)
 234 #define PKE_UNPACK_V2_16 PKE_UNPACK(1, 1)
 235 #define PKE_UNPACK_V2_8  PKE_UNPACK(1, 2)
 236 #define PKE_UNPACK_V3_32 PKE_UNPACK(2, 0)
 237 #define PKE_UNPACK_V3_16 PKE_UNPACK(2, 1)
 238 #define PKE_UNPACK_V3_8  PKE_UNPACK(2, 2)
 239 #define PKE_UNPACK_V4_32 PKE_UNPACK(3, 0)
 240 #define PKE_UNPACK_V4_16 PKE_UNPACK(3, 1)
 241 #define PKE_UNPACK_V4_8  PKE_UNPACK(3, 2)
 242 #define PKE_UNPACK_V4_5  PKE_UNPACK(3, 3)
 243
 244
 245 /* MASK register sub-field definitions */
 246 #define PKE_MASKREG_INPUT 0
 247 #define PKE_MASKREG_ROW 1
 248 #define PKE_MASKREG_COLUMN 2
 249 #define PKE_MASKREG_NOTHING 3
 250
 251
 252 /* STMOD register field definitions */
 253 #define PKE_MODE_INPUT 0
 254 #define PKE_MODE_ADDROW 1
 255 #define PKE_MODE_ACCROW 2
 256
 257
 258 /* extract a MASK register sub-field for row [0..3] and column [0..3] */
 259 /* MASK register is laid out of 2-bit values in this r-c order */
 260 /* m33 m32 m31 m30 m23 m22 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 */
 261 #define PKE_MASKREG_GET(me,row,col) \
 262 ((((me)->regs[PKE_REG_MASK][0]) >> (8*(row) + 2*(col))) & 0x03)
 263
 264
 265 /* and now a few definitions that rightfully belong elsewhere */
 266 #ifdef PKE_DEBUG
 267
 268 /* GPUIF addresses */
 269 #define GPUIF_PATH3_FIFO_ADDR  0x10008020    /* data from CORE        */
 270 #define GPUIF_PATH1_FIFO_ADDR  0x10008030    /* data from VU1         */
 271 #define GPUIF_PATH2_FIFO_ADDR  0x10008040    /* data from PKE1        */
 272
 273 /* VU STAT register */
 274 #define VU_REG_STAT_VGW_E 4
 275 #define VU_REG_STAT_VGW_B 4
 276 #define VU_REG_STAT_VBS_E 0
 277 #define VU_REG_STAT_VBS_B 0
 278
 279 /* VU PC pseudo-registers */ /* omitted from 1998-01-22 e-mail plans */
 280 #define VU0_PC_START 0x20025000
 281 #define VU1_PC_START 0x20026000
 282
 283 /* VU source-addr tracking tables */ /* changed from 1998-01-22 e-mail plans */
 284 #define VU0_MEM0_SRCADDR_START 0x21000000
 285 #define VU0_MEM1_SRCADDR_START 0x21004000
 286 #define VU1_MEM0_SRCADDR_START 0x21008000
 287 #define VU1_MEM1_SRCADDR_START 0x2100C000
 288
 289 #endif /* PKE_DEBUG */
 290
 291
 292 /* operations  */
 293 /* unsigned 32-bit mask of given width */
 294 #define BIT_MASK(width) (width == 31 ? 0xffffffff : (((unsigned_4)1) << (width+1)) - 1)
 295 /* e.g.: BIT_MASK(4) = 00011111 */
 296
 297 /* mask between given given bits numbers (MSB) */
 298 #define BIT_MASK_BTW(begin,end) (BIT_MASK(end) & ~BIT_MASK(begin))
 299 /* e.g.: BIT_MASK_BTW(4,11) = 0000111111110000 */
 300
 301 /* set bitfield value */
 302 #define BIT_MASK_SET(lvalue,begin,end,value) \
 303 do { \
 304   lvalue &= ~BIT_MASK_BTW(begin,end); \
 305   lvalue |= (((value) << (begin)) & BIT_MASK_BTW(begin,end)); \
 306 } while(0)
 307
 308 /* get bitfield value */
 309 #define BIT_MASK_GET(rvalue,begin,end) \
 310   (((rvalue) & BIT_MASK_BTW(begin,end)) >> (begin))
 311 /* e.g., BIT_MASK_GET(0000111100001111, 2, 8) = 0000000100001100 */
 312
 313 /* get bitfield value, sign-extended to given bit number */
 314 #define BIT_MASK_GET_SX(rvalue,begin,end,sx) \
 315   (BIT_MASK_GET(rvalue,begin,end) | ((BIT_MASK_GET(rvalue,begin,end) & BIT_MASK_BTW(end,end)) ? BIT_MASK_BTW(end,sx) : 0))
 316 /* e.g., BIT_MASK_GET_SX(0000111100001111, 2, 8, 15) = 1111111100001100 */
 317
 318
 319 /* These ugly macro hacks allow succinct bitfield accesses */
 320 /* set a bitfield in a register by "name" */
 321 #define PKE_REG_MASK_SET(me,reg,flag,value) \
 322      BIT_MASK_SET(((me)->regs[PKE_REG_##reg][0]), \
 323                   PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E, \
 324                   (value))
 325
 326 /* get a bitfield from a register by "name" */
 327 #define PKE_REG_MASK_GET(me,reg,flag) \
 328      BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
 329                   PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E)
 330
 331
 332 #define PKE_LIMIT(value,max) ((value) > (max) ? (max) : (value))
 333
 334
 335 /* One row in the FIFO */
 336 struct fifo_quadword
 337 {
 338   /* 128 bits of data */
 339   quadword data;
 340   /* source main memory address (or 0: unknown) */
 341   address_word source_address;
 342   /* DMA tag present in lower 64 bits */
 343   unsigned_4 dma_tag_present;
 344 };
 345
 346
 347 /* PKE internal state: FIFOs, registers, handle to VU friend */
 348 struct pke_device
 349 {
 350   /* common device info */
 351   device dev;
 352
 353   /* identity: 0=PKE0, 1=PKE1 */
 354   int pke_number;
 355   int flags;
 356
 357   /* quadword registers */
 358   quadword regs[PKE_NUM_REGS];
 359
 360   /* FIFO */
 361   struct fifo_quadword* fifo;
 362   int fifo_num_elements; /* no. of quadwords occupied in FIFO */
 363   int fifo_buffer_size;  /* no. of quadwords of space in FIFO */
 364   FILE* fifo_trace_file; /* or 0 for no trace */ /* XXX: tracing not done */
 365   /* XXX: assumes FIFOs grow indefinately */
 366
 367   /* PC */
 368   int fifo_pc;  /* 0 .. (fifo_num_elements-1): quadword index of next instruction */
 369   int qw_pc;    /* 0 .. 3:                     word index of next instruction */
 370 };
 371
 372
 373 /* Flags for PKE.flags */
 374
 375 #define PKE_FLAG_NONE 0
 376 /* none at present */
 377
 378
 379 #endif /* H_PKE_H */