1 /* Copyright (C) 1998, Cygnus Solutions */
7 #include "sky-device.h"
11 /* External functions */
13 void pke0_attach(SIM_DESC sd
);
14 void pke0_issue(SIM_DESC sd
);
15 void pke1_attach(SIM_DESC sd
);
16 void pke1_issue(SIM_DESC sd
);
19 /* Quadword data type */
21 typedef unsigned_4 quadword
[4];
23 /* truncate address to quadword */
24 #define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f)
25 /* extract offset in quadword */
26 #define ADDR_OFFSET_QW(addr) ((addr) & 0x0f)
29 /* SCEI memory mapping information */
31 #define PKE0_REGISTER_WINDOW_START 0x10003800
32 #define PKE1_REGISTER_WINDOW_START 0x10003C00
33 #define PKE0_FIFO_ADDR 0x10004000
34 #define PKE1_FIFO_ADDR 0x10005000
37 /* and now a few definitions that rightfully belong elsewhere */
41 /* VU source-addr tracking tables */ /* changed from 1998-01-22 e-mail plans */
42 #define VU0_MEM0_SRCADDR_START 0x21000000
43 #define VU0_MEM1_SRCADDR_START 0x21004000
44 #define VU1_MEM0_SRCADDR_START 0x21008000
45 #define VU1_MEM1_SRCADDR_START 0x2100C000
47 /* GPUIF STAT register */
48 #define GPUIF_REG_STAT_APATH_E 11
49 #define GPUIF_REG_STAT_APATH_B 10
51 /* COP2 STAT register */
52 #define COP2_REG_STAT_ADDR VPU_STAT
53 #define COP2_REG_STAT_VBS1_E 8
54 #define COP2_REG_STAT_VBS1_B 8
55 #define COP2_REG_STAT_VBS0_E 0
56 #define COP2_REG_STAT_VBS0_B 0
58 #endif /* PKE_DEBUG */
61 /* Quadword indices of PKE registers. Actual registers sit at bottom
62 32 bits of each quadword. */
63 #define PKE_REG_STAT 0x00
64 #define PKE_REG_FBRST 0x01
65 #define PKE_REG_ERR 0x02
66 #define PKE_REG_MARK 0x03
67 #define PKE_REG_CYCLE 0x04
68 #define PKE_REG_MODE 0x05
69 #define PKE_REG_NUM 0x06
70 #define PKE_REG_MASK 0x07
71 #define PKE_REG_CODE 0x08
72 #define PKE_REG_ITOPS 0x09
73 #define PKE_REG_BASE 0x0a /* pke1 only */
74 #define PKE_REG_OFST 0x0b /* pke1 only */
75 #define PKE_REG_TOPS 0x0c /* pke1 only */
76 #define PKE_REG_ITOP 0x0d
77 #define PKE_REG_TOP 0x0e /* pke1 only */
78 #define PKE_REG_DBF 0x0f /* pke1 only */
79 #define PKE_REG_R0 0x10 /* R0 .. R3 must be contiguous */
80 #define PKE_REG_R1 0x11
81 #define PKE_REG_R2 0x12
82 #define PKE_REG_R3 0x13
83 #define PKE_REG_C0 0x14 /* C0 .. C3 must be contiguous */
84 #define PKE_REG_C1 0x15
85 #define PKE_REG_C2 0x16
86 #define PKE_REG_C3 0x17
87 /* one plus last index */
88 #define PKE_NUM_REGS 0x18
90 #define PKE_REGISTER_WINDOW_SIZE (sizeof(quadword) * PKE_NUM_REGS)
96 #define PKE_CMD_PKENOP_MASK 0x7F
97 #define PKE_CMD_PKENOP_BITS 0x00
98 #define PKE_CMD_STCYCL_MASK 0x7F
99 #define PKE_CMD_STCYCL_BITS 0x01
100 #define PKE_CMD_OFFSET_MASK 0x7F
101 #define PKE_CMD_OFFSET_BITS 0x02
102 #define PKE_CMD_BASE_MASK 0x7F
103 #define PKE_CMD_BASE_BITS 0x03
104 #define PKE_CMD_ITOP_MASK 0x7F
105 #define PKE_CMD_ITOP_BITS 0x04
106 #define PKE_CMD_STMOD_MASK 0x7F
107 #define PKE_CMD_STMOD_BITS 0x05
108 #define PKE_CMD_MSKPATH3_MASK 0x7F
109 #define PKE_CMD_MSKPATH3_BITS 0x06
110 #define PKE_CMD_PKEMARK_MASK 0x7F
111 #define PKE_CMD_PKEMARK_BITS 0x07
112 #define PKE_CMD_FLUSHE_MASK 0x7F
113 #define PKE_CMD_FLUSHE_BITS 0x10
114 #define PKE_CMD_FLUSH_MASK 0x7F
115 #define PKE_CMD_FLUSH_BITS 0x11
116 #define PKE_CMD_FLUSHA_MASK 0x7F
117 #define PKE_CMD_FLUSHA_BITS 0x13
118 #define PKE_CMD_PKEMSCAL_MASK 0x7F /* CAL == "call" */
119 #define PKE_CMD_PKEMSCAL_BITS 0x14
120 #define PKE_CMD_PKEMSCNT_MASK 0x7F /* CNT == "continue" */
121 #define PKE_CMD_PKEMSCNT_BITS 0x17
122 #define PKE_CMD_PKEMSCALF_MASK 0x7F /* CALF == "call after flush" */
123 #define PKE_CMD_PKEMSCALF_BITS 0x15
124 #define PKE_CMD_STMASK_MASK 0x7F
125 #define PKE_CMD_STMASK_BITS 0x20
126 #define PKE_CMD_STROW_MASK 0x7F
127 #define PKE_CMD_STROW_BITS 0x30
128 #define PKE_CMD_STCOL_MASK 0x7F
129 #define PKE_CMD_STCOL_BITS 0x31
130 #define PKE_CMD_MPG_MASK 0x7F
131 #define PKE_CMD_MPG_BITS 0x4A
132 #define PKE_CMD_DIRECT_MASK 0x7F
133 #define PKE_CMD_DIRECT_BITS 0x50
134 #define PKE_CMD_DIRECTHL_MASK 0x7F
135 #define PKE_CMD_DIRECTHL_BITS 0x51
136 #define PKE_CMD_UNPACK_MASK 0x60
137 #define PKE_CMD_UNPACK_BITS 0x60
139 /* test given word for particular PKE command bit pattern */
140 #define IS_PKE_CMD(word,cmd) (((word) & PKE_CMD_##cmd##_MASK) == PKE_CMD_##cmd##_BITS)
143 /* register bitmasks: bit numbers for end and beginning of fields */
146 #define PKE_OPCODE_I_E 31
147 #define PKE_OPCODE_I_B 31
148 #define PKE_OPCODE_CMD_E 30
149 #define PKE_OPCODE_CMD_B 24
150 #define PKE_OPCODE_NUM_E 23
151 #define PKE_OPCODE_NUM_B 16
152 #define PKE_OPCODE_IMM_E 15
153 #define PKE_OPCODE_IMM_B 0
156 #define PKE_REG_STAT_FQC_E 28
157 #define PKE_REG_STAT_FQC_B 24
158 #define PKE_REG_STAT_FDR_E 23
159 #define PKE_REG_STAT_FDR_B 23
160 #define PKE_REG_STAT_ER1_E 13
161 #define PKE_REG_STAT_ER1_B 13
162 #define PKE_REG_STAT_ER0_E 12
163 #define PKE_REG_STAT_ER0_B 12
164 #define PKE_REG_STAT_INT_E 11
165 #define PKE_REG_STAT_INT_B 11
166 #define PKE_REG_STAT_PIS_E 10
167 #define PKE_REG_STAT_PIS_B 10
168 #define PKE_REG_STAT_PFS_E 9
169 #define PKE_REG_STAT_PFS_B 9
170 #define PKE_REG_STAT_PSS_E 8
171 #define PKE_REG_STAT_PSS_B 8
172 #define PKE_REG_STAT_DBF_E 7
173 #define PKE_REG_STAT_DBF_B 7
174 #define PKE_REG_STAT_MRK_E 6
175 #define PKE_REG_STAT_MRK_B 6
176 #define PKE_REG_STAT_PGW_E 3
177 #define PKE_REG_STAT_PGW_B 3
178 #define PKE_REG_STAT_PEW_E 2
179 #define PKE_REG_STAT_PEW_B 2
180 #define PKE_REG_STAT_PPS_E 1
181 #define PKE_REG_STAT_PPS_B 0
183 #define PKE_REG_STAT_PPS_IDLE 0x00 /* ready to execute next instruction */
184 #define PKE_REG_STAT_PPS_WAIT 0x01 /* not enough words in FIFO */
185 #define PKE_REG_STAT_PPS_DECODE 0x02 /* decoding instruction */
186 #define PKE_REG_STAT_PPS_STALL 0x02 /* alias state for stall (e.g., FLUSHE) */
187 #define PKE_REG_STAT_PPS_XFER 0x03 /* transferring instruction operands */
190 #define PKE_REG_DBF_DF_E 0
191 #define PKE_REG_DBF_DF_B 0
194 #define PKE_REG_OFST_OFFSET_E 9
195 #define PKE_REG_OFST_OFFSET_B 0
198 #define PKE_REG_TOPS_TOPS_E 9
199 #define PKE_REG_TOPS_TOPS_B 0
202 #define PKE_REG_BASE_BASE_E 9
203 #define PKE_REG_BASE_BASE_B 0
206 #define PKE_REG_ITOPS_ITOPS_E 9
207 #define PKE_REG_ITOPS_ITOPS_B 0
210 #define PKE_REG_MODE_MDE_E 1
211 #define PKE_REG_MODE_MDE_B 0
214 #define PKE_REG_NUM_NUM_E 9
215 #define PKE_REG_NUM_NUM_B 0
218 #define PKE_REG_MARK_MARK_E 15
219 #define PKE_REG_MARK_MARK_B 0
222 #define PKE_REG_ITOP_ITOP_E 9
223 #define PKE_REG_ITOP_ITOP_B 0
226 #define PKE_REG_TOP_TOP_E 9
227 #define PKE_REG_TOP_TOP_B 0
230 #define PKE_REG_MASK_MASK_E 31
231 #define PKE_REG_MASK_MASK_B 0
234 #define PKE_REG_CYCLE_WL_E 15
235 #define PKE_REG_CYCLE_WL_B 8
236 #define PKE_REG_CYCLE_CL_E 7
237 #define PKE_REG_CYCLE_CL_B 0
240 #define PKE_REG_ERR_ME1_E 2
241 #define PKE_REG_ERR_ME1_B 2
242 #define PKE_REG_ERR_ME0_E 1
243 #define PKE_REG_ERR_ME0_B 1
244 #define PKE_REG_ERR_MII_E 0
245 #define PKE_REG_ERR_MII_B 0
247 /* FBRST command bitfields */
248 #define PKE_REG_FBRST_STC_E 3
249 #define PKE_REG_FBRST_STC_B 3
250 #define PKE_REG_FBRST_STP_E 2
251 #define PKE_REG_FBRST_STP_B 2
252 #define PKE_REG_FBRST_FBK_E 1
253 #define PKE_REG_FBRST_FBK_B 1
254 #define PKE_REG_FBRST_RST_E 0
255 #define PKE_REG_FBRST_RST_B 0
257 /* MSKPATH3 command bitfields */
258 #define PKE_REG_MSKPATH3_E 15
259 #define PKE_REG_MSKPATH3_B 15
263 #define PKE_UNPACK(vn,vl) ((vn) << 2 | (vl))
264 #define PKE_UNPACK_S_32 PKE_UNPACK(0, 0)
265 #define PKE_UNPACK_S_16 PKE_UNPACK(0, 1)
266 #define PKE_UNPACK_S_8 PKE_UNPACK(0, 2)
267 #define PKE_UNPACK_V2_32 PKE_UNPACK(1, 0)
268 #define PKE_UNPACK_V2_16 PKE_UNPACK(1, 1)
269 #define PKE_UNPACK_V2_8 PKE_UNPACK(1, 2)
270 #define PKE_UNPACK_V3_32 PKE_UNPACK(2, 0)
271 #define PKE_UNPACK_V3_16 PKE_UNPACK(2, 1)
272 #define PKE_UNPACK_V3_8 PKE_UNPACK(2, 2)
273 #define PKE_UNPACK_V4_32 PKE_UNPACK(3, 0)
274 #define PKE_UNPACK_V4_16 PKE_UNPACK(3, 1)
275 #define PKE_UNPACK_V4_8 PKE_UNPACK(3, 2)
276 #define PKE_UNPACK_V4_5 PKE_UNPACK(3, 3)
279 /* MASK register sub-field definitions */
280 #define PKE_MASKREG_INPUT 0
281 #define PKE_MASKREG_ROW 1
282 #define PKE_MASKREG_COLUMN 2
283 #define PKE_MASKREG_NOTHING 3
286 /* STMOD register field definitions */
287 #define PKE_MODE_INPUT 0
288 #define PKE_MODE_ADDROW 1
289 #define PKE_MODE_ACCROW 2
292 /* extract a MASK register sub-field for row [0..3] and column [0..3] */
293 /* MASK register is laid out of 2-bit values in this r-c order */
294 /* m33 m32 m31 m30 m23 m22 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 */
295 #define PKE_MASKREG_GET(me,row,col) \
296 ((((me)->regs[PKE_REG_MASK][0]) >> (8*(row) + 2*(col))) & 0x03)
299 /* operations - replace with those in sim-bits.h when convenient */
301 /* unsigned 32-bit mask of given width */
302 #define BIT_MASK(width) ((width) == 31 ? 0xffffffff : (((unsigned_4)1) << (width+1)) - 1)
303 /* e.g.: BIT_MASK(4) = 00011111 */
305 /* mask between given given bits numbers (MSB) */
306 #define BIT_MASK_BTW(begin,end) ((BIT_MASK(end) & ~((begin) == 0 ? 0 : BIT_MASK((begin)-1))))
307 /* e.g.: BIT_MASK_BTW(4,11) = 0000111111110000 */
309 /* set bitfield value */
310 #define BIT_MASK_SET(lvalue,begin,end,value) \
312 ASSERT((begin) <= (end)); \
313 (lvalue) &= ~BIT_MASK_BTW((begin),(end)); \
314 (lvalue) |= ((value) << (begin)) & BIT_MASK_BTW((begin),(end)); \
317 /* get bitfield value */
318 #define BIT_MASK_GET(rvalue,begin,end) \
319 (((rvalue) & BIT_MASK_BTW(begin,end)) >> (begin))
320 /* e.g., BIT_MASK_GET(0000111100001111, 2, 8) = 0000000100001100 */
322 /* These ugly macro hacks allow succinct bitfield accesses */
323 /* set a bitfield in a register by "name" */
324 #define PKE_REG_MASK_SET(me,reg,flag,value) \
326 unsigned_4 old = BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
327 PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E); \
328 BIT_MASK_SET(((me)->regs[PKE_REG_##reg][0]), \
329 PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E, \
331 if((me)->fifo_trace_file != NULL) \
334 fprintf((me)->fifo_trace_file, "# Reg %s:%s = 0x%x\n", #reg, #flag, (unsigned)(value)); \
338 /* get a bitfield from a register by "name" */
339 #define PKE_REG_MASK_GET(me,reg,flag) \
340 BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
341 PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E)
344 #define PKE_LIMIT(value,max) ((value) > (max) ? (max) : (value))
347 /* Classify words in a FIFO quadword */
357 /* One row in the FIFO */
360 /* 128 bits of data */
362 /* source main memory address (or 0: unknown) */
363 unsigned_4 source_address
;
364 /* classification of words in quadword; wc_dma set on DMA tags at FIFO write */
365 enum wordclass word_class
[4];
369 /* PKE internal state: FIFOs, registers, handle to VU friend */
372 /* common device info */
375 /* identity: 0=PKE0, 1=PKE1 */
379 /* quadword registers: data in [0] word only */
380 quadword regs
[PKE_NUM_REGS
];
382 /* write buffer for FIFO address */
383 quadword fifo_qw_in_progress
;
384 int fifo_qw_done
; /* bitfield */
387 struct fifo_quadword
* fifo
;
388 int fifo_num_elements
; /* no. of quadwords occupied in FIFO */
389 int fifo_buffer_size
; /* no. of quadwords of space in FIFO */
390 FILE* fifo_trace_file
; /* or 0 for no trace */
393 int fifo_pc
; /* 0 .. (fifo_num_elements-1): quadword index of next instruction */
394 int qw_pc
; /* 0 .. 3: word index of next instruction */
398 /* Flags for PKE.flags */
400 #define PKE_FLAG_NONE 0x00
401 #define PKE_FLAG_PENDING_PSS 0x01 /* PSS bit written-to; set STAT:PSS after current instruction */
402 #define PKE_FLAG_INT_NOLOOP 0x02 /* INT PKEcode received; INT/PIS set; suppress loop after resumption */
407 #define PKE_MEM_READ(me,addr,data,size) \
409 sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
410 unsigned_##size value = \
411 sim_core_read_aligned_##size(cpu, CIA_GET(cpu), read_map, \
413 memcpy((unsigned_##size*) (data), (void*) & value, size); \
416 #define PKE_MEM_WRITE(me,addr,data,size) \
417 do { sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
418 unsigned_##size value; \
419 memcpy((void*) & value, (unsigned_##size*)(data), size); \
420 sim_core_write_aligned_##size(cpu, CIA_GET(cpu), write_map, \
421 (SIM_ADDR)(addr), value); \
422 if((me)->fifo_trace_file != NULL) \
425 unsigned_##size value_te; \
426 value_te = H2T_##size(value); \
427 fprintf((me)->fifo_trace_file, "# Write %2d bytes to ", size); \
428 fprintf((me)->fifo_trace_file, "0x%08lx: ", (unsigned long)(addr)); \
429 for(i=0; i<size; i++) \
430 fprintf((me)->fifo_trace_file, " %02x", ((unsigned_1*)(& value_te))[i]); \
431 fprintf((me)->fifo_trace_file, "\n"); \