sim/mips/sky-pke.h

   1 /* Copyright (C) 1998, Cygnus Solutions */
   2
   3 #ifndef H_PKE_H
   4 #define H_PKE_H
   5
   6 #include "sim-main.h"
   7 #include "sky-device.h"
   8
   9
  10
  11 /* External functions */
  12
  13 void pke0_attach(SIM_DESC sd);
  14 void pke0_issue(SIM_DESC sd);
  15 void pke1_attach(SIM_DESC sd);
  16 void pke1_issue(SIM_DESC sd);
  17
  18
  19 /* Quadword data type */
  20
  21 typedef unsigned_4 quadword[4];
  22
  23 /* truncate address to quadword */
  24 #define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f)
  25 /* extract offset in quadword */
  26 #define ADDR_OFFSET_QW(addr) ((addr) & 0x0f)
  27
  28
  29 /* SCEI memory mapping information */
  30
  31 #define PKE0_REGISTER_WINDOW_START 0x10003800
  32 #define PKE1_REGISTER_WINDOW_START 0x10003C00
  33 #define PKE0_FIFO_ADDR             0x10004000
  34 #define PKE1_FIFO_ADDR             0x10005000
  35
  36
  37 /* VU source-addr tracking tables */ /* changed from 1998-01-22 e-mail plans */
  38 #define VU0_MEM0_SRCADDR_START 0x21000000
  39 #define VU0_MEM1_SRCADDR_START 0x21004000
  40 #define VU1_MEM0_SRCADDR_START 0x21008000
  41 #define VU1_MEM1_SRCADDR_START 0x2100C000
  42
  43 /* GPUIF STAT register */
  44 #define GPUIF_REG_STAT_APATH_E 11
  45 #define GPUIF_REG_STAT_APATH_B 10
  46
  47 /* COP2 STAT register */
  48 #define COP2_REG_STAT_ADDR VPU_STAT
  49 #define COP2_REG_STAT_VBS1_E 8
  50 #define COP2_REG_STAT_VBS1_B 8
  51 #define COP2_REG_STAT_VBS0_E 0
  52 #define COP2_REG_STAT_VBS0_B 0
  53
  54
  55 /* Quadword indices of PKE registers.  Actual registers sit at bottom
  56    32 bits of each quadword. */
  57 #define PKE_REG_STAT    0x00
  58 #define PKE_REG_FBRST   0x01
  59 #define PKE_REG_ERR     0x02
  60 #define PKE_REG_MARK    0x03
  61 #define PKE_REG_CYCLE   0x04
  62 #define PKE_REG_MODE    0x05
  63 #define PKE_REG_NUM     0x06
  64 #define PKE_REG_MASK    0x07
  65 #define PKE_REG_CODE    0x08
  66 #define PKE_REG_ITOPS   0x09
  67 #define PKE_REG_BASE    0x0a /* pke1 only */
  68 #define PKE_REG_OFST    0x0b /* pke1 only */
  69 #define PKE_REG_TOPS    0x0c /* pke1 only */
  70 #define PKE_REG_ITOP    0x0d
  71 #define PKE_REG_TOP     0x0e /* pke1 only */
  72 #define PKE_REG_DBF     0x0f /* pke1 only */
  73 #define PKE_REG_R0      0x10 /* R0 .. R3 must be contiguous */
  74 #define PKE_REG_R1      0x11
  75 #define PKE_REG_R2      0x12
  76 #define PKE_REG_R3      0x13
  77 #define PKE_REG_C0      0x14 /* C0 .. C3 must be contiguous */
  78 #define PKE_REG_C1      0x15
  79 #define PKE_REG_C2      0x16
  80 #define PKE_REG_C3      0x17
  81 /* one plus last index */
  82 #define PKE_NUM_REGS    0x18
  83
  84 #define PKE_REGISTER_WINDOW_SIZE  (sizeof(quadword) * PKE_NUM_REGS)
  85
  86
  87
  88 /* PKE commands */
  89
  90 #define PKE_CMD_PKENOP_MASK 0x7F
  91 #define PKE_CMD_PKENOP_BITS 0x00
  92 #define PKE_CMD_STCYCL_MASK 0x7F
  93 #define PKE_CMD_STCYCL_BITS 0x01
  94 #define PKE_CMD_OFFSET_MASK 0x7F
  95 #define PKE_CMD_OFFSET_BITS 0x02
  96 #define PKE_CMD_BASE_MASK 0x7F
  97 #define PKE_CMD_BASE_BITS 0x03
  98 #define PKE_CMD_ITOP_MASK 0x7F
  99 #define PKE_CMD_ITOP_BITS 0x04
 100 #define PKE_CMD_STMOD_MASK 0x7F
 101 #define PKE_CMD_STMOD_BITS 0x05
 102 #define PKE_CMD_MSKPATH3_MASK 0x7F
 103 #define PKE_CMD_MSKPATH3_BITS 0x06
 104 #define PKE_CMD_PKEMARK_MASK 0x7F
 105 #define PKE_CMD_PKEMARK_BITS 0x07
 106 #define PKE_CMD_FLUSHE_MASK 0x7F
 107 #define PKE_CMD_FLUSHE_BITS 0x10
 108 #define PKE_CMD_FLUSH_MASK 0x7F
 109 #define PKE_CMD_FLUSH_BITS 0x11
 110 #define PKE_CMD_FLUSHA_MASK 0x7F
 111 #define PKE_CMD_FLUSHA_BITS 0x13
 112 #define PKE_CMD_PKEMSCAL_MASK 0x7F  /* CAL == "call" */
 113 #define PKE_CMD_PKEMSCAL_BITS 0x14
 114 #define PKE_CMD_PKEMSCNT_MASK 0x7F  /* CNT == "continue" */
 115 #define PKE_CMD_PKEMSCNT_BITS 0x17
 116 #define PKE_CMD_PKEMSCALF_MASK 0x7F /* CALF == "call after flush" */
 117 #define PKE_CMD_PKEMSCALF_BITS 0x15
 118 #define PKE_CMD_STMASK_MASK 0x7F
 119 #define PKE_CMD_STMASK_BITS 0x20
 120 #define PKE_CMD_STROW_MASK 0x7F
 121 #define PKE_CMD_STROW_BITS 0x30
 122 #define PKE_CMD_STCOL_MASK 0x7F
 123 #define PKE_CMD_STCOL_BITS 0x31
 124 #define PKE_CMD_MPG_MASK 0x7F
 125 #define PKE_CMD_MPG_BITS 0x4A
 126 #define PKE_CMD_DIRECT_MASK 0x7F
 127 #define PKE_CMD_DIRECT_BITS 0x50
 128 #define PKE_CMD_DIRECTHL_MASK 0x7F
 129 #define PKE_CMD_DIRECTHL_BITS 0x51
 130 #define PKE_CMD_UNPACK_MASK 0x60
 131 #define PKE_CMD_UNPACK_BITS 0x60
 132
 133 /* test given word for particular PKE command bit pattern */
 134 #define IS_PKE_CMD(word,cmd) (((word) & PKE_CMD_##cmd##_MASK) == PKE_CMD_##cmd##_BITS)
 135
 136
 137 /* register bitmasks: bit numbers for end and beginning of fields */
 138
 139 /* PKE opcode */
 140 #define PKE_OPCODE_I_E 31
 141 #define PKE_OPCODE_I_B 31
 142 #define PKE_OPCODE_CMD_E 30
 143 #define PKE_OPCODE_CMD_B 24
 144 #define PKE_OPCODE_NUM_E 23
 145 #define PKE_OPCODE_NUM_B 16
 146 #define PKE_OPCODE_IMM_E 15
 147 #define PKE_OPCODE_IMM_B 0
 148
 149 /* STAT register */
 150 #define PKE_REG_STAT_FQC_E 28
 151 #define PKE_REG_STAT_FQC_B 24
 152 #define PKE_REG_STAT_FDR_E 23
 153 #define PKE_REG_STAT_FDR_B 23
 154 #define PKE_REG_STAT_ER1_E 13
 155 #define PKE_REG_STAT_ER1_B 13
 156 #define PKE_REG_STAT_ER0_E 12
 157 #define PKE_REG_STAT_ER0_B 12
 158 #define PKE_REG_STAT_INT_E 11
 159 #define PKE_REG_STAT_INT_B 11
 160 #define PKE_REG_STAT_PIS_E 10
 161 #define PKE_REG_STAT_PIS_B 10
 162 #define PKE_REG_STAT_PFS_E 9
 163 #define PKE_REG_STAT_PFS_B 9
 164 #define PKE_REG_STAT_PSS_E 8
 165 #define PKE_REG_STAT_PSS_B 8
 166 #define PKE_REG_STAT_DBF_E 7
 167 #define PKE_REG_STAT_DBF_B 7
 168 #define PKE_REG_STAT_MRK_E 6
 169 #define PKE_REG_STAT_MRK_B 6
 170 #define PKE_REG_STAT_PGW_E 3
 171 #define PKE_REG_STAT_PGW_B 3
 172 #define PKE_REG_STAT_PEW_E 2
 173 #define PKE_REG_STAT_PEW_B 2
 174 #define PKE_REG_STAT_PPS_E 1
 175 #define PKE_REG_STAT_PPS_B 0
 176
 177 #define PKE_REG_STAT_PPS_IDLE 0x00 /* ready to execute next instruction */
 178 #define PKE_REG_STAT_PPS_WAIT 0x01 /* not enough words in FIFO */
 179 #define PKE_REG_STAT_PPS_DECODE 0x02 /* decoding instruction */
 180 #define PKE_REG_STAT_PPS_STALL 0x02 /* alias state for stall (e.g., FLUSHE) */
 181 #define PKE_REG_STAT_PPS_XFER 0x03 /* transferring instruction operands */
 182
 183 /* DBF register */
 184 #define PKE_REG_DBF_DF_E 0
 185 #define PKE_REG_DBF_DF_B 0
 186
 187 /* OFST register */
 188 #define PKE_REG_OFST_OFFSET_E 9
 189 #define PKE_REG_OFST_OFFSET_B 0
 190
 191 /* OFST register */
 192 #define PKE_REG_TOPS_TOPS_E 9
 193 #define PKE_REG_TOPS_TOPS_B 0
 194
 195 /* BASE register */
 196 #define PKE_REG_BASE_BASE_E 9
 197 #define PKE_REG_BASE_BASE_B 0
 198
 199 /* ITOPS register */
 200 #define PKE_REG_ITOPS_ITOPS_E 9
 201 #define PKE_REG_ITOPS_ITOPS_B 0
 202
 203 /* MODE register */
 204 #define PKE_REG_MODE_MDE_E 1
 205 #define PKE_REG_MODE_MDE_B 0
 206
 207 /* NUM register */
 208 #define PKE_REG_NUM_NUM_E 9
 209 #define PKE_REG_NUM_NUM_B 0
 210
 211 /* MARK register */
 212 #define PKE_REG_MARK_MARK_E 15
 213 #define PKE_REG_MARK_MARK_B 0
 214
 215 /* ITOP register */
 216 #define PKE_REG_ITOP_ITOP_E 9
 217 #define PKE_REG_ITOP_ITOP_B 0
 218
 219 /* TOP register */
 220 #define PKE_REG_TOP_TOP_E 9
 221 #define PKE_REG_TOP_TOP_B 0
 222
 223 /* MASK register */
 224 #define PKE_REG_MASK_MASK_E 31
 225 #define PKE_REG_MASK_MASK_B 0
 226
 227 /* CYCLE register */
 228 #define PKE_REG_CYCLE_WL_E 15
 229 #define PKE_REG_CYCLE_WL_B 8
 230 #define PKE_REG_CYCLE_CL_E 7
 231 #define PKE_REG_CYCLE_CL_B 0
 232
 233 /* ERR register */
 234 #define PKE_REG_ERR_ME1_E 2
 235 #define PKE_REG_ERR_ME1_B 2
 236 #define PKE_REG_ERR_ME0_E 1
 237 #define PKE_REG_ERR_ME0_B 1
 238 #define PKE_REG_ERR_MII_E 0
 239 #define PKE_REG_ERR_MII_B 0
 240
 241 /* FBRST command bitfields */
 242 #define PKE_REG_FBRST_STC_E 3
 243 #define PKE_REG_FBRST_STC_B 3
 244 #define PKE_REG_FBRST_STP_E 2
 245 #define PKE_REG_FBRST_STP_B 2
 246 #define PKE_REG_FBRST_FBK_E 1
 247 #define PKE_REG_FBRST_FBK_B 1
 248 #define PKE_REG_FBRST_RST_E 0
 249 #define PKE_REG_FBRST_RST_B 0
 250
 251 /* MSKPATH3 command bitfields */
 252 #define PKE_REG_MSKPATH3_E 15
 253 #define PKE_REG_MSKPATH3_B 15
 254
 255
 256 /* UNPACK opcodes */
 257 #define PKE_UNPACK(vn,vl) ((vn) << 2 | (vl))
 258 #define PKE_UNPACK_S_32  PKE_UNPACK(0, 0)
 259 #define PKE_UNPACK_S_16  PKE_UNPACK(0, 1)
 260 #define PKE_UNPACK_S_8   PKE_UNPACK(0, 2)
 261 #define PKE_UNPACK_V2_32 PKE_UNPACK(1, 0)
 262 #define PKE_UNPACK_V2_16 PKE_UNPACK(1, 1)
 263 #define PKE_UNPACK_V2_8  PKE_UNPACK(1, 2)
 264 #define PKE_UNPACK_V3_32 PKE_UNPACK(2, 0)
 265 #define PKE_UNPACK_V3_16 PKE_UNPACK(2, 1)
 266 #define PKE_UNPACK_V3_8  PKE_UNPACK(2, 2)
 267 #define PKE_UNPACK_V4_32 PKE_UNPACK(3, 0)
 268 #define PKE_UNPACK_V4_16 PKE_UNPACK(3, 1)
 269 #define PKE_UNPACK_V4_8  PKE_UNPACK(3, 2)
 270 #define PKE_UNPACK_V4_5  PKE_UNPACK(3, 3)
 271
 272
 273 /* MASK register sub-field definitions */
 274 #define PKE_MASKREG_INPUT 0
 275 #define PKE_MASKREG_ROW 1
 276 #define PKE_MASKREG_COLUMN 2
 277 #define PKE_MASKREG_NOTHING 3
 278
 279
 280 /* STMOD register field definitions */
 281 #define PKE_MODE_INPUT 0
 282 #define PKE_MODE_ADDROW 1
 283 #define PKE_MODE_ACCROW 2
 284
 285
 286 /* extract a MASK register sub-field for row [0..3] and column [0..3] */
 287 /* MASK register is laid out of 2-bit values in this r-c order */
 288 /* m33 m32 m31 m30 m23 m22 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 */
 289 #define PKE_MASKREG_GET(me,row,col) \
 290 ((((me)->regs[PKE_REG_MASK][0]) >> (8*(row) + 2*(col))) & 0x03)
 291
 292
 293 /* operations - replace with those in sim-bits.h when convenient */
 294
 295 /* unsigned 32-bit mask of given width */
 296 #define BIT_MASK(width) ((width) == 31 ? 0xffffffff : (((unsigned_4)1) << (width+1)) - 1)
 297 /* e.g.: BIT_MASK(4) = 00011111 */
 298
 299 /* mask between given given bits numbers (MSB) */
 300 #define BIT_MASK_BTW(begin,end) ((BIT_MASK(end) & ~((begin) == 0 ? 0 : BIT_MASK((begin)-1))))
 301 /* e.g.: BIT_MASK_BTW(4,11) = 0000111111110000 */
 302
 303 /* set bitfield value */
 304 #define BIT_MASK_SET(lvalue,begin,end,value) \
 305 do { \
 306   ASSERT((begin) <= (end)); \
 307   (lvalue) &= ~BIT_MASK_BTW((begin),(end)); \
 308   (lvalue) |= ((value) << (begin)) & BIT_MASK_BTW((begin),(end)); \
 309 } while(0)
 310
 311 /* get bitfield value */
 312 #define BIT_MASK_GET(rvalue,begin,end) \
 313   (((rvalue) & BIT_MASK_BTW(begin,end)) >> (begin))
 314 /* e.g., BIT_MASK_GET(0000111100001111, 2, 8) = 0000000100001100 */
 315
 316 /* These ugly macro hacks allow succinct bitfield accesses */
 317 /* set a bitfield in a register by "name" */
 318 #define PKE_REG_MASK_SET(me,reg,flag,value) \
 319      do { \
 320        unsigned_4 old = BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
 321                     PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E); \
 322        BIT_MASK_SET(((me)->regs[PKE_REG_##reg][0]), \
 323                     PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E, \
 324                     (value)); \
 325        if((me)->fifo_trace_file != NULL) \
 326          { \
 327            if(old != (value)) \
 328              fprintf((me)->fifo_trace_file, "# Reg %s:%s = 0x%x\n", #reg, #flag, (unsigned)(value)); \
 329          } \
 330      } while(0)
 331
 332 /* get a bitfield from a register by "name" */
 333 #define PKE_REG_MASK_GET(me,reg,flag) \
 334      BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
 335                   PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E)
 336
 337
 338 #define PKE_LIMIT(value,max) ((value) > (max) ? (max) : (value))
 339
 340
 341 /* Classify words in a FIFO quadword */
 342 enum wordclass
 343 {
 344   wc_dma = 'D',
 345   wc_pkecode = 'P',
 346   wc_unknown = '?',
 347   wc_pkedata = '.'
 348 };
 349
 350
 351 /* One row in the FIFO */
 352 struct fifo_quadword
 353 {
 354   /* 128 bits of data */
 355   quadword data;
 356   /* source main memory address (or 0: unknown) */
 357   unsigned_4 source_address;
 358   /* classification of words in quadword; wc_dma set on DMA tags at FIFO write */
 359   enum wordclass word_class[4];
 360 };
 361
 362
 363 /* quadword FIFO structure for PKE */
 364 struct pke_fifo
 365 {
 366   struct fifo_quadword** quadwords; /* pointer to fifo quadwords */
 367   unsigned_4 origin; /* quadword serial number of quadwords[0] */
 368   unsigned_4 length; /* length of quadword pointer array: 0..N */
 369   unsigned_4 next;   /* relative index of first unfilled quadword: 0..length-1 */
 370 };
 371
 372 #define PKE_FIFO_GROW_SIZE 1000 /* number of quadword pointers to allocate */
 373 #define PKE_FIFO_ARCHEOLOGY 1000 /* number of old quadwords to keep as history */
 374
 375
 376 /* PKE internal state: FIFOs, registers, handle to VU friend */
 377 struct pke_device
 378 {
 379   /* common device info */
 380   device dev;
 381
 382   /* identity: 0=PKE0, 1=PKE1 */
 383   int pke_number;
 384   int flags;
 385
 386   /* quadword registers: data in [0] word only */
 387   quadword regs[PKE_NUM_REGS];
 388
 389   /* write buffer for FIFO address */
 390   quadword fifo_qw_in_progress;
 391   int fifo_qw_done; /* bitfield */
 392
 393   /* FIFO - private: use only pke_fifo_* routines to access */
 394   struct pke_fifo fifo;  /* array of FIFO quadword pointers */
 395   FILE* fifo_trace_file; /* stdio stream open in append mode, or 0 for no trace */
 396
 397   /* PC */
 398   int fifo_pc;  /* 0 .. (fifo_num_elements-1): quadword index of next instruction */
 399   int qw_pc;    /* 0 .. 3:                     word index of next instruction */
 400 };
 401
 402
 403 /* Flags for PKE.flags */
 404
 405 #define PKE_FLAG_NONE        0x00
 406 #define PKE_FLAG_PENDING_PSS 0x01 /* PSS bit written-to; set STAT:PSS after current instruction */
 407 #define PKE_FLAG_INT_NOLOOP  0x02 /* INT PKEcode received; INT/PIS set; suppress loop after resumption */
 408
 409
 410 /* Kludge alert */
 411
 412 #define PKE_MEM_READ(me,addr,data,size) \
 413     do { \
 414       sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
 415       unsigned_##size value = \
 416         sim_core_read_aligned_##size(cpu, CIA_GET(cpu), read_map, \
 417                                      (SIM_ADDR)(addr)); \
 418       memcpy((unsigned_##size*) (data), (void*) & value, size); \
 419      } while(0)
 420
 421 #define PKE_MEM_WRITE(me,addr,data,size) \
 422     do { sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
 423          unsigned_##size value; \
 424          memcpy((void*) & value, (unsigned_##size*)(data), size); \
 425          sim_core_write_aligned_##size(cpu, CIA_GET(cpu), write_map, \
 426                                        (SIM_ADDR)(addr), value); \
 427          if((me)->fifo_trace_file != NULL) \
 428            { \
 429              int i; \
 430              unsigned_##size value_te; \
 431              value_te = H2T_##size(value); \
 432              fprintf((me)->fifo_trace_file, "# Write %2d bytes  to  ", size); \
 433              fprintf((me)->fifo_trace_file, "0x%08lx: ", (unsigned long)(addr)); \
 434              for(i=0; i<size; i++) \
 435                fprintf((me)->fifo_trace_file, " %02x", ((unsigned_1*)(& value_te))[i]); \
 436              fprintf((me)->fifo_trace_file, "\n"); \
 437            } \
 438         } while(0)
 439
 440
 441
 442 #endif /* H_PKE_H */