sim/mips/sky-pke.h

   1 /* Copyright (C) 1998, Cygnus Solutions */
   2
   3 #ifndef H_PKE_H
   4 #define H_PKE_H
   5
   6 #include "sim-main.h"
   7 #include "sky-device.h"
   8
   9
  10
  11 /* External functions */
  12
  13 void pke0_attach(SIM_DESC sd);
  14 void pke0_issue(SIM_DESC sd);
  15 void pke1_attach(SIM_DESC sd);
  16 void pke1_issue(SIM_DESC sd);
  17
  18 /* structs declared below */
  19 struct pke_fifo;
  20 struct fifo_quadword;
  21
  22 unsigned_4 pke_fifo_flush(struct pke_fifo*);
  23 void pke_fifo_reset(struct pke_fifo*);
  24 struct fifo_quadword* pke_fifo_fit(struct pke_fifo*);
  25 struct fifo_quadword* pke_fifo_access(struct pke_fifo*, unsigned_4 qwnum);
  26 void pke_fifo_old(struct pke_fifo*, unsigned_4 qwnum);
  27
  28
  29 /* Quadword data type */
  30
  31 typedef unsigned_4 quadword[4];
  32
  33 /* truncate address to quadword */
  34 #define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f)
  35 /* extract offset in quadword */
  36 #define ADDR_OFFSET_QW(addr) ((addr) & 0x0f)
  37
  38
  39 /* SCEI memory mapping information */
  40
  41 #define PKE0_REGISTER_WINDOW_START 0x10003800
  42 #define PKE1_REGISTER_WINDOW_START 0x10003C00
  43 #define PKE0_FIFO_ADDR             0x10004000
  44 #define PKE1_FIFO_ADDR             0x10005000
  45
  46
  47 /* VU source-addr tracking tables */ /* changed from 1998-01-22 e-mail plans */
  48 #define VU0_MEM0_SRCADDR_START 0x21000000
  49 #define VU0_MEM1_SRCADDR_START 0x21004000
  50 #define VU1_MEM0_SRCADDR_START 0x21008000
  51 #define VU1_MEM1_SRCADDR_START 0x2100C000
  52
  53 /* GPUIF STAT register */
  54 #define GPUIF_REG_STAT_APATH_E 11
  55 #define GPUIF_REG_STAT_APATH_B 10
  56
  57 /* COP2 STAT register */
  58 #define COP2_REG_STAT_ADDR VPU_STAT
  59 #define COP2_REG_STAT_VBS1_E 8
  60 #define COP2_REG_STAT_VBS1_B 8
  61 #define COP2_REG_STAT_VBS0_E 0
  62 #define COP2_REG_STAT_VBS0_B 0
  63
  64
  65 /* Quadword indices of PKE registers.  Actual registers sit at bottom
  66    32 bits of each quadword. */
  67 #define PKE_REG_STAT    0x00
  68 #define PKE_REG_FBRST   0x01
  69 #define PKE_REG_ERR     0x02
  70 #define PKE_REG_MARK    0x03
  71 #define PKE_REG_CYCLE   0x04
  72 #define PKE_REG_MODE    0x05
  73 #define PKE_REG_NUM     0x06
  74 #define PKE_REG_MASK    0x07
  75 #define PKE_REG_CODE    0x08
  76 #define PKE_REG_ITOPS   0x09
  77 #define PKE_REG_BASE    0x0a /* pke1 only */
  78 #define PKE_REG_OFST    0x0b /* pke1 only */
  79 #define PKE_REG_TOPS    0x0c /* pke1 only */
  80 #define PKE_REG_ITOP    0x0d
  81 #define PKE_REG_TOP     0x0e /* pke1 only */
  82 #define PKE_REG_DBF     0x0f /* pke1 only */
  83 #define PKE_REG_R0      0x10 /* R0 .. R3 must be contiguous */
  84 #define PKE_REG_R1      0x11
  85 #define PKE_REG_R2      0x12
  86 #define PKE_REG_R3      0x13
  87 #define PKE_REG_C0      0x14 /* C0 .. C3 must be contiguous */
  88 #define PKE_REG_C1      0x15
  89 #define PKE_REG_C2      0x16
  90 #define PKE_REG_C3      0x17
  91 /* one plus last index */
  92 #define PKE_NUM_REGS    0x18
  93
  94 #define PKE_REGISTER_WINDOW_SIZE  (sizeof(quadword) * PKE_NUM_REGS)
  95
  96
  97
  98 /* PKE commands */
  99
 100 #define PKE_CMD_PKENOP_MASK 0x7F
 101 #define PKE_CMD_PKENOP_BITS 0x00
 102 #define PKE_CMD_STCYCL_MASK 0x7F
 103 #define PKE_CMD_STCYCL_BITS 0x01
 104 #define PKE_CMD_OFFSET_MASK 0x7F
 105 #define PKE_CMD_OFFSET_BITS 0x02
 106 #define PKE_CMD_BASE_MASK 0x7F
 107 #define PKE_CMD_BASE_BITS 0x03
 108 #define PKE_CMD_ITOP_MASK 0x7F
 109 #define PKE_CMD_ITOP_BITS 0x04
 110 #define PKE_CMD_STMOD_MASK 0x7F
 111 #define PKE_CMD_STMOD_BITS 0x05
 112 #define PKE_CMD_MSKPATH3_MASK 0x7F
 113 #define PKE_CMD_MSKPATH3_BITS 0x06
 114 #define PKE_CMD_PKEMARK_MASK 0x7F
 115 #define PKE_CMD_PKEMARK_BITS 0x07
 116 #define PKE_CMD_FLUSHE_MASK 0x7F
 117 #define PKE_CMD_FLUSHE_BITS 0x10
 118 #define PKE_CMD_FLUSH_MASK 0x7F
 119 #define PKE_CMD_FLUSH_BITS 0x11
 120 #define PKE_CMD_FLUSHA_MASK 0x7F
 121 #define PKE_CMD_FLUSHA_BITS 0x13
 122 #define PKE_CMD_PKEMSCAL_MASK 0x7F  /* CAL == "call" */
 123 #define PKE_CMD_PKEMSCAL_BITS 0x14
 124 #define PKE_CMD_PKEMSCNT_MASK 0x7F  /* CNT == "continue" */
 125 #define PKE_CMD_PKEMSCNT_BITS 0x17
 126 #define PKE_CMD_PKEMSCALF_MASK 0x7F /* CALF == "call after flush" */
 127 #define PKE_CMD_PKEMSCALF_BITS 0x15
 128 #define PKE_CMD_STMASK_MASK 0x7F
 129 #define PKE_CMD_STMASK_BITS 0x20
 130 #define PKE_CMD_STROW_MASK 0x7F
 131 #define PKE_CMD_STROW_BITS 0x30
 132 #define PKE_CMD_STCOL_MASK 0x7F
 133 #define PKE_CMD_STCOL_BITS 0x31
 134 #define PKE_CMD_MPG_MASK 0x7F
 135 #define PKE_CMD_MPG_BITS 0x4A
 136 #define PKE_CMD_DIRECT_MASK 0x7F
 137 #define PKE_CMD_DIRECT_BITS 0x50
 138 #define PKE_CMD_DIRECTHL_MASK 0x7F
 139 #define PKE_CMD_DIRECTHL_BITS 0x51
 140 #define PKE_CMD_UNPACK_MASK 0x60
 141 #define PKE_CMD_UNPACK_BITS 0x60
 142
 143 /* test given word for particular PKE command bit pattern */
 144 #define IS_PKE_CMD(word,cmd) (((word) & PKE_CMD_##cmd##_MASK) == PKE_CMD_##cmd##_BITS)
 145
 146
 147 /* register bitmasks: bit numbers for end and beginning of fields */
 148
 149 /* PKE opcode */
 150 #define PKE_OPCODE_I_E 31
 151 #define PKE_OPCODE_I_B 31
 152 #define PKE_OPCODE_CMD_E 30
 153 #define PKE_OPCODE_CMD_B 24
 154 #define PKE_OPCODE_NUM_E 23
 155 #define PKE_OPCODE_NUM_B 16
 156 #define PKE_OPCODE_IMM_E 15
 157 #define PKE_OPCODE_IMM_B 0
 158
 159 /* STAT register */
 160 #define PKE_REG_STAT_FQC_E 28
 161 #define PKE_REG_STAT_FQC_B 24
 162 #define PKE_REG_STAT_FDR_E 23
 163 #define PKE_REG_STAT_FDR_B 23
 164 #define PKE_REG_STAT_ER1_E 13
 165 #define PKE_REG_STAT_ER1_B 13
 166 #define PKE_REG_STAT_ER0_E 12
 167 #define PKE_REG_STAT_ER0_B 12
 168 #define PKE_REG_STAT_INT_E 11
 169 #define PKE_REG_STAT_INT_B 11
 170 #define PKE_REG_STAT_PIS_E 10
 171 #define PKE_REG_STAT_PIS_B 10
 172 #define PKE_REG_STAT_PFS_E 9
 173 #define PKE_REG_STAT_PFS_B 9
 174 #define PKE_REG_STAT_PSS_E 8
 175 #define PKE_REG_STAT_PSS_B 8
 176 #define PKE_REG_STAT_DBF_E 7
 177 #define PKE_REG_STAT_DBF_B 7
 178 #define PKE_REG_STAT_MRK_E 6
 179 #define PKE_REG_STAT_MRK_B 6
 180 #define PKE_REG_STAT_PGW_E 3
 181 #define PKE_REG_STAT_PGW_B 3
 182 #define PKE_REG_STAT_PEW_E 2
 183 #define PKE_REG_STAT_PEW_B 2
 184 #define PKE_REG_STAT_PPS_E 1
 185 #define PKE_REG_STAT_PPS_B 0
 186
 187 #define PKE_REG_STAT_PPS_IDLE 0x00 /* ready to execute next instruction */
 188 #define PKE_REG_STAT_PPS_WAIT 0x01 /* not enough words in FIFO */
 189 #define PKE_REG_STAT_PPS_DECODE 0x02 /* decoding instruction */
 190 #define PKE_REG_STAT_PPS_STALL 0x02 /* alias state for stall (e.g., FLUSHE) */
 191 #define PKE_REG_STAT_PPS_XFER 0x03 /* transferring instruction operands */
 192
 193 /* DBF register */
 194 #define PKE_REG_DBF_DF_E 0
 195 #define PKE_REG_DBF_DF_B 0
 196
 197 /* OFST register */
 198 #define PKE_REG_OFST_OFFSET_E 9
 199 #define PKE_REG_OFST_OFFSET_B 0
 200
 201 /* OFST register */
 202 #define PKE_REG_TOPS_TOPS_E 9
 203 #define PKE_REG_TOPS_TOPS_B 0
 204
 205 /* BASE register */
 206 #define PKE_REG_BASE_BASE_E 9
 207 #define PKE_REG_BASE_BASE_B 0
 208
 209 /* ITOPS register */
 210 #define PKE_REG_ITOPS_ITOPS_E 9
 211 #define PKE_REG_ITOPS_ITOPS_B 0
 212
 213 /* MODE register */
 214 #define PKE_REG_MODE_MDE_E 1
 215 #define PKE_REG_MODE_MDE_B 0
 216
 217 /* NUM register */
 218 #define PKE_REG_NUM_NUM_E 9
 219 #define PKE_REG_NUM_NUM_B 0
 220
 221 /* MARK register */
 222 #define PKE_REG_MARK_MARK_E 15
 223 #define PKE_REG_MARK_MARK_B 0
 224
 225 /* ITOP register */
 226 #define PKE_REG_ITOP_ITOP_E 9
 227 #define PKE_REG_ITOP_ITOP_B 0
 228
 229 /* TOP register */
 230 #define PKE_REG_TOP_TOP_E 9
 231 #define PKE_REG_TOP_TOP_B 0
 232
 233 /* MASK register */
 234 #define PKE_REG_MASK_MASK_E 31
 235 #define PKE_REG_MASK_MASK_B 0
 236
 237 /* CYCLE register */
 238 #define PKE_REG_CYCLE_WL_E 15
 239 #define PKE_REG_CYCLE_WL_B 8
 240 #define PKE_REG_CYCLE_CL_E 7
 241 #define PKE_REG_CYCLE_CL_B 0
 242
 243 /* ERR register */
 244 #define PKE_REG_ERR_ME1_E 2
 245 #define PKE_REG_ERR_ME1_B 2
 246 #define PKE_REG_ERR_ME0_E 1
 247 #define PKE_REG_ERR_ME0_B 1
 248 #define PKE_REG_ERR_MII_E 0
 249 #define PKE_REG_ERR_MII_B 0
 250
 251 /* FBRST command bitfields */
 252 #define PKE_REG_FBRST_STC_E 3
 253 #define PKE_REG_FBRST_STC_B 3
 254 #define PKE_REG_FBRST_STP_E 2
 255 #define PKE_REG_FBRST_STP_B 2
 256 #define PKE_REG_FBRST_FBK_E 1
 257 #define PKE_REG_FBRST_FBK_B 1
 258 #define PKE_REG_FBRST_RST_E 0
 259 #define PKE_REG_FBRST_RST_B 0
 260
 261 /* MSKPATH3 command bitfields */
 262 #define PKE_REG_MSKPATH3_E 15
 263 #define PKE_REG_MSKPATH3_B 15
 264
 265
 266 /* UNPACK opcodes */
 267 #define PKE_UNPACK(vn,vl) ((vn) << 2 | (vl))
 268 #define PKE_UNPACK_S_32  PKE_UNPACK(0, 0)
 269 #define PKE_UNPACK_S_16  PKE_UNPACK(0, 1)
 270 #define PKE_UNPACK_S_8   PKE_UNPACK(0, 2)
 271 #define PKE_UNPACK_V2_32 PKE_UNPACK(1, 0)
 272 #define PKE_UNPACK_V2_16 PKE_UNPACK(1, 1)
 273 #define PKE_UNPACK_V2_8  PKE_UNPACK(1, 2)
 274 #define PKE_UNPACK_V3_32 PKE_UNPACK(2, 0)
 275 #define PKE_UNPACK_V3_16 PKE_UNPACK(2, 1)
 276 #define PKE_UNPACK_V3_8  PKE_UNPACK(2, 2)
 277 #define PKE_UNPACK_V4_32 PKE_UNPACK(3, 0)
 278 #define PKE_UNPACK_V4_16 PKE_UNPACK(3, 1)
 279 #define PKE_UNPACK_V4_8  PKE_UNPACK(3, 2)
 280 #define PKE_UNPACK_V4_5  PKE_UNPACK(3, 3)
 281
 282
 283 /* MASK register sub-field definitions */
 284 #define PKE_MASKREG_INPUT 0
 285 #define PKE_MASKREG_ROW 1
 286 #define PKE_MASKREG_COLUMN 2
 287 #define PKE_MASKREG_NOTHING 3
 288
 289
 290 /* STMOD register field definitions */
 291 #define PKE_MODE_INPUT 0
 292 #define PKE_MODE_ADDROW 1
 293 #define PKE_MODE_ACCROW 2
 294
 295
 296 /* extract a MASK register sub-field for row [0..3] and column [0..3] */
 297 /* MASK register is laid out of 2-bit values in this r-c order */
 298 /* m33 m32 m31 m30 m23 m22 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 */
 299 #define PKE_MASKREG_GET(me,row,col) \
 300 ((((me)->regs[PKE_REG_MASK][0]) >> (8*(row) + 2*(col))) & 0x03)
 301
 302
 303 /* operations - replace with those in sim-bits.h when convenient */
 304
 305 /* unsigned 32-bit mask of given width */
 306 #define BIT_MASK(width) ((width) == 31 ? 0xffffffff : (((unsigned_4)1) << (width+1)) - 1)
 307 /* e.g.: BIT_MASK(4) = 00011111 */
 308
 309 /* mask between given given bits numbers (MSB) */
 310 #define BIT_MASK_BTW(begin,end) ((BIT_MASK(end) & ~((begin) == 0 ? 0 : BIT_MASK((begin)-1))))
 311 /* e.g.: BIT_MASK_BTW(4,11) = 0000111111110000 */
 312
 313 /* set bitfield value */
 314 #define BIT_MASK_SET(lvalue,begin,end,value) \
 315 do { \
 316   ASSERT((begin) <= (end)); \
 317   (lvalue) &= ~BIT_MASK_BTW((begin),(end)); \
 318   (lvalue) |= ((value) << (begin)) & BIT_MASK_BTW((begin),(end)); \
 319 } while(0)
 320
 321 /* get bitfield value */
 322 #define BIT_MASK_GET(rvalue,begin,end) \
 323   (((rvalue) & BIT_MASK_BTW(begin,end)) >> (begin))
 324 /* e.g., BIT_MASK_GET(0000111100001111, 2, 8) = 0000000100001100 */
 325
 326 /* These ugly macro hacks allow succinct bitfield accesses */
 327 /* set a bitfield in a register by "name" */
 328 #define PKE_REG_MASK_SET(me,reg,flag,value) \
 329      do { \
 330        unsigned_4 old = BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
 331                     PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E); \
 332        BIT_MASK_SET(((me)->regs[PKE_REG_##reg][0]), \
 333                     PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E, \
 334                     (value)); \
 335        if((me)->fifo_trace_file != NULL) \
 336          { \
 337            if(old != (value)) \
 338              fprintf((me)->fifo_trace_file, "# Reg %s:%s = 0x%x\n", #reg, #flag, (unsigned)(value)); \
 339          } \
 340      } while(0)
 341
 342 /* get a bitfield from a register by "name" */
 343 #define PKE_REG_MASK_GET(me,reg,flag) \
 344      BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
 345                   PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E)
 346
 347
 348 #define PKE_LIMIT(value,max) ((value) > (max) ? (max) : (value))
 349
 350
 351 /* Classify words in a FIFO quadword */
 352 enum wordclass
 353 {
 354   wc_dma = 'D',
 355   wc_pkecode = 'P',
 356   wc_unknown = '?',
 357   wc_pkedata = '.',
 358   wc_gpuiftag = 'g'
 359 };
 360
 361
 362 /* One row in the FIFO */
 363 struct fifo_quadword
 364 {
 365   /* 128 bits of data */
 366   quadword data;
 367   /* source main memory address (or 0: unknown) */
 368   unsigned_4 source_address;
 369   /* classification of words in quadword; wc_dma set on DMA tags at FIFO write */
 370   enum wordclass word_class[4];
 371 };
 372
 373
 374 /* quadword FIFO structure for PKE */
 375 typedef struct pke_fifo
 376 {
 377   struct fifo_quadword** quadwords; /* pointer to fifo quadwords */
 378   unsigned_4 origin; /* quadword serial number of quadwords[0] */
 379   unsigned_4 length; /* length of quadword pointer array: 0..N */
 380   unsigned_4 next;   /* relative index of first unfilled quadword: 0..length-1 */
 381 } pke_fifo;
 382
 383 #define PKE_FIFO_GROW_SIZE 1000 /* number of quadword pointers to allocate */
 384 #define PKE_FIFO_ARCHEOLOGY 1000 /* number of old quadwords to keep as history */
 385
 386
 387 /* PKE internal state: FIFOs, registers, handle to VU friend */
 388 struct pke_device
 389 {
 390   /* common device info */
 391   device dev;
 392
 393   /* identity: 0=PKE0, 1=PKE1 */
 394   int pke_number;
 395   int flags;
 396
 397   /* quadword registers: data in [0] word only */
 398   quadword regs[PKE_NUM_REGS];
 399
 400   /* write buffer for FIFO address */
 401   quadword fifo_qw_in_progress;
 402   int fifo_qw_done; /* bitfield */
 403
 404   /* FIFO - private: use only pke_fifo_* routines to access */
 405   struct pke_fifo fifo;  /* array of FIFO quadword pointers */
 406   FILE* fifo_trace_file; /* stdio stream open in append mode, or 0 for no trace */
 407
 408   /* FIFO cache -- curry last search pke_pcrel_fifo results */
 409   unsigned_4 last_fifo_pc;
 410   unsigned_4 last_qw_pc;
 411   unsigned_4 last_num;
 412   unsigned_4 last_new_fifo_pc;
 413   unsigned_4 last_new_qw_pc;
 414
 415   /* PC */
 416   int fifo_pc;  /* 0 .. (fifo_num_elements-1): quadword index of next instruction */
 417   int qw_pc;    /* 0 .. 3:                     word index of next instruction */
 418 };
 419
 420
 421 /* Flags for PKE.flags */
 422
 423 #define PKE_FLAG_NONE        0x00
 424 #define PKE_FLAG_PENDING_PSS 0x01 /* PSS bit written-to; set STAT:PSS after current instruction */
 425 #define PKE_FLAG_INT_NOLOOP  0x02 /* INT PKEcode received; INT/PIS set; suppress loop after resumption */
 426
 427
 428 /* Kludge alert */
 429
 430 #define PKE_MEM_READ(me,addr,data,size) \
 431     do { \
 432       sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
 433       unsigned_##size value = \
 434         sim_core_read_aligned_##size(cpu, CIA_GET(cpu), read_map, \
 435                                      (SIM_ADDR)(addr)); \
 436       memcpy((unsigned_##size*) (data), (void*) & value, size); \
 437      } while(0)
 438
 439 #define PKE_MEM_WRITE(me,addr,data,size) \
 440     do { sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
 441          unsigned_##size value; \
 442          memcpy((void*) & value, (unsigned_##size*)(data), size); \
 443          sim_core_write_aligned_##size(cpu, CIA_GET(cpu), write_map, \
 444                                        (SIM_ADDR)(addr), value); \
 445          if((me)->fifo_trace_file != NULL) \
 446            { \
 447              int i; \
 448              unsigned_##size value_te; \
 449              value_te = H2T_##size(value); \
 450              fprintf((me)->fifo_trace_file, "# Write %2d bytes  to  ", size); \
 451              fprintf((me)->fifo_trace_file, "0x%08lx: ", (unsigned long)(addr)); \
 452              for(i=0; i<size; i++) \
 453                fprintf((me)->fifo_trace_file, " %02x", ((unsigned_1*)(& value_te))[i]); \
 454              fprintf((me)->fifo_trace_file, "\n"); \
 455            } \
 456         } while(0)
 457
 458
 459
 460 #endif /* H_PKE_H */