sim/mips/vr.igen

   1 // -*- C -*-
   2 //
   3 // NEC specific instructions
   4 //
   5
   6 // Integer Instructions
   7 // --------------------
   8 //
   9 // MulAcc is the Multiply Accumulator.
  10 //     This register is mapped on the the HI and LO registers.
  11 //     Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
  12 //     Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
  13
  14
  15 :function:::unsigned64:MulAcc:
  16 *vr4100:
  17 // start-sanitize-vr4xxx
  18 *vr4121:
  19 // end-sanitize-vr4xxx
  20 // start-sanitize-vr4320
  21 *vr4320:
  22 // end-sanitize-vr4320
  23 // start-sanitize-cygnus
  24 *vr5400:
  25 // end-sanitize-cygnus
  26 {
  27   unsigned64 result = U8_4 (HI, LO);
  28   return result;
  29 }
  30
  31 :function:::void:SET_MulAcc:unsigned64 value
  32 *vr4100:
  33 // start-sanitize-vr4xxx
  34 *vr4121:
  35 // end-sanitize-vr4xxx
  36 // start-sanitize-vr4320
  37 *vr4320:
  38 // end-sanitize-vr4320
  39 // start-sanitize-cygnus
  40 *vr5400:
  41 // end-sanitize-cygnus
  42 {
  43   /* 64 bit specific */
  44   *AL4_8 (&HI) = VH4_8 (value);
  45   *AL4_8 (&LO) = VL4_8 (value);
  46 }
  47
  48 :function:::signed64:SignedMultiply:signed32 l, signed32 r
  49 *vr4100:
  50 // start-sanitize-vr4xxx
  51 *vr4121:
  52 // end-sanitize-vr4xxx
  53 // start-sanitize-vr4320
  54 *vr4320:
  55 // end-sanitize-vr4320
  56 // start-sanitize-cygnus
  57 *vr5400:
  58 // end-sanitize-cygnus
  59 {
  60   signed64 result = (signed64) l * (signed64) r;
  61   return result;
  62 }
  63
  64 :function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
  65 *vr4100:
  66 // start-sanitize-vr4xxx
  67 *vr4121:
  68 // end-sanitize-vr4xxx
  69 // start-sanitize-vr4320
  70 *vr4320:
  71 // end-sanitize-vr4320
  72 // start-sanitize-cygnus
  73 *vr5400:
  74 // end-sanitize-cygnus
  75 {
  76   unsigned64 result = (unsigned64) l * (unsigned64) r;
  77   return result;
  78 }
  79
  80 // start-sanitize-vr4xxx
  81 :function:::signed64:SaturatedAdd:signed32 l, signed32 r
  82 *vr4121:
  83 {
  84   signed64 result = (signed64) l + (signed64) r;
  85   if (result < 0)
  86     result = 0xFFFFFFFF8000000LL;
  87   else if (result > 0x000000007FFFFFFFLL)
  88     result = 0x000000007FFFFFFFLL;
  89   return result;
  90 }
  91
  92 :function:::unsigned64:SaturatedUnsignedAdd:unsigned32 l, unsigned32 r
  93 *vr4121:
  94 {
  95   unsigned64 result = (unsigned64) l + (unsigned64) r;
  96   if (result > 0x000000007FFFFFFFLL)
  97     result = 0xFFFFFFFFFFFFFFFFLL;
  98   return result;
  99 }
 100
 101
 102 // end-sanitize-vr4xxx
 103 :function:::unsigned64:Low32Bits:unsigned64 value
 104 *vr4100:
 105 // start-sanitize-vr4xxx
 106 *vr4121:
 107 // end-sanitize-vr4xxx
 108 // start-sanitize-cygnus
 109 *vr5400:
 110 // end-sanitize-cygnus
 111 {
 112   unsigned64 result = (signed64) (signed32) VL4_8 (value);
 113   return result;
 114 }
 115
 116 :function:::unsigned64:High32Bits:unsigned64 value
 117 *vr4100:
 118 // start-sanitize-vr4xxx
 119 *vr4121:
 120 // end-sanitize-vr4xxx
 121 // start-sanitize-vr4320
 122 *vr4320:
 123 // end-sanitize-vr4320
 124 // start-sanitize-cygnus
 125 *vr5400:
 126 // end-sanitize-cygnus
 127 {
 128   unsigned64 result = (signed64) (signed32) VH4_8 (value);
 129   return result;
 130 }
 131
 132
 133
 134 // Multiply, Accumulate
 135 000000,5.RS,5.RT,00000,00000,101000::64::MAC
 136 "mac r<RS>, r<RT>"
 137 *vr4100:
 138 // start-sanitize-vr4320
 139 *vr4320:
 140 // end-sanitize-vr4320
 141 {
 142   SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 143 }
 144
 145
 146 // D-Multiply, Accumulate
 147 000000,5.RS,5.RT,00000,00000,101001::64::DMAC
 148 "dmac r<RS>, r<RT>"
 149 *vr4100:
 150 // start-sanitize-vr4320
 151 *vr4320:
 152 // end-sanitize-vr4320
 153 {
 154   LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
 155 }
 156
 157
 158 // start-sanitize-vr4320
 159 // Count Leading Zeros
 160 000000,5.RS,00000,5.RD,00000,110101::64::CLZ
 161 "clz r<RD>, r<RS>"
 162 // end-sanitize-vr4320
 163 // start-sanitize-vr4320
 164 *vr4320:
 165 // end-sanitize-vr4320
 166 // start-sanitize-vr4320
 167 {
 168   unsigned32 t = Low32Bits (SD_, GPR[RS]);
 169   signed64 c = 0;
 170
 171   while (! (t & ( 1 << 31))
 172         && c < 32)
 173     {
 174     c++;
 175     t <<= 1;
 176     }
 177
 178   GPR[RD] = c;
 179 }
 180
 181
 182 // end-sanitize-vr4320
 183 // start-sanitize-vr4320
 184 // D-Count Leading Zeros
 185 000000,5.RS,00000,5.RD,00000,111101::64::DCLZ
 186 "dclz r<RD>, r<RS>"
 187 // end-sanitize-vr4320
 188 // start-sanitize-vr4320
 189 *vr4320:
 190 // end-sanitize-vr4320
 191 // start-sanitize-vr4320
 192 {
 193   unsigned64 t = GPR[RS];
 194   signed64 c = 0;
 195
 196   while (! (t & ( (unsigned64)1 << 63))
 197         && c < 64)
 198     {
 199     c++;
 200     t <<= 1;
 201     }
 202
 203   printf("lo %d\n", (int) c);
 204   GPR[RD] = c;
 205 }
 206
 207
 208
 209
 210
 211
 212
 213 // end-sanitize-vr4320
 214 // start-sanitize-cygnus
 215 // Multiply and Move LO.
 216 000000,5.RS,5.RT,5.RD,00100,101000::64::MUL
 217 "mul r<RD>, r<RS>, r<RT>"
 218 // end-sanitize-cygnus
 219 // start-sanitize-vr4320
 220 *vr4320:
 221 // end-sanitize-vr4320
 222 // start-sanitize-cygnus
 223 *vr5400:
 224 // end-sanitize-cygnus
 225 // start-sanitize-cygnus
 226 {
 227   SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 228   GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
 229 }
 230
 231
 232 // end-sanitize-cygnus
 233 // start-sanitize-cygnus
 234 // Unsigned Multiply and Move LO.
 235 000000,5.RS,5.RT,5.RD,00101,101000::64::MULU
 236 "mulu r<RD>, r<RS>, r<RT>"
 237 // end-sanitize-cygnus
 238 // start-sanitize-vr4320
 239 *vr4320:
 240 // end-sanitize-vr4320
 241 // start-sanitize-cygnus
 242 *vr5400:
 243 // end-sanitize-cygnus
 244 // start-sanitize-cygnus
 245 {
 246   SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 247   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 248 }
 249
 250
 251 // end-sanitize-cygnus
 252 // start-sanitize-cygnus
 253 // Multiply and Move HI.
 254 000000,5.RS,5.RT,5.RD,01100,101000::64::MULHI
 255 "mulhi r<RD>, r<RS>, r<RT>"
 256 // end-sanitize-cygnus
 257 // start-sanitize-vr4320
 258 *vr4320:
 259 // end-sanitize-vr4320
 260 // start-sanitize-cygnus
 261 *vr5400:
 262 // end-sanitize-cygnus
 263 // start-sanitize-cygnus
 264 {
 265   SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 266   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 267 }
 268
 269
 270 // end-sanitize-cygnus
 271 // start-sanitize-cygnus
 272 // Unsigned Multiply and Move HI.
 273 000000,5.RS,5.RT,5.RD,01101,101000::64::MULHIU
 274 "mulhiu r<RD>, r<RS>, r<RT>"
 275 // end-sanitize-cygnus
 276 // start-sanitize-vr4320
 277 *vr4320:
 278 // end-sanitize-vr4320
 279 // start-sanitize-cygnus
 280 *vr5400:
 281 // end-sanitize-cygnus
 282 // start-sanitize-cygnus
 283 {
 284   SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 285   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 286 }
 287
 288
 289 // end-sanitize-cygnus
 290 // start-sanitize-cygnus
 291 // Multiply, Negate and Move LO.
 292 000000,5.RS,5.RT,5.RD,00011,011000::64::MULS
 293 "muls r<RD>, r<RS>, r<RT>"
 294 // end-sanitize-cygnus
 295 // start-sanitize-cygnus
 296 *vr5400:
 297 // end-sanitize-cygnus
 298 // start-sanitize-cygnus
 299 {
 300   SET_MulAcc (SD_, 0 - SignedMultiply   (SD_, GPR[RS], GPR[RT]));
 301   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 302 }
 303
 304
 305 // end-sanitize-cygnus
 306 // start-sanitize-cygnus
 307 // Unsigned Multiply, Negate and Move LO.
 308 000000,5.RS,5.RT,5.RD,00011,011001::64::MULSU
 309 "mulsu r<RD>, r<RS>, r<RT>"
 310 // end-sanitize-cygnus
 311 // start-sanitize-cygnus
 312 *vr5400:
 313 // end-sanitize-cygnus
 314 // start-sanitize-cygnus
 315 {
 316   SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 317   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 318 }
 319
 320
 321 // end-sanitize-cygnus
 322 // start-sanitize-cygnus
 323 // Multiply, Negate and Move HI.
 324 000000,5.RS,5.RT,5.RD,01011,011000::64::MULSHI
 325 "mulshi r<RD>, r<RS>, r<RT>"
 326 // end-sanitize-cygnus
 327 // start-sanitize-cygnus
 328 *vr5400:
 329 // end-sanitize-cygnus
 330 // start-sanitize-cygnus
 331 {
 332   SET_MulAcc (SD_, 0 - SignedMultiply   (SD_, GPR[RS], GPR[RT]));
 333   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 334 }
 335
 336
 337 // end-sanitize-cygnus
 338 // start-sanitize-cygnus
 339 // Unsigned Multiply, Negate and Move HI.
 340 000000,5.RS,5.RT,5.RD,01011,011001::64::MULSHIU
 341 "mulshiu r<RD>, r<RS>, r<RT>"
 342 // end-sanitize-cygnus
 343 // start-sanitize-cygnus
 344 *vr5400:
 345 // end-sanitize-cygnus
 346 // start-sanitize-cygnus
 347 {
 348   SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 349   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 350 }
 351
 352
 353 // end-sanitize-cygnus
 354 // start-sanitize-cygnus
 355 //
 356 // Multiply, Accumulate and Move LO.
 357 //
 358 000000,5.RS,5.RT,5.RD,00010,101000::64::MACC
 359 "macc r<RD>, r<RS>, r<RT>"
 360 // end-sanitize-cygnus
 361 // start-sanitize-vr4320
 362 *vr4320:
 363 // end-sanitize-vr4320
 364 // start-sanitize-cygnus
 365 *vr5400:
 366 // end-sanitize-cygnus
 367 // start-sanitize-cygnus
 368 {
 369   SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 370   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 371 }
 372 // end-sanitize-cygnus
 373
 374 // start-sanitize-vr4xxx
 375 000000,5.RS,5.RT,5.RD,00000,101000::::MACC
 376 "macc r<RD>, r<RS>, r<RT>"
 377 *vr4121:
 378 {
 379   SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 380   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 381 }
 382
 383 000000,5.RS,5.RT,5.RD,00000,101001::::DMACC
 384 "dmacc r<RD>, r<RS>, r<RT>"
 385 *vr4121:
 386 {
 387   LO =  LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
 388   GPR[RD] = LO;
 389 }
 390
 391 000000,5.RS,5.RT,5.RD,10000,101000::::MACCS
 392 "maccs r<RD>, r<RS>, r<RT>"
 393 *vr4121:
 394 {
 395   SET_MulAcc (SD_, SaturatedAdd (SD_, MulAcc (SD_),
 396                                  SignedMultiply (SD_, GPR[RS], GPR[RT])));
 397   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 398 }
 399
 400 000000,5.RS,5.RT,5.RD,10000,101001::::DMACCS
 401 "dmaccs r<RD>, r<RS>, r<RT>"
 402 *vr4121:
 403 {
 404   LO = SaturatedAdd (SD_, LO, SignedMultiply (SD_, GPR[RS], GPR[RT]));
 405   GPR[RD] = LO;
 406 }
 407
 408
 409
 410
 411
 412 // end-sanitize-vr4xxx
 413 // start-sanitize-cygnus
 414 //
 415 // Unsigned Multiply, Accumulate and Move LO.
 416 //
 417 000000,5.RS,5.RT,5.RD,00011,101000::64::MACCU
 418 "maccu r<RD>, r<RS>, r<RT>"
 419 // end-sanitize-cygnus
 420 // start-sanitize-vr4320
 421 *vr4320:
 422 // end-sanitize-vr4320
 423 // start-sanitize-cygnus
 424 *vr5400:
 425 // end-sanitize-cygnus
 426 // start-sanitize-cygnus
 427 {
 428   SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 429   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 430 }
 431
 432 // end-sanitize-cygnus
 433 // start-sanitize-vr4xxx
 434 000000,5.RS,5.RT,5.RD,00001,101000::64::MACCU
 435 "maccu r<RD>, r<RS>, r<RT>"
 436 *vr4121:
 437 {
 438   SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 439   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 440 }
 441
 442 000000,5.RS,5.RT,5.RD,00001,101001::64::DMACCU
 443 "dmaccu r<RD>, r<RS>, r<RT>"
 444 *vr4121:
 445 {
 446   LO = LO + UnsignedMultiply (SD_, GPR[RS], GPR[RT]);
 447   GPR[RD] = LO;
 448 }
 449
 450 000000,5.RS,5.RT,5.RD,10001,101000::64::MACCUS
 451 "maccus r<RD>, r<RS>, r<RT>"
 452 *vr4121:
 453 {
 454   SET_MulAcc (SD_,
 455               SaturatedUnsignedAdd (SD_, MulAcc (SD_),
 456                                     UnsignedMultiply (SD_, GPR[RS], GPR[RT])));
 457   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 458 }
 459
 460 000000,5.RS,5.RT,5.RD,10001,101001::64::DMACCUS
 461 "dmaccus r<RD>, r<RS>, r<RT>"
 462 *vr4121:
 463 {
 464   LO = SaturatedUnsignedAdd (SD_, LO,
 465                              UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 466   GPR[RD] = LO;
 467 }
 468
 469
 470
 471 // end-sanitize-vr4xxx
 472 // start-sanitize-cygnus
 473 //
 474 // Multiply, Accumulate and Move HI.
 475 //
 476 000000,5.RS,5.RT,5.RD,01010,101000::64::MACCHI
 477 "macchi r<RD>, r<RS>, r<RT>"
 478 // end-sanitize-cygnus
 479 // start-sanitize-vr4320
 480 *vr4320:
 481 // end-sanitize-vr4320
 482 // start-sanitize-cygnus
 483 *vr5400:
 484 // end-sanitize-cygnus
 485 // start-sanitize-cygnus
 486 {
 487   SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 488   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 489 }
 490
 491 // end-sanitize-cygnus
 492 // start-sanitize-vr4xxx
 493 000000,5.RS,5.RT,5.RD,01000,101000::64::MACCHI
 494 "macchi r<RD>, r<RS>, r<RT>"
 495 *vr4121:
 496 {
 497   SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 498   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 499 }
 500
 501 000000,5.RS,5.RT,5.RD,11000,101000::64::MACCHIS
 502 "macchis r<RD>, r<RS>, r<RT>"
 503 *vr4121:
 504 {
 505   SET_MulAcc (SD_, SaturatedAdd (SD_, MulAcc (SD_),
 506                                  SignedMultiply (SD_, GPR[RS], GPR[RT])));
 507   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 508 }
 509
 510
 511
 512 // end-sanitize-vr4xxx
 513 // start-sanitize-cygnus
 514 //
 515 // Unsigned Multiply, Accumulate and Move HI.
 516 //
 517 000000,5.RS,5.RT,5.RD,01011,101000::64::MACCHIU
 518 "macchiu r<RD>, r<RS>, r<RT>"
 519 // end-sanitize-cygnus
 520 // start-sanitize-vr4320
 521 *vr4320:
 522 // end-sanitize-vr4320
 523 // start-sanitize-cygnus
 524 *vr5400:
 525 // end-sanitize-cygnus
 526 // start-sanitize-cygnus
 527 {
 528   SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 529   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 530
 531 }
 532
 533 // end-sanitize-cygnus
 534 // start-sanitize-vr4xxx
 535 000000,5.RS,5.RT,5.RD,01001,101000::64::MACCHIU
 536 "macchiu r<RD>, r<RS>, r<RT>"
 537 *vr4121:
 538 {
 539   SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 540   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 541
 542 }
 543
 544 000000,5.RS,5.RT,5.RD,11001,101000::64::MACCHIUS
 545 "macchius r<RD>, r<RS>, r<RT>"
 546 *vr4121:
 547 {
 548   SET_MulAcc (SD_,
 549               SaturatedUnsignedAdd (SD_, MulAcc (SD_),
 550                                     UnsignedMultiply (SD_, GPR[RS], GPR[RT])));
 551   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 552
 553 }
 554
 555
 556
 557 // end-sanitize-vr4xxx
 558 // start-sanitize-cygnus
 559 // Unsigned Multiply, Negate, Accumulate and Move LO.
 560 000000,5.RS,5.RT,5.RD,00111,011001::64::MSACU
 561 "msacu r<RD>, r<RS>, r<RT>"
 562 // end-sanitize-cygnus
 563 // start-sanitize-cygnus
 564 *vr5400:
 565 // end-sanitize-cygnus
 566 // start-sanitize-cygnus
 567 {
 568   SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 569   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 570 }
 571
 572
 573 // end-sanitize-cygnus
 574 // start-sanitize-cygnus
 575 // Multiply, Negate, Accumulate and Move HI.
 576 000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI
 577 "msachi r<RD>, r<RS>, r<RT>"
 578 // end-sanitize-cygnus
 579 // start-sanitize-cygnus
 580 *vr5400:
 581 // end-sanitize-cygnus
 582 // start-sanitize-cygnus
 583 {
 584   SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
 585   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 586 }
 587
 588 // end-sanitize-cygnus
 589 // start-sanitize-cygnus
 590 // Unsigned Multiply, Negate, Accumulate and Move HI.
 591 000000,5.RS,5.RT,5.RD,01111,011001::64::MSACHIU
 592 "msachiu r<RD>, r<RS>, r<RT>"
 593 // end-sanitize-cygnus
 594 // start-sanitize-cygnus
 595 *vr5400:
 596 // end-sanitize-cygnus
 597 // start-sanitize-cygnus
 598 {
 599   SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 600   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 601 }
 602
 603
 604 // end-sanitize-cygnus
 605 // start-sanitize-cygnus
 606 // Rotate Right.
 607 000000,00001,5.RT,5.RD,5.SHIFT,000010::64::ROR
 608 "ror r<RD>, r<RT>, <SHIFT>"
 609 // end-sanitize-cygnus
 610 // start-sanitize-cygnus
 611 *vr5400:
 612 // end-sanitize-cygnus
 613 // start-sanitize-cygnus
 614 {
 615   int s = SHIFT;
 616   GPR[RD] = ROTR32 (GPR[RT], s);
 617 }
 618
 619
 620 // end-sanitize-cygnus
 621 // start-sanitize-cygnus
 622 // Rotate Right Variable.
 623 000000,5.RS,5.RT,5.RD,00001,000110::64::RORV
 624 "rorv r<RD>, r<RT>, <RS>"
 625 // end-sanitize-cygnus
 626 // start-sanitize-cygnus
 627 *vr5400:
 628 // end-sanitize-cygnus
 629 // start-sanitize-cygnus
 630 {
 631   int s = MASKED (GPR[RS], 4, 0);
 632   GPR[RD] = ROTR32 (GPR[RT], s);
 633 }
 634
 635
 636 // end-sanitize-cygnus
 637 // start-sanitize-cygnus
 638 // Double Rotate Right.
 639 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
 640 "dror r<RD>, r<RT>, <SHIFT>"
 641 // end-sanitize-cygnus
 642 // start-sanitize-cygnus
 643 *vr5400:
 644 // end-sanitize-cygnus
 645 // start-sanitize-cygnus
 646 {
 647   int s = SHIFT;
 648   GPR[RD] = ROTR64 (GPR[RT], s);
 649 }
 650
 651
 652 // end-sanitize-cygnus
 653 // start-sanitize-cygnus
 654 // Double Rotate Right Plus 32.
 655 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
 656 "dror32 r<RD>, r<RT>, <SHIFT>"
 657 // end-sanitize-cygnus
 658 // start-sanitize-cygnus
 659 *vr5400:
 660 // end-sanitize-cygnus
 661 // start-sanitize-cygnus
 662 {
 663   int s = SHIFT + 32;
 664   GPR[RD] = ROTR64 (GPR[RT], s);
 665 }
 666
 667
 668 // end-sanitize-cygnus
 669 // start-sanitize-cygnus
 670 // Double Rotate Right Variable.
 671 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
 672 "drorv r<RD>, r<RT>, <RS>"
 673 // end-sanitize-cygnus
 674 // start-sanitize-cygnus
 675 *vr5400:
 676 // end-sanitize-cygnus
 677 // start-sanitize-cygnus
 678 {
 679   int s = MASKED (GPR[RS], 5, 0);
 680   GPR[RD] = ROTR64 (GPR[RT], s);
 681 }
 682
 683
 684 // end-sanitize-cygnus