3 // Integer Instructions
4 // --------------------
6 // MulAcc is the Multiply Accumulator.
7 // This register is mapped on the the HI and LO registers.
8 // Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
9 // Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
12 :function:::unsigned64:MulAcc:
14 unsigned64 result = U8_4 (HI, LO);
18 :function:::void:SET_MulAcc:unsigned64 value
20 *AL4_8 (&HI) = VH4_8 (value);
21 *AL4_8 (&LO) = VL4_8 (value);
24 :function:::signed64:SignedMultiply:signed32 l, signed32 r
26 signed64 result = (signed64) l * (signed64) r;
30 :function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
32 unsigned64 result = (unsigned64) l * (unsigned64) r;
36 :function:::unsigned64:Low32Bits:unsigned64 value
38 unsigned64 result = (signed64) (signed32) VL4_8 (value);
42 :function:::unsigned64:High32Bits:unsigned64 value
44 unsigned64 result = (signed64) (signed32) VH4_8 (value);
50 // Multiply and Move LO.
51 000000,5.RS,5.RT,5.RD,00100,101000::::MUL
52 "mul r<RD>, r<RS>, r<RT>"
53 *mipsI,mipsII,mipsIII,mipsIV:
55 SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
56 GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
59 // Unsigned Multiply and Move LO.
60 000000,5.RS,5.RT,5.RD,00101,101000::::MULU
61 "mulu r<RD>, r<RS>, r<RT>"
62 *mipsI,mipsII,mipsIII,mipsIV:
64 SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
65 GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
68 // Multiply and Move HI.
69 000000,5.RS,5.RT,5.RD,01100,101000::::MULHI
70 "mulhi r<RD>, r<RS>, r<RT>"
71 *mipsI,mipsII,mipsIII,mipsIV:
73 SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
74 GPR[RD] = High32Bits (SD_, MulAcc (SD_));
77 // Unsigned Multiply and Move HI.
78 000000,5.RS,5.RT,5.RD,01101,101000::::MULHIU
79 "mulhiu r<RD>, r<RS>, r<RT>"
80 *mipsI,mipsII,mipsIII,mipsIV:
82 SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
83 GPR[RD] = High32Bits (SD_, MulAcc (SD_));
87 // Multiply, Accumulate
88 000000,5.RS,5.RT,00000,00000,101000::::MAC
92 SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
95 // D-Multiply, Accumulate
96 000000,5.RS,5.RT,00000,00000,101001::::DMAC
98 *mipsI,mipsII,mipsIII,mipsIV:
100 LO = MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]);
103 // Multiply, Accumulate and Move LO.
104 000000,5.RS,5.RT,5.RD,00010,101000::::MACC
105 "macc r<RD>, r<RS>, r<RT>"
106 *mipsI,mipsII,mipsIII,mipsIV:
108 SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
109 GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
112 // Unsigned Multiply, Accumulate and Move LO.
113 000000,5.RS,5.RT,5.RD,00011,101000::::MACCU
114 "maccu r<RD>, r<RS>, r<RT>"
115 *mipsI,mipsII,mipsIII,mipsIV:
117 SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
118 GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
121 // Multiply, Accumulate and Move HI.
122 000000,5.RS,5.RT,5.RD,01010,101000::::MACCHI
123 "macchi r<RD>, r<RS>, r<RT>"
124 *mipsI,mipsII,mipsIII,mipsIV:
126 SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
127 GPR[RD] = High32Bits (SD_, MulAcc (SD_));
130 // Unsigned Multiply, Accumulate and Move HI.
131 000000,5.RS,5.RT,5.RD,01011,101000::::MACCHIU
132 "macchiu r<RD>, r<RS>, r<RT>"
133 *mipsI,mipsII,mipsIII,mipsIV:
135 SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
136 GPR[RD] = High32Bits (SD_, MulAcc (SD_));