sim/mips/vr5400.igen

   1
   2
   3 // Integer Instructions
   4 // --------------------
   5 //
   6 // MulAcc is the Multiply Accumulator.
   7 //     This register is mapped on the the HI and LO registers.
   8 //     Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
   9 //     Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
  10
  11
  12 :function:::unsigned64:MulAcc:
  13 {
  14   unsigned64 result = U8_4 (HI, LO);
  15   return result;
  16 }
  17
  18 :function:::void:SET_MulAcc:unsigned64 value
  19 {
  20   *AL4_8 (&HI) = VH4_8 (value);
  21   *AL4_8 (&LO) = VL4_8 (value);
  22 }
  23
  24 :function:::signed64:SignedMultiply:signed32 l, signed32 r
  25 {
  26   signed64 result = (signed64) l * (signed64) r;
  27   return result;
  28 }
  29
  30 :function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
  31 {
  32   unsigned64 result = (unsigned64) l * (unsigned64) r;
  33   return result;
  34 }
  35
  36 :function:::unsigned64:Low32Bits:unsigned64 value
  37 {
  38   unsigned64 result = (signed64) (signed32) VL4_8 (value);
  39   return result;
  40 }
  41
  42 :function:::unsigned64:High32Bits:unsigned64 value
  43 {
  44   unsigned64 result = (signed64) (signed32) VH4_8 (value);
  45   return result;
  46 }
  47
  48
  49
  50 // Multiply and Move LO.
  51 000000,5.RS,5.RT,5.RD,00001,011000::::MUL
  52 "mul r<RD>, r<RS>, r<RT>"
  53 *vr5400:
  54 {
  55   SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
  56   GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
  57 }
  58
  59 // Unsigned Multiply and Move LO.
  60 000000,5.RS,5.RT,5.RD,00001,011001::::MULU
  61 "mulu r<RD>, r<RS>, r<RT>"
  62 *vr5400:
  63 {
  64   SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  65   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
  66 }
  67
  68 // Multiply and Move HI.
  69 000000,5.RS,5.RT,5.RD,01001,011000::::MULHI
  70 "mulhi r<RD>, r<RS>, r<RT>"
  71 *vr5400:
  72 {
  73   SET_MulAcc (SD_, 0 + SignedMultiply   (SD_, GPR[RS], GPR[RT]));
  74   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
  75 }
  76
  77 // Unsigned Multiply and Move HI.
  78 000000,5.RS,5.RT,5.RD,01001,011001::::MULHIU
  79 "mulhiu r<RD>, r<RS>, r<RT>"
  80 *vr5400:
  81 {
  82   SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  83   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
  84 }
  85
  86
  87 // Multiply, Negate and Move LO.
  88 000000,5.RS,5.RT,5.RD,00011,011000::::MULS
  89 "muls r<RD>, r<RS>, r<RT>"
  90 *vr5400:
  91 {
  92   SET_MulAcc (SD_, 0 - SignedMultiply   (SD_, GPR[RS], GPR[RT]));
  93   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
  94 }
  95
  96 // Unsigned Multiply, Negate and Move LO.
  97 000000,5.RS,5.RT,5.RD,00011,011001::::MULSU
  98 "mulsu r<RD>, r<RS>, r<RT>"
  99 *vr5400:
 100 {
 101   SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 102   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 103 }
 104
 105 // Multiply, Negate and Move HI.
 106 000000,5.RS,5.RT,5.RD,01011,011000::::MULSHI
 107 "mulshi r<RD>, r<RS>, r<RT>"
 108 *vr5400:
 109 {
 110   SET_MulAcc (SD_, 0 - SignedMultiply   (SD_, GPR[RS], GPR[RT]));
 111   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 112 }
 113
 114 // Unsigned Multiply, Negate and Move HI.
 115 000000,5.RS,5.RT,5.RD,01011,011001::::MULSHIU
 116 "mulshiu r<RD>, r<RS>, r<RT>"
 117 *vr5400:
 118 {
 119   SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 120   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 121 }
 122
 123
 124 // Multiply, Accumulate and Move LO.
 125 000000,5.RS,5.RT,5.RD,00101,011000::::MACC
 126 "macc r<RD>, r<RS>, r<RT>"
 127 *vr5400:
 128 {
 129   SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 130   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 131 }
 132
 133 // Unsigned Multiply, Accumulate and Move LO.
 134 000000,5.RS,5.RT,5.RD,00101,011001::::MACCU
 135 "maccu r<RD>, r<RS>, r<RT>"
 136 *vr5400:
 137 {
 138   SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 139   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 140 }
 141
 142 // Multiply, Accumulate and Move HI.
 143 000000,5.RS,5.RT,5.RD,01101,011000::::MACCHI
 144 "macchi r<RD>, r<RS>, r<RT>"
 145 *vr5400:
 146 {
 147   SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 148   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 149 }
 150
 151 // Unsigned Multiply, Accumulate and Move HI.
 152 000000,5.RS,5.RT,5.RD,01101,011001::::MACCHIU
 153 "macchiu r<RD>, r<RS>, r<RT>"
 154 *vr5400:
 155 {
 156   SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 157   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 158
 159 }
 160
 161 // Multiply, Negate, Accumulate and Move LO.
 162 000000,5.RS,5.RT,5.RD,00111,011000::::MSAC
 163 "msac r<RD>, r<RS>, r<RT>"
 164 *vr5400:
 165 {
 166   SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
 167   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 168 }
 169
 170 // Unsigned Multiply, Negate, Accumulate and Move LO.
 171 000000,5.RS,5.RT,5.RD,00111,011001::::MSACU
 172 "msacu r<RD>, r<RS>, r<RT>"
 173 *vr5400:
 174 {
 175   SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 176   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 177 }
 178
 179 // Multiply, Negate, Accumulate and Move HI.
 180 000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI
 181 "msachi r<RD>, r<RS>, r<RT>"
 182 *vr5400:
 183 {
 184   SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
 185   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 186 }
 187
 188 // Unsigned Multiply, Negate, Accumulate and Move HI.
 189 000000,5.RS,5.RT,5.RD,01111,011001::::MSACHIU
 190 "msachiu r<RD>, r<RS>, r<RT>"
 191 *vr5400:
 192 {
 193   SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 194   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 195 }
 196
 197
 198 // Rotate Right.
 199 000000,00001,5.RT,5.RD,5.SHIFT,000010::::ROR
 200 "ror r<RD>, r<RT>, <SHIFT>"
 201 *vr5400:
 202 {
 203   int s = SHIFT;
 204   GPR[RD] = ROTR32 (GPR[RT], s);
 205 }
 206
 207 // Rotate Right Variable.
 208 000000,5.RS,5.RT,5.RD,00001,000110::::RORV
 209 "rorv r<RD>, r<RT>, <RS>"
 210 *vr5400:
 211 {
 212   int s = MASKED (GPR[RS], 4, 0);
 213   GPR[RD] = ROTR32 (GPR[RT], s);
 214 }
 215
 216 // Double Rotate Right.
 217 000000,00001,5.RT,5.RD,5.SHIFT,111010::::DROR
 218 "dror r<RD>, r<RT>, <SHIFT>"
 219 *vr5400:
 220 {
 221   int s = SHIFT;
 222   GPR[RD] = ROTR64 (GPR[RT], s);
 223 }
 224
 225 // Double Rotate Right Plus 32.
 226 000000,00001,5.RT,5.RD,5.SHIFT,111110::::DROR32
 227 "dror32 r<RD>, r<RT>, <SHIFT>"
 228 *vr5400:
 229 {
 230   int s = SHIFT + 32;
 231   GPR[RD] = ROTR64 (GPR[RT], s);
 232 }
 233
 234 // Double Rotate Right Variable.
 235 000000,5.RS,5.RT,5.RD,00001,010110::::DRORV
 236 "drorv r<RD>, r<RT>, <RS>"
 237 *vr5400:
 238 {
 239   int s = MASKED (GPR[RS], 5, 0);
 240   GPR[RD] = ROTR64 (GPR[RT], s);
 241 }