sim/mips/vr5400.igen

   1
   2
   3 // Integer Instructions
   4 // --------------------
   5 //
   6 // MulAcc is the Multiply Accumulator.
   7 //     This register is mapped on the the HI and LO registers.
   8 //     Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
   9 //     Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
  10
  11
  12 :function:::unsigned64:MulAcc:
  13 {
  14   unsigned64 result = U8_4 (HI, LO);
  15   return result;
  16 }
  17
  18 :function:::void:SET_MulAcc:unsigned64 value
  19 {
  20   *AL4_8 (&HI) = VH4_8 (value);
  21   *AL4_8 (&LO) = VL4_8 (value);
  22 }
  23
  24 :function:::signed64:SignedMultiply:signed32 l, signed32 r
  25 {
  26   signed64 result = (signed64) l * (signed64) r;
  27   return result;
  28 }
  29
  30 :function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
  31 {
  32   unsigned64 result = (unsigned64) l * (unsigned64) r;
  33   return result;
  34 }
  35
  36 :function:::unsigned64:Low32Bits:unsigned64 value
  37 {
  38   unsigned64 result = VL4_8 (value);
  39   return result;
  40 }
  41
  42 :function:::unsigned64:High32Bits:unsigned64 value
  43 {
  44   unsigned64 result = VH4_8 (value);
  45   return result;
  46 }
  47
  48
  49
  50 // Multiply and Move LO.
  51 000000,5.RS,5.RT,5.RD,00001,011000::::MUL
  52 "mul r<RD>, r<RS>, r<RT>"
  53 *vr5400:
  54 {
  55   SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
  56   GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
  57 }
  58
  59 // Unsigned Multiply and Move Low.
  60 000000,5.RS,5.RT,5.RD,00001,011001::::MULU
  61 "mulu r<RD>, r<RS>, r<RT>"
  62 *vr5400:
  63 {
  64   SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  65   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
  66 }
  67
  68 // Multiply and Move HI.
  69 000000,5.RS,5.RT,5.RD,01001,011000::::MULHI
  70 "mulhi r<RD>, r<RS>, r<RT>"
  71 *vr5400:
  72 {
  73   SET_MulAcc (SD_, 0 + SignedMultiply   (SD_, GPR[RS], GPR[RT]));
  74   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
  75 }
  76
  77 // Unsigned Multiply and Move HI.
  78 000000,5.RS,5.RT,5.RD,01001,011001::::MULHIU
  79 "mulhiu r<RD>, r<RS>, r<RT>"
  80 *vr5400:
  81 {
  82   SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  83   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
  84 }
  85
  86
  87 // Multiply, Negate and Move LO.
  88 000000,5.RS,5.RT,5.RD,00011,011000::::MULS
  89 "muls r<RD>, r<RS>, r<RT>"
  90 *vr5400:
  91 {
  92   SET_MulAcc (SD_, 0 - SignedMultiply   (SD_, GPR[RS], GPR[RT]));
  93   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
  94 }
  95
  96 // Unsigned Multiply, Negate and Move LO.
  97 000000,5.RS,5.RT,5.RD,00011,011001::::MULSU
  98 "mulsu r<RD>, r<RS>, r<RT>"
  99 *vr5400:
 100 {
 101   SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 102   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 103 }
 104
 105 // Multiply, Negate and Move HI.
 106 000000,5.RS,5.RT,5.RD,01011,011000::::MULSHI
 107 "mulshi r<RD>, r<RS>, r<RT>"
 108 *vr5400:
 109 {
 110   SET_MulAcc (SD_, 0 - SignedMultiply   (SD_, GPR[RS], GPR[RT]));
 111   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 112 }
 113
 114 // Unsigned Multiply, Negate and Move HI.
 115 000000,5.RS,5.RT,5.RD,01011,011001::::MULSHIU
 116 "mulshiu r<RD>, r<RS>, r<RT>"
 117 *vr5400:
 118 {
 119   SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 120   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 121 }
 122
 123
 124 // Multiply, Accumulate and Move LO.
 125 000000,5.RS,5.RT,5.RD,00101,011000::::MACC
 126 "macc r<RD>, r<RS>, r<RT>"
 127 *vr5400:
 128 {
 129   SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 130   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 131 }
 132
 133 // Unsigned Multiply, Accumulate and Move LO.
 134 000000,5.RS,5.RT,5.RD,00101,011001::::MACCU
 135 "maccu r<RD>, r<RS>, r<RT>"
 136 *vr5400:
 137 {
 138   SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 139   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 140 }
 141
 142 // Multiply, Accumulate and Move HI.
 143 000000,5.RS,5.RT,5.RD,01101,011000::::MACCHI
 144 "macchi r<RD>, r<RS>, r<RT>"
 145 *vr5400:
 146 {
 147   SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 148   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 149 }
 150
 151 // Unsigned Multiply, Accumulate and Move HI.
 152 000000,5.RS,5.RT,5.RD,01101,011001::::MACCHIU
 153 "macchiu r<RD>, r<RS>, r<RT>"
 154 *vr5400:
 155 {
 156   SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 157   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 158
 159 }
 160
 161 // Multiply, Negate, Accumulate and Move LO.
 162 000000,5.RS,5.RT,5.RD,00111,011000::::MSAC
 163 "msac r<RD>, r<RS>, r<RT>"
 164 *vr5400:
 165 {
 166   SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
 167   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 168 }
 169
 170 // Unsigned Multiply, Negate, Accumulate and Move LO.
 171 000000,5.RS,5.RT,5.RD,00111,011001::::MSACU
 172 "msacu r<RD>, r<RS>, r<RT>"
 173 *vr5400:
 174 {
 175   SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 176   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 177 }
 178
 179 // Multiply, Negate, Accumulate and Move HI.
 180 000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI
 181 "msachi r<RD>, r<RS>, r<RT>"
 182 *vr5400:
 183 {
 184   SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
 185   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 186 }
 187
 188 // Unsigned Multiply, Negate, Accumulate and Move HI.
 189 000000,5.RS,5.RT,5.RD,01111,011001::::MSACHIU
 190 "msachiu r<RD>, r<RS>, r<RT>"
 191 *vr5400:
 192 {
 193   SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 194   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 195 }
 196
 197
 198 // Rotate Right.
 199 000000,00001,5.RT,5.RD,5.SHIFT,000010::::ROR
 200 "ror r<RD>, r<RT>, <SHIFT>"
 201 *vr5400:
 202 {
 203   int s = SHIFT;
 204   GPR[RD] = ROTR32 (GPR[RT], s);
 205 }
 206
 207 // Rotate Right Variable.
 208 000000,5.RS,5.RT,5.RD,00001,000110::::RORV
 209 "rorv r<RD>, r<RT>, <RS>"
 210 *vr5400:
 211 {
 212   int s = MASKED (GPR[RS], 4, 0);
 213   GPR[RD] = ROTR32 (GPR[RT], s);
 214 }
 215
 216 // Double Rotate Right.
 217 000000,00001,5.RT,5.RD,5.SHIFT,111010::::DROR
 218 "dror r<RD>, r<RT>, <SHIFT>"
 219 *vr5400:
 220 {
 221   int s = SHIFT;
 222   GPR[RD] = ROTR64 (GPR[RT], s);
 223 }
 224
 225 // Double Rotate Right Plus 32.
 226 000000,00001,5.RT,5.RD,5.SHIFT,111110::::DROR32
 227 "dror32 r<RD>, r<RT>, <SHIFT>"
 228 *vr5400:
 229 {
 230   int s = SHIFT + 32;
 231   GPR[RD] = ROTR64 (GPR[RT], s);
 232 }
 233
 234 // Double Rotate Right Variable.
 235 000000,5.RS,5.RT,5.RD,00001,010110::::DRORV
 236 "drorv r<RD>, r<RT>, <RS>"
 237 *vr5400:
 238 {
 239   int s = MASKED (GPR[RS], 5, 0);
 240   GPR[RD] = ROTR64 (GPR[RT], s);
 241 }
 242
 243
 244
 245
 246 // Media Instructions
 247 // ------------------
 248
 249 // Note:   Vector unit in R5400 supports only octal byte format.
 250 // Note:   The sel field is deduced by special handling of the "vt"
 251 // operand.
 252 //         If vt is:
 253 //             of the form $vt[0],        then sel is 0000
 254 //             of the form $vt[1],        then sel is 0001
 255 //             of the form $vt[2],        then sel is 0010
 256 //             of the form $vt[3],        then sel is 0011
 257 //             of the form $vt[4],        then sel is 0100
 258 //             of the form $vt[5],        then sel is 0101
 259 //             of the form $vt[6],        then sel is 0110
 260 //             of the form $vt[7],        then sel is 0111
 261 //             Normal register specifier, then sel is 1011
 262 //             Constant,                  then sel is 1111
 263 //
 264 // VecAcc is the Vector Accumulator.
 265 //     This accumulator is organized as 8X24 bit (192 bit) register.
 266 //     This accumulator holds only signed values.
 267
 268 :function:::signed:vr:int fpr, int byte
 269 {
 270   signed8 b = V1_8 (value_fpr (sd, cia, fpr, fmt_long), byte);
 271   return b;
 272 }
 273
 274 :function:::void:set_vr:int fpr, int byte, signed value
 275 {
 276   abort ();
 277 }
 278
 279 :function:::signed:VecAcc:int byte
 280 {
 281   abort ();
 282   return 0;
 283 }
 284
 285 :function:::void:set_VecAcc:int byte, signed value
 286 {
 287   abort ();
 288 }
 289
 290 :function:::int:cc:int i
 291 {
 292   abort ();
 293   return 0;
 294 }
 295
 296 :function:::void:set_cc:int i, int value
 297 {
 298   abort ();
 299 }
 300
 301 :function:::signed:Min:signed l, signed r
 302 {
 303   if (l < r)
 304     return l;
 305   else
 306     return r;
 307 }
 308
 309 :function:::signed:Max:signed l, signed r
 310 {
 311   if (l < r)
 312     return r;
 313   else
 314     return l;
 315 }
 316
 317 :function:::signed:Compare:signed l, signed r
 318 {
 319   abort ();
 320   return 0;
 321 }
 322
 323 :function:::signed:Clamp:signed l
 324 {
 325   abort ();
 326   return 0;
 327 }
 328
 329 :function:::signed:Round:signed l
 330 {
 331   abort ();
 332   return 0;
 333 }
 334
 335 :function:::void:ByteAlign:int vd, int imm, int vs, int vt
 336 {
 337   abort ();
 338 }
 339
 340 :function:::signed:One_of:int vs, int vt
 341 {
 342   abort ();
 343   return 0;
 344 }
 345
 346 :function:::unsigned:do_select:int i, int sel, int vt
 347 {
 348   if (sel < 8)
 349     return vr (SD_, vt, sel);
 350   else if (sel == 0x13)
 351     return vr (SD_, vt, i);
 352   else if (sel == 0x1f)
 353     return vt;
 354   else
 355     semantic_illegal (sd, cia);
 356   return 0;
 357 }
 358
 359 :%s::::VT:int sel, int vt
 360 {
 361   static char buf[20];
 362   if (sel < 8)
 363     sprintf (buf, "v%d[%d]", vt, sel);
 364   else if (sel == 0x13)
 365     sprintf (buf, "v%d", vt);
 366   else if (sel == 0x1f)
 367     sprintf (buf, "%d", vt);
 368   else
 369     sprintf (buf, "(invalid)");
 370   return buf;
 371 }
 372
 373
 374 // Vector Add.
 375 010010,4.SEL,0,5.VT,5.VS,5.VD,001011::::ADD.OB
 376 "add.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 377 *vr5400:
 378 {
 379   int i;
 380   for (i = 0; i < 8; i++)
 381     set_vr (SD_, VD, i, vr (SD_, VS, i) + do_select (SD_, i, SEL, VT));
 382 }
 383
 384 // Vector Align.
 385 010010,00,3.IMM,5.VT,5.VS,5.VD,011000::::ALNI.OB
 386 "alni.ob v<VD>, v<VS>, v<VT>, <IMM>"
 387 *vr5400:
 388 {
 389   ByteAlign (SD_, VD, IMM, VS, VT);
 390 }
 391
 392 // Vector And.
 393 010010,4.SEL,0,5.VT,5.VS,5.VD,001100::::AND.OB
 394 "and.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 395 *vr5400:
 396 {
 397   int i;
 398   for (i = 0; i < 8; i++)
 399     set_vr (SD_, VD, i, vr (SD_, VS, i) & do_select (SD_, i, SEL, VT));
 400 }
 401
 402 // Vector Compare Equal.
 403 010010,4.SEL,0,5.VT,5.VS,00000,000001::::C.EQ.OB
 404 "c.eq.ob v<VS>, %s<VT#SEL,VT>"
 405 *vr5400:
 406 {
 407   int i;
 408   for (i = 0; i < 8; i++)
 409     set_cc (SD_, i, Compare (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
 410 }
 411
 412 // Vector Compare Less Than or Equal.
 413 010010,4.SEL,0,5.VT,5.VS,00000,000101::::C.LE.OB
 414 "c.le.ob v<VS>, %s<VT#SEL,VT>"
 415 *vr5400:
 416 {
 417   int i;
 418   for (i = 0; i < 8; i++)
 419     set_cc (SD_, i, Compare (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
 420 }
 421
 422 // Vector Compare Less Than.
 423 010010,4.SEL,0,5.VT,5.VS,00000,000100::::C.LT.OB
 424 "c.lt.ob v<VS>, %s<VT#SEL,VT>"
 425 *vr5400:
 426 {
 427   int i;
 428   for (i = 0; i < 8; i++)
 429     set_cc (SD_, i, Compare (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
 430 }
 431
 432 // Vector Maximum.
 433 010010,4.SEL,0,5.VT,5.VS,5.VD,000111::::MAX.OB
 434 "max.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 435 *vr5400:
 436 {
 437   int i;
 438   for (i = 0; i < 8; i++)
 439     set_vr (SD_, VD, i, Max (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
 440 }
 441
 442 // Vector Minimum.
 443 010010,4.SEL,0,5.VT,5.VS,5.VD,000110::::MIN.OB
 444 "min.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 445 *vr5400:
 446 {
 447   int i;
 448   for (i = 0; i < 8; i++)
 449     set_vr (SD_, VD, i, Min (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
 450 }
 451
 452 // Vector Multiply.
 453 010010,4.SEL,0,5.VT,5.VS,5.VD,110000::::MUL.OB
 454 "mul.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 455 *vr5400:
 456 {
 457   int i;
 458   for (i = 0; i < 8; i++)
 459     set_vr (SD_, VD, i, vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
 460 }
 461
 462 // Vector Multiply, Accumulate.
 463 010010,4.SEL,0,5.VT,5.VS,00000,110011::::MULA.OB
 464 "mula.ob v<VS>, %s<VT#SEL,VT>"
 465 *vr5400:
 466 {
 467   int i;
 468   for (i = 0; i < 8; i++)
 469     set_VecAcc (SD_, i, VecAcc (SD_, i) + vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
 470 }
 471
 472 // Vector Multiply, Load Accumulator.
 473 010010,4.SEL,0,5.VT,5.VS,10000,110011::::MULL.OB
 474 "mull.ob v<VS>, %s<VT#SEL,VT>"
 475 *vr5400:
 476 {
 477   int i;
 478   for (i = 0; i < 8; i++)
 479     set_VecAcc (SD_, i, 0 + vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
 480 }
 481
 482 // Vector Multiply, Negate, Accumulate.
 483 010010,4.SEL,0,5.VT,5.VS,00000,110010::::MULS.OB
 484 "muls.ob v<VS>, %s<VT#SEL,VT>"
 485 *vr5400:
 486 {
 487   int i;
 488   for (i = 0; i < 8; i++)
 489     set_VecAcc (SD_, i, VecAcc (SD_, i) - vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
 490 }
 491
 492 // Vector Multiply, Negate, Load Accumulator.
 493 010010,4.SEL,0,5.VT,5.VS,10000,110010::::MULSL.OB
 494 "mulsl.ob v<VS>, %s<VT#SEL,VT>"
 495 *vr5400:
 496 {
 497   int i;
 498   for (i = 0; i < 8; i++)
 499     set_VecAcc (SD_, i, 0 - vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
 500 }
 501
 502 // Vector NOr.
 503 010010,4.SEL,0,5.VT,5.VS,5.VD,001111::::NOR.OB
 504 "nor.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 505 *vr5400:
 506 {
 507   int i;
 508   for (i = 0; i < 8; i++)
 509     set_vr (SD_, VD, i, ! (vr (SD_, VS, i) | do_select (SD_, i, SEL, VT)));
 510 }
 511
 512 // Vector Or.
 513 010010,4.SEL,0,5.VT,5.VS,5.VD,001110::::OR.OB
 514 "or.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 515 *vr5400:
 516 {
 517   int i;
 518   for (i = 0; i < 8; i++)
 519     set_vr (SD_, VD, i, vr (SD_, VS, i) | do_select (SD_, i, SEL, VT));
 520 }
 521
 522 // Vector Pick False.
 523 010010,4.SEL,0,5.VT,5.VS,5.VD,000010::::PICKF.OB
 524 "pickf.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 525 *vr5400:
 526 {
 527   int i;
 528   for (i = 0; i < 8; i++)
 529     set_vr (SD_, VD, i, cc (SD_, i) ? do_select (SD_, i, SEL, VT) : vr (SD_, VS, i));
 530 }
 531
 532 // Vector Pick True.
 533 010010,4.SEL,0,5.VT,5.VS,5.VD,000011::::PICKT.OB
 534 "pickt.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 535 *vr5400:
 536 {
 537   int i;
 538   for (i = 0; i < 8; i++)
 539     set_vr (SD_, VD, i, cc (SD_, i) ? vr (SD_, VS, i) : do_select (SD_, i, SEL, VT));
 540 }
 541
 542 // Vector Read  Accumulator High.
 543 010010,1000,0,00000,00000,5.VD,111111::::RACH.OB
 544 "rach.ob v<VD>"
 545 *vr5400:
 546 {
 547   int i;
 548   for (i = 0; i < 8; i++)
 549     set_vr (SD_, VD, i, EXTRACTED (VecAcc (SD_, i), 23, 16));
 550 }
 551
 552 // Vector Read  Accumulator Low.
 553 010010,0000,0,00000,00000,5.VD,111111::::RACL.OB
 554 "racl.ob v<VD>"
 555 *vr5400:
 556 {
 557   int i;
 558   for (i = 0; i < 8; i++)
 559     set_vr (SD_, VD, i, EXTRACTED (VecAcc (SD_, i), 7, 0));
 560 }
 561
 562 // Vector Read  Accumulator Middle.
 563 010010,0100,0,00000,00000,5.VD,111111::::RACM.OB
 564 "racm.ob v<VD>"
 565 *vr5400:
 566 {
 567   int i;
 568   for (i = 0; i < 8; i++)
 569     set_vr (SD_, VD, i, EXTRACTED (VecAcc (SD_, i), 15, 8));
 570 }
 571
 572 // Vector Scale, Round and Clamp Accumulator.
 573 010010,4.SEL,0,5.VT,00000,5.VD,100000::::RZU.OB
 574 "rzu.ob v<VD>, %s<VT#SEL,VT>"
 575 *vr5400:
 576 {
 577   int i;
 578   for (i = 0; i < 8; i++)
 579     set_vr (SD_, VD, i, Clamp (SD_, Round (SD_, VecAcc (SD_, i) >> do_select (SD_, i, SEL, VT))));
 580 }
 581
 582 // Vector Element Shuffle.
 583 010010,0110,0,5.VT,5.VS,5.VD,011111::::SHFL.MIXH.OB
 584 "shfl.mixh.ob v<VD>, v<VS>, <VT>"
 585 *vr5400:
 586 {
 587   int i;
 588   for (i = 0; i < 8; i++)
 589     set_vr (SD_, VD, i, One_of (SD_, VS, VT));
 590 }
 591
 592 // Vector Element Shuffle.
 593 010010,0111,0,5.VT,5.VS,5.VD,011111::::SHFL.MIXL.OB
 594 "shfl.mixl.ob v<VD>, v<VS>, <VT>"
 595 *vr5400:
 596 {
 597   int i;
 598   for (i = 0; i < 8; i++)
 599     set_vr (SD_, VD, i, One_of (SD_, VS, VT));
 600 }
 601
 602 // Vector Element Shuffle.
 603 010010,0100,0,5.VT,5.VS,5.VD,011111::::SHFL.PACH.OB
 604 "shfl.pach.ob v<VD>, v<VS>, <VT>"
 605 *vr5400:
 606 {
 607   int i;
 608   for (i = 0; i < 8; i++)
 609     set_vr (SD_, VD, i, One_of (SD_, VS, VT));
 610 }
 611
 612 // Vector Element Shuffle.
 613 010010,0101,0,5.VT,5.VS,5.VD,011111::::SHFL.PACL.OB
 614 "shfl.pacl.ob v<VD>, v<VS>, <VT>"
 615 *vr5400:
 616 {
 617   int i;
 618   for (i = 0; i < 8; i++)
 619     set_vr (SD_, VD, i, One_of (SD_, VS, VT));
 620 }
 621
 622 // Vector Shift Left  Logical.
 623 010010,4.SEL,0,5.VT,5.VS,5.VD,010000::::SLL.OB
 624 "sll.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 625 *vr5400:
 626 {
 627   int i;
 628   for (i = 0; i < 8; i++)
 629     set_vr (SD_, VD, i, vr (SD_, VS, i) << do_select (SD_, i, SEL, VT));
 630 }
 631
 632 // Vector Shift Right Logical.
 633 010010,4.SEL,0,5.VT,5.VS,5.VD,010010::::SRL.OB
 634 "srl.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 635 *vr5400:
 636 {
 637   int i;
 638   for (i = 0; i < 8; i++)
 639     set_vr (SD_, VD, i, vr (SD_, VS, i) >> do_select (SD_, i, SEL, VT));
 640 }
 641
 642 // Vector Subtract.
 643 010010,4.SEL,0,5.VT,5.VS,5.VD,001010::::SUB.OB
 644 "sub.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 645 *vr5400:
 646 {
 647   int i;
 648   for (i = 0; i < 8; i++)
 649     set_vr (SD_, VD, i, vr (SD_, VS, i) - do_select (SD_, i, SEL, VT));
 650 }
 651
 652 // Vector Write Accumulator High.
 653 010010,1000,0,00000,5.VS,00000,111110::::WACH.OB
 654 "wach.ob v<VS>"
 655 *vr5400:
 656 {
 657   int i;
 658   for (i = 0; i < 8; i++)
 659     /* High8 */ set_VecAcc (SD_, i, (vr (SD_, VS, i) << 16) | MASKED (VecAcc (SD_, i), 15, 0));
 660 }
 661
 662 // Vector Write Accumulator Low.
 663 010010,0000,0,5.VT,5.VS,00000,111110::::WACL.OB
 664 "wacl.ob v<VS>, <VT>"
 665 *vr5400:
 666 {
 667   int i;
 668   for (i = 0; i < 8; i++)
 669     set_VecAcc (SD_, i, (EXTEND8 (vr (SD_, VS, i)) << 8) | vr (SD_, VT, i));
 670 }
 671
 672 // Vector XOr.
 673 010010,4.SEL,0,5.VT,5.VS,5.VD,001101::::XOR.OB
 674 "xor.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
 675 *vr5400:
 676 {
 677   int i;
 678   for (i = 0; i < 8; i++)
 679     set_vr (SD_, VD, i, vr (SD_, VS, i) ^ do_select (SD_, i, SEL, VT));
 680 }