7 #include "mn10200_sim.h"
13 #include <sys/times.h>
16 #define REG0(X) ((X) & 0x3)
17 #define REG1(X) (((X) & 0xc) >> 2)
18 #define REG0_4(X) (((X) & 0x30) >> 4)
19 #define REG0_8(X) (((X) & 0x300) >> 8)
20 #define REG1_8(X) (((X) & 0xc00) >> 10)
21 #define REG0_16(X) (((X) & 0x30000) >> 16)
22 #define REG1_16(X) (((X) & 0xc0000) >> 18)
23 #define TRUNC(X) ((X) & 0xffffff)
26 void OP_8000 (insn
, extension
)
27 unsigned long insn
, extension
;
29 State
.regs
[REG_D0
+ REG0_8 (insn
)] = SEXT8 (insn
& 0xff);
33 void OP_80 (insn
, extension
)
34 unsigned long insn
, extension
;
36 State
.regs
[REG_D0
+ REG0 (insn
)] = State
.regs
[REG_D0
+ REG1 (insn
)];
40 void OP_F230 (insn
, extension
)
41 unsigned long insn
, extension
;
43 State
.regs
[REG_A0
+ REG0 (insn
)] = State
.regs
[REG_D0
+ REG1 (insn
)];
47 void OP_F2F0 (insn
, extension
)
48 unsigned long insn
, extension
;
50 State
.regs
[REG_D0
+ REG0 (insn
)] = State
.regs
[REG_A0
+ REG1 (insn
)];
54 void OP_F270 (insn
, extension
)
55 unsigned long insn
, extension
;
57 State
.regs
[REG_A0
+ REG0 (insn
)] = State
.regs
[REG_A0
+ REG1 (insn
)];
61 void OP_F3F0 (insn
, extension
)
62 unsigned long insn
, extension
;
64 State
.regs
[REG_D0
+ REG0 (insn
)] = PSW
& 0xffff;
68 void OP_F3D0 (insn
, extension
)
69 unsigned long insn
, extension
;
71 PSW
= State
.regs
[REG_D0
+ REG1 (insn
)] & 0xffff ;
75 void OP_F3E0 (insn
, extension
)
76 unsigned long insn
, extension
;
78 State
.regs
[REG_D0
+ REG0 (insn
)] = State
.regs
[REG_MDR
] & 0xffff;
82 void OP_F3C0 (insn
, extension
)
83 unsigned long insn
, extension
;
85 State
.regs
[REG_MDR
] = State
.regs
[REG_D0
+ REG1 (insn
)] & 0xffff;
89 void OP_20 (insn
, extension
)
90 unsigned long insn
, extension
;
92 State
.regs
[REG_D0
+ REG0 (insn
)]
93 = SEXT16 (load_half (State
.regs
[REG_A0
+ REG1 (insn
)]));
97 void OP_6000 (insn
, extension
)
98 unsigned long insn
, extension
;
100 State
.regs
[REG_D0
+ REG0_8 (insn
)]
101 = SEXT16 (load_half ((State
.regs
[REG_A0
+ REG1_8 (insn
)]
102 + SEXT8 (insn
& 0xff))));
105 /* mov (d16,an), dm */
106 void OP_F7C00000 (insn
, extension
)
107 unsigned long insn
, extension
;
109 State
.regs
[REG_D0
+ REG0_16 (insn
)]
110 = SEXT16 (load_half ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
111 + SEXT16 (insn
& 0xffff))));
114 /* mov (d24,am), dn */
115 void OP_F4800000 (insn
, extension
)
116 unsigned long insn
, extension
;
118 State
.regs
[REG_D0
+ REG0_16 (insn
)]
119 = SEXT16 (load_half ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
120 + SEXT24 (((insn
& 0xffff) << 8) + extension
))));
123 /* mov (di,an), dm */
124 void OP_F140 (insn
, extension
)
125 unsigned long insn
, extension
;
127 State
.regs
[REG_D0
+ REG0 (insn
)]
128 = SEXT16 (load_half ((State
.regs
[REG_A0
+ REG1 (insn
)]
129 + State
.regs
[REG_D0
+ REG0_4 (insn
)])));
132 /* mov (abs16), dn */
133 void OP_C80000 (insn
, extension
)
134 unsigned long insn
, extension
;
136 State
.regs
[REG_D0
+ REG0_16 (insn
)] = SEXT16 (load_half ((insn
& 0xffff)));
139 /* mov (abs24), dn */
140 void OP_F4C00000 (insn
, extension
)
141 unsigned long insn
, extension
;
143 State
.regs
[REG_D0
+ REG0_16 (insn
)]
144 = SEXT16 (load_half ((((insn
& 0xffff) << 8) + extension
)));
147 /* mov (d8,an), am */
148 void OP_7000 (insn
, extension
)
149 unsigned long insn
, extension
;
151 State
.regs
[REG_A0
+ REG0_8 (insn
)]
152 = SEXT24 (load_3_byte ((State
.regs
[REG_A0
+ REG1_8 (insn
)]
153 + SEXT8 (insn
& 0xff))));
156 /* mov (d16,an), am */
157 void OP_F7B00000 (insn
, extension
)
158 unsigned long insn
, extension
;
160 State
.regs
[REG_A0
+ REG0_16 (insn
)]
161 = SEXT24 (load_3_byte ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
162 + SEXT16 (insn
& 0xffff))));
165 /* mov (d24,am), an */
166 void OP_F4F00000 (insn
, extension
)
167 unsigned long insn
, extension
;
169 State
.regs
[REG_A0
+ REG0_16 (insn
)]
170 = SEXT24 (load_3_byte ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
171 + SEXT24 (((insn
& 0xffff) << 8) + extension
))));
174 /* mov (di,an), am */
175 void OP_F100 (insn
, extension
)
176 unsigned long insn
, extension
;
178 State
.regs
[REG_A0
+ REG0 (insn
)]
179 = SEXT24 (load_3_byte ((State
.regs
[REG_A0
+ REG1 (insn
)]
180 + State
.regs
[REG_D0
+ REG0_4 (insn
)])));
183 /* mov (abs16), an */
184 void OP_F7300000 (insn
, extension
)
185 unsigned long insn
, extension
;
187 State
.regs
[REG_A0
+ REG0_16 (insn
)] = SEXT24 (load_3_byte ((insn
& 0xffff)));
190 /* mov (abs24), an */
191 void OP_F4D00000 (insn
, extension
)
192 unsigned long insn
, extension
;
194 State
.regs
[REG_A0
+ REG0_16 (insn
)]
195 = SEXT24 (load_3_byte ((((insn
& 0xffff) << 8) + extension
)));
199 void OP_0 (insn
, extension
)
200 unsigned long insn
, extension
;
202 store_half (State
.regs
[REG_A0
+ REG1 (insn
)],
203 State
.regs
[REG_D0
+ REG0 (insn
)]);
206 /* mov dm, (d8,an) */
207 void OP_4000 (insn
, extension
)
208 unsigned long insn
, extension
;
210 store_half (State
.regs
[REG_A0
+ REG1_8 (insn
)] + SEXT8 (insn
& 0xff),
211 State
.regs
[REG_D0
+ REG0_8 (insn
)]);
214 /* mov dm, (d16,an) */
215 void OP_F7800000 (insn
, extension
)
216 unsigned long insn
, extension
;
218 store_half (State
.regs
[REG_A0
+ REG1_16 (insn
)] + SEXT16 (insn
& 0xffff),
219 State
.regs
[REG_D0
+ REG0_16 (insn
)]);
222 /* mov dm, (d24,am) */
223 void OP_F4000000 (insn
, extension
)
224 unsigned long insn
, extension
;
226 store_half ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
227 + SEXT24 (((insn
& 0xffff) << 8) + extension
)),
228 State
.regs
[REG_D0
+ REG0_16 (insn
)]);
231 /* mov dm, (di,an) */
232 void OP_F1C0 (insn
, extension
)
233 unsigned long insn
, extension
;
235 store_half ((State
.regs
[REG_A0
+ REG1 (insn
)]
236 + State
.regs
[REG_D0
+ REG0_4 (insn
)]),
237 State
.regs
[REG_D0
+ REG0 (insn
)]);
240 /* mov dn, (abs16) */
241 void OP_C00000 (insn
, extension
)
242 unsigned long insn
, extension
;
244 store_half ((insn
& 0xffff), State
.regs
[REG_D0
+ REG0_16 (insn
)]);
247 /* mov dn, (abs24) */
248 void OP_F4400000 (insn
, extension
)
249 unsigned long insn
, extension
;
251 store_half (SEXT24 (((insn
& 0xffff) << 8) + extension
),
252 State
.regs
[REG_D0
+ REG0_16 (insn
)]);
255 /* mov am, (d8,an) */
256 void OP_5000 (insn
, extension
)
257 unsigned long insn
, extension
;
259 store_3_byte (State
.regs
[REG_A0
+ REG1_8 (insn
)] + SEXT8 (insn
& 0xff),
260 State
.regs
[REG_A0
+ REG0_8 (insn
)]);
263 /* mov am, (d16,an) */
264 void OP_F7A00000 (insn
, extension
)
265 unsigned long insn
, extension
;
267 store_3_byte (State
.regs
[REG_A0
+ REG1_16 (insn
)] + SEXT16 (insn
& 0xffff),
268 State
.regs
[REG_A0
+ REG0_16 (insn
)]);
271 /* mov am, (d24,an) */
272 void OP_F4100000 (insn
, extension
)
273 unsigned long insn
, extension
;
275 store_3_byte ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
276 + SEXT24 (((insn
& 0xffff) << 8) + extension
)),
277 State
.regs
[REG_A0
+ REG0_16 (insn
)]);
280 /* mov am, (di,an) */
281 void OP_F180 (insn
, extension
)
282 unsigned long insn
, extension
;
284 store_3_byte ((State
.regs
[REG_A0
+ REG1 (insn
)]
285 + State
.regs
[REG_D0
+ REG0_4 (insn
)]),
286 State
.regs
[REG_A0
+ REG0 (insn
)]);
289 /* mov an, (abs16) */
290 void OP_F7200000 (insn
, extension
)
291 unsigned long insn
, extension
;
293 store_3_byte ((insn
& 0xffff), State
.regs
[REG_A0
+ REG0_16 (insn
)]);
296 /* mov an, (abs24) */
297 void OP_F4500000 (insn
, extension
)
298 unsigned long insn
, extension
;
300 store_3_byte (SEXT24 (((insn
& 0xffff) << 8) + extension
),
301 State
.regs
[REG_A0
+ REG0_16 (insn
)]);
305 void OP_F80000 (insn
, extension
)
306 unsigned long insn
, extension
;
308 State
.regs
[REG_D0
+ REG0_16 (insn
)] = SEXT16 (insn
& 0xffff);
312 void OP_F4700000 (insn
, extension
)
313 unsigned long insn
, extension
;
315 State
.regs
[REG_D0
+ REG0_16 (insn
)]
316 = SEXT24 (((insn
& 0xffff) << 8) + extension
);
320 void OP_DC0000 (insn
, extension
)
321 unsigned long insn
, extension
;
323 State
.regs
[REG_A0
+ REG0_16 (insn
)] = insn
& 0xffff;
327 void OP_F4740000 (insn
, extension
)
328 unsigned long insn
, extension
;
330 State
.regs
[REG_A0
+ REG0_16 (insn
)]
331 = SEXT24 (((insn
& 0xffff) << 8) + extension
);
334 /* movx (d8,an), dm */
335 void OP_F57000 (insn
, extension
)
336 unsigned long insn
, extension
;
338 State
.regs
[REG_D0
+ REG0_8 (insn
)]
339 = SEXT24 (load_3_byte ((State
.regs
[REG_A0
+ REG1_8 (insn
)]
340 + SEXT8 (insn
& 0xff))));
343 /* movx (d16,an), dm */
344 void OP_F7700000 (insn
, extension
)
345 unsigned long insn
, extension
;
347 State
.regs
[REG_D0
+ REG0_16 (insn
)]
348 = SEXT24 (load_3_byte ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
349 + SEXT16 (insn
& 0xffff))));
352 /* movx (d24,am), dn */
353 void OP_F4B00000 (insn
, extension
)
354 unsigned long insn
, extension
;
356 State
.regs
[REG_D0
+ REG0_16 (insn
)]
357 = SEXT24 (load_3_byte ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
358 + SEXT24 (((insn
& 0xffff) << 8) + extension
))));
361 /* movx dm, (d8,an) */
362 void OP_F55000 (insn
, extension
)
363 unsigned long insn
, extension
;
365 store_3_byte (State
.regs
[REG_A0
+ REG1_8 (insn
)] + SEXT8 (insn
& 0xff),
366 State
.regs
[REG_D0
+ REG0_8 (insn
)]);
369 /* movx dm, (d16,an) */
370 void OP_F7600000 (insn
, extension
)
371 unsigned long insn
, extension
;
373 store_3_byte (State
.regs
[REG_A0
+ REG1_16 (insn
)] + SEXT16 (insn
& 0xffff),
374 State
.regs
[REG_D0
+ REG0_16 (insn
)]);
377 /* movx dm, (d24,am) */
378 void OP_F4300000 (insn
, extension
)
379 unsigned long insn
, extension
;
381 store_3_byte ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
382 + SEXT24 (((insn
& 0xffff) << 8) + extension
)),
383 State
.regs
[REG_D0
+ REG0_16 (insn
)]);
386 /* movb (d8,an), dm */
387 void OP_F52000 (insn
, extension
)
388 unsigned long insn
, extension
;
390 State
.regs
[REG_D0
+ REG0_8 (insn
)]
391 = SEXT8 (load_byte ((State
.regs
[REG_A0
+ REG1_8 (insn
)]
392 + SEXT8 (insn
& 0xff))));
395 /* movb (d16,an), dm */
396 void OP_F7D00000 (insn
, extension
)
397 unsigned long insn
, extension
;
399 State
.regs
[REG_D0
+ REG0_16 (insn
)]
400 = SEXT8 (load_byte ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
401 + SEXT16 (insn
& 0xffff))));
404 /* movb (d24,am), dn */
405 void OP_F4A00000 (insn
, extension
)
406 unsigned long insn
, extension
;
408 State
.regs
[REG_D0
+ REG0_16 (insn
)]
409 = SEXT8 (load_byte ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
410 + SEXT24 (((insn
& 0xffff) << 8) + extension
))));
413 /* movb (di,an), dm */
414 void OP_F040 (insn
, extension
)
415 unsigned long insn
, extension
;
417 State
.regs
[REG_D0
+ REG0 (insn
)]
418 = SEXT8 (load_byte ((State
.regs
[REG_A0
+ REG1 (insn
)]
419 + State
.regs
[REG_D0
+ REG0_4 (insn
)])));
422 /* mov (abs24), dn */
423 void OP_F4C40000 (insn
, extension
)
424 unsigned long insn
, extension
;
426 State
.regs
[REG_D0
+ REG0_16 (insn
)]
427 = SEXT8 (load_byte ((((insn
& 0xffff) << 8) + extension
)));
431 void OP_10 (insn
, extension
)
432 unsigned long insn
, extension
;
434 store_byte (State
.regs
[REG_A0
+ REG1 (insn
)],
435 State
.regs
[REG_D0
+ REG0 (insn
)]);
438 /* movb dm, (d8,an) */
439 void OP_F51000 (insn
, extension
)
440 unsigned long insn
, extension
;
442 store_byte (State
.regs
[REG_A0
+ REG1_8 (insn
)] + SEXT8 (insn
& 0xff),
443 State
.regs
[REG_D0
+ REG0_8 (insn
)]);
446 /* movb dm, (d16,an) */
447 void OP_F7900000 (insn
, extension
)
448 unsigned long insn
, extension
;
450 store_byte (State
.regs
[REG_A0
+ REG1_16 (insn
)] + SEXT16 (insn
& 0xffff),
451 State
.regs
[REG_D0
+ REG0_16 (insn
)]);
454 /* movb dm, (d24,am) */
455 void OP_F4200000 (insn
, extension
)
456 unsigned long insn
, extension
;
458 store_byte ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
459 + SEXT24 (((insn
& 0xffff) << 8) + extension
)),
460 State
.regs
[REG_D0
+ REG0_16 (insn
)]);
463 /* movb dm, (di,an) */
464 void OP_F0C0 (insn
, extension
)
465 unsigned long insn
, extension
;
467 store_byte ((State
.regs
[REG_A0
+ REG1 (insn
)]
468 + State
.regs
[REG_D0
+ REG0_4 (insn
)]),
469 State
.regs
[REG_D0
+ REG0 (insn
)]);
472 /* movb dn, (abs16) */
473 void OP_C40000 (insn
, extension
)
474 unsigned long insn
, extension
;
476 store_byte ((insn
& 0xffff), State
.regs
[REG_D0
+ REG0_16 (insn
)]);
479 /* movb dn, (abs24) */
480 void OP_F4440000 (insn
, extension
)
481 unsigned long insn
, extension
;
483 store_byte (SEXT24 (((insn
& 0xffff) << 8) + extension
),
484 State
.regs
[REG_D0
+ REG0_16 (insn
)]);
488 void OP_30 (insn
, extension
)
489 unsigned long insn
, extension
;
491 State
.regs
[REG_D0
+ REG0 (insn
)]
492 = load_byte (State
.regs
[REG_A0
+ REG1 (insn
)]);
495 /* movbu (d8,an), dm */
496 void OP_F53000 (insn
, extension
)
497 unsigned long insn
, extension
;
499 State
.regs
[REG_D0
+ REG0_8 (insn
)]
500 = load_byte ((State
.regs
[REG_A0
+ REG1_8 (insn
)] + SEXT8 (insn
& 0xff)));
503 /* movbu (d16,an), dm */
504 void OP_F7500000 (insn
, extension
)
505 unsigned long insn
, extension
;
507 State
.regs
[REG_D0
+ REG0_16 (insn
)]
508 = load_byte ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
509 + SEXT16 (insn
& 0xffff)));
512 /* movbu (d24,am), dn */
513 void OP_F4900000 (insn
, extension
)
514 unsigned long insn
, extension
;
516 State
.regs
[REG_D0
+ REG0_16 (insn
)]
517 = load_byte ((State
.regs
[REG_A0
+ REG1_16 (insn
)]
518 + SEXT24 (((insn
& 0xffff) << 8) + extension
)));
521 /* movbu (di,an), dm */
522 void OP_F080 (insn
, extension
)
523 unsigned long insn
, extension
;
525 State
.regs
[REG_D0
+ REG0 (insn
)]
526 = load_byte ((State
.regs
[REG_A0
+ REG1 (insn
)]
527 + State
.regs
[REG_D0
+ REG0_4 (insn
)]));
530 /* movbu (abs16), dn */
531 void OP_CC0000 (insn
, extension
)
532 unsigned long insn
, extension
;
534 State
.regs
[REG_D0
+ REG0_16 (insn
)] = load_byte ((insn
& 0xffff));
537 /* movbu (abs24), dn */
538 void OP_F4C80000 (insn
, extension
)
539 unsigned long insn
, extension
;
541 State
.regs
[REG_D0
+ REG0_16 (insn
)]
542 = load_byte ((((insn
& 0xffff) << 8) + extension
));
546 void OP_F3C1 (insn
, extension
)
547 unsigned long insn
, extension
;
549 if (State
.regs
[REG_D0
+ REG1 (insn
)] & 0x8000)
550 State
.regs
[REG_MDR
] = 0xffff;
552 State
.regs
[REG_MDR
] = 0;
556 void OP_B0 (insn
, extension
)
557 unsigned long insn
, extension
;
559 State
.regs
[REG_D0
+ REG0 (insn
)] = SEXT16 (State
.regs
[REG_D0
+ REG0 (insn
)]);
563 void OP_B4 (insn
, extension
)
564 unsigned long insn
, extension
;
566 State
.regs
[REG_D0
+ REG0 (insn
)] = State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff;
570 void OP_B8 (insn
, extension
)
571 unsigned long insn
, extension
;
573 State
.regs
[REG_D0
+ REG0 (insn
)] = SEXT8 (State
.regs
[REG_D0
+ REG0 (insn
)]);
577 void OP_BC (insn
, extension
)
578 unsigned long insn
, extension
;
580 State
.regs
[REG_D0
+ REG0 (insn
)] = State
.regs
[REG_D0
+ REG0 (insn
)] & 0xff;
584 void OP_90 (insn
, extension
)
585 unsigned long insn
, extension
;
587 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
588 unsigned long reg1
, reg2
, value
;
590 reg1
= TRUNC (State
.regs
[REG_D0
+ REG1 (insn
)]);
591 reg2
= TRUNC (State
.regs
[REG_D0
+ REG0 (insn
)]);
592 value
= TRUNC (reg1
+ reg2
);
593 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
595 z
= ((value
& 0xffff) == 0);
597 n
= (value
& 0x8000);
598 nx
= (value
& 0x800000);
599 c
= ((value
& 0xffff) < (reg1
& 0xffff))
600 || ((value
& 0xffff) < (reg2
& 0xffff));
601 cx
= (value
< reg1
) || (value
< reg2
);
602 v
= ((reg2
& 0x8000) == (reg1
& 0x8000)
603 && (reg2
& 0x8000) != (value
& 0x8000));
604 vx
= ((reg2
& 0x800000) == (reg1
& 0x800000)
605 && (reg2
& 0x800000) != (value
& 0x800000));
607 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
608 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
609 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
610 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
611 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
612 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
616 void OP_F200 (insn
, extension
)
617 unsigned long insn
, extension
;
619 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
620 unsigned long reg1
, reg2
, value
;
622 reg1
= TRUNC (State
.regs
[REG_D0
+ REG1 (insn
)]);
623 reg2
= TRUNC (State
.regs
[REG_A0
+ REG0 (insn
)]);
624 value
= TRUNC (reg1
+ reg2
);
625 State
.regs
[REG_A0
+ REG0 (insn
)] = value
;
627 z
= ((value
& 0xffff) == 0);
629 n
= (value
& 0x8000);
630 nx
= (value
& 0x800000);
631 c
= ((value
& 0xffff) < (reg1
& 0xffff))
632 || ((value
& 0xffff) < (reg2
& 0xffff));
633 cx
= (value
< reg1
) || (value
< reg2
);
634 v
= ((reg2
& 0x8000) == (reg1
& 0x8000)
635 && (reg2
& 0x8000) != (value
& 0x8000));
636 vx
= ((reg2
& 0x800000) == (reg1
& 0x800000)
637 && (reg2
& 0x800000) != (value
& 0x800000));
639 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
640 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
641 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
642 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
643 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
644 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
648 void OP_F2C0 (insn
, extension
)
649 unsigned long insn
, extension
;
651 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
652 unsigned long reg1
, reg2
, value
;
654 reg1
= TRUNC (State
.regs
[REG_A0
+ REG1 (insn
)]);
655 reg2
= TRUNC (State
.regs
[REG_D0
+ REG0 (insn
)]);
656 value
= TRUNC (reg1
+ reg2
);
657 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
659 z
= ((value
& 0xffff) == 0);
661 n
= (value
& 0x8000);
662 nx
= (value
& 0x800000);
663 c
= ((value
& 0xffff) < (reg1
& 0xffff))
664 || ((value
& 0xffff) < (reg2
& 0xffff));
665 cx
= (value
< reg1
) || (value
< reg2
);
666 v
= ((reg2
& 0x8000) == (reg1
& 0x8000)
667 && (reg2
& 0x8000) != (value
& 0x8000));
668 vx
= ((reg2
& 0x800000) == (reg1
& 0x800000)
669 && (reg2
& 0x800000) != (value
& 0x800000));
671 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
672 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
673 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
674 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
675 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
676 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
680 void OP_F240 (insn
, extension
)
681 unsigned long insn
, extension
;
683 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
684 unsigned long reg1
, reg2
, value
;
686 reg1
= TRUNC (State
.regs
[REG_A0
+ REG1 (insn
)]);
687 reg2
= TRUNC (State
.regs
[REG_A0
+ REG0 (insn
)]);
688 value
= TRUNC (reg1
+ reg2
);
689 State
.regs
[REG_A0
+ REG0 (insn
)] = value
;
691 z
= ((value
& 0xffff) == 0);
693 n
= (value
& 0x8000);
694 nx
= (value
& 0x800000);
695 c
= ((value
& 0xffff) < (reg1
& 0xffff))
696 || ((value
& 0xffff) < (reg2
& 0xffff));
697 cx
= (value
< reg1
) || (value
< reg2
);
698 v
= ((reg2
& 0x8000) == (reg1
& 0x8000)
699 && (reg2
& 0x8000) != (value
& 0x8000));
700 vx
= ((reg2
& 0x800000) == (reg1
& 0x800000)
701 && (reg2
& 0x800000) != (value
& 0x800000));
703 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
704 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
705 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
706 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
707 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
708 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
712 void OP_D400 (insn
, extension
)
713 unsigned long insn
, extension
;
715 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
716 unsigned long reg1
, imm
, value
;
718 reg1
= TRUNC (State
.regs
[REG_D0
+ REG0_8 (insn
)]);
719 imm
= TRUNC (SEXT8 (insn
& 0xff));
720 value
= TRUNC (reg1
+ imm
);
721 State
.regs
[REG_D0
+ REG0_8 (insn
)] = value
;
723 z
= ((value
& 0xffff) == 0);
725 n
= (value
& 0x8000);
726 nx
= (value
& 0x800000);
727 c
= ((value
& 0xffff) < (reg1
& 0xffff))
728 || ((value
& 0xffff) < (imm
& 0xffff));
729 cx
= (value
< reg1
) || (value
< imm
);
730 v
= ((reg1
& 0x8000) == (imm
& 0x8000)
731 && (reg1
& 0x8000) != (value
& 0x8000));
732 vx
= ((reg1
& 0x800000) == (imm
& 0x800000)
733 && (reg1
& 0x800000) != (value
& 0x800000));
735 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
736 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
737 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
738 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
739 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
740 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
744 void OP_F7180000 (insn
, extension
)
745 unsigned long insn
, extension
;
747 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
748 unsigned long reg1
, imm
, value
;
750 reg1
= TRUNC (State
.regs
[REG_D0
+ REG0_16 (insn
)]);
751 imm
= TRUNC (SEXT16 (insn
& 0xffff));
752 value
= TRUNC (reg1
+ imm
);
753 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
755 z
= ((value
& 0xffff) == 0);
757 n
= (value
& 0x8000);
758 nx
= (value
& 0x800000);
759 c
= ((value
& 0xffff) < (reg1
& 0xffff))
760 || ((value
& 0xffff) < (imm
& 0xffff));
761 cx
= (value
< reg1
) || (value
< imm
);
762 v
= ((reg1
& 0x8000) == (imm
& 0x8000)
763 && (reg1
& 0x8000) != (value
& 0x8000));
764 vx
= ((reg1
& 0x800000) == (imm
& 0x800000)
765 && (reg1
& 0x800000) != (value
& 0x800000));
767 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
768 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
769 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
770 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
771 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
772 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
776 void OP_F4600000 (insn
, extension
)
777 unsigned long insn
, extension
;
779 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
780 unsigned long reg1
, imm
, value
;
782 reg1
= TRUNC (State
.regs
[REG_D0
+ REG0_16 (insn
)]);
783 imm
= TRUNC (((insn
& 0xffff) << 8) + extension
);
784 value
= TRUNC (reg1
+ imm
);
785 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
787 z
= ((value
& 0xffff) == 0);
789 n
= (value
& 0x8000);
790 nx
= (value
& 0x800000);
791 c
= ((value
& 0xffff) < (reg1
& 0xffff))
792 || ((value
& 0xffff) < (imm
& 0xffff));
793 cx
= (value
< reg1
) || (value
< imm
);
794 v
= ((reg1
& 0x8000) == (imm
& 0x8000)
795 && (reg1
& 0x8000) != (value
& 0x8000));
796 vx
= ((reg1
& 0x800000) == (imm
& 0x800000)
797 && (reg1
& 0x800000) != (value
& 0x800000));
799 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
800 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
801 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
802 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
803 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
804 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
808 void OP_D000 (insn
, extension
)
809 unsigned long insn
, extension
;
811 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
812 unsigned long reg1
, imm
, value
;
814 reg1
= TRUNC (State
.regs
[REG_A0
+ REG0_8 (insn
)]);
815 imm
= TRUNC (SEXT8 (insn
& 0xff));
816 value
= TRUNC (reg1
+ imm
);
817 State
.regs
[REG_A0
+ REG0_8 (insn
)] = value
;
819 z
= ((value
& 0xffff) == 0);
821 n
= (value
& 0x8000);
822 nx
= (value
& 0x800000);
823 c
= ((value
& 0xffff) < (reg1
& 0xffff))
824 || ((value
& 0xffff) < (imm
& 0xffff));
825 cx
= (value
< reg1
) || (value
< imm
);
826 v
= ((reg1
& 0x8000) == (imm
& 0x8000)
827 && (reg1
& 0x8000) != (value
& 0x8000));
828 vx
= ((reg1
& 0x800000) == (imm
& 0x800000)
829 && (reg1
& 0x800000) != (value
& 0x800000));
831 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
832 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
833 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
834 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
835 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
836 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
840 void OP_F7080000 (insn
, extension
)
841 unsigned long insn
, extension
;
843 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
844 unsigned long reg1
, imm
, value
;
846 reg1
= TRUNC (State
.regs
[REG_A0
+ REG0_16 (insn
)]);
847 imm
= TRUNC (SEXT16 (insn
& 0xffff));
848 value
= TRUNC (reg1
+ imm
);
849 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
851 z
= ((value
& 0xffff) == 0);
853 n
= (value
& 0x8000);
854 nx
= (value
& 0x800000);
855 c
= ((value
& 0xffff) < (reg1
& 0xffff))
856 || ((value
& 0xffff) < (imm
& 0xffff));
857 cx
= (value
< reg1
) || (value
< imm
);
858 v
= ((reg1
& 0x8000) == (imm
& 0x8000)
859 && (reg1
& 0x8000) != (value
& 0x8000));
860 vx
= ((reg1
& 0x800000) == (imm
& 0x800000)
861 && (reg1
& 0x800000) != (value
& 0x800000));
863 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
864 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
865 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
866 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
867 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
868 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
872 void OP_F4640000 (insn
, extension
)
873 unsigned long insn
, extension
;
875 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
876 unsigned long reg1
, imm
, value
;
878 reg1
= TRUNC (State
.regs
[REG_A0
+ REG0_16 (insn
)]);
879 imm
= TRUNC (((insn
& 0xffff) << 8) + extension
);
880 value
= TRUNC (reg1
+ imm
);
881 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
883 z
= ((value
& 0xffff) == 0);
885 n
= (value
& 0x8000);
886 nx
= (value
& 0x800000);
887 c
= ((value
& 0xffff) < (reg1
& 0xffff)) || ((value
& 0xffff) < (imm
& 0xffff));
888 cx
= (value
< reg1
) || (value
< imm
);
889 v
= ((reg1
& 0x8000) == (imm
& 0x8000)
890 && (reg1
& 0x8000) != (value
& 0x8000));
891 vx
= ((reg1
& 0x800000) == (imm
& 0x800000)
892 && (reg1
& 0x800000) != (value
& 0x800000));
894 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
895 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
896 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
897 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
898 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
899 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
903 void OP_F280 (insn
, extension
)
904 unsigned long insn
, extension
;
906 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
907 unsigned long reg1
, reg2
, value
;
909 reg1
= TRUNC (State
.regs
[REG_D0
+ REG1 (insn
)]);
910 reg2
= TRUNC (State
.regs
[REG_D0
+ REG0 (insn
)]);
911 value
= TRUNC (reg1
+ reg2
+ ((PSW
& PSW_CF
) != 0));
912 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
914 z
= ((value
& 0xffff) == 0);
916 n
= (value
& 0x8000);
917 nx
= (value
& 0x800000);
918 c
= ((value
& 0xffff) < (reg1
& 0xffff))
919 || ((value
& 0xffff) < (reg2
& 0xffff));
920 cx
= (value
< reg1
) || (value
< reg2
);
921 v
= ((reg2
& 0x8000) == (reg1
& 0x8000)
922 && (reg2
& 0x8000) != (value
& 0x8000));
923 vx
= ((reg2
& 0x800000) == (reg1
& 0x800000)
924 && (reg2
& 0x800000) != (value
& 0x800000));
926 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
927 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
928 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
929 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
930 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
931 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
935 void OP_F50C00 (insn
, extension
)
936 unsigned long insn
, extension
;
938 unsigned long reg1
, imm
, value
;
940 reg1
= State
.regs
[REG_A0
+ REG0_8 (insn
)];
941 imm
= SEXT8 (insn
& 0xff);
943 State
.regs
[REG_A0
+ REG0_8 (insn
)] = TRUNC (value
);
947 void OP_A0 (insn
, extension
)
948 unsigned long insn
, extension
;
950 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
951 unsigned long reg1
, reg2
, value
;
953 reg1
= TRUNC (State
.regs
[REG_D0
+ REG1 (insn
)]);
954 reg2
= TRUNC (State
.regs
[REG_D0
+ REG0 (insn
)]);
955 value
= TRUNC (reg2
- reg1
);
956 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
958 z
= ((value
& 0xffff) == 0);
960 n
= (value
& 0x8000);
961 nx
= (value
& 0x800000);
962 c
= ((reg1
& 0xffff) > (reg2
& 0xffff));
964 v
= ((reg2
& 0x8000) != (reg1
& 0x8000)
965 && (reg2
& 0x8000) != (value
& 0x8000));
966 vx
= ((reg2
& 0x800000) != (reg1
& 0x800000)
967 && (reg2
& 0x800000) != (value
& 0x800000));
969 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
970 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
971 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
972 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
973 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
974 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
978 void OP_F210 (insn
, extension
)
979 unsigned long insn
, extension
;
981 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
982 unsigned long reg1
, reg2
, value
;
984 reg1
= TRUNC (State
.regs
[REG_D0
+ REG1 (insn
)]);
985 reg2
= TRUNC (State
.regs
[REG_A0
+ REG0 (insn
)]);
986 value
= TRUNC (reg2
- reg1
);
987 State
.regs
[REG_A0
+ REG0 (insn
)] = value
;
989 z
= ((value
& 0xffff) == 0);
991 n
= (value
& 0x8000);
992 nx
= (value
& 0x800000);
993 c
= ((reg1
& 0xffff) > (reg2
& 0xffff));
995 v
= ((reg2
& 0x8000) != (reg1
& 0x8000)
996 && (reg2
& 0x8000) != (value
& 0x8000));
997 vx
= ((reg2
& 0x800000) != (reg1
& 0x800000)
998 && (reg2
& 0x800000) != (value
& 0x800000));
1000 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1001 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1002 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1003 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1004 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1005 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1009 void OP_F2D0 (insn
, extension
)
1010 unsigned long insn
, extension
;
1012 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1013 unsigned long reg1
, reg2
, value
;
1015 reg1
= TRUNC (State
.regs
[REG_A0
+ REG1 (insn
)]);
1016 reg2
= TRUNC (State
.regs
[REG_D0
+ REG0 (insn
)]);
1017 value
= TRUNC (reg2
- reg1
);
1018 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
1020 z
= ((value
& 0xffff) == 0);
1022 n
= (value
& 0x8000);
1023 nx
= (value
& 0x800000);
1024 c
= ((reg1
& 0xffff) > (reg2
& 0xffff));
1026 v
= ((reg2
& 0x8000) != (reg1
& 0x8000)
1027 && (reg2
& 0x8000) != (value
& 0x8000));
1028 vx
= ((reg2
& 0x800000) != (reg1
& 0x800000)
1029 && (reg2
& 0x800000) != (value
& 0x800000));
1031 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1032 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1033 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1034 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1035 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1036 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1040 void OP_F250 (insn
, extension
)
1041 unsigned long insn
, extension
;
1043 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1044 unsigned long reg1
, reg2
, value
;
1046 reg1
= TRUNC (State
.regs
[REG_A0
+ REG1 (insn
)]);
1047 reg2
= TRUNC (State
.regs
[REG_A0
+ REG0 (insn
)]);
1048 value
= TRUNC (reg2
- reg1
);
1049 State
.regs
[REG_A0
+ REG0 (insn
)] = value
;
1051 z
= ((value
& 0xffff) == 0);
1053 n
= (value
& 0x8000);
1054 nx
= (value
& 0x800000);
1055 c
= ((reg1
& 0xffff) > (reg2
& 0xffff));
1057 v
= ((reg2
& 0x8000) != (reg1
& 0x8000)
1058 && (reg2
& 0x8000) != (value
& 0x8000));
1059 vx
= ((reg2
& 0x800000) != (reg1
& 0x800000)
1060 && (reg2
& 0x800000) != (value
& 0x800000));
1062 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1063 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1064 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1065 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1066 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1067 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1071 void OP_F71C0000 (insn
, extension
)
1072 unsigned long insn
, extension
;
1074 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1075 unsigned long reg1
, imm
, value
;
1077 reg1
= TRUNC (State
.regs
[REG_D0
+ REG0_16 (insn
)]);
1078 imm
= TRUNC (SEXT16 (insn
& 0xffff));
1079 value
= TRUNC (reg1
- imm
);
1080 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
1082 z
= ((value
& 0xffff) == 0);
1084 n
= (value
& 0x8000);
1085 nx
= (value
& 0x800000);
1086 c
= ((reg1
& 0xffff) < (imm
& 0xffff));
1088 v
= ((reg1
& 0x8000) != (imm
& 0x8000)
1089 && (reg1
& 0x8000) != (value
& 0x8000));
1090 vx
= ((reg1
& 0x800000) != (imm
& 0x800000)
1091 && (reg1
& 0x800000) != (value
& 0x800000));
1093 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1094 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1095 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1096 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1097 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1098 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1102 void OP_F4680000 (insn
, extension
)
1103 unsigned long insn
, extension
;
1105 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1106 unsigned long reg1
, imm
, value
;
1108 reg1
= TRUNC (State
.regs
[REG_D0
+ REG0_16 (insn
)]);
1109 imm
= TRUNC (((insn
& 0xffff) << 8) + extension
);
1110 value
= TRUNC (reg1
- imm
);
1111 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
1113 z
= ((value
& 0xffff) == 0);
1115 n
= (value
& 0x8000);
1116 nx
= (value
& 0x800000);
1117 c
= ((reg1
& 0xffff) < (imm
& 0xffff));
1119 v
= ((reg1
& 0x8000) != (imm
& 0x8000)
1120 && (reg1
& 0x8000) != (value
& 0x8000));
1121 vx
= ((reg1
& 0x800000) != (imm
& 0x800000)
1122 && (reg1
& 0x800000) != (value
& 0x800000));
1124 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1125 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1126 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1127 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1128 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1129 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1133 void OP_F70C0000 (insn
, extension
)
1134 unsigned long insn
, extension
;
1136 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1137 unsigned long reg1
, imm
, value
;
1139 reg1
= TRUNC (State
.regs
[REG_A0
+ REG0_16 (insn
)]);
1140 imm
= TRUNC (SEXT16 (insn
& 0xffff));
1141 value
= TRUNC (reg1
- imm
);
1142 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
1144 z
= ((value
& 0xffff) == 0);
1146 n
= (value
& 0x8000);
1147 nx
= (value
& 0x800000);
1148 c
= ((reg1
& 0xffff) < (imm
& 0xffff));
1150 v
= ((reg1
& 0x8000) != (imm
& 0x8000)
1151 && (reg1
& 0x8000) != (value
& 0x8000));
1152 vx
= ((reg1
& 0x800000) != (imm
& 0x800000)
1153 && (reg1
& 0x800000) != (value
& 0x800000));
1155 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1156 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1157 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1158 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1159 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1160 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1164 void OP_F46C0000 (insn
, extension
)
1165 unsigned long insn
, extension
;
1167 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1168 unsigned long reg1
, imm
, value
;
1170 reg1
= TRUNC (State
.regs
[REG_A0
+ REG0_16 (insn
)]);
1171 imm
= TRUNC (((insn
& 0xffff) << 8) + extension
);
1172 value
= TRUNC (reg1
- imm
);
1173 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
1175 z
= ((value
& 0xffff) == 0);
1177 n
= (value
& 0x8000);
1178 nx
= (value
& 0x800000);
1179 c
= ((reg1
& 0xffff) < (imm
& 0xffff));
1181 v
= ((reg1
& 0x8000) != (imm
& 0x8000)
1182 && (reg1
& 0x8000) != (value
& 0x8000));
1183 vx
= ((reg1
& 0x800000) != (imm
& 0x800000)
1184 && (reg1
& 0x800000) != (value
& 0x800000));
1186 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1187 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1188 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1189 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1190 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1191 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1195 void OP_F290 (insn
, extension
)
1196 unsigned long insn
, extension
;
1198 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1199 unsigned long reg1
, reg2
, value
;
1201 reg1
= TRUNC (State
.regs
[REG_D0
+ REG1 (insn
)]);
1202 reg2
= TRUNC (State
.regs
[REG_D0
+ REG0 (insn
)]);
1203 value
= TRUNC (reg2
- reg1
- ((PSW
& PSW_CF
) != 0));
1204 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
1206 z
= ((value
& 0xffff) == 0);
1208 n
= (value
& 0x8000);
1209 nx
= (value
& 0x800000);
1210 c
= ((reg1
& 0xffff) > (reg2
& 0xffff));
1212 v
= ((reg2
& 0x8000) != (reg1
& 0x8000)
1213 && (reg2
& 0x8000) != (value
& 0x8000));
1214 vx
= ((reg2
& 0x800000) != (reg1
& 0x800000)
1215 && (reg2
& 0x800000) != (value
& 0x800000));
1217 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1218 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1219 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1220 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1221 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1222 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1226 void OP_F340 (insn
, extension
)
1227 unsigned long insn
, extension
;
1232 temp
= (SEXT16 (State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff)
1233 * SEXT16 ((State
.regs
[REG_D0
+ REG1 (insn
)] & 0xffff)));
1234 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffffff;
1235 State
.regs
[REG_MDR
] = temp
>> 16;
1236 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff) == 0;
1237 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x8000) != 0;
1238 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_VF
);
1239 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0));
1243 void OP_F350 (insn
, extension
)
1244 unsigned long insn
, extension
;
1249 temp
= ((State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff)
1250 * (State
.regs
[REG_D0
+ REG1 (insn
)] & 0xffff));
1251 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffffff;
1252 State
.regs
[REG_MDR
] = temp
>> 16;
1253 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff) == 0;
1254 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x8000) != 0;
1255 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_VF
);
1256 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0));
1261 void OP_F360 (insn
, extension
)
1262 unsigned long insn
, extension
;
1267 temp
= State
.regs
[REG_MDR
];
1270 temp
|= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff);
1271 State
.regs
[REG_MDR
] = (temp
1272 % (unsigned long)(State
.regs
[REG_D0
+ REG1 (insn
)] & 0xffff));
1273 temp
/= (unsigned long)(State
.regs
[REG_D0
+ REG1 (insn
)] & 0xffff);
1274 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffff;
1275 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff) == 0;
1276 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x8000) != 0;
1277 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1278 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0));
1282 void OP_D800 (insn
, extension
)
1283 unsigned long insn
, extension
;
1285 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1286 unsigned long reg1
, imm
, value
;
1288 reg1
= TRUNC (State
.regs
[REG_D0
+ REG0_8 (insn
)]);
1289 imm
= TRUNC (SEXT8 (insn
& 0xff));
1290 value
= TRUNC (reg1
- imm
);
1292 z
= ((value
& 0xffff) == 0);
1294 n
= (value
& 0x8000);
1295 nx
= (value
& 0x800000);
1296 c
= ((reg1
& 0xffff) < (imm
& 0xffff));
1298 v
= ((reg1
& 0x8000) != (imm
& 0x8000)
1299 && (reg1
& 0x8000) != (value
& 0x8000));
1300 vx
= ((reg1
& 0x800000) != (imm
& 0x800000)
1301 && (reg1
& 0x800000) != (value
& 0x800000));
1303 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1304 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1305 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1306 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1307 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1308 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1312 void OP_F390 (insn
, extension
)
1313 unsigned long insn
, extension
;
1315 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1316 unsigned long reg1
, reg2
, value
;
1318 reg1
= TRUNC (State
.regs
[REG_D0
+ REG1 (insn
)]);
1319 reg2
= TRUNC (State
.regs
[REG_D0
+ REG0 (insn
)]);
1320 value
= TRUNC (reg2
- reg1
);
1322 z
= ((value
& 0xffff) == 0);
1324 n
= (value
& 0x8000);
1325 nx
= (value
& 0x800000);
1326 c
= ((reg1
& 0xffff) > (reg2
& 0xffff));
1328 v
= ((reg2
& 0x8000) != (reg1
& 0x8000)
1329 && (reg2
& 0x8000) != (value
& 0x8000));
1330 vx
= ((reg2
& 0x800000) != (reg1
& 0x800000)
1331 && (reg2
& 0x800000) != (value
& 0x800000));
1333 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1334 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1335 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1336 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1337 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1338 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1340 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1341 PSW
|= ((z
? PSW_ZF
: 0) | ( n
? PSW_NF
: 0)
1342 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0));
1346 void OP_F220 (insn
, extension
)
1347 unsigned long insn
, extension
;
1349 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1350 unsigned long reg1
, reg2
, value
;
1352 reg1
= TRUNC (State
.regs
[REG_D0
+ REG1 (insn
)]);
1353 reg2
= TRUNC (State
.regs
[REG_A0
+ REG0 (insn
)]);
1354 value
= TRUNC (reg2
- reg1
);
1356 z
= ((value
& 0xffff) == 0);
1358 n
= (value
& 0x8000);
1359 nx
= (value
& 0x800000);
1360 c
= ((reg1
& 0xffff) > (reg2
& 0xffff));
1362 v
= ((reg2
& 0x8000) != (reg1
& 0x8000)
1363 && (reg2
& 0x8000) != (value
& 0x8000));
1364 vx
= ((reg2
& 0x800000) != (reg1
& 0x800000)
1365 && (reg2
& 0x800000) != (value
& 0x800000));
1367 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1368 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1369 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1370 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1371 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1372 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1374 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1375 PSW
|= ((z
? PSW_ZF
: 0) | ( n
? PSW_NF
: 0)
1376 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0));
1380 void OP_F2E0 (insn
, extension
)
1381 unsigned long insn
, extension
;
1383 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1384 unsigned long reg1
, reg2
, value
;
1386 reg1
= TRUNC (State
.regs
[REG_A0
+ REG1 (insn
)]);
1387 reg2
= TRUNC (State
.regs
[REG_D0
+ REG0 (insn
)]);
1388 value
= TRUNC (reg2
- reg1
);
1390 z
= ((value
& 0xffff) == 0);
1392 n
= (value
& 0x8000);
1393 nx
= (value
& 0x800000);
1394 c
= ((reg1
& 0xffff) > (reg2
& 0xffff));
1396 v
= ((reg2
& 0x8000) != (reg1
& 0x8000)
1397 && (reg2
& 0x8000) != (value
& 0x8000));
1398 vx
= ((reg2
& 0x800000) != (reg1
& 0x800000)
1399 && (reg2
& 0x800000) != (value
& 0x800000));
1401 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1402 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1403 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1404 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1405 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1406 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1408 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1409 PSW
|= ((z
? PSW_ZF
: 0) | ( n
? PSW_NF
: 0)
1410 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0));
1414 void OP_F260 (insn
, extension
)
1415 unsigned long insn
, extension
;
1417 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1418 unsigned long reg1
, reg2
, value
;
1420 reg1
= TRUNC (State
.regs
[REG_A0
+ REG1 (insn
)]);
1421 reg2
= TRUNC (State
.regs
[REG_A0
+ REG0 (insn
)]);
1422 value
= TRUNC (reg2
- reg1
);
1424 z
= ((value
& 0xffff) == 0);
1426 n
= (value
& 0x8000);
1427 nx
= (value
& 0x800000);
1428 c
= ((reg1
& 0xffff) > (reg2
& 0xffff));
1430 v
= ((reg2
& 0x8000) != (reg1
& 0x8000)
1431 && (reg2
& 0x8000) != (value
& 0x8000));
1432 vx
= ((reg2
& 0x800000) != (reg1
& 0x800000)
1433 && (reg2
& 0x800000) != (value
& 0x800000));
1435 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1436 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1437 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1438 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1439 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1440 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1442 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1443 PSW
|= ((z
? PSW_ZF
: 0) | ( n
? PSW_NF
: 0)
1444 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0));
1448 void OP_F7480000 (insn
, extension
)
1449 unsigned long insn
, extension
;
1451 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1452 unsigned long reg1
, imm
, value
;
1454 reg1
= TRUNC (State
.regs
[REG_D0
+ REG0_16 (insn
)]);
1455 imm
= TRUNC (SEXT16 (insn
& 0xffff));
1456 value
= TRUNC (reg1
- imm
);
1458 z
= ((value
& 0xffff) == 0);
1460 n
= (value
& 0x8000);
1461 nx
= (value
& 0x800000);
1462 c
= ((reg1
& 0xffff) < (imm
& 0xffff));
1464 v
= ((reg1
& 0x8000) != (imm
& 0x8000)
1465 && (reg1
& 0x8000) != (value
& 0x8000));
1466 vx
= ((reg1
& 0x800000) != (imm
& 0x800000)
1467 && (reg1
& 0x800000) != (value
& 0x800000));
1469 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1470 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1471 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1472 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1473 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1474 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1476 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1477 PSW
|= ((z
? PSW_ZF
: 0) | ( n
? PSW_NF
: 0)
1478 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0));
1482 void OP_F4780000 (insn
, extension
)
1483 unsigned long insn
, extension
;
1485 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1486 unsigned long reg1
, imm
, value
;
1488 reg1
= TRUNC (State
.regs
[REG_D0
+ REG0_16 (insn
)]);
1489 imm
= TRUNC (((insn
& 0xffff) << 8) + extension
);
1490 value
= TRUNC (reg1
- imm
);
1492 z
= ((value
& 0xffff) == 0);
1494 n
= (value
& 0x8000);
1495 nx
= (value
& 0x800000);
1496 c
= ((reg1
& 0xffff) < (imm
& 0xffff));
1498 v
= ((reg1
& 0x8000) != (imm
& 0x8000)
1499 && (reg1
& 0x8000) != (value
& 0x8000));
1500 vx
= ((reg1
& 0x800000) != (imm
& 0x800000)
1501 && (reg1
& 0x800000) != (value
& 0x800000));
1503 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1504 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1505 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1506 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1507 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1508 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1510 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1511 PSW
|= ((z
? PSW_ZF
: 0) | ( n
? PSW_NF
: 0)
1512 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0));
1516 void OP_EC0000 (insn
, extension
)
1517 unsigned long insn
, extension
;
1519 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1520 unsigned long reg1
, imm
, value
;
1522 reg1
= TRUNC (State
.regs
[REG_A0
+ REG0_16 (insn
)]);
1523 imm
= TRUNC (insn
& 0xffff);
1524 value
= TRUNC (reg1
- imm
);
1526 z
= ((value
& 0xffff) == 0);
1528 n
= (value
& 0x8000);
1529 nx
= (value
& 0x800000);
1530 c
= ((reg1
& 0xffff) < (imm
& 0xffff));
1532 v
= ((reg1
& 0x8000) != (imm
& 0x8000)
1533 && (reg1
& 0x8000) != (value
& 0x8000));
1534 vx
= ((reg1
& 0x800000) != (imm
& 0x800000)
1535 && (reg1
& 0x800000) != (value
& 0x800000));
1537 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1538 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1539 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1540 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1541 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1542 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1544 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1545 PSW
|= ((z
? PSW_ZF
: 0) | ( n
? PSW_NF
: 0)
1546 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0));
1550 void OP_F47C0000 (insn
, extension
)
1551 unsigned long insn
, extension
;
1553 int z
, c
, n
, v
, zx
, cx
, nx
, vx
;
1554 unsigned long reg1
, imm
, value
;
1556 reg1
= TRUNC (State
.regs
[REG_A0
+ REG0_16 (insn
)]);
1557 imm
= TRUNC (((insn
& 0xffff) << 8) + extension
);
1558 value
= TRUNC (reg1
- imm
);
1560 z
= ((value
& 0xffff) == 0);
1562 n
= (value
& 0x8000);
1563 nx
= (value
& 0x800000);
1564 c
= ((reg1
& 0xffff) < (imm
& 0xffff));
1566 v
= ((reg1
& 0x8000) != (imm
& 0x8000)
1567 && (reg1
& 0x8000) != (value
& 0x8000));
1568 vx
= ((reg1
& 0x800000) != (imm
& 0x800000)
1569 && (reg1
& 0x800000) != (value
& 0x800000));
1571 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
1572 | PSW_ZX
| PSW_NX
| PSW_CX
| PSW_VX
);
1573 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0)
1574 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0)
1575 | (zx
? PSW_ZX
: 0) | (nx
? PSW_NX
: 0)
1576 | (cx
? PSW_CX
: 0) | (vx
? PSW_VX
: 0));
1578 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1579 PSW
|= ((z
? PSW_ZF
: 0) | ( n
? PSW_NF
: 0)
1580 | (c
? PSW_CF
: 0) | (v
? PSW_VF
: 0));
1584 void OP_F300 (insn
, extension
)
1585 unsigned long insn
, extension
;
1590 temp
= State
.regs
[REG_D0
+ REG0 (insn
)] & State
.regs
[REG_D0
+ REG1 (insn
)];
1592 State
.regs
[REG_D0
+ REG0 (insn
)] &= ~0xffff;
1593 State
.regs
[REG_D0
+ REG0 (insn
)] |= temp
;
1594 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff) == 0;
1595 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x8000) != 0;
1596 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1597 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0));
1601 void OP_F50000 (insn
, extension
)
1602 unsigned long insn
, extension
;
1607 temp
= State
.regs
[REG_D0
+ REG0_8 (insn
)] & (insn
& 0xff);
1609 State
.regs
[REG_D0
+ REG0_8 (insn
)] &= ~0xffff;
1610 State
.regs
[REG_D0
+ REG0_8 (insn
)] |= temp
;
1611 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0xffff) == 0;
1612 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x8000) != 0;
1613 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1614 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0));
1618 void OP_F7000000 (insn
, extension
)
1619 unsigned long insn
, extension
;
1624 temp
= State
.regs
[REG_D0
+ REG0_16 (insn
)] & (insn
& 0xffff);
1626 State
.regs
[REG_D0
+ REG0_16 (insn
)] &= ~0xffff;
1627 State
.regs
[REG_D0
+ REG0_16 (insn
)] |= temp
;
1628 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0xffff) == 0;
1629 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x8000) != 0;
1630 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1631 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0));
1634 /* and imm16, psw */
1635 void OP_F7100000 (insn
, extension
)
1636 unsigned long insn
, extension
;
1638 PSW
&= (insn
& 0xffff);
1642 void OP_F310 (insn
, extension
)
1643 unsigned long insn
, extension
;
1648 temp
= State
.regs
[REG_D0
+ REG0 (insn
)] | State
.regs
[REG_D0
+ REG1 (insn
)];
1650 State
.regs
[REG_D0
+ REG0 (insn
)] &= ~0xffff;
1651 State
.regs
[REG_D0
+ REG0 (insn
)] |= temp
;
1652 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff) == 0;
1653 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x8000) != 0;
1654 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1655 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0));
1659 void OP_F50800 (insn
, extension
)
1660 unsigned long insn
, extension
;
1665 temp
= State
.regs
[REG_D0
+ REG0_8 (insn
)] | (insn
& 0xff);
1667 State
.regs
[REG_D0
+ REG0_8 (insn
)] &= ~0xffff;
1668 State
.regs
[REG_D0
+ REG0_8 (insn
)] |= temp
;
1669 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0xffff) == 0;
1670 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x8000) != 0;
1671 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1672 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0));
1676 void OP_F7400000 (insn
, extension
)
1677 unsigned long insn
, extension
;
1682 temp
= State
.regs
[REG_D0
+ REG0_16 (insn
)] | (insn
& 0xffff);
1684 State
.regs
[REG_D0
+ REG0_16 (insn
)] &= ~0xffff;
1685 State
.regs
[REG_D0
+ REG0_16 (insn
)] |= temp
;
1686 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0xffff) == 0;
1687 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x8000) != 0;
1688 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1689 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0));
1693 void OP_F7140000 (insn
, extension
)
1694 unsigned long insn
, extension
;
1696 PSW
|= (insn
& 0xffff);
1700 void OP_F320 (insn
, extension
)
1701 unsigned long insn
, extension
;
1706 temp
= State
.regs
[REG_D0
+ REG0 (insn
)] ^ State
.regs
[REG_D0
+ REG1 (insn
)];
1708 State
.regs
[REG_D0
+ REG0 (insn
)] &= ~0xffff;
1709 State
.regs
[REG_D0
+ REG0 (insn
)] |= temp
;
1710 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff) == 0;
1711 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x8000) != 0;
1712 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1713 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0));
1717 void OP_F74C0000 (insn
, extension
)
1718 unsigned long insn
, extension
;
1723 temp
= State
.regs
[REG_D0
+ REG0_16 (insn
)] ^ (insn
& 0xffff);
1725 State
.regs
[REG_D0
+ REG0_16 (insn
)] &= ~0xffff;
1726 State
.regs
[REG_D0
+ REG0_16 (insn
)] |= temp
;
1727 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0xffff) == 0;
1728 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x8000) != 0;
1729 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1730 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0));
1734 void OP_F3E4 (insn
, extension
)
1735 unsigned long insn
, extension
;
1740 temp
= ~State
.regs
[REG_D0
+ REG0 (insn
)];
1742 State
.regs
[REG_D0
+ REG0 (insn
)] &= ~0xffff;
1743 State
.regs
[REG_D0
+ REG0 (insn
)] |= temp
;
1744 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff) == 0;
1745 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x8000) != 0;
1746 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1747 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0));
1751 void OP_F338 (insn
, extension
)
1752 unsigned long insn
, extension
;
1757 temp
= State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff;
1759 high
= temp
& 0x8000;
1763 State
.regs
[REG_D0
+ REG0 (insn
)] &= ~0xffff;
1764 State
.regs
[REG_D0
+ REG0 (insn
)] |= temp
;
1765 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff) == 0;
1766 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x8000) != 0;
1767 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
);
1768 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0) | (c
? PSW_CF
: 0));
1772 void OP_F33C (insn
, extension
)
1773 unsigned long insn
, extension
;
1778 temp
= State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff;
1782 State
.regs
[REG_D0
+ REG0 (insn
)] &= ~0xffff;
1783 State
.regs
[REG_D0
+ REG0 (insn
)] |= temp
;
1784 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff) == 0;
1785 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x8000) != 0;
1786 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
);
1787 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0) | (c
? PSW_CF
: 0));
1791 void OP_F334 (insn
, extension
)
1792 unsigned long insn
, extension
;
1794 unsigned long value
;
1797 value
= State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff;
1801 value
|= (PSW
& PSW_CF
? 0x8000 : 0);
1803 State
.regs
[REG_D0
+ REG0 (insn
)] &= ~0xffff;
1804 State
.regs
[REG_D0
+ REG0 (insn
)] |= value
;
1806 n
= (value
& 0x8000) != 0;
1807 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1808 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0) | (c
? PSW_CF
: 0));
1812 void OP_F330 (insn
, extension
)
1813 unsigned long insn
, extension
;
1815 unsigned long value
;
1818 value
= State
.regs
[REG_D0
+ REG0 (insn
)] & 0xffff;
1819 c
= (value
& 0x8000) ? 1 : 0;
1822 value
|= (PSW
& PSW_CF
? 0x1 : 0);
1824 State
.regs
[REG_D0
+ REG0 (insn
)] &= ~0xffff;
1825 State
.regs
[REG_D0
+ REG0 (insn
)] |= value
;
1827 n
= (value
& 0x8000) != 0;
1828 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1829 PSW
|= ((z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0) | (c
? PSW_CF
: 0));
1833 void OP_F50400 (insn
, extension
)
1834 unsigned long insn
, extension
;
1839 temp
= State
.regs
[REG_D0
+ REG0_8 (insn
)];
1840 temp
&= (insn
& 0xff);
1842 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1843 PSW
|= (z
? PSW_ZF
: 0);
1846 /* btst imm16, dn */
1847 void OP_F7040000 (insn
, extension
)
1848 unsigned long insn
, extension
;
1853 temp
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1855 temp
&= (insn
& 0xffff);
1856 n
= (temp
& 0x8000) != 0;
1858 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1859 PSW
|= (z
? PSW_ZF
: 0) | (n
? PSW_NF
: 0) | (c
? PSW_CF
: 0);
1863 void OP_F020 (insn
, extension
)
1864 unsigned long insn
, extension
;
1869 temp
= load_byte (State
.regs
[REG_A0
+ REG1 (insn
)]);
1870 z
= (temp
& State
.regs
[REG_D0
+ REG0 (insn
)]) == 0;
1871 temp
|= State
.regs
[REG_D0
+ REG0 (insn
)];
1872 store_byte (State
.regs
[REG_A0
+ REG1 (insn
)], temp
);
1873 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1874 PSW
|= (z
? PSW_ZF
: 0);
1878 void OP_F030 (insn
, extension
)
1879 unsigned long insn
, extension
;
1884 temp
= load_byte (State
.regs
[REG_A0
+ REG1 (insn
)]);
1885 z
= (temp
& State
.regs
[REG_D0
+ REG0 (insn
)]) == 0;
1886 temp
= temp
& ~State
.regs
[REG_D0
+ REG0 (insn
)];
1887 store_byte (State
.regs
[REG_A0
+ REG1 (insn
)], temp
);
1888 PSW
&= ~(PSW_ZF
| PSW_NF
| PSW_CF
| PSW_VF
);
1889 PSW
|= (z
? PSW_ZF
: 0);
1893 void OP_F5E800 (insn
, extension
)
1894 unsigned long insn
, extension
;
1896 /* The dispatching code will add 3 after we return, so
1897 we subtract two here to make things right. */
1899 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
1903 void OP_F5E900 (insn
, extension
)
1904 unsigned long insn
, extension
;
1906 /* The dispatching code will add 3 after we return, so
1907 we subtract two here to make things right. */
1908 if (!(PSW
& PSW_ZX
))
1909 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
1913 void OP_F5E100 (insn
, extension
)
1914 unsigned long insn
, extension
;
1916 /* The dispatching code will add 3 after we return, so
1917 we subtract two here to make things right. */
1918 if (!((PSW
& PSW_ZX
)
1919 || (((PSW
& PSW_NX
) != 0) ^ ((PSW
& PSW_VX
) != 0))))
1920 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
1924 void OP_F5E200 (insn
, extension
)
1925 unsigned long insn
, extension
;
1927 /* The dispatching code will add 3 after we return, so
1928 we subtract two here to make things right. */
1929 if (!(((PSW
& PSW_NX
) != 0) ^ ((PSW
& PSW_VX
) != 0)))
1930 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
1934 void OP_F5E300 (insn
, extension
)
1935 unsigned long insn
, extension
;
1937 /* The dispatching code will add 3 after we return, so
1938 we subtract two here to make things right. */
1940 || (((PSW
& PSW_NX
) != 0) ^ ((PSW
& PSW_VX
) != 0)))
1941 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
1945 void OP_F5E000 (insn
, extension
)
1946 unsigned long insn
, extension
;
1948 /* The dispatching code will add 3 after we return, so
1949 we subtract two here to make things right. */
1950 if (((PSW
& PSW_NX
) != 0) ^ ((PSW
& PSW_VX
) != 0))
1951 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
1955 void OP_F5E500 (insn
, extension
)
1956 unsigned long insn
, extension
;
1958 /* The dispatching code will add 3 after we return, so
1959 we subtract two here to make things right. */
1960 if (!(((PSW
& PSW_CX
) != 0) || (PSW
& PSW_ZX
) != 0))
1961 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
1965 void OP_F5E600 (insn
, extension
)
1966 unsigned long insn
, extension
;
1968 /* The dispatching code will add 3 after we return, so
1969 we subtract two here to make things right. */
1970 if (!(PSW
& PSW_CX
))
1971 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
1975 void OP_F5E700 (insn
, extension
)
1976 unsigned long insn
, extension
;
1978 /* The dispatching code will add 3 after we return, so
1979 we subtract two here to make things right. */
1980 if (((PSW
& PSW_CX
) != 0) || (PSW
& PSW_ZX
) != 0)
1981 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
1985 void OP_F5E400 (insn
, extension
)
1986 unsigned long insn
, extension
;
1988 /* The dispatching code will add 3 after we return, so
1989 we subtract two here to make things right. */
1991 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
1995 void OP_F5EC00 (insn
, extension
)
1996 unsigned long insn
, extension
;
1998 /* The dispatching code will add 3 after we return, so
1999 we subtract two here to make things right. */
2000 if (!(PSW
& PSW_VX
))
2001 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2005 void OP_F5ED00 (insn
, extension
)
2006 unsigned long insn
, extension
;
2008 /* The dispatching code will add 3 after we return, so
2009 we subtract two here to make things right. */
2011 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2015 void OP_F5EE00 (insn
, extension
)
2016 unsigned long insn
, extension
;
2018 /* The dispatching code will add 3 after we return, so
2019 we subtract two here to make things right. */
2020 if (!(PSW
& PSW_NX
))
2021 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2025 void OP_F5EF00 (insn
, extension
)
2026 unsigned long insn
, extension
;
2028 /* The dispatching code will add 3 after we return, so
2029 we subtract two here to make things right. */
2031 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2035 void OP_E800 (insn
, extension
)
2036 unsigned long insn
, extension
;
2038 /* The dispatching code will add 2 after we return, so
2039 we subtract two here to make things right. */
2041 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2045 void OP_E900 (insn
, extension
)
2046 unsigned long insn
, extension
;
2048 /* The dispatching code will add 2 after we return, so
2049 we subtract two here to make things right. */
2050 if (!(PSW
& PSW_ZF
))
2051 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2055 void OP_E100 (insn
, extension
)
2056 unsigned long insn
, extension
;
2058 /* The dispatching code will add 2 after we return, so
2059 we subtract two here to make things right. */
2060 if (!((PSW
& PSW_ZF
)
2061 || (((PSW
& PSW_NF
) != 0) ^ ((PSW
& PSW_VF
) != 0))))
2062 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2066 void OP_E200 (insn
, extension
)
2067 unsigned long insn
, extension
;
2069 /* The dispatching code will add 2 after we return, so
2070 we subtract two here to make things right. */
2071 if (!(((PSW
& PSW_NF
) != 0) ^ ((PSW
& PSW_VF
) != 0)))
2072 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2076 void OP_E300 (insn
, extension
)
2077 unsigned long insn
, extension
;
2079 /* The dispatching code will add 2 after we return, so
2080 we subtract two here to make things right. */
2082 || (((PSW
& PSW_NF
) != 0) ^ ((PSW
& PSW_VF
) != 0)))
2083 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2087 void OP_E000 (insn
, extension
)
2088 unsigned long insn
, extension
;
2090 /* The dispatching code will add 2 after we return, so
2091 we subtract two here to make things right. */
2092 if (((PSW
& PSW_NF
) != 0) ^ ((PSW
& PSW_VF
) != 0))
2093 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2097 void OP_E500 (insn
, extension
)
2098 unsigned long insn
, extension
;
2100 /* The dispatching code will add 2 after we return, so
2101 we subtract two here to make things right. */
2102 if (!(((PSW
& PSW_CF
) != 0) || (PSW
& PSW_ZF
) != 0))
2103 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2107 void OP_E600 (insn
, extension
)
2108 unsigned long insn
, extension
;
2110 /* The dispatching code will add 2 after we return, so
2111 we subtract two here to make things right. */
2112 if (!(PSW
& PSW_CF
))
2113 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2117 void OP_E700 (insn
, extension
)
2118 unsigned long insn
, extension
;
2120 /* The dispatching code will add 2 after we return, so
2121 we subtract two here to make things right. */
2122 if (((PSW
& PSW_CF
) != 0) || (PSW
& PSW_ZF
) != 0)
2123 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2127 void OP_E400 (insn
, extension
)
2128 unsigned long insn
, extension
;
2130 /* The dispatching code will add 2 after we return, so
2131 we subtract two here to make things right. */
2133 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2137 void OP_F5FC00 (insn
, extension
)
2138 unsigned long insn
, extension
;
2140 /* The dispatching code will add 3 after we return, so
2141 we subtract two here to make things right. */
2142 if (!(PSW
& PSW_VF
))
2143 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2147 void OP_F5FD00 (insn
, extension
)
2148 unsigned long insn
, extension
;
2150 /* The dispatching code will add 3 after we return, so
2151 we subtract two here to make things right. */
2153 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2157 void OP_F5FE00 (insn
, extension
)
2158 unsigned long insn
, extension
;
2160 /* The dispatching code will add 3 after we return, so
2161 we subtract two here to make things right. */
2162 if (!(PSW
& PSW_NF
))
2163 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2167 void OP_F5FF00 (insn
, extension
)
2168 unsigned long insn
, extension
;
2170 /* The dispatching code will add 3 after we return, so
2171 we subtract two here to make things right. */
2173 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2177 void OP_EA00 (insn
, extension
)
2178 unsigned long insn
, extension
;
2180 /* The dispatching code will add 2 after we return, so
2181 we subtract two here to make things right. */
2182 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT8 (insn
& 0xff));
2186 void OP_F000 (insn
, extension
)
2187 unsigned long insn
, extension
;
2189 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_A0
+ REG1 (insn
)] - 2);
2193 void OP_FC0000 (insn
, extension
)
2194 unsigned long insn
, extension
;
2196 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT16 (insn
& 0xffff));
2200 void OP_F4E00000 (insn
, extension
)
2201 unsigned long insn
, extension
;
2204 = TRUNC (State
.regs
[REG_PC
] + (((insn
& 0xffff) << 8) + extension
));
2208 void OP_F001 (insn
, extension
)
2209 unsigned long insn
, extension
;
2211 unsigned int next_pc
, sp
;
2213 sp
= State
.regs
[REG_SP
];
2215 State
.regs
[REG_SP
] = sp
;
2216 next_pc
= State
.regs
[REG_PC
] + 2;
2217 State
.mem
[sp
] = next_pc
& 0xff;
2218 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2219 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2220 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_A0
+ REG1 (insn
)] - 2);
2224 void OP_FD0000 (insn
, extension
)
2225 unsigned long insn
, extension
;
2227 unsigned int next_pc
, sp
;
2229 sp
= State
.regs
[REG_SP
];
2231 State
.regs
[REG_SP
] = sp
;
2232 next_pc
= State
.regs
[REG_PC
] + 3;
2233 State
.mem
[sp
] = next_pc
& 0xff;
2234 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2235 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2236 State
.regs
[REG_PC
] = TRUNC (State
.regs
[REG_PC
] + SEXT16 (insn
& 0xffff));
2240 void OP_F4E10000 (insn
, extension
)
2241 unsigned long insn
, extension
;
2243 unsigned int next_pc
, sp
;
2245 sp
= State
.regs
[REG_SP
];
2247 State
.regs
[REG_SP
] = sp
;
2248 next_pc
= State
.regs
[REG_PC
] + 5;
2249 State
.mem
[sp
] = next_pc
& 0xff;
2250 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2251 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2253 = TRUNC (State
.regs
[REG_PC
] + (((insn
& 0xffff) << 8) + extension
));
2257 void OP_FE (insn
, extension
)
2258 unsigned long insn
, extension
;
2262 sp
= State
.regs
[REG_SP
];
2263 State
.regs
[REG_PC
] = (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2264 | (State
.mem
[sp
+2] << 16));
2265 State
.regs
[REG_PC
] -= 1;
2266 State
.regs
[REG_SP
] += 4;
2270 void OP_EB (insn
, extension
)
2271 unsigned long insn
, extension
;
2273 PSW
= load_half (State
.regs
[REG_A0
+ 3]);
2274 State
.regs
[REG_PC
] = load_3_byte (State
.regs
[REG_A0
+ 3] + 2) - 1;
2275 State
.regs
[REG_A0
+ 3] += 6;
2279 void OP_F010 (insn
, extension
)
2280 unsigned long insn
, extension
;
2282 /* We use this for simulated system calls; we may need to change
2283 it to a reserved instruction if we conflict with uses at
2285 int save_errno
= errno
;
2289 /* Registers passed to syscall 0 */
2291 /* Function number. */
2292 #define FUNC (State.regs[0])
2294 #define PARM1 (State.regs[1])
2297 #define PARM(x, y) (load_mem (State.regs[REG_SP] + x, y))
2299 /* Registers set by syscall 0 */
2301 #define RETVAL State.regs[0] /* return value */
2302 #define RETERR State.regs[1] /* return error code */
2304 /* Turn a pointer in a register into a pointer into real memory. */
2306 #define MEMPTR(x) (State.mem + (x & 0xffffff))
2310 #if !defined(__GO32__) && !defined(_WIN32)
2311 #ifdef TARGET_SYS_fork
2312 case TARGET_SYS_fork
:
2316 #ifdef TARGET_SYS_execve
2317 case TARGET_SYS_execve
:
2318 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM (4, 4)),
2319 (char **)MEMPTR (PARM (8, 4)));
2322 #ifdef TARGET_SYS_execv
2323 case TARGET_SYS_execv
:
2324 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM (4, 4)), NULL
);
2329 case TARGET_SYS_read
:
2330 RETVAL
= mn10200_callback
->read (mn10200_callback
, PARM1
,
2331 MEMPTR (PARM (4, 4)), PARM (8, 4));
2333 case TARGET_SYS_write
:
2334 RETVAL
= (int)mn10200_callback
->write (mn10200_callback
, PARM1
,
2335 MEMPTR (PARM (4, 4)),
2338 case TARGET_SYS_lseek
:
2339 RETVAL
= mn10200_callback
->lseek (mn10200_callback
, PARM1
,
2340 PARM (4, 4), PARM (8, 2));
2342 case TARGET_SYS_close
:
2343 RETVAL
= mn10200_callback
->close (mn10200_callback
, PARM1
);
2345 case TARGET_SYS_open
:
2346 RETVAL
= mn10200_callback
->open (mn10200_callback
, MEMPTR (PARM1
),
2349 case TARGET_SYS_exit
:
2350 /* EXIT - caller can look in PARM1 to work out the
2352 if (PARM1
== 0xdead)
2353 State
.exception
= SIGABRT
;
2355 State
.exception
= SIGQUIT
;
2359 case TARGET_SYS_stat
: /* added at hmsi */
2360 /* stat system call */
2362 struct stat host_stat
;
2365 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2369 /* Just wild-assed guesses. */
2370 store_half (buf
, host_stat
.st_dev
);
2371 store_half (buf
+ 2, host_stat
.st_ino
);
2372 store_word (buf
+ 4, host_stat
.st_mode
);
2373 store_half (buf
+ 8, host_stat
.st_nlink
);
2374 store_half (buf
+ 10, host_stat
.st_uid
);
2375 store_half (buf
+ 12, host_stat
.st_gid
);
2376 store_half (buf
+ 14, host_stat
.st_rdev
);
2377 store_word (buf
+ 16, host_stat
.st_size
);
2378 store_word (buf
+ 20, host_stat
.st_atime
);
2379 store_word (buf
+ 28, host_stat
.st_mtime
);
2380 store_word (buf
+ 36, host_stat
.st_ctime
);
2384 #ifdef TARGET_SYS_chown
2385 case TARGET_SYS_chown
:
2386 RETVAL
= chown (MEMPTR (PARM1
), PARM (4, 2), PARM (6, 2));
2389 case TARGET_SYS_chmod
:
2390 RETVAL
= chmod (MEMPTR (PARM1
), PARM (4, 2));
2392 #ifdef TARGET_SYS_time
2393 case TARGET_SYS_time
:
2394 RETVAL
= time ((time_t *)MEMPTR (PARM1
));
2397 #ifdef TARGET_SYS_times
2398 case TARGET_SYS_times
:
2401 RETVAL
= times (&tms
);
2402 store_word (PARM1
, tms
.tms_utime
);
2403 store_word (PARM1
+ 4, tms
.tms_stime
);
2404 store_word (PARM1
+ 8, tms
.tms_cutime
);
2405 store_word (PARM1
+ 12, tms
.tms_cstime
);
2409 #ifdef TARGET_SYS_gettimeofday
2410 case TARGET_SYS_gettimeofday
:
2414 RETVAL
= gettimeofday (&t
, &tz
);
2415 store_word (PARM1
, t
.tv_sec
);
2416 store_word (PARM1
+ 4, t
.tv_usec
);
2417 store_word (PARM (4, 4), tz
.tz_minuteswest
);
2418 store_word (PARM (4, 4) + 4, tz
.tz_dsttime
);
2422 #ifdef TARGET_SYS_utime
2423 case TARGET_SYS_utime
:
2424 /* Cast the second argument to void *, to avoid type mismatch
2425 if a prototype is present. */
2426 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM (4, 4)));
2437 void OP_F6 (insn
, extension
)
2438 unsigned long insn
, extension
;
2444 OP_FF (insn
, extension
)
2445 unsigned long insn
, extension
;
2447 State
.exception
= SIGTRAP
;
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