sim/mn10300/ChangeLog

   1 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
   4
   5         * simops.c: Fix thinkos in last change to "inc dn".
   6
   7 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
   8
   9         * simops.c: "add imm,sp" does not effect the condition codes.
  10         "inc dn" does effect the condition codes.
  11
  12 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
  13
  14         * simops.c: Treat both operands as signed values for
  15         "div" instruction.
  16
  17         * simops.c: Fix simulation of division instructions.
  18         Fix typos/thinkos in several "cmp" and "sub" instructions.
  19
  20 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
  21
  22         * simops.c: Fix carry bit handling in "sub" and "cmp"
  23         instructions.
  24
  25         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
  26
  27 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
  28
  29         * simops.c: Fix overflow computation for many instructions.
  30
  31         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
  32
  33         * simops.c: Fix "mov am, dn".
  34
  35         * simops.c: Fix more bugs in "add imm,an" and
  36         "add imm,dn".
  37
  38 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
  39
  40         * simops.c: Fix bugs in "movm" and "add imm,an".
  41
  42         * simops.c: Don't lose the upper 24 bits of the return
  43         pointer in "call" and "calls" instructions.  Rough cut
  44         at emulated system calls.
  45
  46         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
  47
  48         * simops.c: Implement remaining 4 byte instructions.
  49
  50         * simops.c: Implement remaining 3 byte instructions.
  51
  52         * simops.c: Implement remaining 2 byte instructions.  Call
  53         abort for instructions we're not implementing now.
  54
  55 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
  56
  57         * simops.c: Implement lots of random instructions.
  58
  59         * simops.c: Implement "movm" and "bCC" insns.
  60
  61         * mn10300_sim.h (_state): Add another register (MDR).
  62         (REG_MDR): Define.
  63         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
  64         a few additional random insns.
  65
  66         * mn10300_sim.h (PSW_*): Define for CC status tracking.
  67         (REG_D0, REG_A0, REG_SP): Define.
  68         * simops.c: Implement "add", "addc" and a few other random
  69         instructions.
  70
  71         * gencode.c, interp.c: Snapshot current simulator code.
  72
  73 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
  74
  75         * Makefile.in, config.in, configure, configure.in: New files.
  76         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
  77