sim/mn10300/ChangeLog

   1 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
   2
   3         * configure: Regenerated to track ../common/aclocal.m4 changes.
   4
   5 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
   6
   7         * configure: Regenerated to track ../common/aclocal.m4 changes.
   8
   9 Thu Mar 20 11:58:02 1997  Jeffrey A Law  (law@cygnus.com)
  10
  11         * simops.c: Fix register extraction for a two "movbu" variants.
  12         Somewhat simplify "sub" instructions.
  13         Correctly sign extend operands for "mul".  Put the correct
  14         half of the result in MDR for "mul" and "mulu".
  15         Implement remaining instructions.
  16         Tweak opcode for "syscall".
  17
  18 Tue Mar 18 14:21:21 1997  Jeffrey A Law  (law@cygnus.com)
  19
  20         * simops.c: Do syscall emulation in "syscall" instruction.  Add
  21         dummy "trap" instruction.
  22
  23 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  24
  25         * configure: Regenerated to track ../common/aclocal.m4 changes.
  26
  27 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  28
  29         * configure: Re-generate.
  30
  31 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
  32
  33         * configure: Regenerate to track ../common/aclocal.m4 changes.
  34
  35 Thu Mar 13 12:54:45 1997  Doug Evans  <dje@canuck.cygnus.com>
  36
  37         * interp.c (sim_open): New SIM_DESC result.  Argument is now
  38         in argv form.
  39         (other sim_*): New SIM_DESC argument.
  40
  41 Wed Mar 12 15:04:00 1997  Jeffrey A Law  (law@cygnus.com)
  42
  43         * simops.c: Fix carry bit computation for "add" instructions.
  44
  45         * simops.c: Fix typos in bset insns.  Fix arguments to store_mem
  46         for bset imm8,(d8,an) and bclr imm8,(d8,an).
  47
  48 Wed Mar  5 15:00:10 1997  Jeffrey A Law  (law@cygnus.com)
  49
  50         * simops.c: Fix register references when computing Z and N bits
  51         for lsr imm8,dn.
  52
  53 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
  54
  55         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
  56         COMMON_{PRE,POST}_CONFIG_FRAG instead.
  57         * configure.in: sinclude ../common/aclocal.m4.
  58         * configure: Regenerated.
  59
  60 Fri Jan 24 10:47:25 1997  Jeffrey A Law  (law@cygnus.com)
  61
  62         * interp.c (init_system): Allocate 2^19 bytes of space for the
  63         simulator.
  64
  65 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
  66
  67         * configure configure.in Makefile.in:  Update to new configure
  68         scheme which is more compatible with WinGDB builds.
  69         * configure.in:  Improve comment on how to run autoconf.
  70         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
  71         * Makefile.in:  Use autoconf substitution to install common
  72         makefile fragment.
  73
  74 Tue Jan 21 15:03:04 1997  Jeffrey A Law  (law@cygnus.com)
  75
  76         * simops.c: Undo last change to "rol" and "ror", original code
  77         was correct!
  78
  79 Thu Jan 16 11:28:14 1997  Jeffrey A Law  (law@cygnus.com)
  80
  81         * simops.c: Fix "rol" and "ror".
  82
  83 Wed Jan 15 06:45:58 1997  Jeffrey A Law  (law@cygnus.com)
  84
  85         * simops.c: Fix typo in last change.
  86
  87 Mon Jan 13 13:22:35 1997  Jeffrey A Law  (law@cygnus.com)
  88
  89         * simops.c: Use REG macros in few places not using them yet.
  90
  91 Mon Jan  6 16:21:19 1997  Jeffrey A Law  (law@cygnus.com)
  92
  93         * mn10300_sim.h (struct _state): Fix number of registers!
  94
  95 Tue Dec 31 16:20:41 1996  Jeffrey A Law  (law@cygnus.com)
  96
  97         * mn10300_sim.h (struct _state): Put all registers into a single
  98         array to make gdb implementation easier.
  99         (REG_*): Add definitions for all registers in the state array.
 100         (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
 101         * simops.c: Related changes.
 102
 103 Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
 104
 105         * interp.c (sim_resume): Handle 0xff as a single byte insn.
 106
 107         * simops.c: Fix overflow computation for "add" and "inc"
 108         instructions.
 109
 110 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
 111
 112         * simops.c: Handle "break" instruction.
 113
 114         * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
 115
 116 Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)
 117
 118         * gencode.c (write_opcodes): Also write out the format of the
 119         opcode.
 120         * mn10300_sim.h (simops): Add "format" field.
 121         * interp.c (sim_resume): Deal with endianness issues here.
 122
 123 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
 124
 125         * simops.c (REG0_4): Define.
 126         Use REG0_4 for indexed loads/stores.
 127
 128 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
 129
 130         * simops.c (REG0_16): Fix typo.
 131
 132 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
 133
 134         * simops.c: Call abort for any instruction that's not currently
 135         simulated.
 136
 137         * simops.c: Define accessor macros to extract register
 138         values from instructions.  Use them consistently.
 139
 140         * interp.c: Delete unused global variable "OP".
 141         (sim_resume): Remove unused variable "opcode".
 142         * simops.c: Fix some uninitialized variable problems, add
 143         parens to fix various -Wall warnings.
 144
 145         * gencode.c (write_header): Add "insn" and "extension" arguments
 146         to the OP_* declarations.
 147         (write_template): Similarly for function templates.
 148         * interp.c (insn, extension): Remove global variables.  Instead
 149         pass them as arguments to the OP_* functions.
 150         * mn10300_sim.h: Remove decls for "insn" and "extension".
 151         * simops.c (OP_*): Accept "insn" and "extension" as arguments
 152         instead of using globals.
 153
 154 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
 155
 156         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
 157
 158         * simops.c: Fix thinkos in last change to "inc dn".
 159
 160 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
 161
 162         * simops.c: "add imm,sp" does not effect the condition codes.
 163         "inc dn" does effect the condition codes.
 164
 165 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
 166
 167         * simops.c: Treat both operands as signed values for
 168         "div" instruction.
 169
 170         * simops.c: Fix simulation of division instructions.
 171         Fix typos/thinkos in several "cmp" and "sub" instructions.
 172
 173 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
 174
 175         * simops.c: Fix carry bit handling in "sub" and "cmp"
 176         instructions.
 177
 178         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
 179
 180 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
 181
 182         * simops.c: Fix overflow computation for many instructions.
 183
 184         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
 185
 186         * simops.c: Fix "mov am, dn".
 187
 188         * simops.c: Fix more bugs in "add imm,an" and
 189         "add imm,dn".
 190
 191 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
 192
 193         * simops.c: Fix bugs in "movm" and "add imm,an".
 194
 195         * simops.c: Don't lose the upper 24 bits of the return
 196         pointer in "call" and "calls" instructions.  Rough cut
 197         at emulated system calls.
 198
 199         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
 200
 201         * simops.c: Implement remaining 4 byte instructions.
 202
 203         * simops.c: Implement remaining 3 byte instructions.
 204
 205         * simops.c: Implement remaining 2 byte instructions.  Call
 206         abort for instructions we're not implementing now.
 207
 208 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
 209
 210         * simops.c: Implement lots of random instructions.
 211
 212         * simops.c: Implement "movm" and "bCC" insns.
 213
 214         * mn10300_sim.h (_state): Add another register (MDR).
 215         (REG_MDR): Define.
 216         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
 217         a few additional random insns.
 218
 219         * mn10300_sim.h (PSW_*): Define for CC status tracking.
 220         (REG_D0, REG_A0, REG_SP): Define.
 221         * simops.c: Implement "add", "addc" and a few other random
 222         instructions.
 223
 224         * gencode.c, interp.c: Snapshot current simulator code.
 225
 226 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 227
 228         * Makefile.in, config.in, configure, configure.in: New files.
 229         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 230