sim/mn10300/ChangeLog

   1 Mon May  5 18:07:48 1997  Jeffrey A Law  (law@cygnus.com)
   2
   3         * mn10300_sim.h (struct _state): Add space for mdrq register.
   4         (REG_MDRQ): Define.
   5         * simops.c: Don't abort for trap.  Add support for the extended
   6         instructions, "getx", "putx", "mulq", "mulqu", "sat16", "sat24",
   7         and "bsch".
   8
   9 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
  10
  11         * configure: Regenerated to track ../common/aclocal.m4 changes.
  12
  13 Fri Apr 18 14:04:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  14
  15         * interp.c (sim_stop): Add stub function.
  16
  17 Thu Apr 17 03:26:59 1997  Doug Evans  <dje@canuck.cygnus.com>
  18
  19         * Makefile.in (SIM_OBJS): Add sim-load.o.
  20         * interp.c (sim_kind, myname): New static locals.
  21         (sim_open): Set sim_kind, myname.  Ignore -E arg.
  22         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
  23         load file into simulator.  Set start address from bfd.
  24         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
  25
  26 Wed Apr 16 19:30:44 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  27
  28         * simops.c (OP_F020): SYS_execv, SYS_time, SYS_times, SYS_utime
  29         only include if implemented by host.
  30         (OP_F020): Typecast arg passed to time function;
  31
  32 Mon Apr  7 23:57:49 1997  Jeffrey A Law  (law@cygnus.com)
  33
  34         * simops.c (syscall): Handle new mn10300 calling conventions.
  35
  36 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  37
  38         * configure: Regenerated to track ../common/aclocal.m4 changes.
  39         * config.in: Ditto.
  40
  41 Fri Apr  4 20:02:37 1997  Ian Lance Taylor  <ian@cygnus.com>
  42
  43         * Makefile.in: Change mn10300-opc.o to m10300-opc.o, to match
  44         corresponding change in opcodes directory.
  45
  46 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
  47
  48         * interp.c (sim_open): New arg `kind'.
  49
  50         * configure: Regenerated to track ../common/aclocal.m4 changes.
  51
  52 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
  53
  54         * configure: Regenerated to track ../common/aclocal.m4 changes.
  55
  56 Thu Mar 20 11:58:02 1997  Jeffrey A Law  (law@cygnus.com)
  57
  58         * simops.c: Fix register extraction for a two "movbu" variants.
  59         Somewhat simplify "sub" instructions.
  60         Correctly sign extend operands for "mul".  Put the correct
  61         half of the result in MDR for "mul" and "mulu".
  62         Implement remaining instructions.
  63         Tweak opcode for "syscall".
  64
  65 Tue Mar 18 14:21:21 1997  Jeffrey A Law  (law@cygnus.com)
  66
  67         * simops.c: Do syscall emulation in "syscall" instruction.  Add
  68         dummy "trap" instruction.
  69
  70 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  71
  72         * configure: Regenerated to track ../common/aclocal.m4 changes.
  73
  74 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  75
  76         * configure: Re-generate.
  77
  78 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
  79
  80         * configure: Regenerate to track ../common/aclocal.m4 changes.
  81
  82 Thu Mar 13 12:54:45 1997  Doug Evans  <dje@canuck.cygnus.com>
  83
  84         * interp.c (sim_open): New SIM_DESC result.  Argument is now
  85         in argv form.
  86         (other sim_*): New SIM_DESC argument.
  87
  88 Wed Mar 12 15:04:00 1997  Jeffrey A Law  (law@cygnus.com)
  89
  90         * simops.c: Fix carry bit computation for "add" instructions.
  91
  92         * simops.c: Fix typos in bset insns.  Fix arguments to store_mem
  93         for bset imm8,(d8,an) and bclr imm8,(d8,an).
  94
  95 Wed Mar  5 15:00:10 1997  Jeffrey A Law  (law@cygnus.com)
  96
  97         * simops.c: Fix register references when computing Z and N bits
  98         for lsr imm8,dn.
  99
 100 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
 101
 102         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
 103         COMMON_{PRE,POST}_CONFIG_FRAG instead.
 104         * configure.in: sinclude ../common/aclocal.m4.
 105         * configure: Regenerated.
 106
 107 Fri Jan 24 10:47:25 1997  Jeffrey A Law  (law@cygnus.com)
 108
 109         * interp.c (init_system): Allocate 2^19 bytes of space for the
 110         simulator.
 111
 112 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
 113
 114         * configure configure.in Makefile.in:  Update to new configure
 115         scheme which is more compatible with WinGDB builds.
 116         * configure.in:  Improve comment on how to run autoconf.
 117         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
 118         * Makefile.in:  Use autoconf substitution to install common
 119         makefile fragment.
 120
 121 Tue Jan 21 15:03:04 1997  Jeffrey A Law  (law@cygnus.com)
 122
 123         * simops.c: Undo last change to "rol" and "ror", original code
 124         was correct!
 125
 126 Thu Jan 16 11:28:14 1997  Jeffrey A Law  (law@cygnus.com)
 127
 128         * simops.c: Fix "rol" and "ror".
 129
 130 Wed Jan 15 06:45:58 1997  Jeffrey A Law  (law@cygnus.com)
 131
 132         * simops.c: Fix typo in last change.
 133
 134 Mon Jan 13 13:22:35 1997  Jeffrey A Law  (law@cygnus.com)
 135
 136         * simops.c: Use REG macros in few places not using them yet.
 137
 138 Mon Jan  6 16:21:19 1997  Jeffrey A Law  (law@cygnus.com)
 139
 140         * mn10300_sim.h (struct _state): Fix number of registers!
 141
 142 Tue Dec 31 16:20:41 1996  Jeffrey A Law  (law@cygnus.com)
 143
 144         * mn10300_sim.h (struct _state): Put all registers into a single
 145         array to make gdb implementation easier.
 146         (REG_*): Add definitions for all registers in the state array.
 147         (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
 148         * simops.c: Related changes.
 149
 150 Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
 151
 152         * interp.c (sim_resume): Handle 0xff as a single byte insn.
 153
 154         * simops.c: Fix overflow computation for "add" and "inc"
 155         instructions.
 156
 157 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
 158
 159         * simops.c: Handle "break" instruction.
 160
 161         * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
 162
 163 Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)
 164
 165         * gencode.c (write_opcodes): Also write out the format of the
 166         opcode.
 167         * mn10300_sim.h (simops): Add "format" field.
 168         * interp.c (sim_resume): Deal with endianness issues here.
 169
 170 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
 171
 172         * simops.c (REG0_4): Define.
 173         Use REG0_4 for indexed loads/stores.
 174
 175 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
 176
 177         * simops.c (REG0_16): Fix typo.
 178
 179 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
 180
 181         * simops.c: Call abort for any instruction that's not currently
 182         simulated.
 183
 184         * simops.c: Define accessor macros to extract register
 185         values from instructions.  Use them consistently.
 186
 187         * interp.c: Delete unused global variable "OP".
 188         (sim_resume): Remove unused variable "opcode".
 189         * simops.c: Fix some uninitialized variable problems, add
 190         parens to fix various -Wall warnings.
 191
 192         * gencode.c (write_header): Add "insn" and "extension" arguments
 193         to the OP_* declarations.
 194         (write_template): Similarly for function templates.
 195         * interp.c (insn, extension): Remove global variables.  Instead
 196         pass them as arguments to the OP_* functions.
 197         * mn10300_sim.h: Remove decls for "insn" and "extension".
 198         * simops.c (OP_*): Accept "insn" and "extension" as arguments
 199         instead of using globals.
 200
 201 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
 202
 203         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
 204
 205         * simops.c: Fix thinkos in last change to "inc dn".
 206
 207 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
 208
 209         * simops.c: "add imm,sp" does not effect the condition codes.
 210         "inc dn" does effect the condition codes.
 211
 212 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
 213
 214         * simops.c: Treat both operands as signed values for
 215         "div" instruction.
 216
 217         * simops.c: Fix simulation of division instructions.
 218         Fix typos/thinkos in several "cmp" and "sub" instructions.
 219
 220 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
 221
 222         * simops.c: Fix carry bit handling in "sub" and "cmp"
 223         instructions.
 224
 225         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
 226
 227 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
 228
 229         * simops.c: Fix overflow computation for many instructions.
 230
 231         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
 232
 233         * simops.c: Fix "mov am, dn".
 234
 235         * simops.c: Fix more bugs in "add imm,an" and
 236         "add imm,dn".
 237
 238 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
 239
 240         * simops.c: Fix bugs in "movm" and "add imm,an".
 241
 242         * simops.c: Don't lose the upper 24 bits of the return
 243         pointer in "call" and "calls" instructions.  Rough cut
 244         at emulated system calls.
 245
 246         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
 247
 248         * simops.c: Implement remaining 4 byte instructions.
 249
 250         * simops.c: Implement remaining 3 byte instructions.
 251
 252         * simops.c: Implement remaining 2 byte instructions.  Call
 253         abort for instructions we're not implementing now.
 254
 255 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
 256
 257         * simops.c: Implement lots of random instructions.
 258
 259         * simops.c: Implement "movm" and "bCC" insns.
 260
 261         * mn10300_sim.h (_state): Add another register (MDR).
 262         (REG_MDR): Define.
 263         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
 264         a few additional random insns.
 265
 266         * mn10300_sim.h (PSW_*): Define for CC status tracking.
 267         (REG_D0, REG_A0, REG_SP): Define.
 268         * simops.c: Implement "add", "addc" and a few other random
 269         instructions.
 270
 271         * gencode.c, interp.c: Snapshot current simulator code.
 272
 273 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 274
 275         * Makefile.in, config.in, configure, configure.in: New files.
 276         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 277