sim/mn10300/ChangeLog

   1 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
   2
   3         * configure configure.in Makefile.in:  Update to new configure
   4         scheme which is more compatible with WinGDB builds.
   5         * configure.in:  Improve comment on how to run autoconf.
   6         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
   7         * Makefile.in:  Use autoconf substitution to install common
   8         makefile fragment.
   9
  10 Tue Jan 21 15:03:04 1997  Jeffrey A Law  (law@cygnus.com)
  11
  12         * simops.c: Undo last change to "rol" and "ror", original code
  13         was correct!
  14
  15 Thu Jan 16 11:28:14 1997  Jeffrey A Law  (law@cygnus.com)
  16
  17         * simops.c: Fix "rol" and "ror".
  18
  19 Wed Jan 15 06:45:58 1997  Jeffrey A Law  (law@cygnus.com)
  20
  21         * simops.c: Fix typo in last change.
  22
  23 Mon Jan 13 13:22:35 1997  Jeffrey A Law  (law@cygnus.com)
  24
  25         * simops.c: Use REG macros in few places not using them yet.
  26
  27 Mon Jan  6 16:21:19 1997  Jeffrey A Law  (law@cygnus.com)
  28
  29         * mn10300_sim.h (struct _state): Fix number of registers!
  30
  31 Tue Dec 31 16:20:41 1996  Jeffrey A Law  (law@cygnus.com)
  32
  33         * mn10300_sim.h (struct _state): Put all registers into a single
  34         array to make gdb implementation easier.
  35         (REG_*): Add definitions for all registers in the state array.
  36         (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
  37         * simops.c: Related changes.
  38
  39 Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
  40
  41         * interp.c (sim_resume): Handle 0xff as a single byte insn.
  42
  43         * simops.c: Fix overflow computation for "add" and "inc"
  44         instructions.
  45
  46 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
  47
  48         * simops.c: Handle "break" instruction.
  49
  50         * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
  51
  52 Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)
  53
  54         * gencode.c (write_opcodes): Also write out the format of the
  55         opcode.
  56         * mn10300_sim.h (simops): Add "format" field.
  57         * interp.c (sim_resume): Deal with endianness issues here.
  58
  59 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
  60
  61         * simops.c (REG0_4): Define.
  62         Use REG0_4 for indexed loads/stores.
  63
  64 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
  65
  66         * simops.c (REG0_16): Fix typo.
  67
  68 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
  69
  70         * simops.c: Call abort for any instruction that's not currently
  71         simulated.
  72
  73         * simops.c: Define accessor macros to extract register
  74         values from instructions.  Use them consistently.
  75
  76         * interp.c: Delete unused global variable "OP".
  77         (sim_resume): Remove unused variable "opcode".
  78         * simops.c: Fix some uninitialized variable problems, add
  79         parens to fix various -Wall warnings.
  80
  81         * gencode.c (write_header): Add "insn" and "extension" arguments
  82         to the OP_* declarations.
  83         (write_template): Similarly for function templates.
  84         * interp.c (insn, extension): Remove global variables.  Instead
  85         pass them as arguments to the OP_* functions.
  86         * mn10300_sim.h: Remove decls for "insn" and "extension".
  87         * simops.c (OP_*): Accept "insn" and "extension" as arguments
  88         instead of using globals.
  89
  90 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
  91
  92         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
  93
  94         * simops.c: Fix thinkos in last change to "inc dn".
  95
  96 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
  97
  98         * simops.c: "add imm,sp" does not effect the condition codes.
  99         "inc dn" does effect the condition codes.
 100
 101 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
 102
 103         * simops.c: Treat both operands as signed values for
 104         "div" instruction.
 105
 106         * simops.c: Fix simulation of division instructions.
 107         Fix typos/thinkos in several "cmp" and "sub" instructions.
 108
 109 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
 110
 111         * simops.c: Fix carry bit handling in "sub" and "cmp"
 112         instructions.
 113
 114         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
 115
 116 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
 117
 118         * simops.c: Fix overflow computation for many instructions.
 119
 120         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
 121
 122         * simops.c: Fix "mov am, dn".
 123
 124         * simops.c: Fix more bugs in "add imm,an" and
 125         "add imm,dn".
 126
 127 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
 128
 129         * simops.c: Fix bugs in "movm" and "add imm,an".
 130
 131         * simops.c: Don't lose the upper 24 bits of the return
 132         pointer in "call" and "calls" instructions.  Rough cut
 133         at emulated system calls.
 134
 135         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
 136
 137         * simops.c: Implement remaining 4 byte instructions.
 138
 139         * simops.c: Implement remaining 3 byte instructions.
 140
 141         * simops.c: Implement remaining 2 byte instructions.  Call
 142         abort for instructions we're not implementing now.
 143
 144 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
 145
 146         * simops.c: Implement lots of random instructions.
 147
 148         * simops.c: Implement "movm" and "bCC" insns.
 149
 150         * mn10300_sim.h (_state): Add another register (MDR).
 151         (REG_MDR): Define.
 152         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
 153         a few additional random insns.
 154
 155         * mn10300_sim.h (PSW_*): Define for CC status tracking.
 156         (REG_D0, REG_A0, REG_SP): Define.
 157         * simops.c: Implement "add", "addc" and a few other random
 158         instructions.
 159
 160         * gencode.c, interp.c: Snapshot current simulator code.
 161
 162 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 163
 164         * Makefile.in, config.in, configure, configure.in: New files.
 165         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 166