sim/mn10300/ChangeLog

   1 Mon May 19 13:54:22 1997  Jeffrey A Law  (law@cygnus.com)
   2
   3         * interp.c (dispatch): Make this an inline function.
   4
   5         * simops.c (syscall): Use callback->write regardless of
   6         what file descriptor we're writing too.
   7
   8 Sun May 18 16:46:31 1997  Jeffrey A Law  (law@cygnus.com)
   9
  10         * interp.c (load_mem_big): Remove function.  It's now a macro
  11         defined elsewhere.
  12         (compare_simops): New function.
  13         (sim_open): Sort the Simops table before inserting entries
  14         into the hash table.
  15         * mn10300_sim.h: Remove unused #defines.
  16         (load_mem_big): Define.
  17
  18 Fri May 16 16:36:17 1997  Jeffrey A Law  (law@cygnus.com)
  19
  20         * interp.c (load_mem): If we get a load from an out of range
  21         address, abort.
  22         (store_mem): Likewise for stores.
  23         (max_mem): New variable.
  24
  25 Tue May  6 13:24:36 1997  Jeffrey A Law  (law@cygnus.com)
  26
  27         * mn10300_sim.h: Fix ordering of bits in the PSW.
  28
  29         * interp.c: Improve hashing routine to avoid long list
  30         traversals for common instructions.  Add HASH_STAT support.
  31         Rewrite opcode dispatch code using a big switch instead of
  32         cascaded if/else statements.  Avoid useless calls to load_mem.
  33
  34 Mon May  5 18:07:48 1997  Jeffrey A Law  (law@cygnus.com)
  35
  36         * mn10300_sim.h (struct _state): Add space for mdrq register.
  37         (REG_MDRQ): Define.
  38         * simops.c: Don't abort for trap.  Add support for the extended
  39         instructions, "getx", "putx", "mulq", "mulqu", "sat16", "sat24",
  40         and "bsch".
  41
  42 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
  43
  44         * configure: Regenerated to track ../common/aclocal.m4 changes.
  45
  46 Fri Apr 18 14:04:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  47
  48         * interp.c (sim_stop): Add stub function.
  49
  50 Thu Apr 17 03:26:59 1997  Doug Evans  <dje@canuck.cygnus.com>
  51
  52         * Makefile.in (SIM_OBJS): Add sim-load.o.
  53         * interp.c (sim_kind, myname): New static locals.
  54         (sim_open): Set sim_kind, myname.  Ignore -E arg.
  55         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
  56         load file into simulator.  Set start address from bfd.
  57         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
  58
  59 Wed Apr 16 19:30:44 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  60
  61         * simops.c (OP_F020): SYS_execv, SYS_time, SYS_times, SYS_utime
  62         only include if implemented by host.
  63         (OP_F020): Typecast arg passed to time function;
  64
  65 Mon Apr  7 23:57:49 1997  Jeffrey A Law  (law@cygnus.com)
  66
  67         * simops.c (syscall): Handle new mn10300 calling conventions.
  68
  69 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  70
  71         * configure: Regenerated to track ../common/aclocal.m4 changes.
  72         * config.in: Ditto.
  73
  74 Fri Apr  4 20:02:37 1997  Ian Lance Taylor  <ian@cygnus.com>
  75
  76         * Makefile.in: Change mn10300-opc.o to m10300-opc.o, to match
  77         corresponding change in opcodes directory.
  78
  79 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
  80
  81         * interp.c (sim_open): New arg `kind'.
  82
  83         * configure: Regenerated to track ../common/aclocal.m4 changes.
  84
  85 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
  86
  87         * configure: Regenerated to track ../common/aclocal.m4 changes.
  88
  89 Thu Mar 20 11:58:02 1997  Jeffrey A Law  (law@cygnus.com)
  90
  91         * simops.c: Fix register extraction for a two "movbu" variants.
  92         Somewhat simplify "sub" instructions.
  93         Correctly sign extend operands for "mul".  Put the correct
  94         half of the result in MDR for "mul" and "mulu".
  95         Implement remaining instructions.
  96         Tweak opcode for "syscall".
  97
  98 Tue Mar 18 14:21:21 1997  Jeffrey A Law  (law@cygnus.com)
  99
 100         * simops.c: Do syscall emulation in "syscall" instruction.  Add
 101         dummy "trap" instruction.
 102
 103 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
 104
 105         * configure: Regenerated to track ../common/aclocal.m4 changes.
 106
 107 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
 108
 109         * configure: Re-generate.
 110
 111 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
 112
 113         * configure: Regenerate to track ../common/aclocal.m4 changes.
 114
 115 Thu Mar 13 12:54:45 1997  Doug Evans  <dje@canuck.cygnus.com>
 116
 117         * interp.c (sim_open): New SIM_DESC result.  Argument is now
 118         in argv form.
 119         (other sim_*): New SIM_DESC argument.
 120
 121 Wed Mar 12 15:04:00 1997  Jeffrey A Law  (law@cygnus.com)
 122
 123         * simops.c: Fix carry bit computation for "add" instructions.
 124
 125         * simops.c: Fix typos in bset insns.  Fix arguments to store_mem
 126         for bset imm8,(d8,an) and bclr imm8,(d8,an).
 127
 128 Wed Mar  5 15:00:10 1997  Jeffrey A Law  (law@cygnus.com)
 129
 130         * simops.c: Fix register references when computing Z and N bits
 131         for lsr imm8,dn.
 132
 133 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
 134
 135         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
 136         COMMON_{PRE,POST}_CONFIG_FRAG instead.
 137         * configure.in: sinclude ../common/aclocal.m4.
 138         * configure: Regenerated.
 139
 140 Fri Jan 24 10:47:25 1997  Jeffrey A Law  (law@cygnus.com)
 141
 142         * interp.c (init_system): Allocate 2^19 bytes of space for the
 143         simulator.
 144
 145 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
 146
 147         * configure configure.in Makefile.in:  Update to new configure
 148         scheme which is more compatible with WinGDB builds.
 149         * configure.in:  Improve comment on how to run autoconf.
 150         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
 151         * Makefile.in:  Use autoconf substitution to install common
 152         makefile fragment.
 153
 154 Tue Jan 21 15:03:04 1997  Jeffrey A Law  (law@cygnus.com)
 155
 156         * simops.c: Undo last change to "rol" and "ror", original code
 157         was correct!
 158
 159 Thu Jan 16 11:28:14 1997  Jeffrey A Law  (law@cygnus.com)
 160
 161         * simops.c: Fix "rol" and "ror".
 162
 163 Wed Jan 15 06:45:58 1997  Jeffrey A Law  (law@cygnus.com)
 164
 165         * simops.c: Fix typo in last change.
 166
 167 Mon Jan 13 13:22:35 1997  Jeffrey A Law  (law@cygnus.com)
 168
 169         * simops.c: Use REG macros in few places not using them yet.
 170
 171 Mon Jan  6 16:21:19 1997  Jeffrey A Law  (law@cygnus.com)
 172
 173         * mn10300_sim.h (struct _state): Fix number of registers!
 174
 175 Tue Dec 31 16:20:41 1996  Jeffrey A Law  (law@cygnus.com)
 176
 177         * mn10300_sim.h (struct _state): Put all registers into a single
 178         array to make gdb implementation easier.
 179         (REG_*): Add definitions for all registers in the state array.
 180         (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
 181         * simops.c: Related changes.
 182
 183 Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
 184
 185         * interp.c (sim_resume): Handle 0xff as a single byte insn.
 186
 187         * simops.c: Fix overflow computation for "add" and "inc"
 188         instructions.
 189
 190 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
 191
 192         * simops.c: Handle "break" instruction.
 193
 194         * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
 195
 196 Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)
 197
 198         * gencode.c (write_opcodes): Also write out the format of the
 199         opcode.
 200         * mn10300_sim.h (simops): Add "format" field.
 201         * interp.c (sim_resume): Deal with endianness issues here.
 202
 203 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
 204
 205         * simops.c (REG0_4): Define.
 206         Use REG0_4 for indexed loads/stores.
 207
 208 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
 209
 210         * simops.c (REG0_16): Fix typo.
 211
 212 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
 213
 214         * simops.c: Call abort for any instruction that's not currently
 215         simulated.
 216
 217         * simops.c: Define accessor macros to extract register
 218         values from instructions.  Use them consistently.
 219
 220         * interp.c: Delete unused global variable "OP".
 221         (sim_resume): Remove unused variable "opcode".
 222         * simops.c: Fix some uninitialized variable problems, add
 223         parens to fix various -Wall warnings.
 224
 225         * gencode.c (write_header): Add "insn" and "extension" arguments
 226         to the OP_* declarations.
 227         (write_template): Similarly for function templates.
 228         * interp.c (insn, extension): Remove global variables.  Instead
 229         pass them as arguments to the OP_* functions.
 230         * mn10300_sim.h: Remove decls for "insn" and "extension".
 231         * simops.c (OP_*): Accept "insn" and "extension" as arguments
 232         instead of using globals.
 233
 234 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
 235
 236         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
 237
 238         * simops.c: Fix thinkos in last change to "inc dn".
 239
 240 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
 241
 242         * simops.c: "add imm,sp" does not effect the condition codes.
 243         "inc dn" does effect the condition codes.
 244
 245 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
 246
 247         * simops.c: Treat both operands as signed values for
 248         "div" instruction.
 249
 250         * simops.c: Fix simulation of division instructions.
 251         Fix typos/thinkos in several "cmp" and "sub" instructions.
 252
 253 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
 254
 255         * simops.c: Fix carry bit handling in "sub" and "cmp"
 256         instructions.
 257
 258         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
 259
 260 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
 261
 262         * simops.c: Fix overflow computation for many instructions.
 263
 264         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
 265
 266         * simops.c: Fix "mov am, dn".
 267
 268         * simops.c: Fix more bugs in "add imm,an" and
 269         "add imm,dn".
 270
 271 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
 272
 273         * simops.c: Fix bugs in "movm" and "add imm,an".
 274
 275         * simops.c: Don't lose the upper 24 bits of the return
 276         pointer in "call" and "calls" instructions.  Rough cut
 277         at emulated system calls.
 278
 279         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
 280
 281         * simops.c: Implement remaining 4 byte instructions.
 282
 283         * simops.c: Implement remaining 3 byte instructions.
 284
 285         * simops.c: Implement remaining 2 byte instructions.  Call
 286         abort for instructions we're not implementing now.
 287
 288 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
 289
 290         * simops.c: Implement lots of random instructions.
 291
 292         * simops.c: Implement "movm" and "bCC" insns.
 293
 294         * mn10300_sim.h (_state): Add another register (MDR).
 295         (REG_MDR): Define.
 296         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
 297         a few additional random insns.
 298
 299         * mn10300_sim.h (PSW_*): Define for CC status tracking.
 300         (REG_D0, REG_A0, REG_SP): Define.
 301         * simops.c: Implement "add", "addc" and a few other random
 302         instructions.
 303
 304         * gencode.c, interp.c: Snapshot current simulator code.
 305
 306 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 307
 308         * Makefile.in, config.in, configure, configure.in: New files.
 309         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 310