1 Thu Apr 17 03:26:59 1997 Doug Evans <dje@canuck.cygnus.com>
3 * Makefile.in (SIM_OBJS): Add sim-load.o.
4 * interp.c (sim_kind, myname): New static locals.
5 (sim_open): Set sim_kind, myname. Ignore -E arg.
6 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
7 load file into simulator. Set start address from bfd.
8 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
10 Wed Apr 16 19:30:44 1997 Andrew Cagney <cagney@b1.cygnus.com>
12 * simops.c (OP_F020): SYS_execv, SYS_time, SYS_times, SYS_utime
13 only include if implemented by host.
14 (OP_F020): Typecast arg passed to time function;
16 Mon Apr 7 23:57:49 1997 Jeffrey A Law (law@cygnus.com)
18 * simops.c (syscall): Handle new mn10300 calling conventions.
20 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
22 * configure: Regenerated to track ../common/aclocal.m4 changes.
25 Fri Apr 4 20:02:37 1997 Ian Lance Taylor <ian@cygnus.com>
27 * Makefile.in: Change mn10300-opc.o to m10300-opc.o, to match
28 corresponding change in opcodes directory.
30 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
32 * interp.c (sim_open): New arg `kind'.
34 * configure: Regenerated to track ../common/aclocal.m4 changes.
36 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
38 * configure: Regenerated to track ../common/aclocal.m4 changes.
40 Thu Mar 20 11:58:02 1997 Jeffrey A Law (law@cygnus.com)
42 * simops.c: Fix register extraction for a two "movbu" variants.
43 Somewhat simplify "sub" instructions.
44 Correctly sign extend operands for "mul". Put the correct
45 half of the result in MDR for "mul" and "mulu".
46 Implement remaining instructions.
47 Tweak opcode for "syscall".
49 Tue Mar 18 14:21:21 1997 Jeffrey A Law (law@cygnus.com)
51 * simops.c: Do syscall emulation in "syscall" instruction. Add
52 dummy "trap" instruction.
54 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
56 * configure: Regenerated to track ../common/aclocal.m4 changes.
58 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
60 * configure: Re-generate.
62 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
64 * configure: Regenerate to track ../common/aclocal.m4 changes.
66 Thu Mar 13 12:54:45 1997 Doug Evans <dje@canuck.cygnus.com>
68 * interp.c (sim_open): New SIM_DESC result. Argument is now
70 (other sim_*): New SIM_DESC argument.
72 Wed Mar 12 15:04:00 1997 Jeffrey A Law (law@cygnus.com)
74 * simops.c: Fix carry bit computation for "add" instructions.
76 * simops.c: Fix typos in bset insns. Fix arguments to store_mem
77 for bset imm8,(d8,an) and bclr imm8,(d8,an).
79 Wed Mar 5 15:00:10 1997 Jeffrey A Law (law@cygnus.com)
81 * simops.c: Fix register references when computing Z and N bits
84 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
86 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
87 COMMON_{PRE,POST}_CONFIG_FRAG instead.
88 * configure.in: sinclude ../common/aclocal.m4.
89 * configure: Regenerated.
91 Fri Jan 24 10:47:25 1997 Jeffrey A Law (law@cygnus.com)
93 * interp.c (init_system): Allocate 2^19 bytes of space for the
96 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
98 * configure configure.in Makefile.in: Update to new configure
99 scheme which is more compatible with WinGDB builds.
100 * configure.in: Improve comment on how to run autoconf.
101 * configure: Re-run autoconf to get new ../common/aclocal.m4.
102 * Makefile.in: Use autoconf substitution to install common
105 Tue Jan 21 15:03:04 1997 Jeffrey A Law (law@cygnus.com)
107 * simops.c: Undo last change to "rol" and "ror", original code
110 Thu Jan 16 11:28:14 1997 Jeffrey A Law (law@cygnus.com)
112 * simops.c: Fix "rol" and "ror".
114 Wed Jan 15 06:45:58 1997 Jeffrey A Law (law@cygnus.com)
116 * simops.c: Fix typo in last change.
118 Mon Jan 13 13:22:35 1997 Jeffrey A Law (law@cygnus.com)
120 * simops.c: Use REG macros in few places not using them yet.
122 Mon Jan 6 16:21:19 1997 Jeffrey A Law (law@cygnus.com)
124 * mn10300_sim.h (struct _state): Fix number of registers!
126 Tue Dec 31 16:20:41 1996 Jeffrey A Law (law@cygnus.com)
128 * mn10300_sim.h (struct _state): Put all registers into a single
129 array to make gdb implementation easier.
130 (REG_*): Add definitions for all registers in the state array.
131 (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
132 * simops.c: Related changes.
134 Wed Dec 18 10:10:45 1996 Jeffrey A Law (law@cygnus.com)
136 * interp.c (sim_resume): Handle 0xff as a single byte insn.
138 * simops.c: Fix overflow computation for "add" and "inc"
141 Mon Dec 16 10:03:52 1996 Jeffrey A Law (law@cygnus.com)
143 * simops.c: Handle "break" instruction.
145 * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
147 Wed Dec 11 09:53:10 1996 Jeffrey A Law (law@cygnus.com)
149 * gencode.c (write_opcodes): Also write out the format of the
151 * mn10300_sim.h (simops): Add "format" field.
152 * interp.c (sim_resume): Deal with endianness issues here.
154 Tue Dec 10 15:05:37 1996 Jeffrey A Law (law@cygnus.com)
156 * simops.c (REG0_4): Define.
157 Use REG0_4 for indexed loads/stores.
159 Sat Dec 7 09:50:28 1996 Jeffrey A Law (law@cygnus.com)
161 * simops.c (REG0_16): Fix typo.
163 Fri Dec 6 14:13:34 1996 Jeffrey A Law (law@cygnus.com)
165 * simops.c: Call abort for any instruction that's not currently
168 * simops.c: Define accessor macros to extract register
169 values from instructions. Use them consistently.
171 * interp.c: Delete unused global variable "OP".
172 (sim_resume): Remove unused variable "opcode".
173 * simops.c: Fix some uninitialized variable problems, add
174 parens to fix various -Wall warnings.
176 * gencode.c (write_header): Add "insn" and "extension" arguments
177 to the OP_* declarations.
178 (write_template): Similarly for function templates.
179 * interp.c (insn, extension): Remove global variables. Instead
180 pass them as arguments to the OP_* functions.
181 * mn10300_sim.h: Remove decls for "insn" and "extension".
182 * simops.c (OP_*): Accept "insn" and "extension" as arguments
183 instead of using globals.
185 Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com)
187 * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
189 * simops.c: Fix thinkos in last change to "inc dn".
191 Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com)
193 * simops.c: "add imm,sp" does not effect the condition codes.
194 "inc dn" does effect the condition codes.
196 Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com)
198 * simops.c: Treat both operands as signed values for
201 * simops.c: Fix simulation of division instructions.
202 Fix typos/thinkos in several "cmp" and "sub" instructions.
204 Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com)
206 * simops.c: Fix carry bit handling in "sub" and "cmp"
209 * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
211 Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com)
213 * simops.c: Fix overflow computation for many instructions.
215 * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
217 * simops.c: Fix "mov am, dn".
219 * simops.c: Fix more bugs in "add imm,an" and
222 Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
224 * simops.c: Fix bugs in "movm" and "add imm,an".
226 * simops.c: Don't lose the upper 24 bits of the return
227 pointer in "call" and "calls" instructions. Rough cut
228 at emulated system calls.
230 * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
232 * simops.c: Implement remaining 4 byte instructions.
234 * simops.c: Implement remaining 3 byte instructions.
236 * simops.c: Implement remaining 2 byte instructions. Call
237 abort for instructions we're not implementing now.
239 Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
241 * simops.c: Implement lots of random instructions.
243 * simops.c: Implement "movm" and "bCC" insns.
245 * mn10300_sim.h (_state): Add another register (MDR).
247 * simops.c: Implement "cmp", "calls", "rets", "jmp" and
248 a few additional random insns.
250 * mn10300_sim.h (PSW_*): Define for CC status tracking.
251 (REG_D0, REG_A0, REG_SP): Define.
252 * simops.c: Implement "add", "addc" and a few other random
255 * gencode.c, interp.c: Snapshot current simulator code.
257 Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com)
259 * Makefile.in, config.in, configure, configure.in: New files.
260 * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.