1 Fri Dec 6 14:13:34 1996 Jeffrey A Law (law@cygnus.com)
3 * interp.c: Delete unused global variable "OP".
4 (sim_resume): Remove unused variable "opcode".
5 * simops.c: Fix some uninitialized variable problems, add
6 parens to fix various -Wall warnings.
8 * gencode.c (write_header): Add "insn" and "extension" arguments
9 to the OP_* declarations.
10 (write_template): Similarly for function templates.
11 * interp.c (insn, extension): Remove global variables. Instead
12 pass them as arguments to the OP_* functions.
13 * mn10300_sim.h: Remove decls for "insn" and "extension".
14 * simops.c (OP_*): Accept "insn" and "extension" as arguments
15 instead of using globals.
17 Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com)
19 * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
21 * simops.c: Fix thinkos in last change to "inc dn".
23 Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com)
25 * simops.c: "add imm,sp" does not effect the condition codes.
26 "inc dn" does effect the condition codes.
28 Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com)
30 * simops.c: Treat both operands as signed values for
33 * simops.c: Fix simulation of division instructions.
34 Fix typos/thinkos in several "cmp" and "sub" instructions.
36 Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com)
38 * simops.c: Fix carry bit handling in "sub" and "cmp"
41 * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
43 Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com)
45 * simops.c: Fix overflow computation for many instructions.
47 * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
49 * simops.c: Fix "mov am, dn".
51 * simops.c: Fix more bugs in "add imm,an" and
54 Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
56 * simops.c: Fix bugs in "movm" and "add imm,an".
58 * simops.c: Don't lose the upper 24 bits of the return
59 pointer in "call" and "calls" instructions. Rough cut
60 at emulated system calls.
62 * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
64 * simops.c: Implement remaining 4 byte instructions.
66 * simops.c: Implement remaining 3 byte instructions.
68 * simops.c: Implement remaining 2 byte instructions. Call
69 abort for instructions we're not implementing now.
71 Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
73 * simops.c: Implement lots of random instructions.
75 * simops.c: Implement "movm" and "bCC" insns.
77 * mn10300_sim.h (_state): Add another register (MDR).
79 * simops.c: Implement "cmp", "calls", "rets", "jmp" and
80 a few additional random insns.
82 * mn10300_sim.h (PSW_*): Define for CC status tracking.
83 (REG_D0, REG_A0, REG_SP): Define.
84 * simops.c: Implement "add", "addc" and a few other random
87 * gencode.c, interp.c: Snapshot current simulator code.
89 Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com)
91 * Makefile.in, config.in, configure, configure.in: New files.
92 * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.