sim/mn10300/ChangeLog

   1 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * simops.c (REG0_4): Define.
   4         Use REG0_4 for indexed loads/stores.
   5
   6 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
   7
   8         * simops.c (REG0_16): Fix typo.
   9
  10 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
  11
  12         * simops.c: Call abort for any instruction that's not currently
  13         simulated.
  14
  15         * simops.c: Define accessor macros to extract register
  16         values from instructions.  Use them consistently.
  17
  18         * interp.c: Delete unused global variable "OP".
  19         (sim_resume): Remove unused variable "opcode".
  20         * simops.c: Fix some uninitialized variable problems, add
  21         parens to fix various -Wall warnings.
  22
  23         * gencode.c (write_header): Add "insn" and "extension" arguments
  24         to the OP_* declarations.
  25         (write_template): Similarly for function templates.
  26         * interp.c (insn, extension): Remove global variables.  Instead
  27         pass them as arguments to the OP_* functions.
  28         * mn10300_sim.h: Remove decls for "insn" and "extension".
  29         * simops.c (OP_*): Accept "insn" and "extension" as arguments
  30         instead of using globals.
  31
  32 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
  33
  34         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
  35
  36         * simops.c: Fix thinkos in last change to "inc dn".
  37
  38 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
  39
  40         * simops.c: "add imm,sp" does not effect the condition codes.
  41         "inc dn" does effect the condition codes.
  42
  43 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
  44
  45         * simops.c: Treat both operands as signed values for
  46         "div" instruction.
  47
  48         * simops.c: Fix simulation of division instructions.
  49         Fix typos/thinkos in several "cmp" and "sub" instructions.
  50
  51 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
  52
  53         * simops.c: Fix carry bit handling in "sub" and "cmp"
  54         instructions.
  55
  56         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
  57
  58 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
  59
  60         * simops.c: Fix overflow computation for many instructions.
  61
  62         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
  63
  64         * simops.c: Fix "mov am, dn".
  65
  66         * simops.c: Fix more bugs in "add imm,an" and
  67         "add imm,dn".
  68
  69 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
  70
  71         * simops.c: Fix bugs in "movm" and "add imm,an".
  72
  73         * simops.c: Don't lose the upper 24 bits of the return
  74         pointer in "call" and "calls" instructions.  Rough cut
  75         at emulated system calls.
  76
  77         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
  78
  79         * simops.c: Implement remaining 4 byte instructions.
  80
  81         * simops.c: Implement remaining 3 byte instructions.
  82
  83         * simops.c: Implement remaining 2 byte instructions.  Call
  84         abort for instructions we're not implementing now.
  85
  86 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
  87
  88         * simops.c: Implement lots of random instructions.
  89
  90         * simops.c: Implement "movm" and "bCC" insns.
  91
  92         * mn10300_sim.h (_state): Add another register (MDR).
  93         (REG_MDR): Define.
  94         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
  95         a few additional random insns.
  96
  97         * mn10300_sim.h (PSW_*): Define for CC status tracking.
  98         (REG_D0, REG_A0, REG_SP): Define.
  99         * simops.c: Implement "add", "addc" and a few other random
 100         instructions.
 101
 102         * gencode.c, interp.c: Snapshot current simulator code.
 103
 104 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 105
 106         * Makefile.in, config.in, configure, configure.in: New files.
 107         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 108