sim/mn10300/ChangeLog

   1 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
   2
   3         * configure: Regenerated to track ../common/aclocal.m4 changes.
   4
   5 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
   6
   7         * configure: Re-generate.
   8
   9 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
  10
  11         * configure: Regenerate to track ../common/aclocal.m4 changes.
  12
  13 Thu Mar 13 12:54:45 1997  Doug Evans  <dje@canuck.cygnus.com>
  14
  15         * interp.c (sim_open): New SIM_DESC result.  Argument is now
  16         in argv form.
  17         (other sim_*): New SIM_DESC argument.
  18
  19 Wed Mar 12 15:04:00 1997  Jeffrey A Law  (law@cygnus.com)
  20
  21         * simops.c: Fix carry bit computation for "add" instructions.
  22
  23         * simops.c: Fix typos in bset insns.  Fix arguments to store_mem
  24         for bset imm8,(d8,an) and bclr imm8,(d8,an).
  25
  26 Wed Mar  5 15:00:10 1997  Jeffrey A Law  (law@cygnus.com)
  27
  28         * simops.c: Fix register references when computing Z and N bits
  29         for lsr imm8,dn.
  30
  31 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
  32
  33         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
  34         COMMON_{PRE,POST}_CONFIG_FRAG instead.
  35         * configure.in: sinclude ../common/aclocal.m4.
  36         * configure: Regenerated.
  37
  38 Fri Jan 24 10:47:25 1997  Jeffrey A Law  (law@cygnus.com)
  39
  40         * interp.c (init_system): Allocate 2^19 bytes of space for the
  41         simulator.
  42
  43 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
  44
  45         * configure configure.in Makefile.in:  Update to new configure
  46         scheme which is more compatible with WinGDB builds.
  47         * configure.in:  Improve comment on how to run autoconf.
  48         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
  49         * Makefile.in:  Use autoconf substitution to install common
  50         makefile fragment.
  51
  52 Tue Jan 21 15:03:04 1997  Jeffrey A Law  (law@cygnus.com)
  53
  54         * simops.c: Undo last change to "rol" and "ror", original code
  55         was correct!
  56
  57 Thu Jan 16 11:28:14 1997  Jeffrey A Law  (law@cygnus.com)
  58
  59         * simops.c: Fix "rol" and "ror".
  60
  61 Wed Jan 15 06:45:58 1997  Jeffrey A Law  (law@cygnus.com)
  62
  63         * simops.c: Fix typo in last change.
  64
  65 Mon Jan 13 13:22:35 1997  Jeffrey A Law  (law@cygnus.com)
  66
  67         * simops.c: Use REG macros in few places not using them yet.
  68
  69 Mon Jan  6 16:21:19 1997  Jeffrey A Law  (law@cygnus.com)
  70
  71         * mn10300_sim.h (struct _state): Fix number of registers!
  72
  73 Tue Dec 31 16:20:41 1996  Jeffrey A Law  (law@cygnus.com)
  74
  75         * mn10300_sim.h (struct _state): Put all registers into a single
  76         array to make gdb implementation easier.
  77         (REG_*): Add definitions for all registers in the state array.
  78         (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
  79         * simops.c: Related changes.
  80
  81 Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
  82
  83         * interp.c (sim_resume): Handle 0xff as a single byte insn.
  84
  85         * simops.c: Fix overflow computation for "add" and "inc"
  86         instructions.
  87
  88 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
  89
  90         * simops.c: Handle "break" instruction.
  91
  92         * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
  93
  94 Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)
  95
  96         * gencode.c (write_opcodes): Also write out the format of the
  97         opcode.
  98         * mn10300_sim.h (simops): Add "format" field.
  99         * interp.c (sim_resume): Deal with endianness issues here.
 100
 101 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
 102
 103         * simops.c (REG0_4): Define.
 104         Use REG0_4 for indexed loads/stores.
 105
 106 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
 107
 108         * simops.c (REG0_16): Fix typo.
 109
 110 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
 111
 112         * simops.c: Call abort for any instruction that's not currently
 113         simulated.
 114
 115         * simops.c: Define accessor macros to extract register
 116         values from instructions.  Use them consistently.
 117
 118         * interp.c: Delete unused global variable "OP".
 119         (sim_resume): Remove unused variable "opcode".
 120         * simops.c: Fix some uninitialized variable problems, add
 121         parens to fix various -Wall warnings.
 122
 123         * gencode.c (write_header): Add "insn" and "extension" arguments
 124         to the OP_* declarations.
 125         (write_template): Similarly for function templates.
 126         * interp.c (insn, extension): Remove global variables.  Instead
 127         pass them as arguments to the OP_* functions.
 128         * mn10300_sim.h: Remove decls for "insn" and "extension".
 129         * simops.c (OP_*): Accept "insn" and "extension" as arguments
 130         instead of using globals.
 131
 132 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
 133
 134         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
 135
 136         * simops.c: Fix thinkos in last change to "inc dn".
 137
 138 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
 139
 140         * simops.c: "add imm,sp" does not effect the condition codes.
 141         "inc dn" does effect the condition codes.
 142
 143 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
 144
 145         * simops.c: Treat both operands as signed values for
 146         "div" instruction.
 147
 148         * simops.c: Fix simulation of division instructions.
 149         Fix typos/thinkos in several "cmp" and "sub" instructions.
 150
 151 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
 152
 153         * simops.c: Fix carry bit handling in "sub" and "cmp"
 154         instructions.
 155
 156         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
 157
 158 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
 159
 160         * simops.c: Fix overflow computation for many instructions.
 161
 162         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
 163
 164         * simops.c: Fix "mov am, dn".
 165
 166         * simops.c: Fix more bugs in "add imm,an" and
 167         "add imm,dn".
 168
 169 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
 170
 171         * simops.c: Fix bugs in "movm" and "add imm,an".
 172
 173         * simops.c: Don't lose the upper 24 bits of the return
 174         pointer in "call" and "calls" instructions.  Rough cut
 175         at emulated system calls.
 176
 177         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
 178
 179         * simops.c: Implement remaining 4 byte instructions.
 180
 181         * simops.c: Implement remaining 3 byte instructions.
 182
 183         * simops.c: Implement remaining 2 byte instructions.  Call
 184         abort for instructions we're not implementing now.
 185
 186 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
 187
 188         * simops.c: Implement lots of random instructions.
 189
 190         * simops.c: Implement "movm" and "bCC" insns.
 191
 192         * mn10300_sim.h (_state): Add another register (MDR).
 193         (REG_MDR): Define.
 194         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
 195         a few additional random insns.
 196
 197         * mn10300_sim.h (PSW_*): Define for CC status tracking.
 198         (REG_D0, REG_A0, REG_SP): Define.
 199         * simops.c: Implement "add", "addc" and a few other random
 200         instructions.
 201
 202         * gencode.c, interp.c: Snapshot current simulator code.
 203
 204 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 205
 206         * Makefile.in, config.in, configure, configure.in: New files.
 207         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 208