sim/mn10300/ChangeLog

   1 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * simops.c: Treat both operands as signed values for
   4         "div" instruction.
   5
   6         * simops.c: Fix simulation of division instructions.
   7         Fix typos/thinkos in several "cmp" and "sub" instructions.
   8
   9 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
  10
  11         * simops.c: Fix carry bit handling in "sub" and "cmp"
  12         instructions.
  13
  14         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
  15
  16 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
  17
  18         * simops.c: Fix overflow computation for many instructions.
  19
  20         * simops.c: Fix "movdm, an", "movbu dm, (an)", and "movhu dm, (an)".
  21
  22         * simops.c: Fix "mov am, dn".
  23
  24         * simops.c: Fix more bugs in "add imm,an" and
  25         "add imm,dn".
  26
  27 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
  28
  29         * simops.c: Fix bugs in "movm" and "add imm,an".
  30
  31         * simops.c: Don't lose the upper 24 bits of the return
  32         pointer in "call" and "calls" instructions.  Rough cut
  33         at emulated system calls.
  34
  35         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
  36
  37         * simops.c: Implement remaining 4 byte instructions.
  38
  39         * simops.c: Implement remaining 3 byte instructions.
  40
  41         * simops.c: Implement remaining 2 byte instructions.  Call
  42         abort for instructions we're not implementing now.
  43
  44 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
  45
  46         * simops.c: Implement lots of random instructions.
  47
  48         * simops.c: Implement "movm" and "bCC" insns.
  49
  50         * mn10300_sim.h (_state): Add another register (MDR).
  51         (REG_MDR): Define.
  52         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
  53         a few additional random insns.
  54
  55         * mn10300_sim.h (PSW_*): Define for CC status tracking.
  56         (REG_D0, REG_A0, REG_SP): Define.
  57         * simops.c: Implement "add", "addc" and a few other random
  58         instructions.
  59
  60         * gencode.c, interp.c: Snapshot current simulator code.
  61
  62 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
  63
  64         * Makefile.in, config.in, configure, configure.in: New files.
  65         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
  66