1 Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com)
3 * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
5 Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com)
7 * simops.c: Fix overflow computation for many instructions.
9 * simops.c: Fix "movdm, an", "movbu dm, (an)", and "movhu dm, (an)".
11 * simops.c: Fix "mov am, dn".
13 * simops.c: Fix more bugs in "add imm,an" and
16 Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
18 * simops.c: Fix bugs in "movm" and "add imm,an".
20 * simops.c: Don't lose the upper 24 bits of the return
21 pointer in "call" and "calls" instructions. Rough cut
22 at emulated system calls.
24 * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
26 * simops.c: Implement remaining 4 byte instructions.
28 * simops.c: Implement remaining 3 byte instructions.
30 * simops.c: Implement remaining 2 byte instructions. Call
31 abort for instructions we're not implementing now.
33 Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
35 * simops.c: Implement lots of random instructions.
37 * simops.c: Implement "movm" and "bCC" insns.
39 * mn10300_sim.h (_state): Add another register (MDR).
41 * simops.c: Implement "cmp", "calls", "rets", "jmp" and
42 a few additional random insns.
44 * mn10300_sim.h (PSW_*): Define for CC status tracking.
45 (REG_D0, REG_A0, REG_SP): Define.
46 * simops.c: Implement "add", "addc" and a few other random
49 * gencode.c, interp.c: Snapshot current simulator code.
51 Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com)
53 * Makefile.in, config.in, configure, configure.in: New files.
54 * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.