3 // Given an extended register number, translate it into an index into the
4 // register array. This is necessary as the upper 8 extended registers are
5 // actually synonyms for the d0-d3/a0-a3 registers.
9 :function:::int:translate_rreg:int rreg
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
22 // 1111 0000 0010 00An; mov USP,An
23 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
28 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
32 // 1111 0000 0010 01An; mov SSP,An
33 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
38 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
42 // 1111 0000 0010 10An; mov MSP,An
43 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
48 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
52 // 1111 0000 0010 11An; mov PC,An
53 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
58 State.regs[REG_A0 + AN0] = PC;
62 // 1111 0000 0011 Am00; mov Am,USP
63 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
68 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
71 // 1111 0000 0011 Am01; mov Am,SSP
72 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
77 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
80 // 1111 0000 0011 Am10; mov Am,MSP
81 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
86 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
90 // 1111 0000 1110 imm4; syscall
91 8.0xf0+4.0xe,IMM4:D0t:::syscall
95 unsigned int sp, next_pc;
98 sp = State.regs[REG_SP];
99 next_pc = State.regs[REG_PC] + 2;
100 store_word (sp - 4, next_pc);
101 store_word (sp - 8, PSW);
102 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
107 // 1111 0010 1110 11Dn; mov EPSW,Dn
108 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
113 State.regs[REG_D0 + DN0] = PSW;
117 // 1111 0010 1111 Dm01; mov Dm,EPSW
118 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
123 PSW = State.regs[REG_D0 + DM1];
126 // 1111 0101 00Am Rn; mov Am,Rn
127 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
131 int destreg = translate_rreg (SD_, RN0);
134 State.regs[destreg] = State.regs[REG_A0 + AM1];
137 // 1111 0101 01Dm Rn; mov Dm,Rn
138 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
142 int destreg = translate_rreg (SD_, RN0);
145 State.regs[destreg] = State.regs[REG_D0 + DM1];
148 // 1111 0101 10Rm An; mov Rm,An
149 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
153 int destreg = translate_rreg (SD_, RM1);
156 State.regs[REG_A0 + AN0] = State.regs[destreg];
159 // 1111 0101 11Rm Dn; mov Rm,Dn
160 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
164 int destreg = translate_rreg (SD_, RM1);
167 State.regs[REG_D0 + DN0] = State.regs[destreg];
171 // 1111 1000 1100 1110 regs....; movm (USP),regs
172 8.0xf8+8.0xce+8.REGS:D1a:::movm
176 unsigned long usp = State.regs[REG_USP];
185 State.regs[REG_LAR] = load_word (usp);
187 State.regs[REG_LIR] = load_word (usp);
189 State.regs[REG_MDR] = load_word (usp);
191 State.regs[REG_A0 + 1] = load_word (usp);
193 State.regs[REG_A0] = load_word (usp);
195 State.regs[REG_D0 + 1] = load_word (usp);
197 State.regs[REG_D0] = load_word (usp);
203 State.regs[REG_A0 + 3] = load_word (usp);
209 State.regs[REG_A0 + 2] = load_word (usp);
215 State.regs[REG_D0 + 3] = load_word (usp);
221 State.regs[REG_D0 + 2] = load_word (usp);
225 /* start-sanitize-am33 */
226 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
230 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
232 State.regs[REG_E0 + 1] = load_word (usp);
234 State.regs[REG_E0 + 0] = load_word (usp);
240 State.regs[REG_E0 + 7] = load_word (usp);
242 State.regs[REG_E0 + 6] = load_word (usp);
244 State.regs[REG_E0 + 5] = load_word (usp);
246 State.regs[REG_E0 + 4] = load_word (usp);
252 State.regs[REG_E0 + 3] = load_word (usp);
254 State.regs[REG_E0 + 2] = load_word (usp);
258 /* end-sanitize-am33 */
260 /* And make sure to update the stack pointer. */
261 State.regs[REG_USP] = usp;
264 // 1111 1000 1100 1111 regs....; movm (USP),regs
265 8.0xf8+8.0xcf+8.REGS:D1b:::movm
269 unsigned long usp = State.regs[REG_USP];
272 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
277 store_word (usp, State.regs[REG_E0 + 2]);
279 store_word (usp, State.regs[REG_E0 + 3]);
285 store_word (usp, State.regs[REG_E0 + 4]);
287 store_word (usp, State.regs[REG_E0 + 5]);
289 store_word (usp, State.regs[REG_E0 + 6]);
291 store_word (usp, State.regs[REG_E0 + 7]);
297 store_word (usp, State.regs[REG_E0 + 0]);
299 store_word (usp, State.regs[REG_E0 + 1]);
301 /* Need to save MDQR, MCRH, MCRL, and MCVF */
304 /* end-sanitize-am33 */
309 store_word (usp, State.regs[REG_D0 + 2]);
315 store_word (usp, State.regs[REG_D0 + 3]);
321 store_word (usp, State.regs[REG_A0 + 2]);
327 store_word (usp, State.regs[REG_A0 + 3]);
333 store_word (usp, State.regs[REG_D0]);
335 store_word (usp, State.regs[REG_D0 + 1]);
337 store_word (usp, State.regs[REG_A0]);
339 store_word (usp, State.regs[REG_A0 + 1]);
341 store_word (usp, State.regs[REG_MDR]);
343 store_word (usp, State.regs[REG_LIR]);
345 store_word (usp, State.regs[REG_LAR]);
349 /* And make sure to update the stack pointer. */
350 State.regs[REG_USP] = usp;
353 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
354 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
359 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
362 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
363 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
368 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
371 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
372 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
380 srcreg = translate_rreg (SD_, RM2);
381 dstreg = translate_rreg (SD_, RN0);
382 State.regs[dstreg] = State.regs[srcreg];
385 // 1111 1001 0001 1000 Rn Rn; ext Rn
386 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
393 srcreg = translate_rreg (SD_, RN0);
394 if (State.regs[srcreg] & 0x80000000)
395 State.regs[REG_MDR] = -1;
397 State.regs[REG_MDR] = 0;
400 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
401 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
408 srcreg = translate_rreg (SD_, RM2);
409 dstreg = translate_rreg (SD_, RN0);
410 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
413 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
414 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
421 srcreg = translate_rreg (SD_, RM2);
422 dstreg = translate_rreg (SD_, RN0);
423 State.regs[dstreg] = State.regs[srcreg] & 0xff;
426 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
427 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
434 srcreg = translate_rreg (SD_, RM2);
435 dstreg = translate_rreg (SD_, RN0);
436 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
439 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
440 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
447 srcreg = translate_rreg (SD_, RM2);
448 dstreg = translate_rreg (SD_, RN0);
449 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
452 // 1111 1001 0110 1000 Rn Rn; clr Rn
453 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
460 dstreg = translate_rreg (SD_, RN0);
461 State.regs[dstreg] = 0;
463 PSW &= ~(PSW_V | PSW_C | PSW_N);
466 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
467 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
474 srcreg = translate_rreg (SD_, RM2);
475 dstreg = translate_rreg (SD_, RN0);
476 genericAdd (State.regs[srcreg], dstreg);
479 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
480 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
486 unsigned long reg1, reg2, sum;
489 srcreg = translate_rreg (SD_, RM2);
490 dstreg = translate_rreg (SD_, RN0);
492 reg1 = State.regs[srcreg];
493 reg2 = State.regs[dstreg];
494 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
495 State.regs[dstreg] = sum;
497 z = ((PSW & PSW_Z) != 0) && (sum == 0);
498 n = (sum & 0x80000000);
499 c = (sum < reg1) || (sum < reg2);
500 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
501 && (reg2 & 0x80000000) != (sum & 0x80000000));
503 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
504 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
505 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
508 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
509 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
516 srcreg = translate_rreg (SD_, RM2);
517 dstreg = translate_rreg (SD_, RN0);
518 genericSub (State.regs[srcreg], dstreg);
521 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
522 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
528 unsigned long reg1, reg2, difference;
531 srcreg = translate_rreg (SD_, RM2);
532 dstreg = translate_rreg (SD_, RN0);
534 reg1 = State.regs[srcreg];
535 reg2 = State.regs[dstreg];
536 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
537 State.regs[dstreg] = difference;
539 z = ((PSW & PSW_Z) != 0) && (difference == 0);
540 n = (difference & 0x80000000);
542 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
543 && (reg2 & 0x80000000) != (difference & 0x80000000));
545 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
546 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
547 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
550 // 1111 1001 1011 1000 Rn Rn; inc Rn
551 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
558 dstreg = translate_rreg (SD_, RN0);
559 genericAdd (1, dstreg);
562 // 1111 1001 1101 1000 Rn Rn; inc Rn
563 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
570 dstreg = translate_rreg (SD_, RN0);
571 State.regs[dstreg] += 4;
574 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
575 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
579 int srcreg1, srcreg2;
582 srcreg1 = translate_rreg (SD_, RN0);
583 srcreg2 = translate_rreg (SD_, RM2);
584 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
587 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
588 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
595 dstreg = translate_rreg (SD_, RN0);
599 State.regs[dstreg] = State.regs[REG_SP];
605 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
606 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
613 srcreg = translate_rreg (SD_, RM2);
617 State.regs[REG_SP] = State.regs[srcreg];
623 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
624 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
633 srcreg = translate_rreg (SD_, RM2);
634 dstreg = translate_rreg (SD_, RN0);
636 State.regs[dstreg] &= State.regs[srcreg];
637 z = (State.regs[dstreg] == 0);
638 n = (State.regs[dstreg] & 0x80000000) != 0;
639 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
640 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
643 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
644 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
652 srcreg = translate_rreg (SD_, RM2);
653 dstreg = translate_rreg (SD_, RN0);
655 State.regs[dstreg] |= State.regs[srcreg];
656 z = (State.regs[dstreg] == 0);
657 n = (State.regs[dstreg] & 0x80000000) != 0;
658 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
659 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
662 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
663 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
671 srcreg = translate_rreg (SD_, RM2);
672 dstreg = translate_rreg (SD_, RN0);
674 State.regs[dstreg] ^= State.regs[srcreg];
675 z = (State.regs[dstreg] == 0);
676 n = (State.regs[dstreg] & 0x80000000) != 0;
677 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
678 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
681 // 1111 1001 0011 1001 Rn Rn; not Rn
682 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
690 dstreg = translate_rreg (SD_, RN0);
692 State.regs[dstreg] = ~State.regs[dstreg];
693 z = (State.regs[dstreg] == 0);
694 n = (State.regs[dstreg] & 0x80000000) != 0;
695 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
696 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
699 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
700 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
709 srcreg = translate_rreg (SD_, RM2);
710 dstreg = translate_rreg (SD_, RN0);
712 temp = State.regs[dstreg];
714 temp >>= State.regs[srcreg];
715 State.regs[dstreg] = temp;
716 z = (State.regs[dstreg] == 0);
717 n = (State.regs[dstreg] & 0x80000000) != 0;
718 PSW &= ~(PSW_Z | PSW_N | PSW_C);
719 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
722 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
723 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
732 srcreg = translate_rreg (SD_, RM2);
733 dstreg = translate_rreg (SD_, RN0);
735 c = State.regs[dstreg] & 1;
736 State.regs[dstreg] >>= State.regs[srcreg];
737 z = (State.regs[dstreg] == 0);
738 n = (State.regs[dstreg] & 0x80000000) != 0;
739 PSW &= ~(PSW_Z | PSW_N | PSW_C);
740 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
743 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
744 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
752 srcreg = translate_rreg (SD_, RM2);
753 dstreg = translate_rreg (SD_, RN0);
755 State.regs[dstreg] <<= State.regs[srcreg];
756 z = (State.regs[dstreg] == 0);
757 n = (State.regs[dstreg] & 0x80000000) != 0;
758 PSW &= ~(PSW_Z | PSW_N);
759 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
762 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
763 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
771 dstreg = translate_rreg (SD_, RN0);
773 State.regs[dstreg] <<= 2;
774 z = (State.regs[dstreg] == 0);
775 n = (State.regs[dstreg] & 0x80000000) != 0;
776 PSW &= ~(PSW_Z | PSW_N);
777 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
780 // 1111 1001 1000 1001 Rn Rn; ror Rn
781 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
790 dstreg = translate_rreg (SD_, RN0);
792 value = State.regs[dstreg];
796 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
797 State.regs[dstreg] = value;
799 n = (value & 0x80000000) != 0;
800 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
801 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
804 // 1111 1001 1001 1001 Rn Rn; rol Rn
805 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
814 dstreg = translate_rreg (SD_, RN0);
816 value = State.regs[dstreg];
817 c = (value & 0x80000000) ? 1 : 0;
820 value |= ((PSW & PSW_C) != 0);
821 State.regs[dstreg] = value;
823 n = (value & 0x80000000) != 0;
824 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
825 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
828 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
829 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
834 unsigned long long temp;
838 srcreg = translate_rreg (SD_, RM2);
839 dstreg = translate_rreg (SD_, RN0);
841 temp = ((signed64)(signed32)State.regs[dstreg]
842 * (signed64)(signed32)State.regs[srcreg]);
843 State.regs[dstreg] = temp & 0xffffffff;
844 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
845 z = (State.regs[dstreg] == 0);
846 n = (State.regs[dstreg] & 0x80000000) != 0;
847 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
848 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
851 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
852 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
857 unsigned long long temp;
861 srcreg = translate_rreg (SD_, RM2);
862 dstreg = translate_rreg (SD_, RN0);
864 temp = ((unsigned64)State.regs[dstreg]
865 * (unsigned64)State.regs[srcreg]);
866 State.regs[dstreg] = temp & 0xffffffff;
867 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
868 z = (State.regs[dstreg] == 0);
869 n = (State.regs[dstreg] & 0x80000000) != 0;
870 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
871 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
874 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
875 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
884 srcreg = translate_rreg (SD_, RM2);
885 dstreg = translate_rreg (SD_, RN0);
887 temp = State.regs[REG_MDR];
889 temp |= State.regs[dstreg];
890 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
891 temp /= (signed32)State.regs[srcreg];
892 State.regs[dstreg] = temp & 0xffffffff;
893 z = (State.regs[dstreg] == 0);
894 n = (State.regs[dstreg] & 0x80000000) != 0;
895 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
896 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
899 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
900 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
905 unsigned long long temp;
909 srcreg = translate_rreg (SD_, RM2);
910 dstreg = translate_rreg (SD_, RN0);
912 temp = State.regs[REG_MDR];
914 temp |= State.regs[dstreg];
915 State.regs[REG_MDR] = temp % State.regs[srcreg];
916 temp /= State.regs[srcreg];
917 State.regs[dstreg] = temp & 0xffffffff;
918 z = (State.regs[dstreg] == 0);
919 n = (State.regs[dstreg] & 0x80000000) != 0;
920 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
921 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
925 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
926 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
933 srcreg = translate_rreg (SD_, RM0);
934 dstreg = translate_rreg (SD_, RN2);
935 State.regs[dstreg] = load_word (State.regs[srcreg]);
938 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
939 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
946 srcreg = translate_rreg (SD_, RM2);
947 dstreg = translate_rreg (SD_, RN0);
948 store_word (State.regs[dstreg], State.regs[srcreg]);
951 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
952 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
959 srcreg = translate_rreg (SD_, RM0);
960 dstreg = translate_rreg (SD_, RN2);
961 State.regs[dstreg] = load_byte (State.regs[srcreg]);
964 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
965 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
972 srcreg = translate_rreg (SD_, RM2);
973 dstreg = translate_rreg (SD_, RN0);
974 store_byte (State.regs[dstreg], State.regs[srcreg]);
977 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
978 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
985 srcreg = translate_rreg (SD_, RM0);
986 dstreg = translate_rreg (SD_, RN2);
987 State.regs[dstreg] = load_half (State.regs[srcreg]);
990 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
991 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
998 srcreg = translate_rreg (SD_, RM2);
999 dstreg = translate_rreg (SD_, RN0);
1000 store_half (State.regs[dstreg], State.regs[srcreg]);
1003 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1004 8.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
1011 srcreg = translate_rreg (SD_, RM0);
1012 dstreg = translate_rreg (SD_, RN2);
1013 State.regs[dstreg] = load_word (State.regs[srcreg]);
1014 State.regs[srcreg] += 4;
1017 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1018 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1025 srcreg = translate_rreg (SD_, RM2);
1026 dstreg = translate_rreg (SD_, RN0);
1027 store_word (State.regs[dstreg], State.regs[srcreg]);
1028 State.regs[dstreg] += 4;
1031 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1032 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1039 dstreg = translate_rreg (SD_, RN2);
1040 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1043 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1044 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1051 srcreg = translate_rreg (SD_, RM2);
1052 store_word (State.regs[REG_SP], State.regs[srcreg]);
1055 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1056 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1063 dstreg = translate_rreg (SD_, RN2);
1064 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1067 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1068 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1075 srcreg = translate_rreg (SD_, RM2);
1076 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1079 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1080 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1087 dstreg = translate_rreg (SD_, RN2);
1088 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1091 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1092 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1099 srcreg = translate_rreg (SD_, RM2);
1100 store_half (State.regs[REG_SP], State.regs[srcreg]);
1103 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1104 8.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
1111 srcreg = translate_rreg (SD_, RM0);
1112 dstreg = translate_rreg (SD_, RN2);
1113 State.regs[dstreg] = load_half (State.regs[srcreg]);
1114 State.regs[srcreg] += 2;
1117 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1118 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1125 srcreg = translate_rreg (SD_, RM2);
1126 dstreg = translate_rreg (SD_, RN0);
1127 store_half (State.regs[dstreg], State.regs[srcreg]);
1128 State.regs[dstreg] += 2;
1132 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1133 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1137 int srcreg1, srcreg2;
1138 long long temp, sum;
1142 srcreg1 = translate_rreg (SD_, RM2);
1143 srcreg2 = translate_rreg (SD_, RN0);
1145 temp = ((signed64)(signed32)State.regs[srcreg2]
1146 * (signed64)(signed32)State.regs[srcreg1]);
1147 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1148 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1149 State.regs[REG_MCRL] = sum;
1152 sum = State.regs[REG_MCRH] + temp + c;
1153 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1154 && (temp & 0x80000000) != (sum & 0x80000000));
1155 State.regs[REG_MCRH] = sum;
1157 State.regs[REG_MCVF] = 1;
1160 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1161 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1165 int srcreg1, srcreg2;
1166 unsigned long long temp, sum;
1170 srcreg1 = translate_rreg (SD_, RM2);
1171 srcreg2 = translate_rreg (SD_, RN0);
1173 temp = ((unsigned64)State.regs[srcreg2]
1174 * (unsigned64)State.regs[srcreg1]);
1175 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1176 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1177 State.regs[REG_MCRL] = sum;
1180 sum = State.regs[REG_MCRH] + temp + c;
1181 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1182 && (temp & 0x80000000) != (sum & 0x80000000));
1183 State.regs[REG_MCRH] = sum;
1185 State.regs[REG_MCVF] = 1;
1188 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1189 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1193 int srcreg1, srcreg2;
1198 srcreg1 = translate_rreg (SD_, RM2);
1199 srcreg2 = translate_rreg (SD_, RN0);
1201 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1202 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
1203 sum = State.regs[REG_MCRL] + temp;
1204 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1205 && (temp & 0x80000000) != (sum & 0x80000000));
1206 State.regs[REG_MCRL] = sum;
1208 State.regs[REG_MCVF] = 1;
1211 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1212 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1216 int srcreg1, srcreg2;
1217 long long temp, sum;
1221 srcreg1 = translate_rreg (SD_, RM2);
1222 srcreg2 = translate_rreg (SD_, RN0);
1224 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1225 * (unsigned32)(State.regs[srcreg1] & 0xff));
1226 sum = State.regs[REG_MCRL] + temp;
1227 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1228 && (temp & 0x80000000) != (sum & 0x80000000));
1229 State.regs[REG_MCRL] = sum;
1231 State.regs[REG_MCVF] = 1;
1234 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1235 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1239 int srcreg1, srcreg2;
1240 long long temp, sum;
1244 srcreg1 = translate_rreg (SD_, RM2);
1245 srcreg2 = translate_rreg (SD_, RN0);
1247 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1248 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
1249 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1250 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1251 State.regs[REG_MCRL] = sum;
1254 sum = State.regs[REG_MCRH] + temp + c;
1255 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1256 && (temp & 0x80000000) != (sum & 0x80000000));
1257 State.regs[REG_MCRH] = sum;
1259 State.regs[REG_MCVF] = 1;
1262 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1263 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1267 int srcreg1, srcreg2;
1268 long long temp, sum;
1272 srcreg1 = translate_rreg (SD_, RM2);
1273 srcreg2 = translate_rreg (SD_, RN0);
1275 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1276 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1277 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1278 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1279 State.regs[REG_MCRL] = sum;
1282 sum = State.regs[REG_MCRH] + temp + c;
1283 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1284 && (temp & 0x80000000) != (sum & 0x80000000));
1285 State.regs[REG_MCRH] = sum;
1287 State.regs[REG_MCVF] = 1;
1290 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1291 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1295 int srcreg1, srcreg2;
1296 long temp, temp2, sum;
1300 srcreg1 = translate_rreg (SD_, RM2);
1301 srcreg2 = translate_rreg (SD_, RN0);
1303 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1304 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1305 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1306 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
1307 sum = temp + temp2 + State.regs[REG_MCRL];
1308 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1309 && (temp & 0x80000000) != (sum & 0x80000000));
1310 State.regs[REG_MCRL] = sum;
1312 State.regs[REG_MCVF] = 1;
1315 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1316 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1320 int srcreg1, srcreg2;
1321 unsigned long temp, temp2, sum;
1325 srcreg1 = translate_rreg (SD_, RM2);
1326 srcreg2 = translate_rreg (SD_, RN0);
1328 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1329 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1330 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1331 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1332 sum = temp + temp2 + State.regs[REG_MCRL];
1333 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1334 && (temp & 0x80000000) != (sum & 0x80000000));
1335 State.regs[REG_MCRL] = sum;
1337 State.regs[REG_MCVF] = 1;
1340 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1341 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1349 srcreg = translate_rreg (SD_, RM2);
1350 dstreg = translate_rreg (SD_, RN0);
1352 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1353 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
1354 State.regs[REG_MDRQ] = temp;
1355 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1356 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
1357 State.regs[dstreg] = temp;
1360 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1361 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1369 srcreg = translate_rreg (SD_, RM2);
1370 dstreg = translate_rreg (SD_, RN0);
1372 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1373 * (unsigned32)(State.regs[srcreg] & 0xffff));
1374 State.regs[REG_MDRQ] = temp;
1375 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1376 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1377 State.regs[dstreg] = temp;
1380 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1381 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1389 srcreg = translate_rreg (SD_, RM2);
1390 dstreg = translate_rreg (SD_, RN0);
1392 value = State.regs[srcreg];
1394 if (value >= 0x7fff)
1395 State.regs[dstreg] = 0x7fff;
1396 else if (value <= 0xffff8000)
1397 State.regs[dstreg] = 0xffff8000;
1399 State.regs[dstreg] = value;
1401 n = (State.regs[dstreg] & 0x8000) != 0;
1402 z = (State.regs[dstreg] == 0);
1403 PSW &= ~(PSW_Z | PSW_N);
1404 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1407 // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
1408 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1415 srcreg = translate_rreg (SD_, RM2);
1416 dstreg = translate_rreg (SD_, RN0);
1418 PSW &= ~(PSW_V | PSW_C);
1419 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1421 /* 32bit saturation. */
1422 if (State.regs[srcreg] == 0x20)
1426 tmp = State.regs[REG_MCRH];
1428 tmp += State.regs[REG_MCRL];
1430 if (tmp > 0x7fffffff)
1431 State.regs[dstreg] = 0x7fffffff;
1432 else if (tmp < 0xffffffff80000000LL)
1433 State.regs[dstreg] = 0x80000000;
1435 State.regs[dstreg] = tmp;
1437 /* 16bit saturation */
1438 else if (State.regs[srcreg] == 0x10)
1442 tmp = State.regs[REG_MCRH];
1444 tmp += State.regs[REG_MCRL];
1447 State.regs[dstreg] = 0x7fff;
1448 else if (tmp < 0xffffffffffff8000LL)
1449 State.regs[dstreg] = 0x8000;
1451 State.regs[dstreg] = tmp;
1453 /* 8 bit saturation */
1454 else if (State.regs[srcreg] == 0x8)
1458 tmp = State.regs[REG_MCRH];
1460 tmp += State.regs[REG_MCRL];
1463 State.regs[dstreg] = 0x7f;
1464 else if (tmp < 0xffffffffffffff80LL)
1465 State.regs[dstreg] = 0x80;
1467 State.regs[dstreg] = tmp;
1469 /* 9 bit saturation */
1470 else if (State.regs[srcreg] == 0x9)
1474 tmp = State.regs[REG_MCRH];
1476 tmp += State.regs[REG_MCRL];
1479 State.regs[dstreg] = 0x80;
1480 else if (tmp < 0xffffffffffffff81LL)
1481 State.regs[dstreg] = 0x81;
1483 State.regs[dstreg] = tmp;
1485 /* 9 bit saturation */
1486 else if (State.regs[srcreg] == 0x30)
1490 tmp = State.regs[REG_MCRH];
1492 tmp += State.regs[REG_MCRL];
1494 if (tmp > 0x7fffffffffffLL)
1495 tmp = 0x7fffffffffffLL;
1496 else if (tmp < 0xffff800000000000LL)
1497 tmp = 0xffff800000000000LL;
1500 State.regs[dstreg] = tmp;
1504 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1505 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1512 srcreg = translate_rreg (SD_, RM2);
1513 dstreg = translate_rreg (SD_, RN0);
1515 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1516 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1517 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1518 | ((State.regs[srcreg] >> 24) & 0xff));
1521 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1522 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1529 srcreg = translate_rreg (SD_, RM2);
1530 dstreg = translate_rreg (SD_, RN0);
1532 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1533 | ((State.regs[srcreg] >> 8) & 0xff)
1534 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1535 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1538 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1539 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1546 srcreg = translate_rreg (SD_, RM2);
1547 dstreg = translate_rreg (SD_, RN0);
1549 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1550 | ((State.regs[srcreg] >> 16) & 0xffff));
1553 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1554 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1563 srcreg = translate_rreg (SD_, RM2);
1564 dstreg = translate_rreg (SD_, RN0);
1566 temp = State.regs[srcreg];
1567 start = (State.regs[dstreg] & 0x1f) - 1;
1571 for (i = start; i >= 0; i--)
1573 if (temp & (1 << i))
1576 State.regs[dstreg] = i;
1584 State.regs[dstreg] = 0;
1587 PSW |= (c ? PSW_C : 0);
1591 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1592 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1599 dstreg = translate_rreg (SD_, RN0);
1600 State.regs[dstreg] = EXTEND8 (IMM8);
1603 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1604 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1611 dstreg = translate_rreg (SD_, RN0);
1612 State.regs[dstreg] = IMM8 & 0xff;
1615 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1616 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1623 dstreg = translate_rreg (SD_, RN0);
1624 genericAdd (EXTEND8 (IMM8), dstreg);
1627 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1628 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1634 unsigned long reg1, reg2, sum;
1637 dstreg = translate_rreg (SD_, RN0);
1639 imm = EXTEND8 (IMM8);
1640 reg2 = State.regs[dstreg];
1641 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1642 State.regs[dstreg] = sum;
1644 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1645 n = (sum & 0x80000000);
1646 c = (sum < imm) || (sum < reg2);
1647 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1648 && (reg2 & 0x80000000) != (sum & 0x80000000));
1650 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1651 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1652 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1655 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1656 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1663 dstreg = translate_rreg (SD_, RN0);
1665 genericSub (EXTEND8 (IMM8), dstreg);
1668 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1669 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1675 unsigned long reg1, reg2, difference;
1678 dstreg = translate_rreg (SD_, RN0);
1680 imm = EXTEND8 (IMM8);
1681 reg2 = State.regs[dstreg];
1682 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1683 State.regs[dstreg] = difference;
1685 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1686 n = (difference & 0x80000000);
1688 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1689 && (reg2 & 0x80000000) != (difference & 0x80000000));
1691 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1692 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1693 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1696 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1697 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1704 srcreg = translate_rreg (SD_, RN0);
1705 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1708 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1709 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1718 State.regs[REG_SP] = IMM8;
1723 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1724 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1732 dstreg = translate_rreg (SD_, RN0);
1734 State.regs[dstreg] &= (IMM8 & 0xff);
1735 z = (State.regs[dstreg] == 0);
1736 n = (State.regs[dstreg] & 0x80000000) != 0;
1737 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1738 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1741 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1742 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1750 dstreg = translate_rreg (SD_, RN0);
1752 State.regs[dstreg] |= (IMM8 & 0xff);
1753 z = (State.regs[dstreg] == 0);
1754 n = (State.regs[dstreg] & 0x80000000) != 0;
1755 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1756 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1759 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1760 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1768 dstreg = translate_rreg (SD_, RN0);
1770 State.regs[dstreg] ^= (IMM8 & 0xff);
1771 z = (State.regs[dstreg] == 0);
1772 n = (State.regs[dstreg] & 0x80000000) != 0;
1773 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1774 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1777 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1778 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1787 dstreg = translate_rreg (SD_, RN0);
1789 temp = State.regs[dstreg];
1791 temp >>= (IMM8 & 0xff);
1792 State.regs[dstreg] = temp;
1793 z = (State.regs[dstreg] == 0);
1794 n = (State.regs[dstreg] & 0x80000000) != 0;
1795 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1796 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1799 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1800 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1808 dstreg = translate_rreg (SD_, RN0);
1810 c = State.regs[dstreg] & 1;
1811 State.regs[dstreg] >>= (IMM8 & 0xff);
1812 z = (State.regs[dstreg] == 0);
1813 n = (State.regs[dstreg] & 0x80000000) != 0;
1814 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1815 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1818 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1819 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1827 dstreg = translate_rreg (SD_, RN0);
1829 State.regs[dstreg] <<= (IMM8 & 0xff);
1830 z = (State.regs[dstreg] == 0);
1831 n = (State.regs[dstreg] & 0x80000000) != 0;
1832 PSW &= ~(PSW_Z | PSW_N);
1833 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1836 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1837 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1842 unsigned long long temp;
1846 dstreg = translate_rreg (SD_, RN0);
1848 temp = ((signed64)(signed32)State.regs[dstreg]
1849 * (signed64)(signed32)EXTEND8 (IMM8));
1850 State.regs[dstreg] = temp & 0xffffffff;
1851 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1852 z = (State.regs[dstreg] == 0);
1853 n = (State.regs[dstreg] & 0x80000000) != 0;
1854 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1855 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1858 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1859 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1864 unsigned long long temp;
1868 dstreg = translate_rreg (SD_, RN0);
1870 temp = ((unsigned64)State.regs[dstreg]
1871 * (unsigned64)(IMM8 & 0xff));
1872 State.regs[dstreg] = temp & 0xffffffff;
1873 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1874 z = (State.regs[dstreg] == 0);
1875 n = (State.regs[dstreg] & 0x80000000) != 0;
1876 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1877 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1880 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1881 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1888 srcreg = translate_rreg (SD_, RM0);
1889 genericBtst(IMM8, State.regs[srcreg]);
1892 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1893 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1900 srcreg = translate_rreg (SD_, RM0);
1901 dstreg = translate_rreg (SD_, RN2);
1902 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1905 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1906 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1912 srcreg = translate_rreg (SD_, RM2);
1913 dstreg = translate_rreg (SD_, RN0);
1914 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1917 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1918 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1924 srcreg = translate_rreg (SD_, RM0);
1925 dstreg = translate_rreg (SD_, RN2);
1926 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1929 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1930 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1936 srcreg = translate_rreg (SD_, RM2);
1937 dstreg = translate_rreg (SD_, RN0);
1938 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1941 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1942 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1948 srcreg = translate_rreg (SD_, RM0);
1949 dstreg = translate_rreg (SD_, RN2);
1950 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1953 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1954 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1960 srcreg = translate_rreg (SD_, RM2);
1961 dstreg = translate_rreg (SD_, RN0);
1962 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1965 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1966 8.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
1973 srcreg = translate_rreg (SD_, RM0);
1974 dstreg = translate_rreg (SD_, RN2);
1975 State.regs[dstreg] = load_word (State.regs[srcreg]);
1976 State.regs[srcreg] += EXTEND8 (IMM8);
1979 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1980 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1986 srcreg = translate_rreg (SD_, RM2);
1987 dstreg = translate_rreg (SD_, RN0);
1988 store_word (State.regs[dstreg], State.regs[srcreg]);
1989 State.regs[dstreg] += EXTEND8 (IMM8);
1993 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
1994 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2000 dstreg = translate_rreg (SD_, RN2);
2001 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2004 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2005 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2011 srcreg = translate_rreg (SD_, RM2);
2012 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2015 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2016 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2022 dstreg = translate_rreg (SD_, RN2);
2023 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2026 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2027 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2033 srcreg = translate_rreg (SD_, RM2);
2034 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2037 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2038 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2044 dstreg = translate_rreg (SD_, RN2);
2045 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2048 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2049 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2055 srcreg = translate_rreg (SD_, RM2);
2056 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2059 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2060 8.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
2067 srcreg = translate_rreg (SD_, RM0);
2068 dstreg = translate_rreg (SD_, RN2);
2069 State.regs[dstreg] = load_half (State.regs[srcreg]);
2070 State.regs[srcreg] += EXTEND8 (IMM8);
2073 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2074 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2080 srcreg = translate_rreg (SD_, RM2);
2081 dstreg = translate_rreg (SD_, RN0);
2082 store_half (State.regs[dstreg], State.regs[srcreg]);
2083 State.regs[dstreg] += EXTEND8 (IMM8);
2087 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2088 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2092 long long temp, sum;
2096 srcreg = translate_rreg (SD_, RN2);
2098 temp = ((signed64)(signed32)EXTEND8 (IMM8)
2099 * (signed64)(signed32)State.regs[srcreg]);
2100 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2101 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2102 State.regs[REG_MCRL] = sum;
2105 sum = State.regs[REG_MCRH] + temp + c;
2106 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2107 && (temp & 0x80000000) != (sum & 0x80000000));
2108 State.regs[REG_MCRH] = sum;
2110 State.regs[REG_MCVF] = 1;
2113 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2114 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2118 long long temp, sum;
2122 srcreg = translate_rreg (SD_, RN2);
2124 temp = ((unsigned64) (IMM8)
2125 * (unsigned64)State.regs[srcreg]);
2126 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2127 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2128 State.regs[REG_MCRL] = sum;
2131 sum = State.regs[REG_MCRH] + temp + c;
2132 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2133 && (temp & 0x80000000) != (sum & 0x80000000));
2134 State.regs[REG_MCRH] = sum;
2136 State.regs[REG_MCVF] = 1;
2139 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2140 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2144 long long temp, sum;
2148 srcreg = translate_rreg (SD_, RN2);
2150 temp = ((signed64)(signed8)EXTEND8 (IMM8)
2151 * (signed64)(signed8)State.regs[srcreg] & 0xff);
2152 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2153 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2154 State.regs[REG_MCRL] = sum;
2157 sum = State.regs[REG_MCRH] + temp + c;
2158 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2159 && (temp & 0x80000000) != (sum & 0x80000000));
2160 State.regs[REG_MCRH] = sum;
2162 State.regs[REG_MCVF] = 1;
2165 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2166 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2170 long long temp, sum;
2174 srcreg = translate_rreg (SD_, RN2);
2176 temp = ((unsigned64) (IMM8)
2177 * (unsigned64)State.regs[srcreg] & 0xff);
2178 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2179 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2180 State.regs[REG_MCRL] = sum;
2183 sum = State.regs[REG_MCRH] + temp + c;
2184 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2185 && (temp & 0x80000000) != (sum & 0x80000000));
2186 State.regs[REG_MCRH] = sum;
2188 State.regs[REG_MCVF] = 1;
2191 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2192 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2196 long long temp, sum;
2200 srcreg = translate_rreg (SD_, RN2);
2202 temp = ((signed64)(signed16)EXTEND8 (IMM8)
2203 * (signed64)(signed16)State.regs[srcreg] & 0xffff);
2204 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2205 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2206 State.regs[REG_MCRL] = sum;
2209 sum = State.regs[REG_MCRH] + temp + c;
2210 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2211 && (temp & 0x80000000) != (sum & 0x80000000));
2212 State.regs[REG_MCRH] = sum;
2214 State.regs[REG_MCVF] = 1;
2217 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2218 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2222 long long temp, sum;
2226 srcreg = translate_rreg (SD_, RN2);
2228 temp = ((unsigned64) (IMM8)
2229 * (unsigned64)State.regs[srcreg] & 0xffff);
2230 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2231 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2232 State.regs[REG_MCRL] = sum;
2235 sum = State.regs[REG_MCRH] + temp + c;
2236 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2237 && (temp & 0x80000000) != (sum & 0x80000000));
2238 State.regs[REG_MCRH] = sum;
2240 State.regs[REG_MCVF] = 1;
2243 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
2244 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2250 dstreg = translate_rreg (SD_, RN0);
2252 PSW &= ~(PSW_V | PSW_C);
2253 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2255 /* 32bit saturation. */
2260 tmp = State.regs[REG_MCRH];
2262 tmp += State.regs[REG_MCRL];
2264 if (tmp > 0x7fffffff)
2265 State.regs[dstreg] = 0x7fffffff;
2266 else if (tmp < 0xffffffff80000000LL)
2267 State.regs[dstreg] = 0x80000000;
2269 State.regs[dstreg] = tmp;
2271 /* 16bit saturation */
2272 else if (IMM8 == 0x10)
2276 tmp = State.regs[REG_MCRH];
2278 tmp += State.regs[REG_MCRL];
2281 State.regs[dstreg] = 0x7fff;
2282 else if (tmp < 0xffffffffffff8000LL)
2283 State.regs[dstreg] = 0x8000;
2285 State.regs[dstreg] = tmp;
2287 /* 8 bit saturation */
2288 else if (IMM8 == 0x8)
2292 tmp = State.regs[REG_MCRH];
2294 tmp += State.regs[REG_MCRL];
2297 State.regs[dstreg] = 0x7f;
2298 else if (tmp < 0xffffffffffffff80LL)
2299 State.regs[dstreg] = 0x80;
2301 State.regs[dstreg] = tmp;
2303 /* 9 bit saturation */
2304 else if (IMM8 == 0x9)
2308 tmp = State.regs[REG_MCRH];
2310 tmp += State.regs[REG_MCRL];
2313 State.regs[dstreg] = 0x80;
2314 else if (tmp < 0xffffffffffffff81LL)
2315 State.regs[dstreg] = 0x81;
2317 State.regs[dstreg] = tmp;
2319 /* 9 bit saturation */
2320 else if (IMM8 == 0x30)
2324 tmp = State.regs[REG_MCRH];
2326 tmp += State.regs[REG_MCRL];
2328 if (tmp > 0x7fffffffffffLL)
2329 tmp = 0x7fffffffffffLL;
2330 else if (tmp < 0xffff800000000000LL)
2331 tmp = 0xffff800000000000LL;
2334 State.regs[dstreg] = tmp;
2338 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2339 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2344 unsigned long sum, source1, source2;
2345 int srcreg1, srcreg2, dstreg;
2348 srcreg1 = translate_rreg (SD_, RM2);
2349 srcreg2 = translate_rreg (SD_, RN0);
2350 dstreg = translate_rreg (SD_, RD0);
2352 source1 = State.regs[srcreg1];
2353 source2 = State.regs[srcreg2];
2354 sum = source1 + source2;
2355 State.regs[dstreg] = sum;
2358 n = (sum & 0x80000000);
2359 c = (sum < source1) || (sum < source2);
2360 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2361 && (source1 & 0x80000000) != (sum & 0x80000000));
2363 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2364 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2365 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2368 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2369 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2374 unsigned long sum, source1, source2;
2375 int srcreg1, srcreg2, dstreg;
2378 srcreg1 = translate_rreg (SD_, RM2);
2379 srcreg2 = translate_rreg (SD_, RN0);
2380 dstreg = translate_rreg (SD_, RD0);
2382 source1 = State.regs[srcreg1];
2383 source2 = State.regs[srcreg2];
2384 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2385 State.regs[dstreg] = sum;
2387 z = ((PSW & PSW_Z) != 0) && (sum == 0);
2388 n = (sum & 0x80000000);
2389 c = (sum < source1) || (sum < source2);
2390 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2391 && (source1 & 0x80000000) != (sum & 0x80000000));
2393 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2394 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2395 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2398 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2399 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2404 unsigned long difference, source1, source2;
2405 int srcreg1, srcreg2, dstreg;
2408 srcreg1 = translate_rreg (SD_, RM2);
2409 srcreg2 = translate_rreg (SD_, RN0);
2410 dstreg = translate_rreg (SD_, RD0);
2412 source1 = State.regs[srcreg1];
2413 source2 = State.regs[srcreg2];
2414 difference = source2 - source1;
2415 State.regs[dstreg] = difference;
2417 z = (difference == 0);
2418 n = (difference & 0x80000000);
2419 c = (source1 > source1);
2420 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2421 && (source1 & 0x80000000) != (difference & 0x80000000));
2423 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2424 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2425 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2428 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2429 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2434 unsigned long difference, source1, source2;
2435 int srcreg1, srcreg2, dstreg;
2438 srcreg1 = translate_rreg (SD_, RM2);
2439 srcreg2 = translate_rreg (SD_, RN0);
2440 dstreg = translate_rreg (SD_, RD0);
2442 source1 = State.regs[srcreg1];
2443 source2 = State.regs[srcreg2];
2444 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2445 State.regs[dstreg] = difference;
2447 z = ((PSW & PSW_Z) != 0) && (difference == 0);
2448 n = (difference & 0x80000000);
2449 c = (source1 > source2);
2450 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2451 && (source1 & 0x80000000) != (difference & 0x80000000));
2453 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2454 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2455 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2458 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2459 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2464 int srcreg1, srcreg2, dstreg;
2467 srcreg1 = translate_rreg (SD_, RM2);
2468 srcreg2 = translate_rreg (SD_, RN0);
2469 dstreg = translate_rreg (SD_, RD0);
2471 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2473 z = (State.regs[dstreg] == 0);
2474 n = (State.regs[dstreg] & 0x80000000);
2476 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2477 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2480 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2481 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2486 int srcreg1, srcreg2, dstreg;
2489 srcreg1 = translate_rreg (SD_, RM2);
2490 srcreg2 = translate_rreg (SD_, RN0);
2491 dstreg = translate_rreg (SD_, RD0);
2493 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2495 z = (State.regs[dstreg] == 0);
2496 n = (State.regs[dstreg] & 0x80000000);
2498 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2499 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2502 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2503 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2508 int srcreg1, srcreg2, dstreg;
2511 srcreg1 = translate_rreg (SD_, RM2);
2512 srcreg2 = translate_rreg (SD_, RN0);
2513 dstreg = translate_rreg (SD_, RD0);
2515 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2517 z = (State.regs[dstreg] == 0);
2518 n = (State.regs[dstreg] & 0x80000000);
2520 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2521 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2524 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2525 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2531 int srcreg1, srcreg2, dstreg;
2534 srcreg1 = translate_rreg (SD_, RM2);
2535 srcreg2 = translate_rreg (SD_, RN0);
2536 dstreg = translate_rreg (SD_, RD0);
2538 temp = State.regs[srcreg2];
2540 temp >>= State.regs[srcreg1];
2541 State.regs[dstreg] = temp;
2543 z = (State.regs[dstreg] == 0);
2544 n = (State.regs[dstreg] & 0x80000000);
2546 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2547 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2550 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2551 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2556 int srcreg1, srcreg2, dstreg;
2559 srcreg1 = translate_rreg (SD_, RM2);
2560 srcreg2 = translate_rreg (SD_, RN0);
2561 dstreg = translate_rreg (SD_, RD0);
2563 c = State.regs[srcreg2] & 1;
2564 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2566 z = (State.regs[dstreg] == 0);
2567 n = (State.regs[dstreg] & 0x80000000);
2569 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2570 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2573 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2574 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2579 int srcreg1, srcreg2, dstreg;
2582 srcreg1 = translate_rreg (SD_, RM2);
2583 srcreg2 = translate_rreg (SD_, RN0);
2584 dstreg = translate_rreg (SD_, RD0);
2586 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2588 z = (State.regs[dstreg] == 0);
2589 n = (State.regs[dstreg] & 0x80000000);
2591 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2592 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2595 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2596 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
2600 int srcreg1, srcreg2, dstreg1, dstreg2;
2601 signed long long temp;
2605 srcreg1 = translate_rreg (SD_, RM2);
2606 srcreg2 = translate_rreg (SD_, RN0);
2607 dstreg1 = translate_rreg (SD_, RD0);
2608 dstreg2 = translate_rreg (SD_, RD2);
2610 temp = ((signed64)(signed32)State.regs[srcreg1]
2611 * (signed64)(signed32)State.regs[srcreg2]);
2612 State.regs[dstreg1] = temp & 0xffffffff;
2613 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2615 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2616 n = (State.regs[dstreg2] & 0x80000000);
2618 PSW &= ~(PSW_Z | PSW_N);
2619 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2622 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2623 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
2627 int srcreg1, srcreg2, dstreg1, dstreg2;
2628 signed long long temp;
2632 srcreg1 = translate_rreg (SD_, RM2);
2633 srcreg2 = translate_rreg (SD_, RN0);
2634 dstreg1 = translate_rreg (SD_, RD0);
2635 dstreg2 = translate_rreg (SD_, RD2);
2637 temp = ((unsigned64)State.regs[srcreg1]
2638 * (unsigned64)State.regs[srcreg2]);
2639 State.regs[dstreg1] = temp & 0xffffffff;
2640 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2642 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2643 n = (State.regs[dstreg2] & 0x80000000);
2645 PSW &= ~(PSW_Z | PSW_N);
2646 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2649 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2650 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2657 dstreg = translate_rreg (SD_, RN2);
2658 State.regs[dstreg] = load_word (IMM8);
2661 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2662 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2669 srcreg = translate_rreg (SD_, RM2);
2670 store_word (IMM8, State.regs[srcreg]);
2673 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2674 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2681 dstreg = translate_rreg (SD_, RN2);
2682 State.regs[dstreg] = load_byte (IMM8);
2685 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2686 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2693 srcreg = translate_rreg (SD_, RM2);
2694 store_byte (IMM8, State.regs[srcreg]);
2697 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2698 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2705 dstreg = translate_rreg (SD_, RN2);
2706 State.regs[dstreg] = load_half (IMM8);
2709 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2710 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2717 srcreg = translate_rreg (SD_, RM2);
2718 store_half (IMM8, State.regs[srcreg]);
2721 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2722 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2726 int srcreg1, srcreg2, dstreg;
2729 srcreg1 = translate_rreg (SD_, RM0);
2730 srcreg1 = translate_rreg (SD_, RI0);
2731 dstreg = translate_rreg (SD_, RN0);
2732 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2735 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2736 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2740 int srcreg, dstreg1, dstreg2;
2743 srcreg = translate_rreg (SD_, RM0);
2744 dstreg1 = translate_rreg (SD_, RI0);
2745 dstreg2 = translate_rreg (SD_, RN0);
2746 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2749 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2750 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2754 int srcreg1, srcreg2, dstreg;
2757 srcreg1 = translate_rreg (SD_, RM0);
2758 srcreg1 = translate_rreg (SD_, RI0);
2759 dstreg = translate_rreg (SD_, RN0);
2760 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2763 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2764 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2768 int srcreg, dstreg1, dstreg2;
2771 srcreg = translate_rreg (SD_, RM0);
2772 dstreg1 = translate_rreg (SD_, RI0);
2773 dstreg2 = translate_rreg (SD_, RN0);
2774 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2777 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2778 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2782 int srcreg1, srcreg2, dstreg;
2785 srcreg1 = translate_rreg (SD_, RM0);
2786 srcreg1 = translate_rreg (SD_, RI0);
2787 dstreg = translate_rreg (SD_, RN0);
2788 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2791 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2792 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2796 int srcreg, dstreg1, dstreg2;
2799 srcreg = translate_rreg (SD_, RM0);
2800 dstreg1 = translate_rreg (SD_, RI0);
2801 dstreg2 = translate_rreg (SD_, RN0);
2802 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2805 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
2806 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mac
2810 int srcreg1, srcreg2, dstreg1, dstreg2;
2811 signed long long temp;
2816 srcreg1 = translate_rreg (SD_, RM2);
2817 srcreg2 = translate_rreg (SD_, RN0);
2818 dstreg1 = translate_rreg (SD_, RD0);
2819 dstreg2 = translate_rreg (SD_, RD2);
2821 temp = ((signed64)(signed32)State.regs[srcreg1]
2822 * (signed64)(signed32)State.regs[srcreg2]);
2824 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2825 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2826 State.regs[dstreg2] = sum;
2829 sum = State.regs[dstreg1] + temp + c;
2830 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2831 && (temp & 0x80000000) != (sum & 0x80000000));
2832 State.regs[dstreg1] = sum;
2835 State.regs[REG_MCVF] = 1;
2837 PSW |= (( v ? PSW_V : 0));
2841 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
2842 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::macu
2846 int srcreg1, srcreg2, dstreg1, dstreg2;
2847 signed long long temp;
2852 srcreg1 = translate_rreg (SD_, RM2);
2853 srcreg2 = translate_rreg (SD_, RN0);
2854 dstreg1 = translate_rreg (SD_, RD0);
2855 dstreg2 = translate_rreg (SD_, RD2);
2857 temp = ((unsigned64)State.regs[srcreg1]
2858 * (unsigned64)State.regs[srcreg2]);
2860 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2861 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2862 State.regs[dstreg2] = sum;
2865 sum = State.regs[dstreg1] + temp + c;
2866 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2867 && (temp & 0x80000000) != (sum & 0x80000000));
2868 State.regs[dstreg1] = sum;
2871 State.regs[REG_MCVF] = 1;
2873 PSW |= (( v ? PSW_V : 0));
2877 // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
2878 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2882 int srcreg1, srcreg2, dstreg;
2887 srcreg1 = translate_rreg (SD_, RM2);
2888 srcreg2 = translate_rreg (SD_, RN0);
2889 dstreg = translate_rreg (SD_, RD0);
2891 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2892 * (signed32)(State.regs[srcreg1] & 0xff));
2893 sum = State.regs[dstreg] + temp;
2894 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2895 && (temp & 0x80000000) != (sum & 0x80000000));
2896 State.regs[dstreg] = sum;
2899 State.regs[REG_MCVF] = 1;
2901 PSW |= ((v ? PSW_V : 0));
2905 // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
2906 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2910 int srcreg1, srcreg2, dstreg;
2915 srcreg1 = translate_rreg (SD_, RM2);
2916 srcreg2 = translate_rreg (SD_, RN0);
2917 dstreg = translate_rreg (SD_, RD0);
2919 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2920 * (unsigned32)(State.regs[srcreg1] & 0xff));
2921 sum = State.regs[dstreg] + temp;
2922 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2923 && (temp & 0x80000000) != (sum & 0x80000000));
2924 State.regs[dstreg] = sum;
2927 State.regs[REG_MCVF] = 1;
2929 PSW |= ((v ? PSW_V : 0));
2933 // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1
2934 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::mach
2938 int srcreg1, srcreg2, dstreg;
2943 srcreg1 = translate_rreg (SD_, RM2);
2944 srcreg2 = translate_rreg (SD_, RN0);
2945 dstreg = translate_rreg (SD_, RD0);
2947 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2948 * (signed32)(State.regs[srcreg1] & 0xffff));
2949 sum = State.regs[dstreg] + temp;
2950 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2951 && (temp & 0x80000000) != (sum & 0x80000000));
2952 State.regs[dstreg] = sum;
2955 State.regs[REG_MCVF] = 1;
2957 PSW |= ((v ? PSW_V : 0));
2961 // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1
2962 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::machu
2966 int srcreg1, srcreg2, dstreg;
2971 srcreg1 = translate_rreg (SD_, RM2);
2972 srcreg2 = translate_rreg (SD_, RN0);
2973 dstreg = translate_rreg (SD_, RD0);
2975 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2976 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2977 sum = State.regs[dstreg] + temp;
2978 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2979 && (temp & 0x80000000) != (sum & 0x80000000));
2980 State.regs[dstreg] = sum;
2983 State.regs[REG_MCVF] = 1;
2985 PSW |= ((v ? PSW_V : 0));
2989 // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
2990 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
2994 int srcreg1, srcreg2, dstreg;
2995 long temp, temp2, sum;
2999 srcreg1 = translate_rreg (SD_, RM2);
3000 srcreg2 = translate_rreg (SD_, RN0);
3001 dstreg = translate_rreg (SD_, RD0);
3003 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
3004 * (signed32)(State.regs[srcreg1] & 0xffff));
3005 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3006 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
3007 sum = temp + temp2 + State.regs[dstreg];
3008 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3009 && (temp & 0x80000000) != (sum & 0x80000000));
3010 State.regs[dstreg] = sum;
3013 State.regs[REG_MCVF] = 1;
3015 PSW |= ((v ? PSW_V : 0));
3019 // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
3020 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
3024 int srcreg1, srcreg2, dstreg;
3025 long temp, temp2, sum;
3029 srcreg1 = translate_rreg (SD_, RM2);
3030 srcreg2 = translate_rreg (SD_, RN0);
3031 dstreg = translate_rreg (SD_, RD0);
3033 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3034 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3035 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3036 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
3037 sum = temp + temp2 + State.regs[dstreg];
3038 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3039 && (temp & 0x80000000) != (sum & 0x80000000));
3040 State.regs[dstreg] = sum;
3043 State.regs[REG_MCVF] = 1;
3045 PSW |= ((v ? PSW_V : 0));
3049 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3050 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulh
3054 int srcreg1, srcreg2, dstreg1, dstreg2;
3055 signed long long temp;
3058 srcreg1 = translate_rreg (SD_, RM2);
3059 srcreg2 = translate_rreg (SD_, RN0);
3060 dstreg1 = translate_rreg (SD_, RD0);
3061 dstreg2 = translate_rreg (SD_, RD2);
3063 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3064 * (signed32)(State.regs[srcreg1] & 0xffff));
3065 State.regs[dstreg2] = temp;
3066 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3067 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3068 State.regs[dstreg1] = temp;
3071 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3072 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulhu
3076 int srcreg1, srcreg2, dstreg1, dstreg2;
3077 signed long long temp;
3080 srcreg1 = translate_rreg (SD_, RM2);
3081 srcreg2 = translate_rreg (SD_, RN0);
3082 dstreg1 = translate_rreg (SD_, RD0);
3083 dstreg2 = translate_rreg (SD_, RD2);
3085 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3086 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3087 State.regs[dstreg2] = temp;
3088 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3089 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3090 State.regs[dstreg1] = temp;
3093 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3094 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3102 srcreg = translate_rreg (SD_, RM2);
3103 dstreg = translate_rreg (SD_, RN0);
3105 value = State.regs[srcreg];
3107 if (value >= 0x7fffff)
3108 State.regs[dstreg] = 0x7fffff;
3109 else if (value <= 0xff800000)
3110 State.regs[dstreg] = 0xff800000;
3112 State.regs[dstreg] = value;
3114 n = (State.regs[dstreg] & 0x800000) != 0;
3115 z = (State.regs[dstreg] == 0);
3116 PSW &= ~(PSW_Z | PSW_N);
3117 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3120 // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
3121 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3126 int srcreg1, srcreg2, dstreg;
3130 srcreg1 = translate_rreg (SD_, RM2);
3131 srcreg2 = translate_rreg (SD_, RN0);
3132 dstreg = translate_rreg (SD_, RD0);
3134 temp = State.regs[srcreg1];
3135 start = (State.regs[srcreg2] & 0x1f) - 1;
3139 for (i = start; i >= 0; i--)
3141 if (temp & (1 << i))
3144 State.regs[dstreg] = i;
3152 State.regs[dstreg] = 0;
3155 PSW |= (c ? PSW_C : 0);
3158 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3159 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3166 dstreg = translate_rreg (SD_, RN0);
3167 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3170 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
3171 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3178 dstreg = translate_rreg (SD_, RN0);
3179 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3182 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
3183 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3190 dstreg = translate_rreg (SD_, RN0);
3191 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3194 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
3195 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3199 int dstreg, z, n, c, v;
3200 unsigned long sum, imm, reg2;
3203 dstreg = translate_rreg (SD_, RN0);
3205 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3206 reg2 = State.regs[dstreg];
3207 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3208 State.regs[dstreg] = sum;
3210 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3211 n = (sum & 0x80000000);
3212 c = (sum < imm) || (sum < reg2);
3213 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3214 && (reg2 & 0x80000000) != (sum & 0x80000000));
3216 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3217 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3218 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3221 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
3222 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3229 dstreg = translate_rreg (SD_, RN0);
3230 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3233 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
3234 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3238 int dstreg, z, n, c, v;
3239 unsigned long difference, imm, reg2;
3242 dstreg = translate_rreg (SD_, RN0);
3244 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3245 reg2 = State.regs[dstreg];
3246 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3247 State.regs[dstreg] = difference;
3249 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3250 n = (difference & 0x80000000);
3252 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3253 && (reg2 & 0x80000000) != (difference & 0x80000000));
3255 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3256 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3257 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3260 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
3261 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3268 srcreg = translate_rreg (SD_, RN0);
3269 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3272 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
3273 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3281 State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3287 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3288 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3296 dstreg = translate_rreg (SD_, RN0);
3298 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3299 z = (State.regs[dstreg] == 0);
3300 n = (State.regs[dstreg] & 0x80000000) != 0;
3301 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3302 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3305 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3306 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3314 dstreg = translate_rreg (SD_, RN0);
3316 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3317 z = (State.regs[dstreg] == 0);
3318 n = (State.regs[dstreg] & 0x80000000) != 0;
3319 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3320 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3323 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3324 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3332 dstreg = translate_rreg (SD_, RN0);
3334 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3335 z = (State.regs[dstreg] == 0);
3336 n = (State.regs[dstreg] & 0x80000000) != 0;
3337 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3338 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3341 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3342 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3351 dstreg = translate_rreg (SD_, RN0);
3353 temp = State.regs[dstreg];
3355 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3356 State.regs[dstreg] = temp;
3357 z = (State.regs[dstreg] == 0);
3358 n = (State.regs[dstreg] & 0x80000000) != 0;
3359 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3360 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3364 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3365 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3373 dstreg = translate_rreg (SD_, RN0);
3375 c = State.regs[dstreg] & 1;
3376 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3377 z = (State.regs[dstreg] == 0);
3378 n = (State.regs[dstreg] & 0x80000000) != 0;
3379 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3380 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3383 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3384 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3392 dstreg = translate_rreg (SD_, RN0);
3394 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3395 z = (State.regs[dstreg] == 0);
3396 n = (State.regs[dstreg] & 0x80000000) != 0;
3397 PSW &= ~(PSW_Z | PSW_N);
3398 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3401 // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3402 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3407 unsigned long long temp;
3411 dstreg = translate_rreg (SD_, RN0);
3413 temp = ((signed64)(signed32)State.regs[dstreg]
3414 * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3415 State.regs[dstreg] = temp & 0xffffffff;
3416 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3417 z = (State.regs[dstreg] == 0);
3418 n = (State.regs[dstreg] & 0x80000000) != 0;
3419 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3420 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3423 // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3424 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3429 unsigned long long temp;
3433 dstreg = translate_rreg (SD_, RN0);
3435 temp = ((unsigned64)State.regs[dstreg]
3436 * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3437 State.regs[dstreg] = temp & 0xffffffff;
3438 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3439 z = (State.regs[dstreg] == 0);
3440 n = (State.regs[dstreg] & 0x80000000) != 0;
3441 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3442 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3445 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3446 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3453 srcreg = translate_rreg (SD_, RN0);
3454 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3457 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3458 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3465 srcreg = translate_rreg (SD_, RM0);
3466 dstreg = translate_rreg (SD_, RN2);
3467 State.regs[dstreg] = load_word (State.regs[srcreg]
3468 + EXTEND24 (FETCH24 (IMM24A,
3472 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3473 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3480 srcreg = translate_rreg (SD_, RM2);
3481 dstreg = translate_rreg (SD_, RN0);
3482 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3483 State.regs[srcreg]);
3486 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3487 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3494 srcreg = translate_rreg (SD_, RM0);
3495 dstreg = translate_rreg (SD_, RN2);
3496 State.regs[dstreg] = load_byte (State.regs[srcreg]
3497 + EXTEND24 (FETCH24 (IMM24A,
3501 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3502 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3509 srcreg = translate_rreg (SD_, RM2);
3510 dstreg = translate_rreg (SD_, RN0);
3511 store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3512 State.regs[srcreg]);
3515 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3516 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3523 srcreg = translate_rreg (SD_, RM0);
3524 dstreg = translate_rreg (SD_, RN2);
3525 State.regs[dstreg] = load_half (State.regs[srcreg]
3526 + EXTEND24 (FETCH24 (IMM24A,
3530 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3531 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3538 srcreg = translate_rreg (SD_, RM2);
3539 dstreg = translate_rreg (SD_, RN0);
3540 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3541 State.regs[srcreg]);
3544 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3545 8.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3552 srcreg = translate_rreg (SD_, RM0);
3553 dstreg = translate_rreg (SD_, RN2);
3554 State.regs[dstreg] = load_word (State.regs[srcreg]);
3555 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3558 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3559 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3566 srcreg = translate_rreg (SD_, RM2);
3567 dstreg = translate_rreg (SD_, RN0);
3568 store_word (State.regs[dstreg], State.regs[srcreg]);
3569 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3573 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3574 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3581 dstreg = translate_rreg (SD_, RN2);
3582 State.regs[dstreg] = load_word (State.regs[REG_SP]
3583 + EXTEND24 (FETCH24 (IMM24A,
3587 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3588 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3595 srcreg = translate_rreg (SD_, RM2);
3596 store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3597 State.regs[srcreg]);
3600 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
3601 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3608 dstreg = translate_rreg (SD_, RN2);
3609 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3610 + EXTEND24 (FETCH24 (IMM24A,
3614 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3615 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3622 srcreg = translate_rreg (SD_, RM2);
3623 store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3624 State.regs[srcreg]);
3627 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3628 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3635 dstreg = translate_rreg (SD_, RN2);
3636 State.regs[dstreg] = load_half (State.regs[REG_SP]
3637 + EXTEND24 (FETCH24 (IMM24A,
3641 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3642 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3649 srcreg = translate_rreg (SD_, RM2);
3650 store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3651 State.regs[srcreg]);
3654 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3655 8.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3662 srcreg = translate_rreg (SD_, RM0);
3663 dstreg = translate_rreg (SD_, RN2);
3664 State.regs[dstreg] = load_half (State.regs[srcreg]);
3665 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3668 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3669 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3676 srcreg = translate_rreg (SD_, RM2);
3677 dstreg = translate_rreg (SD_, RN0);
3678 store_half (State.regs[dstreg], State.regs[srcreg]);
3679 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3682 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
3683 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3688 long long temp, sum;
3692 srcreg = translate_rreg (SD_, RN2);
3694 temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
3695 * (signed64)State.regs[srcreg]);
3696 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3697 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3698 State.regs[REG_MCRL] = sum;
3701 sum = State.regs[REG_MCRH] + temp + c;
3702 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3703 && (temp & 0x80000000) != (sum & 0x80000000));
3704 State.regs[REG_MCRH] = sum;
3706 State.regs[REG_MCVF] = 1;
3709 // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
3710 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3715 long long temp, sum;
3719 srcreg = translate_rreg (SD_, RN2);
3721 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3722 * (unsigned64)State.regs[srcreg]);
3723 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3724 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3725 State.regs[REG_MCRL] = sum;
3728 sum = State.regs[REG_MCRH] + temp + c;
3729 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3730 && (temp & 0x80000000) != (sum & 0x80000000));
3731 State.regs[REG_MCRH] = sum;
3733 State.regs[REG_MCVF] = 1;
3736 // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
3737 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3742 long long temp, sum;
3746 srcreg = translate_rreg (SD_, RN2);
3748 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3749 * (signed64)State.regs[srcreg] & 0xff);
3750 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3751 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3752 State.regs[REG_MCRL] = sum;
3755 sum = State.regs[REG_MCRH] + temp + c;
3756 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3757 && (temp & 0x80000000) != (sum & 0x80000000));
3758 State.regs[REG_MCRH] = sum;
3760 State.regs[REG_MCVF] = 1;
3763 // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
3764 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3769 long long temp, sum;
3773 srcreg = translate_rreg (SD_, RN2);
3775 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3776 * (unsigned64)State.regs[srcreg] & 0xff);
3777 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3778 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3779 State.regs[REG_MCRL] = sum;
3782 sum = State.regs[REG_MCRH] + temp + c;
3783 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3784 && (temp & 0x80000000) != (sum & 0x80000000));
3785 State.regs[REG_MCRH] = sum;
3787 State.regs[REG_MCVF] = 1;
3790 // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
3791 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3796 long long temp, sum;
3800 srcreg = translate_rreg (SD_, RN2);
3802 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3803 * (signed64)State.regs[srcreg] & 0xffff);
3804 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3805 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3806 State.regs[REG_MCRL] = sum;
3809 sum = State.regs[REG_MCRH] + temp + c;
3810 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3811 && (temp & 0x80000000) != (sum & 0x80000000));
3812 State.regs[REG_MCRH] = sum;
3814 State.regs[REG_MCVF] = 1;
3817 // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
3818 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3823 long long temp, sum;
3827 srcreg = translate_rreg (SD_, RN2);
3829 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3830 * (unsigned64)State.regs[srcreg] & 0xffff);
3831 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3832 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3833 State.regs[REG_MCRL] = sum;
3836 sum = State.regs[REG_MCRH] + temp + c;
3837 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3838 && (temp & 0x80000000) != (sum & 0x80000000));
3839 State.regs[REG_MCRH] = sum;
3841 State.regs[REG_MCVF] = 1;
3844 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3845 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3852 dstreg = translate_rreg (SD_, RN2);
3853 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3856 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3857 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3864 srcreg = translate_rreg (SD_, RM2);
3865 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3869 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3870 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3877 dstreg = translate_rreg (SD_, RN2);
3878 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3881 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3882 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3889 srcreg = translate_rreg (SD_, RM2);
3890 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3894 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3895 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3902 dstreg = translate_rreg (SD_, RN2);
3903 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3906 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3907 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3914 srcreg = translate_rreg (SD_, RM2);
3915 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3919 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3920 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3927 dstreg = translate_rreg (SD_, RN0);
3928 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3931 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3932 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3939 dstreg = translate_rreg (SD_, RN0);
3940 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3943 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3944 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3951 dstreg = translate_rreg (SD_, RN0);
3952 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3955 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3956 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3961 unsigned int imm, reg2, sum;
3965 dstreg = translate_rreg (SD_, RN0);
3967 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3968 reg2 = State.regs[dstreg];
3969 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3970 State.regs[dstreg] = sum;
3972 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3973 n = (sum & 0x80000000);
3974 c = (sum < imm) || (sum < reg2);
3975 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3976 && (reg2 & 0x80000000) != (sum & 0x80000000));
3978 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3979 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3980 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3983 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
3984 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3991 dstreg = translate_rreg (SD_, RN0);
3992 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3995 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
3996 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4001 unsigned int imm, reg2, difference;
4005 dstreg = translate_rreg (SD_, RN0);
4007 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4008 reg2 = State.regs[dstreg];
4009 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4010 State.regs[dstreg] = difference;
4012 z = ((PSW & PSW_Z) != 0) && (difference == 0);
4013 n = (difference & 0x80000000);
4015 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4016 && (reg2 & 0x80000000) != (difference & 0x80000000));
4018 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4019 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4020 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4023 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
4024 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4031 srcreg = translate_rreg (SD_, RN0);
4032 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4035 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
4036 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
4043 State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4048 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
4049 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4057 dstreg = translate_rreg (SD_, RN0);
4059 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4060 z = (State.regs[dstreg] == 0);
4061 n = (State.regs[dstreg] & 0x80000000) != 0;
4062 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4063 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4066 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
4067 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4075 dstreg = translate_rreg (SD_, RN0);
4077 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4078 z = (State.regs[dstreg] == 0);
4079 n = (State.regs[dstreg] & 0x80000000) != 0;
4080 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4081 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4084 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
4085 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4093 dstreg = translate_rreg (SD_, RN0);
4095 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4096 z = (State.regs[dstreg] == 0);
4097 n = (State.regs[dstreg] & 0x80000000) != 0;
4098 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4099 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4102 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
4103 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4112 dstreg = translate_rreg (SD_, RN0);
4114 temp = State.regs[dstreg];
4116 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4117 State.regs[dstreg] = temp;
4118 z = (State.regs[dstreg] == 0);
4119 n = (State.regs[dstreg] & 0x80000000) != 0;
4120 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4121 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4124 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
4125 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4133 dstreg = translate_rreg (SD_, RN0);
4135 c = State.regs[dstreg] & 1;
4136 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4137 z = (State.regs[dstreg] == 0);
4138 n = (State.regs[dstreg] & 0x80000000) != 0;
4139 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4140 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4143 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
4144 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4152 dstreg = translate_rreg (SD_, RN0);
4154 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4155 z = (State.regs[dstreg] == 0);
4156 n = (State.regs[dstreg] & 0x80000000) != 0;
4157 PSW &= ~(PSW_Z | PSW_N);
4158 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4161 // 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
4162 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
4167 unsigned long long temp;
4171 dstreg = translate_rreg (SD_, RN0);
4173 temp = ((signed64)(signed32)State.regs[dstreg]
4174 * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4175 State.regs[dstreg] = temp & 0xffffffff;
4176 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
4177 z = (State.regs[dstreg] == 0);
4178 n = (State.regs[dstreg] & 0x80000000) != 0;
4179 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4180 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4183 // 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
4184 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
4189 unsigned long long temp;
4193 dstreg = translate_rreg (SD_, RN0);
4195 temp = ((unsigned64)State.regs[dstreg]
4196 * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4197 State.regs[dstreg] = temp & 0xffffffff;
4198 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
4199 z = (State.regs[dstreg] == 0);
4200 n = (State.regs[dstreg] & 0x80000000) != 0;
4201 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4202 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4205 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
4206 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4213 srcreg = translate_rreg (SD_, RN0);
4214 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4217 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
4218 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4225 srcreg = translate_rreg (SD_, RM0);
4226 dstreg = translate_rreg (SD_, RN2);
4227 State.regs[dstreg] = load_word (State.regs[srcreg]
4228 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4231 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
4232 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4239 srcreg = translate_rreg (SD_, RM2);
4240 dstreg = translate_rreg (SD_, RN0);
4241 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4242 State.regs[srcreg]);
4245 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
4246 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4253 srcreg = translate_rreg (SD_, RM0);
4254 dstreg = translate_rreg (SD_, RN2);
4255 State.regs[dstreg] = load_byte (State.regs[srcreg]
4256 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4259 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
4260 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4267 srcreg = translate_rreg (SD_, RM2);
4268 dstreg = translate_rreg (SD_, RN0);
4269 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4270 State.regs[srcreg]);
4273 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
4274 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4281 srcreg = translate_rreg (SD_, RM0);
4282 dstreg = translate_rreg (SD_, RN2);
4283 State.regs[dstreg] = load_half (State.regs[srcreg]
4284 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4287 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
4288 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4295 srcreg = translate_rreg (SD_, RM2);
4296 dstreg = translate_rreg (SD_, RN0);
4297 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4298 State.regs[srcreg]);
4301 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
4302 8.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4309 srcreg = translate_rreg (SD_, RM0);
4310 dstreg = translate_rreg (SD_, RN2);
4311 State.regs[dstreg] = load_word (State.regs[srcreg]);
4312 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4315 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
4316 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4323 srcreg = translate_rreg (SD_, RM2);
4324 dstreg = translate_rreg (SD_, RN0);
4325 store_word (State.regs[dstreg], State.regs[srcreg]);
4326 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4330 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
4331 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4338 dstreg = translate_rreg (SD_, RN2);
4339 State.regs[dstreg] = load_word (State.regs[REG_SP]
4340 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4343 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
4344 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4351 srcreg = translate_rreg (SD_, RM2);
4352 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4353 State.regs[srcreg]);
4356 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
4357 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4364 dstreg = translate_rreg (SD_, RN2);
4365 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4366 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4369 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
4370 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4377 srcreg = translate_rreg (SD_, RM2);
4378 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4379 State.regs[srcreg]);
4382 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4383 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4390 dstreg = translate_rreg (SD_, RN2);
4391 State.regs[dstreg] = load_half (State.regs[REG_SP]
4392 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4395 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4396 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4403 srcreg = translate_rreg (SD_, RM2);
4404 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4405 State.regs[srcreg]);
4409 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
4410 8.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4417 srcreg = translate_rreg (SD_, RM0);
4418 dstreg = translate_rreg (SD_, RN2);
4419 State.regs[dstreg] = load_half (State.regs[srcreg]);
4420 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4423 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
4424 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4431 srcreg = translate_rreg (SD_, RM2);
4432 dstreg = translate_rreg (SD_, RN0);
4433 store_half (State.regs[dstreg], State.regs[srcreg]);
4434 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4438 // 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
4439 8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
4444 long long temp, sum;
4448 srcreg = translate_rreg (SD_, RN0);
4449 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4451 temp = ((signed64)(signed32)State.regs[srcreg]
4452 * (signed64)(signed32)imm);
4453 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4454 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4455 State.regs[REG_MCRL] = sum;
4458 sum = State.regs[REG_MCRH] + temp + c;
4459 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4460 && (temp & 0x80000000) != (sum & 0x80000000));
4461 State.regs[REG_MCRH] = sum;
4463 State.regs[REG_MCVF] = 1;
4466 // 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
4467 8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
4472 long long temp, sum;
4476 srcreg = translate_rreg (SD_, RN0);
4477 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4479 temp = ((unsigned64)State.regs[srcreg]
4481 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4482 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4483 State.regs[REG_MCRL] = sum;
4486 sum = State.regs[REG_MCRH] + temp + c;
4487 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4488 && (temp & 0x80000000) != (sum & 0x80000000));
4489 State.regs[REG_MCRH] = sum;
4491 State.regs[REG_MCVF] = 1;
4494 // 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
4495 8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
4504 srcreg = translate_rreg (SD_, RN0);
4505 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4507 temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
4508 * (signed32)(signed8)(imm & 0xff));
4509 sum = State.regs[REG_MCRL] + temp;
4510 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4511 && (temp & 0x80000000) != (sum & 0x80000000));
4512 State.regs[REG_MCRL] = sum;
4514 State.regs[REG_MCVF] = 1;
4517 // 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
4518 8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
4527 srcreg = translate_rreg (SD_, RN0);
4528 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4530 temp = ((unsigned32)(State.regs[srcreg] & 0xff)
4531 * (unsigned32)(imm & 0xff));
4532 sum = State.regs[REG_MCRL] + temp;
4533 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4534 && (temp & 0x80000000) != (sum & 0x80000000));
4535 State.regs[REG_MCRL] = sum;
4537 State.regs[REG_MCVF] = 1;
4540 // 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
4541 8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
4550 srcreg = translate_rreg (SD_, RN0);
4551 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4553 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4554 * (signed32)(signed16)(imm & 0xffff));
4555 sum = State.regs[REG_MCRL] + temp;
4556 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4557 && (temp & 0x80000000) != (sum & 0x80000000));
4558 State.regs[REG_MCRL] = sum;
4560 State.regs[REG_MCVF] = 1;
4563 // 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
4564 8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
4573 srcreg = translate_rreg (SD_, RN0);
4574 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4576 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4577 * (unsigned32)(imm & 0xffff));
4578 sum = State.regs[REG_MCRL] + temp;
4579 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4580 && (temp & 0x80000000) != (sum & 0x80000000));
4581 State.regs[REG_MCRL] = sum;
4583 State.regs[REG_MCVF] = 1;
4586 // 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
4587 8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
4592 long temp, temp2, sum;
4596 srcreg = translate_rreg (SD_, RN0);
4597 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4599 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4600 * (signed32)(signed16)(imm & 0xffff));
4601 temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
4602 * (signed32)(signed16)((imm >> 16) & 0xffff));
4603 sum = temp + temp2 + State.regs[REG_MCRL];
4604 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4605 && (temp & 0x80000000) != (sum & 0x80000000));
4606 State.regs[REG_MCRL] = sum;
4608 State.regs[REG_MCVF] = 1;
4611 // 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
4612 8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
4617 long temp, temp2, sum;
4621 srcreg = translate_rreg (SD_, RN0);
4622 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4624 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4625 * (unsigned32)(imm & 0xffff));
4626 temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
4627 * (unsigned32)((imm >> 16) & 0xffff));
4628 sum = temp + temp2 + State.regs[REG_MCRL];
4629 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4630 && (temp & 0x80000000) != (sum & 0x80000000));
4631 State.regs[REG_MCRL] = sum;
4633 State.regs[REG_MCVF] = 1;
4636 // 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
4637 8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
4645 dstreg = translate_rreg (SD_, RN0);
4646 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4648 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
4649 * (signed32)(signed16)(imm & 0xffff));
4650 State.regs[REG_MDRQ] = temp;
4651 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
4652 * (signed32)(signed16)((imm>>16) & 0xffff));
4653 State.regs[dstreg] = temp;
4656 // 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
4657 8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
4665 dstreg = translate_rreg (SD_, RN0);
4666 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4668 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
4669 * (unsigned32)(imm & 0xffff));
4670 State.regs[REG_MDRQ] = temp;
4671 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
4672 * (unsigned32)((imm >>16) & 0xffff));
4673 State.regs[dstreg] = temp;
4676 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4677 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4684 dstreg = translate_rreg (SD_, RN2);
4685 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4688 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4689 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4696 srcreg = translate_rreg (SD_, RM2);
4697 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4700 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4701 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4708 dstreg = translate_rreg (SD_, RN2);
4709 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4712 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4713 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4720 srcreg = translate_rreg (SD_, RM2);
4721 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4724 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4725 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4732 dstreg = translate_rreg (SD_, RN2);
4733 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4736 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4737 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4744 srcreg = translate_rreg (SD_, RM2);
4745 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4748 // 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
4749 8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_add
4753 int srcreg1, srcreg2, dstreg1, dstreg2;
4756 srcreg1 = translate_rreg (SD_, RM1);
4757 srcreg2 = translate_rreg (SD_, RM2);
4758 dstreg1 = translate_rreg (SD_, RN1);
4759 dstreg2 = translate_rreg (SD_, RN2);
4761 State.regs[dstreg1] += State.regs[srcreg1];
4762 State.regs[dstreg2] += State.regs[srcreg2];
4765 // 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
4766 8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_add
4770 int srcreg1, dstreg1, dstreg2;
4773 srcreg1 = translate_rreg (SD_, RM1);
4774 dstreg1 = translate_rreg (SD_, RN1);
4775 dstreg2 = translate_rreg (SD_, RN2);
4777 State.regs[dstreg1] += State.regs[srcreg1];
4778 State.regs[dstreg2] += EXTEND4 (IMM4);
4781 // 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
4782 8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_sub
4786 int srcreg1, srcreg2, dstreg1, dstreg2;
4789 srcreg1 = translate_rreg (SD_, RM1);
4790 srcreg2 = translate_rreg (SD_, RM2);
4791 dstreg1 = translate_rreg (SD_, RN1);
4792 dstreg2 = translate_rreg (SD_, RN2);
4794 State.regs[dstreg1] += State.regs[srcreg1];
4795 State.regs[dstreg2] -= State.regs[srcreg2];
4798 // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
4799 8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_sub
4803 int srcreg1, dstreg1, dstreg2;
4806 srcreg1 = translate_rreg (SD_, RM1);
4807 dstreg1 = translate_rreg (SD_, RN1);
4808 dstreg2 = translate_rreg (SD_, RN2);
4810 State.regs[dstreg1] += State.regs[srcreg1];
4811 State.regs[dstreg2] -= EXTEND4 (IMM4);
4814 // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
4815 8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_cmp
4819 int srcreg1, srcreg2, dstreg1, dstreg2;
4822 srcreg1 = translate_rreg (SD_, RM1);
4823 srcreg2 = translate_rreg (SD_, RM2);
4824 dstreg1 = translate_rreg (SD_, RN1);
4825 dstreg2 = translate_rreg (SD_, RN2);
4827 State.regs[dstreg1] += State.regs[srcreg1];
4828 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
4831 // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
4832 8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_cmp
4836 int srcreg1, dstreg1, dstreg2;
4839 srcreg1 = translate_rreg (SD_, RM1);
4840 dstreg1 = translate_rreg (SD_, RN1);
4841 dstreg2 = translate_rreg (SD_, RN2);
4843 State.regs[dstreg1] += State.regs[srcreg1];
4844 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
4847 // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
4848 8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_mov
4852 int srcreg1, srcreg2, dstreg1, dstreg2;
4855 srcreg1 = translate_rreg (SD_, RM1);
4856 srcreg2 = translate_rreg (SD_, RM2);
4857 dstreg1 = translate_rreg (SD_, RN1);
4858 dstreg2 = translate_rreg (SD_, RN2);
4860 State.regs[dstreg1] += State.regs[srcreg1];
4861 State.regs[dstreg2] = State.regs[srcreg2];
4864 // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
4865 8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_mov
4869 int srcreg1, dstreg1, dstreg2;
4872 srcreg1 = translate_rreg (SD_, RM1);
4873 dstreg1 = translate_rreg (SD_, RN1);
4874 dstreg2 = translate_rreg (SD_, RN2);
4876 State.regs[dstreg1] += State.regs[srcreg1];
4877 State.regs[dstreg2] = EXTEND4 (IMM4);
4880 // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
4881 8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asr
4885 int srcreg1, srcreg2, dstreg1, dstreg2;
4889 srcreg1 = translate_rreg (SD_, RM1);
4890 srcreg2 = translate_rreg (SD_, RM2);
4891 dstreg1 = translate_rreg (SD_, RN1);
4892 dstreg2 = translate_rreg (SD_, RN2);
4894 State.regs[dstreg1] += State.regs[srcreg1];
4895 temp = State.regs[dstreg2];
4896 temp >>= State.regs[srcreg2];
4897 State.regs[dstreg2] = temp;
4900 // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
4901 8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asr
4905 int srcreg1, dstreg1, dstreg2;
4909 srcreg1 = translate_rreg (SD_, RM1);
4910 dstreg1 = translate_rreg (SD_, RN1);
4911 dstreg2 = translate_rreg (SD_, RN2);
4913 State.regs[dstreg1] += State.regs[srcreg1];
4914 temp = State.regs[dstreg2];
4916 State.regs[dstreg2] = temp;
4919 // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
4920 8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_lsr
4924 int srcreg1, srcreg2, dstreg1, dstreg2;
4927 srcreg1 = translate_rreg (SD_, RM1);
4928 srcreg2 = translate_rreg (SD_, RM2);
4929 dstreg1 = translate_rreg (SD_, RN1);
4930 dstreg2 = translate_rreg (SD_, RN2);
4932 State.regs[dstreg1] += State.regs[srcreg1];
4933 State.regs[dstreg2] >>= State.regs[srcreg2];
4936 // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
4937 8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_lsr
4941 int srcreg1, dstreg1, dstreg2;
4945 srcreg1 = translate_rreg (SD_, RM1);
4946 dstreg1 = translate_rreg (SD_, RN1);
4947 dstreg2 = translate_rreg (SD_, RN2);
4949 State.regs[dstreg1] += State.regs[srcreg1];
4950 State.regs[dstreg2] >>= IMM4;
4954 // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
4955 8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asl
4959 int srcreg1, srcreg2, dstreg1, dstreg2;
4962 srcreg1 = translate_rreg (SD_, RM1);
4963 srcreg2 = translate_rreg (SD_, RM2);
4964 dstreg1 = translate_rreg (SD_, RN1);
4965 dstreg2 = translate_rreg (SD_, RN2);
4967 State.regs[dstreg1] += State.regs[srcreg1];
4968 State.regs[dstreg2] <<= State.regs[srcreg2];
4971 // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
4972 8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asl
4976 int srcreg1, dstreg1, dstreg2;
4980 srcreg1 = translate_rreg (SD_, RM1);
4981 dstreg1 = translate_rreg (SD_, RN1);
4982 dstreg2 = translate_rreg (SD_, RN2);
4984 State.regs[dstreg1] += State.regs[srcreg1];
4985 State.regs[dstreg2] <<= IMM4;
4988 // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
4989 8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_add
4993 int srcreg1, srcreg2, dstreg1, dstreg2;
4996 srcreg1 = translate_rreg (SD_, RM1);
4997 srcreg2 = translate_rreg (SD_, RM2);
4998 dstreg1 = translate_rreg (SD_, RN1);
4999 dstreg2 = translate_rreg (SD_, RN2);
5001 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5002 State.regs[dstreg2] += State.regs[srcreg2];
5005 // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
5006 8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_add
5010 int srcreg1, dstreg1, dstreg2;
5013 srcreg1 = translate_rreg (SD_, RM1);
5014 dstreg1 = translate_rreg (SD_, RN1);
5015 dstreg2 = translate_rreg (SD_, RN2);
5017 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5018 State.regs[dstreg2] += EXTEND4 (IMM4);
5021 // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
5022 8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_sub
5026 int srcreg1, srcreg2, dstreg1, dstreg2;
5029 srcreg1 = translate_rreg (SD_, RM1);
5030 srcreg2 = translate_rreg (SD_, RM2);
5031 dstreg1 = translate_rreg (SD_, RN1);
5032 dstreg2 = translate_rreg (SD_, RN2);
5034 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5035 State.regs[dstreg2] -= State.regs[srcreg2];
5038 // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
5039 8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_sub
5043 int srcreg1, dstreg1, dstreg2;
5046 srcreg1 = translate_rreg (SD_, RM1);
5047 dstreg1 = translate_rreg (SD_, RN1);
5048 dstreg2 = translate_rreg (SD_, RN2);
5050 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5051 State.regs[dstreg2] -= EXTEND4 (IMM4);
5054 // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
5055 8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_mov
5059 int srcreg1, srcreg2, dstreg1, dstreg2;
5062 srcreg1 = translate_rreg (SD_, RM1);
5063 srcreg2 = translate_rreg (SD_, RM2);
5064 dstreg1 = translate_rreg (SD_, RN1);
5065 dstreg2 = translate_rreg (SD_, RN2);
5067 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5068 State.regs[dstreg2] = State.regs[srcreg2];
5071 // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
5072 8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_mov
5076 int srcreg1, dstreg1, dstreg2;
5079 srcreg1 = translate_rreg (SD_, RM1);
5080 dstreg1 = translate_rreg (SD_, RN1);
5081 dstreg2 = translate_rreg (SD_, RN2);
5083 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5084 State.regs[dstreg2] = EXTEND4 (IMM4);
5087 // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
5088 8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asr
5092 int srcreg1, srcreg2, dstreg1, dstreg2;
5096 srcreg1 = translate_rreg (SD_, RM1);
5097 srcreg2 = translate_rreg (SD_, RM2);
5098 dstreg1 = translate_rreg (SD_, RN1);
5099 dstreg2 = translate_rreg (SD_, RN2);
5101 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5102 temp = State.regs[dstreg2];
5103 temp >>= State.regs[srcreg2];
5104 State.regs[dstreg2] = temp;
5107 // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
5108 8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asr
5112 int srcreg1, dstreg1, dstreg2;
5116 srcreg1 = translate_rreg (SD_, RM1);
5117 dstreg1 = translate_rreg (SD_, RN1);
5118 dstreg2 = translate_rreg (SD_, RN2);
5120 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5121 temp = State.regs[dstreg2];
5123 State.regs[dstreg2] = temp;
5126 // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
5127 8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_lsr
5131 int srcreg1, srcreg2, dstreg1, dstreg2;
5134 srcreg1 = translate_rreg (SD_, RM1);
5135 srcreg2 = translate_rreg (SD_, RM2);
5136 dstreg1 = translate_rreg (SD_, RN1);
5137 dstreg2 = translate_rreg (SD_, RN2);
5139 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5140 State.regs[dstreg2] >>= State.regs[srcreg2];
5143 // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
5144 8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_lsr
5148 int srcreg1, dstreg1, dstreg2;
5152 srcreg1 = translate_rreg (SD_, RM1);
5153 dstreg1 = translate_rreg (SD_, RN1);
5154 dstreg2 = translate_rreg (SD_, RN2);
5156 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5157 State.regs[dstreg2] >>= IMM4;
5161 // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
5162 8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asl
5166 int srcreg1, srcreg2, dstreg1, dstreg2;
5169 srcreg1 = translate_rreg (SD_, RM1);
5170 srcreg2 = translate_rreg (SD_, RM2);
5171 dstreg1 = translate_rreg (SD_, RN1);
5172 dstreg2 = translate_rreg (SD_, RN2);
5174 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5175 State.regs[dstreg2] <<= State.regs[srcreg2];
5178 // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
5179 8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asl
5183 int srcreg1, dstreg1, dstreg2;
5187 srcreg1 = translate_rreg (SD_, RM1);
5188 dstreg1 = translate_rreg (SD_, RN1);
5189 dstreg2 = translate_rreg (SD_, RN2);
5191 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5192 State.regs[dstreg2] <<= IMM4;
5195 // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
5196 8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_add
5200 int srcreg1, srcreg2, dstreg1, dstreg2;
5203 srcreg1 = translate_rreg (SD_, RM1);
5204 srcreg2 = translate_rreg (SD_, RM2);
5205 dstreg1 = translate_rreg (SD_, RN1);
5206 dstreg2 = translate_rreg (SD_, RN2);
5208 State.regs[dstreg1] -= State.regs[srcreg1];
5209 State.regs[dstreg2] += State.regs[srcreg2];
5212 // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
5213 8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_add
5217 int srcreg1, dstreg1, dstreg2;
5220 srcreg1 = translate_rreg (SD_, RM1);
5221 dstreg1 = translate_rreg (SD_, RN1);
5222 dstreg2 = translate_rreg (SD_, RN2);
5224 State.regs[dstreg1] -= State.regs[srcreg1];
5225 State.regs[dstreg2] += EXTEND4 (IMM4);
5228 // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
5229 8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_sub
5233 int srcreg1, srcreg2, dstreg1, dstreg2;
5236 srcreg1 = translate_rreg (SD_, RM1);
5237 srcreg2 = translate_rreg (SD_, RM2);
5238 dstreg1 = translate_rreg (SD_, RN1);
5239 dstreg2 = translate_rreg (SD_, RN2);
5241 State.regs[dstreg1] -= State.regs[srcreg1];
5242 State.regs[dstreg2] -= State.regs[srcreg2];
5245 // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
5246 8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_sub
5250 int srcreg1, dstreg1, dstreg2;
5253 srcreg1 = translate_rreg (SD_, RM1);
5254 dstreg1 = translate_rreg (SD_, RN1);
5255 dstreg2 = translate_rreg (SD_, RN2);
5257 State.regs[dstreg1] -= State.regs[srcreg1];
5258 State.regs[dstreg2] -= EXTEND4 (IMM4);
5261 // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
5262 8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_cmp
5266 int srcreg1, srcreg2, dstreg1, dstreg2;
5269 srcreg1 = translate_rreg (SD_, RM1);
5270 srcreg2 = translate_rreg (SD_, RM2);
5271 dstreg1 = translate_rreg (SD_, RN1);
5272 dstreg2 = translate_rreg (SD_, RN2);
5274 State.regs[dstreg1] -= State.regs[srcreg1];
5275 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5278 // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
5279 8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_cmp
5283 int srcreg1, dstreg1, dstreg2;
5286 srcreg1 = translate_rreg (SD_, RM1);
5287 dstreg1 = translate_rreg (SD_, RN1);
5288 dstreg2 = translate_rreg (SD_, RN2);
5290 State.regs[dstreg1] -= State.regs[srcreg1];
5291 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5294 // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
5295 8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_mov
5299 int srcreg1, srcreg2, dstreg1, dstreg2;
5302 srcreg1 = translate_rreg (SD_, RM1);
5303 srcreg2 = translate_rreg (SD_, RM2);
5304 dstreg1 = translate_rreg (SD_, RN1);
5305 dstreg2 = translate_rreg (SD_, RN2);
5307 State.regs[dstreg1] -= State.regs[srcreg1];
5308 State.regs[dstreg2] = State.regs[srcreg2];
5311 // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
5312 8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_mov
5316 int srcreg1, dstreg1, dstreg2;
5319 srcreg1 = translate_rreg (SD_, RM1);
5320 dstreg1 = translate_rreg (SD_, RN1);
5321 dstreg2 = translate_rreg (SD_, RN2);
5323 State.regs[dstreg1] -= State.regs[srcreg1];
5324 State.regs[dstreg2] = EXTEND4 (IMM4);
5327 // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
5328 8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asr
5332 int srcreg1, srcreg2, dstreg1, dstreg2;
5336 srcreg1 = translate_rreg (SD_, RM1);
5337 srcreg2 = translate_rreg (SD_, RM2);
5338 dstreg1 = translate_rreg (SD_, RN1);
5339 dstreg2 = translate_rreg (SD_, RN2);
5341 State.regs[dstreg1] -= State.regs[srcreg1];
5342 temp = State.regs[dstreg2];
5343 temp >>= State.regs[srcreg2];
5344 State.regs[dstreg2] = temp;
5347 // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
5348 8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asr
5352 int srcreg1, dstreg1, dstreg2;
5356 srcreg1 = translate_rreg (SD_, RM1);
5357 dstreg1 = translate_rreg (SD_, RN1);
5358 dstreg2 = translate_rreg (SD_, RN2);
5360 State.regs[dstreg1] -= State.regs[srcreg1];
5361 temp = State.regs[dstreg2];
5363 State.regs[dstreg2] = temp;
5366 // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
5367 8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_lsr
5371 int srcreg1, srcreg2, dstreg1, dstreg2;
5374 srcreg1 = translate_rreg (SD_, RM1);
5375 srcreg2 = translate_rreg (SD_, RM2);
5376 dstreg1 = translate_rreg (SD_, RN1);
5377 dstreg2 = translate_rreg (SD_, RN2);
5379 State.regs[dstreg1] -= State.regs[srcreg1];
5380 State.regs[dstreg2] >>= State.regs[srcreg2];
5383 // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
5384 8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_lsr
5388 int srcreg1, dstreg1, dstreg2;
5392 srcreg1 = translate_rreg (SD_, RM1);
5393 dstreg1 = translate_rreg (SD_, RN1);
5394 dstreg2 = translate_rreg (SD_, RN2);
5396 State.regs[dstreg1] -= State.regs[srcreg1];
5397 State.regs[dstreg2] >>= IMM4;
5401 // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
5402 8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asl
5406 int srcreg1, srcreg2, dstreg1, dstreg2;
5409 srcreg1 = translate_rreg (SD_, RM1);
5410 srcreg2 = translate_rreg (SD_, RM2);
5411 dstreg1 = translate_rreg (SD_, RN1);
5412 dstreg2 = translate_rreg (SD_, RN2);
5414 State.regs[dstreg1] -= State.regs[srcreg1];
5415 State.regs[dstreg2] <<= State.regs[srcreg2];
5418 // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
5419 8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asl
5423 int srcreg1, dstreg1, dstreg2;
5427 srcreg1 = translate_rreg (SD_, RM1);
5428 dstreg1 = translate_rreg (SD_, RN1);
5429 dstreg2 = translate_rreg (SD_, RN2);
5431 State.regs[dstreg1] -= State.regs[srcreg1];
5432 State.regs[dstreg2] <<= IMM4;
5435 // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
5436 8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_add
5440 int srcreg1, srcreg2, dstreg1, dstreg2;
5443 srcreg1 = translate_rreg (SD_, RM1);
5444 srcreg2 = translate_rreg (SD_, RM2);
5445 dstreg1 = translate_rreg (SD_, RN1);
5446 dstreg2 = translate_rreg (SD_, RN2);
5448 State.regs[dstreg1] = State.regs[srcreg1];
5449 State.regs[dstreg2] += State.regs[srcreg2];
5452 // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
5453 8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_add
5457 int srcreg1, dstreg1, dstreg2;
5460 srcreg1 = translate_rreg (SD_, RM1);
5461 dstreg1 = translate_rreg (SD_, RN1);
5462 dstreg2 = translate_rreg (SD_, RN2);
5464 State.regs[dstreg1] = State.regs[srcreg1];
5465 State.regs[dstreg2] += EXTEND4 (IMM4);
5468 // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
5469 8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_sub
5473 int srcreg1, srcreg2, dstreg1, dstreg2;
5476 srcreg1 = translate_rreg (SD_, RM1);
5477 srcreg2 = translate_rreg (SD_, RM2);
5478 dstreg1 = translate_rreg (SD_, RN1);
5479 dstreg2 = translate_rreg (SD_, RN2);
5481 State.regs[dstreg1] = State.regs[srcreg1];
5482 State.regs[dstreg2] -= State.regs[srcreg2];
5485 // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
5486 8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_sub
5490 int srcreg1, dstreg1, dstreg2;
5493 srcreg1 = translate_rreg (SD_, RM1);
5494 dstreg1 = translate_rreg (SD_, RN1);
5495 dstreg2 = translate_rreg (SD_, RN2);
5497 State.regs[dstreg1] = State.regs[srcreg1];
5498 State.regs[dstreg2] -= EXTEND4 (IMM4);
5501 // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
5502 8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_cmp
5506 int srcreg1, srcreg2, dstreg1, dstreg2;
5509 srcreg1 = translate_rreg (SD_, RM1);
5510 srcreg2 = translate_rreg (SD_, RM2);
5511 dstreg1 = translate_rreg (SD_, RN1);
5512 dstreg2 = translate_rreg (SD_, RN2);
5514 State.regs[dstreg1] = State.regs[srcreg1];
5515 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5518 // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
5519 8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_cmp
5523 int srcreg1, dstreg1, dstreg2;
5526 srcreg1 = translate_rreg (SD_, RM1);
5527 dstreg1 = translate_rreg (SD_, RN1);
5528 dstreg2 = translate_rreg (SD_, RN2);
5530 State.regs[dstreg1] = State.regs[srcreg1];
5531 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5534 // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
5535 8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_mov
5539 int srcreg1, srcreg2, dstreg1, dstreg2;
5542 srcreg1 = translate_rreg (SD_, RM1);
5543 srcreg2 = translate_rreg (SD_, RM2);
5544 dstreg1 = translate_rreg (SD_, RN1);
5545 dstreg2 = translate_rreg (SD_, RN2);
5547 State.regs[dstreg1] = State.regs[srcreg1];
5548 State.regs[dstreg2] = State.regs[srcreg2];
5551 // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
5552 8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_mov
5556 int srcreg1, dstreg1, dstreg2;
5559 srcreg1 = translate_rreg (SD_, RM1);
5560 dstreg1 = translate_rreg (SD_, RN1);
5561 dstreg2 = translate_rreg (SD_, RN2);
5563 State.regs[dstreg1] = State.regs[srcreg1];
5564 State.regs[dstreg2] = EXTEND4 (IMM4);
5567 // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
5568 8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asr
5572 int srcreg1, srcreg2, dstreg1, dstreg2;
5576 srcreg1 = translate_rreg (SD_, RM1);
5577 srcreg2 = translate_rreg (SD_, RM2);
5578 dstreg1 = translate_rreg (SD_, RN1);
5579 dstreg2 = translate_rreg (SD_, RN2);
5581 State.regs[dstreg1] = State.regs[srcreg1];
5582 temp = State.regs[dstreg2];
5583 temp >>= State.regs[srcreg2];
5584 State.regs[dstreg2] = temp;
5587 // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
5588 8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asr
5592 int srcreg1, dstreg1, dstreg2;
5596 srcreg1 = translate_rreg (SD_, RM1);
5597 dstreg1 = translate_rreg (SD_, RN1);
5598 dstreg2 = translate_rreg (SD_, RN2);
5600 State.regs[dstreg1] = State.regs[srcreg1];
5601 temp = State.regs[dstreg2];
5603 State.regs[dstreg2] = temp;
5606 // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
5607 8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_lsr
5611 int srcreg1, srcreg2, dstreg1, dstreg2;
5614 srcreg1 = translate_rreg (SD_, RM1);
5615 srcreg2 = translate_rreg (SD_, RM2);
5616 dstreg1 = translate_rreg (SD_, RN1);
5617 dstreg2 = translate_rreg (SD_, RN2);
5619 State.regs[dstreg1] = State.regs[srcreg1];
5620 State.regs[dstreg2] >>= State.regs[srcreg2];
5623 // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
5624 8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_lsr
5628 int srcreg1, dstreg1, dstreg2;
5632 srcreg1 = translate_rreg (SD_, RM1);
5633 dstreg1 = translate_rreg (SD_, RN1);
5634 dstreg2 = translate_rreg (SD_, RN2);
5636 State.regs[dstreg1] = State.regs[srcreg1];
5637 State.regs[dstreg2] >>= IMM4;
5641 // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
5642 8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asl
5646 int srcreg1, srcreg2, dstreg1, dstreg2;
5649 srcreg1 = translate_rreg (SD_, RM1);
5650 srcreg2 = translate_rreg (SD_, RM2);
5651 dstreg1 = translate_rreg (SD_, RN1);
5652 dstreg2 = translate_rreg (SD_, RN2);
5654 State.regs[dstreg1] = State.regs[srcreg1];
5655 State.regs[dstreg2] <<= State.regs[srcreg2];
5658 // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
5659 8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asl
5663 int srcreg1, dstreg1, dstreg2;
5667 srcreg1 = translate_rreg (SD_, RM1);
5668 dstreg1 = translate_rreg (SD_, RN1);
5669 dstreg2 = translate_rreg (SD_, RN2);
5671 State.regs[dstreg1] = State.regs[srcreg1];
5672 State.regs[dstreg2] <<= IMM4;
5675 // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
5676 8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_add
5680 int srcreg2, dstreg1, dstreg2;
5683 srcreg2 = translate_rreg (SD_, RM2);
5684 dstreg1 = translate_rreg (SD_, RN1);
5685 dstreg2 = translate_rreg (SD_, RN2);
5687 State.regs[dstreg1] += EXTEND4 (IMM4A);
5688 State.regs[dstreg2] += State.regs[srcreg2];
5691 // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
5692 8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_add
5696 int dstreg1, dstreg2;
5699 dstreg1 = translate_rreg (SD_, RN1);
5700 dstreg2 = translate_rreg (SD_, RN2);
5702 State.regs[dstreg1] += EXTEND4 (IMM4A);
5703 State.regs[dstreg2] += EXTEND4 (IMM4);
5706 // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
5707 8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_sub
5711 int srcreg2, dstreg1, dstreg2;
5714 srcreg2 = translate_rreg (SD_, RM2);
5715 dstreg1 = translate_rreg (SD_, RN1);
5716 dstreg2 = translate_rreg (SD_, RN2);
5718 State.regs[dstreg1] += EXTEND4 (IMM4A);
5719 State.regs[dstreg2] -= State.regs[srcreg2];
5722 // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
5723 8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_sub
5727 int dstreg1, dstreg2;
5730 dstreg1 = translate_rreg (SD_, RN1);
5731 dstreg2 = translate_rreg (SD_, RN2);
5733 State.regs[dstreg1] += EXTEND4 (IMM4A);
5734 State.regs[dstreg2] -= EXTEND4 (IMM4);
5737 // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
5738 8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_cmp
5742 int srcreg2, dstreg1, dstreg2;
5745 srcreg2 = translate_rreg (SD_, RM2);
5746 dstreg1 = translate_rreg (SD_, RN1);
5747 dstreg2 = translate_rreg (SD_, RN2);
5749 State.regs[dstreg1] += EXTEND4 (IMM4A);
5750 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5753 // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
5754 8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_cmp
5758 int dstreg1, dstreg2;
5761 dstreg1 = translate_rreg (SD_, RN1);
5762 dstreg2 = translate_rreg (SD_, RN2);
5764 State.regs[dstreg1] += EXTEND4 (IMM4A);
5765 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5768 // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
5769 8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_mov
5773 int srcreg2, dstreg1, dstreg2;
5776 srcreg2 = translate_rreg (SD_, RM2);
5777 dstreg1 = translate_rreg (SD_, RN1);
5778 dstreg2 = translate_rreg (SD_, RN2);
5780 State.regs[dstreg1] += EXTEND4 (IMM4A);
5781 State.regs[dstreg2] = State.regs[srcreg2];
5784 // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
5785 8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_mov
5789 int dstreg1, dstreg2;
5792 dstreg1 = translate_rreg (SD_, RN1);
5793 dstreg2 = translate_rreg (SD_, RN2);
5795 State.regs[dstreg1] += EXTEND4 (IMM4A);
5796 State.regs[dstreg2] = EXTEND4 (IMM4);
5799 // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
5800 8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asr
5804 int srcreg2, dstreg1, dstreg2;
5808 srcreg2 = translate_rreg (SD_, RM2);
5809 dstreg1 = translate_rreg (SD_, RN1);
5810 dstreg2 = translate_rreg (SD_, RN2);
5812 State.regs[dstreg1] += EXTEND4 (IMM4A);
5813 temp = State.regs[dstreg2];
5814 temp >>= State.regs[srcreg2];
5815 State.regs[dstreg2] = temp;
5818 // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
5819 8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asr
5823 int dstreg1, dstreg2;
5827 dstreg1 = translate_rreg (SD_, RN1);
5828 dstreg2 = translate_rreg (SD_, RN2);
5830 State.regs[dstreg1] += EXTEND4 (IMM4A);
5831 temp = State.regs[dstreg2];
5833 State.regs[dstreg2] = temp;
5836 // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
5837 8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_lsr
5841 int srcreg2, dstreg1, dstreg2;
5844 srcreg2 = translate_rreg (SD_, RM2);
5845 dstreg1 = translate_rreg (SD_, RN1);
5846 dstreg2 = translate_rreg (SD_, RN2);
5848 State.regs[dstreg1] += EXTEND4 (IMM4A);
5849 State.regs[dstreg2] >>= State.regs[srcreg2];
5852 // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
5853 8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_lsr
5857 int dstreg1, dstreg2;
5861 dstreg1 = translate_rreg (SD_, RN1);
5862 dstreg2 = translate_rreg (SD_, RN2);
5864 State.regs[dstreg1] += EXTEND4 (IMM4A);
5865 State.regs[dstreg2] >>= IMM4;
5869 // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
5870 8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asl
5874 int srcreg2, dstreg1, dstreg2;
5877 srcreg2 = translate_rreg (SD_, RM2);
5878 dstreg1 = translate_rreg (SD_, RN1);
5879 dstreg2 = translate_rreg (SD_, RN2);
5881 State.regs[dstreg1] += EXTEND4 (IMM4A);
5882 State.regs[dstreg2] <<= State.regs[srcreg2];
5885 // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
5886 8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asl
5890 int dstreg1, dstreg2;
5894 dstreg1 = translate_rreg (SD_, RN1);
5895 dstreg2 = translate_rreg (SD_, RN2);
5897 State.regs[dstreg1] += EXTEND4 (IMM4A);
5898 State.regs[dstreg2] <<= IMM4;
5901 // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
5902 8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_add
5906 int srcreg2, dstreg1, dstreg2;
5909 srcreg2 = translate_rreg (SD_, RM2);
5910 dstreg1 = translate_rreg (SD_, RN1);
5911 dstreg2 = translate_rreg (SD_, RN2);
5913 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5914 State.regs[dstreg2] += State.regs[srcreg2];
5917 // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
5918 8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_add
5922 int dstreg1, dstreg2;
5925 dstreg1 = translate_rreg (SD_, RN1);
5926 dstreg2 = translate_rreg (SD_, RN2);
5928 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5929 State.regs[dstreg2] += EXTEND4 (IMM4);
5932 // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
5933 8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_sub
5937 int srcreg2, dstreg1, dstreg2;
5940 srcreg2 = translate_rreg (SD_, RM2);
5941 dstreg1 = translate_rreg (SD_, RN1);
5942 dstreg2 = translate_rreg (SD_, RN2);
5944 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5945 State.regs[dstreg2] -= State.regs[srcreg2];
5948 // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
5949 8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_sub
5953 int dstreg1, dstreg2;
5956 dstreg1 = translate_rreg (SD_, RN1);
5957 dstreg2 = translate_rreg (SD_, RN2);
5959 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5960 State.regs[dstreg2] -= EXTEND4 (IMM4);
5963 // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
5964 8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_mov
5968 int srcreg2, dstreg1, dstreg2;
5971 srcreg2 = translate_rreg (SD_, RM2);
5972 dstreg1 = translate_rreg (SD_, RN1);
5973 dstreg2 = translate_rreg (SD_, RN2);
5975 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5976 State.regs[dstreg2] = State.regs[srcreg2];
5979 // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
5980 8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_mov
5984 int dstreg1, dstreg2;
5987 dstreg1 = translate_rreg (SD_, RN1);
5988 dstreg2 = translate_rreg (SD_, RN2);
5990 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5991 State.regs[dstreg2] = EXTEND4 (IMM4);
5994 // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
5995 8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asr
5999 int srcreg2, dstreg1, dstreg2;
6003 srcreg2 = translate_rreg (SD_, RM2);
6004 dstreg1 = translate_rreg (SD_, RN1);
6005 dstreg2 = translate_rreg (SD_, RN2);
6007 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6008 temp = State.regs[dstreg2];
6009 temp >>= State.regs[srcreg2];
6010 State.regs[dstreg2] = temp;
6013 // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
6014 8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asr
6018 int dstreg1, dstreg2;
6022 dstreg1 = translate_rreg (SD_, RN1);
6023 dstreg2 = translate_rreg (SD_, RN2);
6025 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6026 temp = State.regs[dstreg2];
6028 State.regs[dstreg2] = temp;
6031 // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
6032 8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_lsr
6036 int srcreg2, dstreg1, dstreg2;
6039 srcreg2 = translate_rreg (SD_, RM2);
6040 dstreg1 = translate_rreg (SD_, RN1);
6041 dstreg2 = translate_rreg (SD_, RN2);
6043 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6044 State.regs[dstreg2] >>= State.regs[srcreg2];
6047 // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
6048 8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_lsr
6052 int dstreg1, dstreg2;
6056 dstreg1 = translate_rreg (SD_, RN1);
6057 dstreg2 = translate_rreg (SD_, RN2);
6059 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6060 State.regs[dstreg2] >>= IMM4;
6064 // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
6065 8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asl
6069 int srcreg2, dstreg1, dstreg2;
6072 srcreg2 = translate_rreg (SD_, RM2);
6073 dstreg1 = translate_rreg (SD_, RN1);
6074 dstreg2 = translate_rreg (SD_, RN2);
6076 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6077 State.regs[dstreg2] <<= State.regs[srcreg2];
6080 // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
6081 8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asl
6085 int dstreg1, dstreg2;
6089 dstreg1 = translate_rreg (SD_, RN1);
6090 dstreg2 = translate_rreg (SD_, RN2);
6092 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6093 State.regs[dstreg2] <<= IMM4;
6096 // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
6097 8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_add
6101 int srcreg2, dstreg1, dstreg2;
6104 srcreg2 = translate_rreg (SD_, RM2);
6105 dstreg1 = translate_rreg (SD_, RN1);
6106 dstreg2 = translate_rreg (SD_, RN2);
6108 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6109 State.regs[dstreg2] += State.regs[srcreg2];
6112 // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
6113 8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_add
6117 int dstreg1, dstreg2;
6120 dstreg1 = translate_rreg (SD_, RN1);
6121 dstreg2 = translate_rreg (SD_, RN2);
6123 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6124 State.regs[dstreg2] += EXTEND4 (IMM4);
6127 // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
6128 8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_sub
6132 int srcreg2, dstreg1, dstreg2;
6135 srcreg2 = translate_rreg (SD_, RM2);
6136 dstreg1 = translate_rreg (SD_, RN1);
6137 dstreg2 = translate_rreg (SD_, RN2);
6139 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6140 State.regs[dstreg2] -= State.regs[srcreg2];
6143 // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
6144 8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_sub
6148 int dstreg1, dstreg2;
6151 dstreg1 = translate_rreg (SD_, RN1);
6152 dstreg2 = translate_rreg (SD_, RN2);
6154 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6155 State.regs[dstreg2] -= EXTEND4 (IMM4);
6158 // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
6159 8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_cmp
6163 int srcreg2, dstreg1, dstreg2;
6166 srcreg2 = translate_rreg (SD_, RM2);
6167 dstreg1 = translate_rreg (SD_, RN1);
6168 dstreg2 = translate_rreg (SD_, RN2);
6170 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6171 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6174 // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
6175 8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_cmp
6179 int dstreg1, dstreg2;
6182 dstreg1 = translate_rreg (SD_, RN1);
6183 dstreg2 = translate_rreg (SD_, RN2);
6185 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6186 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6189 // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
6190 8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_mov
6194 int srcreg2, dstreg1, dstreg2;
6197 srcreg2 = translate_rreg (SD_, RM2);
6198 dstreg1 = translate_rreg (SD_, RN1);
6199 dstreg2 = translate_rreg (SD_, RN2);
6201 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6202 State.regs[dstreg2] = State.regs[srcreg2];
6205 // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
6206 8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_mov
6210 int dstreg1, dstreg2;
6213 dstreg1 = translate_rreg (SD_, RN1);
6214 dstreg2 = translate_rreg (SD_, RN2);
6216 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6217 State.regs[dstreg2] = EXTEND4 (IMM4);
6220 // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
6221 8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asr
6225 int srcreg2, dstreg1, dstreg2;
6229 srcreg2 = translate_rreg (SD_, RM2);
6230 dstreg1 = translate_rreg (SD_, RN1);
6231 dstreg2 = translate_rreg (SD_, RN2);
6233 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6234 temp = State.regs[dstreg2];
6235 temp >>= State.regs[srcreg2];
6236 State.regs[dstreg2] = temp;
6239 // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
6240 8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asr
6244 int dstreg1, dstreg2;
6248 dstreg1 = translate_rreg (SD_, RN1);
6249 dstreg2 = translate_rreg (SD_, RN2);
6251 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6252 temp = State.regs[dstreg2];
6254 State.regs[dstreg2] = temp;
6257 // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
6258 8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_lsr
6262 int srcreg2, dstreg1, dstreg2;
6265 srcreg2 = translate_rreg (SD_, RM2);
6266 dstreg1 = translate_rreg (SD_, RN1);
6267 dstreg2 = translate_rreg (SD_, RN2);
6269 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6270 State.regs[dstreg2] >>= State.regs[srcreg2];
6273 // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
6274 8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_lsr
6278 int dstreg1, dstreg2;
6282 dstreg1 = translate_rreg (SD_, RN1);
6283 dstreg2 = translate_rreg (SD_, RN2);
6285 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6286 State.regs[dstreg2] >>= IMM4;
6290 // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
6291 8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asl
6295 int srcreg2, dstreg1, dstreg2;
6298 srcreg2 = translate_rreg (SD_, RM2);
6299 dstreg1 = translate_rreg (SD_, RN1);
6300 dstreg2 = translate_rreg (SD_, RN2);
6302 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6303 State.regs[dstreg2] <<= State.regs[srcreg2];
6306 // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
6307 8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asl
6311 int dstreg1, dstreg2;
6315 dstreg1 = translate_rreg (SD_, RN1);
6316 dstreg2 = translate_rreg (SD_, RN2);
6318 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6319 State.regs[dstreg2] <<= IMM4;
6322 // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
6323 8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_add
6327 int srcreg2, dstreg1, dstreg2;
6330 srcreg2 = translate_rreg (SD_, RM2);
6331 dstreg1 = translate_rreg (SD_, RN1);
6332 dstreg2 = translate_rreg (SD_, RN2);
6334 State.regs[dstreg1] = EXTEND4 (IMM4A);
6335 State.regs[dstreg2] += State.regs[srcreg2];
6338 // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
6339 8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_add
6343 int dstreg1, dstreg2;
6346 dstreg1 = translate_rreg (SD_, RN1);
6347 dstreg2 = translate_rreg (SD_, RN2);
6349 State.regs[dstreg1] = EXTEND4 (IMM4A);
6350 State.regs[dstreg2] += EXTEND4 (IMM4);
6353 // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
6354 8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_sub
6358 int srcreg2, dstreg1, dstreg2;
6361 srcreg2 = translate_rreg (SD_, RM2);
6362 dstreg1 = translate_rreg (SD_, RN1);
6363 dstreg2 = translate_rreg (SD_, RN2);
6365 State.regs[dstreg1] = EXTEND4 (IMM4A);
6366 State.regs[dstreg2] -= State.regs[srcreg2];
6369 // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
6370 8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_sub
6374 int dstreg1, dstreg2;
6377 dstreg1 = translate_rreg (SD_, RN1);
6378 dstreg2 = translate_rreg (SD_, RN2);
6380 State.regs[dstreg1] = EXTEND4 (IMM4A);
6381 State.regs[dstreg2] -= EXTEND4 (IMM4);
6384 // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
6385 8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_cmp
6389 int srcreg2, dstreg1, dstreg2;
6392 srcreg2 = translate_rreg (SD_, RM2);
6393 dstreg1 = translate_rreg (SD_, RN1);
6394 dstreg2 = translate_rreg (SD_, RN2);
6396 State.regs[dstreg1] = EXTEND4 (IMM4A);
6397 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6400 // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
6401 8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_cmp
6405 int dstreg1, dstreg2;
6408 dstreg1 = translate_rreg (SD_, RN1);
6409 dstreg2 = translate_rreg (SD_, RN2);
6411 State.regs[dstreg1] = EXTEND4 (IMM4A);
6412 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6415 // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
6416 8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_mov
6420 int srcreg2, dstreg1, dstreg2;
6423 srcreg2 = translate_rreg (SD_, RM2);
6424 dstreg1 = translate_rreg (SD_, RN1);
6425 dstreg2 = translate_rreg (SD_, RN2);
6427 State.regs[dstreg1] = EXTEND4 (IMM4A);
6428 State.regs[dstreg2] = State.regs[srcreg2];
6431 // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
6432 8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_mov
6436 int dstreg1, dstreg2;
6439 dstreg1 = translate_rreg (SD_, RN1);
6440 dstreg2 = translate_rreg (SD_, RN2);
6442 State.regs[dstreg1] = EXTEND4 (IMM4A);
6443 State.regs[dstreg2] = EXTEND4 (IMM4);
6446 // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
6447 8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asr
6451 int srcreg2, dstreg1, dstreg2;
6455 srcreg2 = translate_rreg (SD_, RM2);
6456 dstreg1 = translate_rreg (SD_, RN1);
6457 dstreg2 = translate_rreg (SD_, RN2);
6459 State.regs[dstreg1] = EXTEND4 (IMM4A);
6460 temp = State.regs[dstreg2];
6461 temp >>= State.regs[srcreg2];
6462 State.regs[dstreg2] = temp;
6465 // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
6466 8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asr
6470 int dstreg1, dstreg2;
6474 dstreg1 = translate_rreg (SD_, RN1);
6475 dstreg2 = translate_rreg (SD_, RN2);
6477 State.regs[dstreg1] = EXTEND4 (IMM4A);
6478 temp = State.regs[dstreg2];
6480 State.regs[dstreg2] = temp;
6483 // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
6484 8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_lsr
6488 int srcreg2, dstreg1, dstreg2;
6491 srcreg2 = translate_rreg (SD_, RM2);
6492 dstreg1 = translate_rreg (SD_, RN1);
6493 dstreg2 = translate_rreg (SD_, RN2);
6495 State.regs[dstreg1] = EXTEND4 (IMM4A);
6496 State.regs[dstreg2] >>= State.regs[srcreg2];
6499 // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
6500 8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_lsr
6504 int dstreg1, dstreg2;
6508 dstreg1 = translate_rreg (SD_, RN1);
6509 dstreg2 = translate_rreg (SD_, RN2);
6511 State.regs[dstreg1] = EXTEND4 (IMM4A);
6512 State.regs[dstreg2] >>= IMM4;
6516 // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
6517 8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asl
6521 int srcreg2, dstreg1, dstreg2;
6524 srcreg2 = translate_rreg (SD_, RM2);
6525 dstreg1 = translate_rreg (SD_, RN1);
6526 dstreg2 = translate_rreg (SD_, RN2);
6528 State.regs[dstreg1] = EXTEND4 (IMM4A);
6529 State.regs[dstreg2] <<= State.regs[srcreg2];
6532 // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
6533 8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asl
6537 int dstreg1, dstreg2;
6541 dstreg1 = translate_rreg (SD_, RN1);
6542 dstreg2 = translate_rreg (SD_, RN2);
6544 State.regs[dstreg1] = EXTEND4 (IMM4A);
6545 State.regs[dstreg2] <<= IMM4;
6548 // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
6549 8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_add
6553 int srcreg1, srcreg2, dstreg1, dstreg2;
6556 srcreg1 = translate_rreg (SD_, RM1);
6557 srcreg2 = translate_rreg (SD_, RM2);
6558 dstreg1 = translate_rreg (SD_, RN1);
6559 dstreg2 = translate_rreg (SD_, RN2);
6561 State.regs[dstreg1] &= State.regs[srcreg1];
6562 State.regs[dstreg2] += State.regs[srcreg2];
6565 // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
6566 8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_add
6570 int srcreg1, dstreg1, dstreg2;
6573 srcreg1 = translate_rreg (SD_, RM1);
6574 dstreg1 = translate_rreg (SD_, RN1);
6575 dstreg2 = translate_rreg (SD_, RN2);
6577 State.regs[dstreg1] &= State.regs[srcreg1];
6578 State.regs[dstreg2] += EXTEND4 (IMM4);
6581 // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
6582 8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_sub
6586 int srcreg1, srcreg2, dstreg1, dstreg2;
6589 srcreg1 = translate_rreg (SD_, RM1);
6590 srcreg2 = translate_rreg (SD_, RM2);
6591 dstreg1 = translate_rreg (SD_, RN1);
6592 dstreg2 = translate_rreg (SD_, RN2);
6594 State.regs[dstreg1] &= State.regs[srcreg1];
6595 State.regs[dstreg2] -= State.regs[srcreg2];
6598 // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
6599 8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_sub
6603 int srcreg1, dstreg1, dstreg2;
6606 srcreg1 = translate_rreg (SD_, RM1);
6607 dstreg1 = translate_rreg (SD_, RN1);
6608 dstreg2 = translate_rreg (SD_, RN2);
6610 State.regs[dstreg1] &= State.regs[srcreg1];
6611 State.regs[dstreg2] -= EXTEND4 (IMM4);
6614 // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
6615 8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_cmp
6619 int srcreg1, srcreg2, dstreg1, dstreg2;
6622 srcreg1 = translate_rreg (SD_, RM1);
6623 srcreg2 = translate_rreg (SD_, RM2);
6624 dstreg1 = translate_rreg (SD_, RN1);
6625 dstreg2 = translate_rreg (SD_, RN2);
6627 State.regs[dstreg1] &= State.regs[srcreg1];
6628 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6631 // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
6632 8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_cmp
6636 int srcreg1, dstreg1, dstreg2;
6639 srcreg1 = translate_rreg (SD_, RM1);
6640 dstreg1 = translate_rreg (SD_, RN1);
6641 dstreg2 = translate_rreg (SD_, RN2);
6643 State.regs[dstreg1] &= State.regs[srcreg1];
6644 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6647 // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
6648 8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_mov
6652 int srcreg1, srcreg2, dstreg1, dstreg2;
6655 srcreg1 = translate_rreg (SD_, RM1);
6656 srcreg2 = translate_rreg (SD_, RM2);
6657 dstreg1 = translate_rreg (SD_, RN1);
6658 dstreg2 = translate_rreg (SD_, RN2);
6660 State.regs[dstreg1] &= State.regs[srcreg1];
6661 State.regs[dstreg2] = State.regs[srcreg2];
6664 // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
6665 8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_mov
6669 int srcreg1, dstreg1, dstreg2;
6672 srcreg1 = translate_rreg (SD_, RM1);
6673 dstreg1 = translate_rreg (SD_, RN1);
6674 dstreg2 = translate_rreg (SD_, RN2);
6676 State.regs[dstreg1] &= State.regs[srcreg1];
6677 State.regs[dstreg2] = EXTEND4 (IMM4);
6680 // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
6681 8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asr
6685 int srcreg1, srcreg2, dstreg1, dstreg2;
6689 srcreg1 = translate_rreg (SD_, RM1);
6690 srcreg2 = translate_rreg (SD_, RM2);
6691 dstreg1 = translate_rreg (SD_, RN1);
6692 dstreg2 = translate_rreg (SD_, RN2);
6694 State.regs[dstreg1] &= State.regs[srcreg1];
6695 temp = State.regs[dstreg2];
6696 temp >>= State.regs[srcreg2];
6697 State.regs[dstreg2] = temp;
6700 // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
6701 8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asr
6705 int srcreg1, dstreg1, dstreg2;
6709 srcreg1 = translate_rreg (SD_, RM1);
6710 dstreg1 = translate_rreg (SD_, RN1);
6711 dstreg2 = translate_rreg (SD_, RN2);
6713 State.regs[dstreg1] &= State.regs[srcreg1];
6714 temp = State.regs[dstreg2];
6716 State.regs[dstreg2] = temp;
6719 // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
6720 8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_lsr
6724 int srcreg1, srcreg2, dstreg1, dstreg2;
6727 srcreg1 = translate_rreg (SD_, RM1);
6728 srcreg2 = translate_rreg (SD_, RM2);
6729 dstreg1 = translate_rreg (SD_, RN1);
6730 dstreg2 = translate_rreg (SD_, RN2);
6732 State.regs[dstreg1] &= State.regs[srcreg1];
6733 State.regs[dstreg2] >>= State.regs[srcreg2];
6736 // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
6737 8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_lsr
6741 int srcreg1, dstreg1, dstreg2;
6745 srcreg1 = translate_rreg (SD_, RM1);
6746 dstreg1 = translate_rreg (SD_, RN1);
6747 dstreg2 = translate_rreg (SD_, RN2);
6749 State.regs[dstreg1] &= State.regs[srcreg1];
6750 State.regs[dstreg2] >>= IMM4;
6754 // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
6755 8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asl
6759 int srcreg1, srcreg2, dstreg1, dstreg2;
6762 srcreg1 = translate_rreg (SD_, RM1);
6763 srcreg2 = translate_rreg (SD_, RM2);
6764 dstreg1 = translate_rreg (SD_, RN1);
6765 dstreg2 = translate_rreg (SD_, RN2);
6767 State.regs[dstreg1] &= State.regs[srcreg1];
6768 State.regs[dstreg2] <<= State.regs[srcreg2];
6771 // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
6772 8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asl
6776 int srcreg1, dstreg1, dstreg2;
6780 srcreg1 = translate_rreg (SD_, RM1);
6781 dstreg1 = translate_rreg (SD_, RN1);
6782 dstreg2 = translate_rreg (SD_, RN2);
6784 State.regs[dstreg1] &= State.regs[srcreg1];
6785 State.regs[dstreg2] <<= IMM4;
6788 // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
6789 8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_add
6793 int srcreg1, srcreg2, dstreg1, dstreg2;
6794 long temp, temp2, sum;
6797 srcreg1 = translate_rreg (SD_, RM1);
6798 srcreg2 = translate_rreg (SD_, RM2);
6799 dstreg1 = translate_rreg (SD_, RN1);
6800 dstreg2 = translate_rreg (SD_, RN2);
6802 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6803 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6804 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6805 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6806 sum = temp + temp2 + State.regs[REG_MCRL];
6808 State.regs[dstreg1] = sum;
6809 State.regs[dstreg2] += State.regs[srcreg2];
6812 // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
6813 8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_add
6817 int srcreg1, dstreg1, dstreg2;
6818 long temp, temp2, sum;
6821 srcreg1 = translate_rreg (SD_, RM1);
6822 dstreg1 = translate_rreg (SD_, RN1);
6823 dstreg2 = translate_rreg (SD_, RN2);
6825 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6826 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6827 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6828 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6829 sum = temp + temp2 + State.regs[REG_MCRL];
6831 State.regs[dstreg1] = sum;
6832 State.regs[dstreg2] += EXTEND4 (IMM4);
6835 // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
6836 8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_sub
6840 int srcreg1, srcreg2, dstreg1, dstreg2;
6841 long temp, temp2, sum;
6844 srcreg1 = translate_rreg (SD_, RM1);
6845 srcreg2 = translate_rreg (SD_, RM2);
6846 dstreg1 = translate_rreg (SD_, RN1);
6847 dstreg2 = translate_rreg (SD_, RN2);
6849 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6850 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6851 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6852 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6853 sum = temp + temp2 + State.regs[REG_MCRL];
6855 State.regs[dstreg1] = sum;
6856 State.regs[dstreg2] -= State.regs[srcreg2];
6859 // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
6860 8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_sub
6864 int srcreg1, dstreg1, dstreg2;
6865 long temp, temp2, sum;
6868 srcreg1 = translate_rreg (SD_, RM1);
6869 dstreg1 = translate_rreg (SD_, RN1);
6870 dstreg2 = translate_rreg (SD_, RN2);
6872 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6873 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6874 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6875 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6876 sum = temp + temp2 + State.regs[REG_MCRL];
6878 State.regs[dstreg1] = sum;
6879 State.regs[dstreg2] -= EXTEND4 (IMM4);
6882 // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
6883 8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_cmp
6887 int srcreg1, srcreg2, dstreg1, dstreg2;
6888 long temp, temp2, sum;
6891 srcreg1 = translate_rreg (SD_, RM1);
6892 srcreg2 = translate_rreg (SD_, RM2);
6893 dstreg1 = translate_rreg (SD_, RN1);
6894 dstreg2 = translate_rreg (SD_, RN2);
6896 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6897 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6898 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6899 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6900 sum = temp + temp2 + State.regs[REG_MCRL];
6902 State.regs[dstreg1] = sum;
6903 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6906 // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
6907 8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_cmp
6911 int srcreg1, dstreg1, dstreg2;
6912 long temp, temp2, sum;
6915 srcreg1 = translate_rreg (SD_, RM1);
6916 dstreg1 = translate_rreg (SD_, RN1);
6917 dstreg2 = translate_rreg (SD_, RN2);
6919 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6920 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6921 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6922 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6923 sum = temp + temp2 + State.regs[REG_MCRL];
6925 State.regs[dstreg1] = sum;
6926 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6929 // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
6930 8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_mov
6934 int srcreg1, srcreg2, dstreg1, dstreg2;
6935 long temp, temp2, sum;
6938 srcreg1 = translate_rreg (SD_, RM1);
6939 srcreg2 = translate_rreg (SD_, RM2);
6940 dstreg1 = translate_rreg (SD_, RN1);
6941 dstreg2 = translate_rreg (SD_, RN2);
6943 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6944 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6945 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6946 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6947 sum = temp + temp2 + State.regs[REG_MCRL];
6949 State.regs[dstreg1] = sum;
6950 State.regs[dstreg2] = State.regs[srcreg2];
6953 // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
6954 8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_mov
6958 int srcreg1, dstreg1, dstreg2;
6959 long temp, temp2, sum;
6962 srcreg1 = translate_rreg (SD_, RM1);
6963 dstreg1 = translate_rreg (SD_, RN1);
6964 dstreg2 = translate_rreg (SD_, RN2);
6966 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6967 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6968 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6969 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6970 sum = temp + temp2 + State.regs[REG_MCRL];
6972 State.regs[dstreg1] = sum;
6973 State.regs[dstreg2] = EXTEND4 (IMM4);
6976 // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
6977 8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asr
6981 int srcreg1, srcreg2, dstreg1, dstreg2;
6982 long temp, temp2, sum;
6985 srcreg1 = translate_rreg (SD_, RM1);
6986 srcreg2 = translate_rreg (SD_, RM2);
6987 dstreg1 = translate_rreg (SD_, RN1);
6988 dstreg2 = translate_rreg (SD_, RN2);
6990 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6991 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6992 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6993 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6994 sum = temp + temp2 + State.regs[REG_MCRL];
6996 State.regs[dstreg1] = sum;
6997 temp = State.regs[dstreg2];
6998 temp >>= State.regs[srcreg2];
6999 State.regs[dstreg2] = temp;
7002 // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
7003 8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asr
7007 int srcreg1, dstreg1, dstreg2;
7008 long temp, temp2, sum;
7011 srcreg1 = translate_rreg (SD_, RM1);
7012 dstreg1 = translate_rreg (SD_, RN1);
7013 dstreg2 = translate_rreg (SD_, RN2);
7015 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7016 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7017 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7018 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7019 sum = temp + temp2 + State.regs[REG_MCRL];
7021 State.regs[dstreg1] = sum;
7022 temp = State.regs[dstreg2];
7024 State.regs[dstreg2] = temp;
7027 // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
7028 8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_lsr
7032 int srcreg1, srcreg2, dstreg1, dstreg2;
7033 long temp, temp2, sum;
7036 srcreg1 = translate_rreg (SD_, RM1);
7037 srcreg2 = translate_rreg (SD_, RM2);
7038 dstreg1 = translate_rreg (SD_, RN1);
7039 dstreg2 = translate_rreg (SD_, RN2);
7041 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7042 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7043 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7044 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7045 sum = temp + temp2 + State.regs[REG_MCRL];
7047 State.regs[dstreg1] = sum;
7048 State.regs[dstreg2] >>= State.regs[srcreg2];
7051 // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
7052 8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_lsr
7056 int srcreg1, dstreg1, dstreg2;
7057 long temp, temp2, sum;
7060 srcreg1 = translate_rreg (SD_, RM1);
7061 dstreg1 = translate_rreg (SD_, RN1);
7062 dstreg2 = translate_rreg (SD_, RN2);
7064 State.regs[dstreg2] >>= IMM4;
7068 // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
7069 8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asl
7073 int srcreg1, srcreg2, dstreg1, dstreg2;
7074 long temp, temp2, sum;
7077 srcreg1 = translate_rreg (SD_, RM1);
7078 srcreg2 = translate_rreg (SD_, RM2);
7079 dstreg1 = translate_rreg (SD_, RN1);
7080 dstreg2 = translate_rreg (SD_, RN2);
7082 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7083 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7084 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7085 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7086 sum = temp + temp2 + State.regs[REG_MCRL];
7088 State.regs[dstreg1] = sum;
7089 State.regs[dstreg2] <<= State.regs[srcreg2];
7092 // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
7093 8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asl
7097 int srcreg1, dstreg1, dstreg2;
7098 long temp, temp2, sum;
7101 srcreg1 = translate_rreg (SD_, RM1);
7102 dstreg1 = translate_rreg (SD_, RN1);
7103 dstreg2 = translate_rreg (SD_, RN2);
7105 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7106 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7107 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7108 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7109 sum = temp + temp2 + State.regs[REG_MCRL];
7111 State.regs[dstreg1] = sum;
7112 State.regs[dstreg2] <<= IMM4;
7115 // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
7116 8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_add
7120 int srcreg1, srcreg2, dstreg1, dstreg2;
7123 srcreg1 = translate_rreg (SD_, RM1);
7124 srcreg2 = translate_rreg (SD_, RM2);
7125 dstreg1 = translate_rreg (SD_, RN1);
7126 dstreg2 = translate_rreg (SD_, RN2);
7128 State.regs[dstreg1] ^= State.regs[srcreg1];
7129 State.regs[dstreg2] += State.regs[srcreg2];
7132 // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
7133 8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_add
7137 int srcreg1, dstreg1, dstreg2;
7140 srcreg1 = translate_rreg (SD_, RM1);
7141 dstreg1 = translate_rreg (SD_, RN1);
7142 dstreg2 = translate_rreg (SD_, RN2);
7144 State.regs[dstreg1] ^= State.regs[srcreg1];
7145 State.regs[dstreg2] += EXTEND4 (IMM4);
7148 // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
7149 8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_sub
7153 int srcreg1, srcreg2, dstreg1, dstreg2;
7156 srcreg1 = translate_rreg (SD_, RM1);
7157 srcreg2 = translate_rreg (SD_, RM2);
7158 dstreg1 = translate_rreg (SD_, RN1);
7159 dstreg2 = translate_rreg (SD_, RN2);
7161 State.regs[dstreg1] ^= State.regs[srcreg1];
7162 State.regs[dstreg2] -= State.regs[srcreg2];
7165 // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
7166 8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_sub
7170 int srcreg1, dstreg1, dstreg2;
7173 srcreg1 = translate_rreg (SD_, RM1);
7174 dstreg1 = translate_rreg (SD_, RN1);
7175 dstreg2 = translate_rreg (SD_, RN2);
7177 State.regs[dstreg1] ^= State.regs[srcreg1];
7178 State.regs[dstreg2] -= EXTEND4 (IMM4);
7181 // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
7182 8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_cmp
7186 int srcreg1, srcreg2, dstreg1, dstreg2;
7189 srcreg1 = translate_rreg (SD_, RM1);
7190 srcreg2 = translate_rreg (SD_, RM2);
7191 dstreg1 = translate_rreg (SD_, RN1);
7192 dstreg2 = translate_rreg (SD_, RN2);
7194 State.regs[dstreg1] ^= State.regs[srcreg1];
7195 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7198 // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
7199 8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_cmp
7203 int srcreg1, dstreg1, dstreg2;
7206 srcreg1 = translate_rreg (SD_, RM1);
7207 dstreg1 = translate_rreg (SD_, RN1);
7208 dstreg2 = translate_rreg (SD_, RN2);
7210 State.regs[dstreg1] ^= State.regs[srcreg1];
7211 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7214 // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
7215 8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_mov
7219 int srcreg1, srcreg2, dstreg1, dstreg2;
7222 srcreg1 = translate_rreg (SD_, RM1);
7223 srcreg2 = translate_rreg (SD_, RM2);
7224 dstreg1 = translate_rreg (SD_, RN1);
7225 dstreg2 = translate_rreg (SD_, RN2);
7227 State.regs[dstreg1] ^= State.regs[srcreg1];
7228 State.regs[dstreg2] = State.regs[srcreg2];
7231 // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
7232 8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_mov
7236 int srcreg1, dstreg1, dstreg2;
7239 srcreg1 = translate_rreg (SD_, RM1);
7240 dstreg1 = translate_rreg (SD_, RN1);
7241 dstreg2 = translate_rreg (SD_, RN2);
7243 State.regs[dstreg1] ^= State.regs[srcreg1];
7244 State.regs[dstreg2] = EXTEND4 (IMM4);
7247 // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
7248 8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asr
7252 int srcreg1, srcreg2, dstreg1, dstreg2;
7256 srcreg1 = translate_rreg (SD_, RM1);
7257 srcreg2 = translate_rreg (SD_, RM2);
7258 dstreg1 = translate_rreg (SD_, RN1);
7259 dstreg2 = translate_rreg (SD_, RN2);
7261 State.regs[dstreg1] ^= State.regs[srcreg1];
7262 temp = State.regs[dstreg2];
7263 temp >>= State.regs[srcreg2];
7264 State.regs[dstreg2] = temp;
7267 // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
7268 8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asr
7272 int srcreg1, dstreg1, dstreg2;
7276 srcreg1 = translate_rreg (SD_, RM1);
7277 dstreg1 = translate_rreg (SD_, RN1);
7278 dstreg2 = translate_rreg (SD_, RN2);
7280 State.regs[dstreg1] ^= State.regs[srcreg1];
7281 temp = State.regs[dstreg2];
7283 State.regs[dstreg2] = temp;
7286 // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
7287 8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_lsr
7291 int srcreg1, srcreg2, dstreg1, dstreg2;
7294 srcreg1 = translate_rreg (SD_, RM1);
7295 srcreg2 = translate_rreg (SD_, RM2);
7296 dstreg1 = translate_rreg (SD_, RN1);
7297 dstreg2 = translate_rreg (SD_, RN2);
7299 State.regs[dstreg1] ^= State.regs[srcreg1];
7300 State.regs[dstreg2] >>= State.regs[srcreg2];
7303 // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
7304 8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_lsr
7308 int srcreg1, dstreg1, dstreg2;
7312 srcreg1 = translate_rreg (SD_, RM1);
7313 dstreg1 = translate_rreg (SD_, RN1);
7314 dstreg2 = translate_rreg (SD_, RN2);
7316 State.regs[dstreg1] ^= State.regs[srcreg1];
7317 State.regs[dstreg2] >>= IMM4;
7321 // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
7322 8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asl
7326 int srcreg1, srcreg2, dstreg1, dstreg2;
7329 srcreg1 = translate_rreg (SD_, RM1);
7330 srcreg2 = translate_rreg (SD_, RM2);
7331 dstreg1 = translate_rreg (SD_, RN1);
7332 dstreg2 = translate_rreg (SD_, RN2);
7334 State.regs[dstreg1] ^= State.regs[srcreg1];
7335 State.regs[dstreg2] <<= State.regs[srcreg2];
7338 // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
7339 8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asl
7343 int srcreg1, dstreg1, dstreg2;
7347 srcreg1 = translate_rreg (SD_, RM1);
7348 dstreg1 = translate_rreg (SD_, RN1);
7349 dstreg2 = translate_rreg (SD_, RN2);
7351 State.regs[dstreg1] ^= State.regs[srcreg1];
7352 State.regs[dstreg2] <<= IMM4;
7355 // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
7356 8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_add
7360 int srcreg1, srcreg2, dstreg1, dstreg2;
7363 srcreg1 = translate_rreg (SD_, RM1);
7364 srcreg2 = translate_rreg (SD_, RM2);
7365 dstreg1 = translate_rreg (SD_, RN1);
7366 dstreg2 = translate_rreg (SD_, RN2);
7368 State.regs[dstreg1] ^= State.regs[srcreg1];
7369 State.regs[dstreg2] += State.regs[srcreg2];
7372 // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
7373 8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_add
7377 int srcreg1, dstreg1, dstreg2;
7380 srcreg1 = translate_rreg (SD_, RM1);
7381 dstreg1 = translate_rreg (SD_, RN1);
7382 dstreg2 = translate_rreg (SD_, RN2);
7384 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7385 | ((State.regs[srcreg1] >> 16) & 0xffff));
7386 State.regs[dstreg2] += EXTEND4 (IMM4);
7389 // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
7390 8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_sub
7394 int srcreg1, srcreg2, dstreg1, dstreg2;
7397 srcreg1 = translate_rreg (SD_, RM1);
7398 srcreg2 = translate_rreg (SD_, RM2);
7399 dstreg1 = translate_rreg (SD_, RN1);
7400 dstreg2 = translate_rreg (SD_, RN2);
7402 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7403 | ((State.regs[srcreg1] >> 16) & 0xffff));
7404 State.regs[dstreg2] -= State.regs[srcreg2];
7407 // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
7408 8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_sub
7412 int srcreg1, dstreg1, dstreg2;
7415 srcreg1 = translate_rreg (SD_, RM1);
7416 dstreg1 = translate_rreg (SD_, RN1);
7417 dstreg2 = translate_rreg (SD_, RN2);
7419 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7420 | ((State.regs[srcreg1] >> 16) & 0xffff));
7421 State.regs[dstreg2] -= EXTEND4 (IMM4);
7424 // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
7425 8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_cmp
7429 int srcreg1, srcreg2, dstreg1, dstreg2;
7432 srcreg1 = translate_rreg (SD_, RM1);
7433 srcreg2 = translate_rreg (SD_, RM2);
7434 dstreg1 = translate_rreg (SD_, RN1);
7435 dstreg2 = translate_rreg (SD_, RN2);
7437 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7438 | ((State.regs[srcreg1] >> 16) & 0xffff));
7439 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7442 // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
7443 8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_cmp
7447 int srcreg1, dstreg1, dstreg2;
7450 srcreg1 = translate_rreg (SD_, RM1);
7451 dstreg1 = translate_rreg (SD_, RN1);
7452 dstreg2 = translate_rreg (SD_, RN2);
7454 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7455 | ((State.regs[srcreg1] >> 16) & 0xffff));
7456 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7459 // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
7460 8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_mov
7464 int srcreg1, srcreg2, dstreg1, dstreg2;
7467 srcreg1 = translate_rreg (SD_, RM1);
7468 srcreg2 = translate_rreg (SD_, RM2);
7469 dstreg1 = translate_rreg (SD_, RN1);
7470 dstreg2 = translate_rreg (SD_, RN2);
7472 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7473 | ((State.regs[srcreg1] >> 16) & 0xffff));
7474 State.regs[dstreg2] = State.regs[srcreg2];
7477 // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
7478 8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_mov
7482 int srcreg1, dstreg1, dstreg2;
7485 srcreg1 = translate_rreg (SD_, RM1);
7486 dstreg1 = translate_rreg (SD_, RN1);
7487 dstreg2 = translate_rreg (SD_, RN2);
7489 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7490 | ((State.regs[srcreg1] >> 16) & 0xffff));
7491 State.regs[dstreg2] = EXTEND4 (IMM4);
7494 // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
7495 8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asr
7499 int srcreg1, srcreg2, dstreg1, dstreg2;
7503 srcreg1 = translate_rreg (SD_, RM1);
7504 srcreg2 = translate_rreg (SD_, RM2);
7505 dstreg1 = translate_rreg (SD_, RN1);
7506 dstreg2 = translate_rreg (SD_, RN2);
7508 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7509 | ((State.regs[srcreg1] >> 16) & 0xffff));
7510 temp = State.regs[dstreg2];
7511 temp >>= State.regs[srcreg2];
7512 State.regs[dstreg2] = temp;
7515 // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
7516 8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asr
7520 int srcreg1, dstreg1, dstreg2;
7524 srcreg1 = translate_rreg (SD_, RM1);
7525 dstreg1 = translate_rreg (SD_, RN1);
7526 dstreg2 = translate_rreg (SD_, RN2);
7528 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7529 | ((State.regs[srcreg1] >> 16) & 0xffff));
7530 temp = State.regs[dstreg2];
7532 State.regs[dstreg2] = temp;
7535 // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
7536 8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_lsr
7540 int srcreg1, srcreg2, dstreg1, dstreg2;
7543 srcreg1 = translate_rreg (SD_, RM1);
7544 srcreg2 = translate_rreg (SD_, RM2);
7545 dstreg1 = translate_rreg (SD_, RN1);
7546 dstreg2 = translate_rreg (SD_, RN2);
7548 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7549 | ((State.regs[srcreg1] >> 16) & 0xffff));
7550 State.regs[dstreg2] >>= State.regs[srcreg2];
7553 // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
7554 8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_lsr
7558 int srcreg1, dstreg1, dstreg2;
7562 srcreg1 = translate_rreg (SD_, RM1);
7563 dstreg1 = translate_rreg (SD_, RN1);
7564 dstreg2 = translate_rreg (SD_, RN2);
7566 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7567 | ((State.regs[srcreg1] >> 16) & 0xffff));
7568 State.regs[dstreg2] >>= IMM4;
7572 // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
7573 8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asl
7577 int srcreg1, srcreg2, dstreg1, dstreg2;
7580 srcreg1 = translate_rreg (SD_, RM1);
7581 srcreg2 = translate_rreg (SD_, RM2);
7582 dstreg1 = translate_rreg (SD_, RN1);
7583 dstreg2 = translate_rreg (SD_, RN2);
7585 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7586 | ((State.regs[srcreg1] >> 16) & 0xffff));
7587 State.regs[dstreg2] <<= State.regs[srcreg2];
7590 // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
7591 8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asl
7595 int srcreg1, dstreg1, dstreg2;
7599 srcreg1 = translate_rreg (SD_, RM1);
7600 dstreg1 = translate_rreg (SD_, RN1);
7601 dstreg2 = translate_rreg (SD_, RN2);
7603 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7604 | ((State.regs[srcreg1] >> 16) & 0xffff));
7605 State.regs[dstreg2] <<= IMM4;
7608 // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
7609 8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_add
7613 int srcreg1, srcreg2, dstreg1, dstreg2;
7616 srcreg1 = translate_rreg (SD_, RM1);
7617 srcreg2 = translate_rreg (SD_, RM2);
7618 dstreg1 = translate_rreg (SD_, RN1);
7619 dstreg2 = translate_rreg (SD_, RN2);
7621 State.regs[dstreg1] |= State.regs[srcreg1];
7622 State.regs[dstreg2] += State.regs[srcreg2];
7625 // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
7626 8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_add
7630 int srcreg1, dstreg1, dstreg2;
7633 srcreg1 = translate_rreg (SD_, RM1);
7634 dstreg1 = translate_rreg (SD_, RN1);
7635 dstreg2 = translate_rreg (SD_, RN2);
7637 State.regs[dstreg1] |= State.regs[srcreg1];
7638 State.regs[dstreg2] += EXTEND4 (IMM4);
7641 // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
7642 8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_sub
7646 int srcreg1, srcreg2, dstreg1, dstreg2;
7649 srcreg1 = translate_rreg (SD_, RM1);
7650 srcreg2 = translate_rreg (SD_, RM2);
7651 dstreg1 = translate_rreg (SD_, RN1);
7652 dstreg2 = translate_rreg (SD_, RN2);
7654 State.regs[dstreg1] |= State.regs[srcreg1];
7655 State.regs[dstreg2] -= State.regs[srcreg2];
7658 // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
7659 8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_sub
7663 int srcreg1, dstreg1, dstreg2;
7666 srcreg1 = translate_rreg (SD_, RM1);
7667 dstreg1 = translate_rreg (SD_, RN1);
7668 dstreg2 = translate_rreg (SD_, RN2);
7670 State.regs[dstreg1] |= State.regs[srcreg1];
7671 State.regs[dstreg2] -= EXTEND4 (IMM4);
7674 // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
7675 8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_cmp
7679 int srcreg1, srcreg2, dstreg1, dstreg2;
7682 srcreg1 = translate_rreg (SD_, RM1);
7683 srcreg2 = translate_rreg (SD_, RM2);
7684 dstreg1 = translate_rreg (SD_, RN1);
7685 dstreg2 = translate_rreg (SD_, RN2);
7687 State.regs[dstreg1] |= State.regs[srcreg1];
7688 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7691 // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
7692 8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_cmp
7696 int srcreg1, dstreg1, dstreg2;
7699 srcreg1 = translate_rreg (SD_, RM1);
7700 dstreg1 = translate_rreg (SD_, RN1);
7701 dstreg2 = translate_rreg (SD_, RN2);
7703 State.regs[dstreg1] |= State.regs[srcreg1];
7704 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7707 // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
7708 8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_mov
7712 int srcreg1, srcreg2, dstreg1, dstreg2;
7715 srcreg1 = translate_rreg (SD_, RM1);
7716 srcreg2 = translate_rreg (SD_, RM2);
7717 dstreg1 = translate_rreg (SD_, RN1);
7718 dstreg2 = translate_rreg (SD_, RN2);
7720 State.regs[dstreg1] |= State.regs[srcreg1];
7721 State.regs[dstreg2] = State.regs[srcreg2];
7724 // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
7725 8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_mov
7729 int srcreg1, dstreg1, dstreg2;
7732 srcreg1 = translate_rreg (SD_, RM1);
7733 dstreg1 = translate_rreg (SD_, RN1);
7734 dstreg2 = translate_rreg (SD_, RN2);
7736 State.regs[dstreg1] |= State.regs[srcreg1];
7737 State.regs[dstreg2] = EXTEND4 (IMM4);
7740 // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
7741 8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asr
7745 int srcreg1, srcreg2, dstreg1, dstreg2;
7749 srcreg1 = translate_rreg (SD_, RM1);
7750 srcreg2 = translate_rreg (SD_, RM2);
7751 dstreg1 = translate_rreg (SD_, RN1);
7752 dstreg2 = translate_rreg (SD_, RN2);
7754 State.regs[dstreg1] |= State.regs[srcreg1];
7755 temp = State.regs[dstreg2];
7756 temp >>= State.regs[srcreg2];
7757 State.regs[dstreg2] = temp;
7760 // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
7761 8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asr
7765 int srcreg1, dstreg1, dstreg2;
7769 srcreg1 = translate_rreg (SD_, RM1);
7770 dstreg1 = translate_rreg (SD_, RN1);
7771 dstreg2 = translate_rreg (SD_, RN2);
7773 State.regs[dstreg1] |= State.regs[srcreg1];
7774 temp = State.regs[dstreg2];
7776 State.regs[dstreg2] = temp;
7779 // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
7780 8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_lsr
7784 int srcreg1, srcreg2, dstreg1, dstreg2;
7787 srcreg1 = translate_rreg (SD_, RM1);
7788 srcreg2 = translate_rreg (SD_, RM2);
7789 dstreg1 = translate_rreg (SD_, RN1);
7790 dstreg2 = translate_rreg (SD_, RN2);
7792 State.regs[dstreg1] |= State.regs[srcreg1];
7793 State.regs[dstreg2] >>= State.regs[srcreg2];
7796 // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
7797 8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_lsr
7801 int srcreg1, dstreg1, dstreg2;
7805 srcreg1 = translate_rreg (SD_, RM1);
7806 dstreg1 = translate_rreg (SD_, RN1);
7807 dstreg2 = translate_rreg (SD_, RN2);
7809 State.regs[dstreg1] |= State.regs[srcreg1];
7810 State.regs[dstreg2] >>= IMM4;
7814 // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
7815 8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asl
7819 int srcreg1, srcreg2, dstreg1, dstreg2;
7822 srcreg1 = translate_rreg (SD_, RM1);
7823 srcreg2 = translate_rreg (SD_, RM2);
7824 dstreg1 = translate_rreg (SD_, RN1);
7825 dstreg2 = translate_rreg (SD_, RN2);
7827 State.regs[dstreg1] |= State.regs[srcreg1];
7828 State.regs[dstreg2] <<= State.regs[srcreg2];
7831 // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
7832 8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asl
7836 int srcreg1, dstreg1, dstreg2;
7840 srcreg1 = translate_rreg (SD_, RM1);
7841 dstreg1 = translate_rreg (SD_, RN1);
7842 dstreg2 = translate_rreg (SD_, RN2);
7844 State.regs[dstreg1] |= State.regs[srcreg1];
7845 State.regs[dstreg2] <<= IMM4;
7848 // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
7849 8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_add
7853 int srcreg1, srcreg2, dstreg1, dstreg2;
7856 srcreg1 = translate_rreg (SD_, RM1);
7857 srcreg2 = translate_rreg (SD_, RM2);
7858 dstreg1 = translate_rreg (SD_, RN1);
7859 dstreg2 = translate_rreg (SD_, RN2);
7861 if (State.regs[srcreg1] >= 0x7fff)
7862 State.regs[dstreg1] = 0x7fff;
7863 else if (State.regs[srcreg1] <= 0xffff8000)
7864 State.regs[dstreg1] = 0xffff8000;
7866 State.regs[dstreg1] = State.regs[srcreg1];
7868 State.regs[dstreg2] += State.regs[srcreg2];
7871 // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
7872 8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_add
7876 int srcreg1, dstreg1, dstreg2;
7879 srcreg1 = translate_rreg (SD_, RM1);
7880 dstreg1 = translate_rreg (SD_, RN1);
7881 dstreg2 = translate_rreg (SD_, RN2);
7883 if (State.regs[srcreg1] >= 0x7fff)
7884 State.regs[dstreg1] = 0x7fff;
7885 else if (State.regs[srcreg1] <= 0xffff8000)
7886 State.regs[dstreg1] = 0xffff8000;
7888 State.regs[dstreg1] = State.regs[srcreg1];
7890 State.regs[dstreg2] += EXTEND4 (IMM4);
7893 // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
7894 8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_sub
7898 int srcreg1, srcreg2, dstreg1, dstreg2;
7901 srcreg1 = translate_rreg (SD_, RM1);
7902 srcreg2 = translate_rreg (SD_, RM2);
7903 dstreg1 = translate_rreg (SD_, RN1);
7904 dstreg2 = translate_rreg (SD_, RN2);
7906 if (State.regs[srcreg1] >= 0x7fff)
7907 State.regs[dstreg1] = 0x7fff;
7908 else if (State.regs[srcreg1] <= 0xffff8000)
7909 State.regs[dstreg1] = 0xffff8000;
7911 State.regs[dstreg1] = State.regs[srcreg1];
7913 State.regs[dstreg2] -= State.regs[srcreg2];
7916 // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
7917 8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_sub
7921 int srcreg1, dstreg1, dstreg2;
7924 srcreg1 = translate_rreg (SD_, RM1);
7925 dstreg1 = translate_rreg (SD_, RN1);
7926 dstreg2 = translate_rreg (SD_, RN2);
7928 if (State.regs[srcreg1] >= 0x7fff)
7929 State.regs[dstreg1] = 0x7fff;
7930 else if (State.regs[srcreg1] <= 0xffff8000)
7931 State.regs[dstreg1] = 0xffff8000;
7933 State.regs[dstreg1] = State.regs[srcreg1];
7935 State.regs[dstreg2] -= EXTEND4 (IMM4);
7938 // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
7939 8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_cmp
7943 int srcreg1, srcreg2, dstreg1, dstreg2;
7946 srcreg1 = translate_rreg (SD_, RM1);
7947 srcreg2 = translate_rreg (SD_, RM2);
7948 dstreg1 = translate_rreg (SD_, RN1);
7949 dstreg2 = translate_rreg (SD_, RN2);
7951 if (State.regs[srcreg1] >= 0x7fff)
7952 State.regs[dstreg1] = 0x7fff;
7953 else if (State.regs[srcreg1] <= 0xffff8000)
7954 State.regs[dstreg1] = 0xffff8000;
7956 State.regs[dstreg1] = State.regs[srcreg1];
7958 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7961 // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
7962 8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_cmp
7966 int srcreg1, dstreg1, dstreg2;
7969 srcreg1 = translate_rreg (SD_, RM1);
7970 dstreg1 = translate_rreg (SD_, RN1);
7971 dstreg2 = translate_rreg (SD_, RN2);
7973 if (State.regs[srcreg1] >= 0x7fff)
7974 State.regs[dstreg1] = 0x7fff;
7975 else if (State.regs[srcreg1] <= 0xffff8000)
7976 State.regs[dstreg1] = 0xffff8000;
7978 State.regs[dstreg1] = State.regs[srcreg1];
7980 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7983 // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
7984 8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_mov
7988 int srcreg1, srcreg2, dstreg1, dstreg2;
7991 srcreg1 = translate_rreg (SD_, RM1);
7992 srcreg2 = translate_rreg (SD_, RM2);
7993 dstreg1 = translate_rreg (SD_, RN1);
7994 dstreg2 = translate_rreg (SD_, RN2);
7996 if (State.regs[srcreg1] >= 0x7fff)
7997 State.regs[dstreg1] = 0x7fff;
7998 else if (State.regs[srcreg1] <= 0xffff8000)
7999 State.regs[dstreg1] = 0xffff8000;
8001 State.regs[dstreg1] = State.regs[srcreg1];
8003 State.regs[dstreg2] = State.regs[srcreg2];
8006 // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
8007 8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_mov
8011 int srcreg1, dstreg1, dstreg2;
8014 srcreg1 = translate_rreg (SD_, RM1);
8015 dstreg1 = translate_rreg (SD_, RN1);
8016 dstreg2 = translate_rreg (SD_, RN2);
8018 if (State.regs[srcreg1] >= 0x7fff)
8019 State.regs[dstreg1] = 0x7fff;
8020 else if (State.regs[srcreg1] <= 0xffff8000)
8021 State.regs[dstreg1] = 0xffff8000;
8023 State.regs[dstreg1] = State.regs[srcreg1];
8025 State.regs[dstreg2] = EXTEND4 (IMM4);
8028 // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
8029 8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asr
8033 int srcreg1, srcreg2, dstreg1, dstreg2;
8037 srcreg1 = translate_rreg (SD_, RM1);
8038 srcreg2 = translate_rreg (SD_, RM2);
8039 dstreg1 = translate_rreg (SD_, RN1);
8040 dstreg2 = translate_rreg (SD_, RN2);
8042 if (State.regs[srcreg1] >= 0x7fff)
8043 State.regs[dstreg1] = 0x7fff;
8044 else if (State.regs[srcreg1] <= 0xffff8000)
8045 State.regs[dstreg1] = 0xffff8000;
8047 State.regs[dstreg1] = State.regs[srcreg1];
8049 temp = State.regs[dstreg2];
8050 temp >>= State.regs[srcreg2];
8051 State.regs[dstreg2] = temp;
8054 // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
8055 8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asr
8059 int srcreg1, dstreg1, dstreg2;
8063 srcreg1 = translate_rreg (SD_, RM1);
8064 dstreg1 = translate_rreg (SD_, RN1);
8065 dstreg2 = translate_rreg (SD_, RN2);
8067 if (State.regs[srcreg1] >= 0x7fff)
8068 State.regs[dstreg1] = 0x7fff;
8069 else if (State.regs[srcreg1] <= 0xffff8000)
8070 State.regs[dstreg1] = 0xffff8000;
8072 State.regs[dstreg1] = State.regs[srcreg1];
8074 temp = State.regs[dstreg2];
8076 State.regs[dstreg2] = temp;
8079 // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
8080 8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_lsr
8084 int srcreg1, srcreg2, dstreg1, dstreg2;
8087 srcreg1 = translate_rreg (SD_, RM1);
8088 srcreg2 = translate_rreg (SD_, RM2);
8089 dstreg1 = translate_rreg (SD_, RN1);
8090 dstreg2 = translate_rreg (SD_, RN2);
8092 if (State.regs[srcreg1] >= 0x7fff)
8093 State.regs[dstreg1] = 0x7fff;
8094 else if (State.regs[srcreg1] <= 0xffff8000)
8095 State.regs[dstreg1] = 0xffff8000;
8097 State.regs[dstreg1] = State.regs[srcreg1];
8099 State.regs[dstreg2] >>= State.regs[srcreg2];
8102 // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
8103 8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_lsr
8107 int srcreg1, dstreg1, dstreg2;
8111 srcreg1 = translate_rreg (SD_, RM1);
8112 dstreg1 = translate_rreg (SD_, RN1);
8113 dstreg2 = translate_rreg (SD_, RN2);
8115 if (State.regs[srcreg1] >= 0x7fff)
8116 State.regs[dstreg1] = 0x7fff;
8117 else if (State.regs[srcreg1] <= 0xffff8000)
8118 State.regs[dstreg1] = 0xffff8000;
8120 State.regs[dstreg1] = State.regs[srcreg1];
8122 State.regs[dstreg2] >>= IMM4;
8126 // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
8127 8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asl
8131 int srcreg1, srcreg2, dstreg1, dstreg2;
8134 srcreg1 = translate_rreg (SD_, RM1);
8135 srcreg2 = translate_rreg (SD_, RM2);
8136 dstreg1 = translate_rreg (SD_, RN1);
8137 dstreg2 = translate_rreg (SD_, RN2);
8139 if (State.regs[srcreg1] >= 0x7fff)
8140 State.regs[dstreg1] = 0x7fff;
8141 else if (State.regs[srcreg1] <= 0xffff8000)
8142 State.regs[dstreg1] = 0xffff8000;
8144 State.regs[dstreg1] = State.regs[srcreg1];
8146 State.regs[dstreg2] <<= State.regs[srcreg2];
8149 // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
8150 8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asl
8154 int srcreg1, dstreg1, dstreg2;
8158 srcreg1 = translate_rreg (SD_, RM1);
8159 dstreg1 = translate_rreg (SD_, RN1);
8160 dstreg2 = translate_rreg (SD_, RN2);
8162 if (State.regs[srcreg1] >= 0x7fff)
8163 State.regs[dstreg1] = 0x7fff;
8164 else if (State.regs[srcreg1] <= 0xffff8000)
8165 State.regs[dstreg1] = 0xffff8000;
8167 State.regs[dstreg1] = State.regs[srcreg1];
8169 State.regs[dstreg2] <<= IMM4;
8172 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
8173 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x0:D2:::mov_llt
8180 srcreg = translate_rreg (SD_, RM);
8181 dstreg = translate_rreg (SD_, RN);
8183 State.regs[dstreg] = load_word (State.regs[srcreg]);
8184 State.regs[srcreg] += EXTEND4 (IMM4);
8186 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
8188 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8193 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
8194 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x1:D2:::mov_lgt
8201 srcreg = translate_rreg (SD_, RM);
8202 dstreg = translate_rreg (SD_, RN);
8204 State.regs[dstreg] = load_word (State.regs[srcreg]);
8205 State.regs[srcreg] += EXTEND4 (IMM4);
8208 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
8210 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8215 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
8216 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x2:D2:::mov_lge
8223 srcreg = translate_rreg (SD_, RM);
8224 dstreg = translate_rreg (SD_, RN);
8226 State.regs[dstreg] = load_word (State.regs[srcreg]);
8227 State.regs[srcreg] += EXTEND4 (IMM4);
8229 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8231 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8236 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
8237 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x3:D2:::mov_lle
8244 srcreg = translate_rreg (SD_, RM);
8245 dstreg = translate_rreg (SD_, RN);
8247 State.regs[dstreg] = load_word (State.regs[srcreg]);
8248 State.regs[srcreg] += EXTEND4 (IMM4);
8251 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8253 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8258 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
8259 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x4:D2:::mov_lcs
8266 srcreg = translate_rreg (SD_, RM);
8267 dstreg = translate_rreg (SD_, RN);
8269 State.regs[dstreg] = load_word (State.regs[srcreg]);
8270 State.regs[srcreg] += EXTEND4 (IMM4);
8274 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8279 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
8280 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x5:D2:::mov_lhi
8287 srcreg = translate_rreg (SD_, RM);
8288 dstreg = translate_rreg (SD_, RN);
8290 State.regs[dstreg] = load_word (State.regs[srcreg]);
8291 State.regs[srcreg] += EXTEND4 (IMM4);
8293 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
8295 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8300 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
8301 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x6:D2:::mov_lcc
8308 srcreg = translate_rreg (SD_, RM);
8309 dstreg = translate_rreg (SD_, RN);
8311 State.regs[dstreg] = load_word (State.regs[srcreg]);
8312 State.regs[srcreg] += EXTEND4 (IMM4);
8316 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8321 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
8322 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x7:D2:::mov_lls
8329 srcreg = translate_rreg (SD_, RM);
8330 dstreg = translate_rreg (SD_, RN);
8332 State.regs[dstreg] = load_word (State.regs[srcreg]);
8333 State.regs[srcreg] += EXTEND4 (IMM4);
8335 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
8337 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8342 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
8343 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x8:D2:::mov_leq
8350 srcreg = translate_rreg (SD_, RM);
8351 dstreg = translate_rreg (SD_, RN);
8353 State.regs[dstreg] = load_word (State.regs[srcreg]);
8354 State.regs[srcreg] += EXTEND4 (IMM4);
8358 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8363 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
8364 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x9:D2:::mov_lne
8371 srcreg = translate_rreg (SD_, RM);
8372 dstreg = translate_rreg (SD_, RN);
8374 State.regs[dstreg] = load_word (State.regs[srcreg]);
8375 State.regs[srcreg] += EXTEND4 (IMM4);
8379 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8384 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
8385 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0xa:D2:::mov_lra
8392 srcreg = translate_rreg (SD_, RM);
8393 dstreg = translate_rreg (SD_, RN);
8395 State.regs[dstreg] = load_word (State.regs[srcreg]);
8396 State.regs[srcreg] += EXTEND4 (IMM4);
8398 State.regs[REG_PC] = State.regs[REG_LAR] - 4;