3 // Given an extended register number, translate it into an index into the
4 // register array. This is necessary as the upper 8 extended registers are
5 // actually synonyms for the d0-d3/a0-a3 registers.
9 :function:::int:translate_rreg:int rreg
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
22 :function:::int:translate_xreg:int xreg
41 // 1111 0000 0010 00An; mov USP,An
42 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
47 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
51 // 1111 0000 0010 01An; mov SSP,An
52 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
57 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
61 // 1111 0000 0010 10An; mov MSP,An
62 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
67 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
71 // 1111 0000 0010 11An; mov PC,An
72 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
77 State.regs[REG_A0 + AN0] = PC;
81 // 1111 0000 0011 Am00; mov Am,USP
82 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
87 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
90 // 1111 0000 0011 Am01; mov Am,SSP
91 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
96 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
99 // 1111 0000 0011 Am10; mov Am,MSP
100 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
105 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
109 // 1111 0000 1110 imm4; syscall
110 8.0xf0+4.0xe,IMM4:D0t:::syscall
114 unsigned32 sp, next_pc;
117 sp = State.regs[REG_SP];
118 next_pc = State.regs[REG_PC] + 2;
119 store_word (sp - 4, next_pc);
120 store_word (sp - 8, PSW);
121 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
126 // 1111 0010 1110 11Dn; mov EPSW,Dn
127 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
132 State.regs[REG_D0 + DN0] = PSW;
136 // 1111 0010 1111 Dm01; mov Dm,EPSW
137 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
142 PSW = State.regs[REG_D0 + DM1];
145 // 1111 0101 00Am Rn; mov Am,Rn
146 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
150 int destreg = translate_rreg (SD_, RN0);
153 State.regs[destreg] = State.regs[REG_A0 + AM1];
156 // 1111 0101 01Dm Rn; mov Dm,Rn
157 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
161 int destreg = translate_rreg (SD_, RN0);
164 State.regs[destreg] = State.regs[REG_D0 + DM1];
167 // 1111 0101 10Rm An; mov Rm,An
168 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
172 int destreg = translate_rreg (SD_, RM1);
175 State.regs[REG_A0 + AN0] = State.regs[destreg];
178 // 1111 0101 11Rm Dn; mov Rm,Dn
179 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
183 int destreg = translate_rreg (SD_, RM1);
186 State.regs[REG_D0 + DN0] = State.regs[destreg];
190 // 1111 1000 1100 1110 regs....; movm (USP),regs
191 8.0xf8+8.0xce+8.REGS:D1a:::movm
195 unsigned32 usp = State.regs[REG_USP];
204 State.regs[REG_LAR] = load_word (usp);
206 State.regs[REG_LIR] = load_word (usp);
208 State.regs[REG_MDR] = load_word (usp);
210 State.regs[REG_A0 + 1] = load_word (usp);
212 State.regs[REG_A0] = load_word (usp);
214 State.regs[REG_D0 + 1] = load_word (usp);
216 State.regs[REG_D0] = load_word (usp);
222 State.regs[REG_A0 + 3] = load_word (usp);
228 State.regs[REG_A0 + 2] = load_word (usp);
234 State.regs[REG_D0 + 3] = load_word (usp);
240 State.regs[REG_D0 + 2] = load_word (usp);
244 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
249 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
251 State.regs[REG_E0 + 1] = load_word (usp);
253 State.regs[REG_E0 + 0] = load_word (usp);
259 State.regs[REG_E0 + 7] = load_word (usp);
261 State.regs[REG_E0 + 6] = load_word (usp);
263 State.regs[REG_E0 + 5] = load_word (usp);
265 State.regs[REG_E0 + 4] = load_word (usp);
271 State.regs[REG_E0 + 3] = load_word (usp);
273 State.regs[REG_E0 + 2] = load_word (usp);
278 /* And make sure to update the stack pointer. */
279 State.regs[REG_USP] = usp;
282 // 1111 1000 1100 1111 regs....; movm (USP),regs
283 8.0xf8+8.0xcf+8.REGS:D1b:::movm
287 unsigned32 usp = State.regs[REG_USP];
293 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
299 store_word (usp, State.regs[REG_E0 + 2]);
301 store_word (usp, State.regs[REG_E0 + 3]);
307 store_word (usp, State.regs[REG_E0 + 4]);
309 store_word (usp, State.regs[REG_E0 + 5]);
311 store_word (usp, State.regs[REG_E0 + 6]);
313 store_word (usp, State.regs[REG_E0 + 7]);
319 store_word (usp, State.regs[REG_E0 + 0]);
321 store_word (usp, State.regs[REG_E0 + 1]);
323 /* Need to save MDQR, MCRH, MCRL, and MCVF */
330 store_word (usp, State.regs[REG_D0 + 2]);
336 store_word (usp, State.regs[REG_D0 + 3]);
342 store_word (usp, State.regs[REG_A0 + 2]);
348 store_word (usp, State.regs[REG_A0 + 3]);
354 store_word (usp, State.regs[REG_D0]);
356 store_word (usp, State.regs[REG_D0 + 1]);
358 store_word (usp, State.regs[REG_A0]);
360 store_word (usp, State.regs[REG_A0 + 1]);
362 store_word (usp, State.regs[REG_MDR]);
364 store_word (usp, State.regs[REG_LIR]);
366 store_word (usp, State.regs[REG_LAR]);
370 /* And make sure to update the stack pointer. */
371 State.regs[REG_USP] = usp;
374 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
375 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
380 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
383 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
384 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
389 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
392 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
393 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
401 srcreg = translate_rreg (SD_, RM2);
402 dstreg = translate_rreg (SD_, RN0);
403 State.regs[dstreg] = State.regs[srcreg];
406 // 1111 1001 0001 1000 Rn Rn; ext Rn
407 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
414 srcreg = translate_rreg (SD_, RN0);
415 if (State.regs[srcreg] & 0x80000000)
416 State.regs[REG_MDR] = -1;
418 State.regs[REG_MDR] = 0;
421 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
422 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
429 srcreg = translate_rreg (SD_, RM2);
430 dstreg = translate_rreg (SD_, RN0);
431 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
434 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
435 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
442 srcreg = translate_rreg (SD_, RM2);
443 dstreg = translate_rreg (SD_, RN0);
444 State.regs[dstreg] = State.regs[srcreg] & 0xff;
447 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
448 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
455 srcreg = translate_rreg (SD_, RM2);
456 dstreg = translate_rreg (SD_, RN0);
457 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
460 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
461 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
468 srcreg = translate_rreg (SD_, RM2);
469 dstreg = translate_rreg (SD_, RN0);
470 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
473 // 1111 1001 0110 1000 Rn Rn; clr Rn
474 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
481 dstreg = translate_rreg (SD_, RN0);
482 State.regs[dstreg] = 0;
484 PSW &= ~(PSW_V | PSW_C | PSW_N);
487 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
488 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
495 srcreg = translate_rreg (SD_, RM2);
496 dstreg = translate_rreg (SD_, RN0);
497 genericAdd (State.regs[srcreg], dstreg);
500 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
501 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
507 unsigned32 reg1, reg2, sum;
510 srcreg = translate_rreg (SD_, RM2);
511 dstreg = translate_rreg (SD_, RN0);
513 reg1 = State.regs[srcreg];
514 reg2 = State.regs[dstreg];
515 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
516 State.regs[dstreg] = sum;
518 z = ((PSW & PSW_Z) != 0) && (sum == 0);
519 n = (sum & 0x80000000);
520 c = (sum < reg1) || (sum < reg2);
521 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
522 && (reg2 & 0x80000000) != (sum & 0x80000000));
524 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
525 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
526 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
529 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
530 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
537 srcreg = translate_rreg (SD_, RM2);
538 dstreg = translate_rreg (SD_, RN0);
539 genericSub (State.regs[srcreg], dstreg);
542 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
543 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
549 unsigned32 reg1, reg2, difference;
552 srcreg = translate_rreg (SD_, RM2);
553 dstreg = translate_rreg (SD_, RN0);
555 reg1 = State.regs[srcreg];
556 reg2 = State.regs[dstreg];
557 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
558 State.regs[dstreg] = difference;
560 z = ((PSW & PSW_Z) != 0) && (difference == 0);
561 n = (difference & 0x80000000);
563 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
564 && (reg2 & 0x80000000) != (difference & 0x80000000));
566 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
567 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
568 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
571 // 1111 1001 1011 1000 Rn Rn; inc Rn
572 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
579 dstreg = translate_rreg (SD_, RN0);
580 genericAdd (1, dstreg);
583 // 1111 1001 1101 1000 Rn Rn; inc Rn
584 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
591 dstreg = translate_rreg (SD_, RN0);
592 genericAdd (4, dstreg);
595 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
596 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
600 int srcreg1, srcreg2;
603 srcreg1 = translate_rreg (SD_, RN0);
604 srcreg2 = translate_rreg (SD_, RM2);
605 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
608 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
609 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
616 dstreg = translate_rreg (SD_, RN0);
617 srcreg = translate_xreg (SD_, XRM2);
619 State.regs[dstreg] = State.regs[srcreg];
622 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
623 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
630 srcreg = translate_rreg (SD_, RM2);
631 dstreg = translate_xreg (SD_, XRN0);
633 State.regs[dstreg] = State.regs[srcreg];
636 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
637 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
646 srcreg = translate_rreg (SD_, RM2);
647 dstreg = translate_rreg (SD_, RN0);
649 State.regs[dstreg] &= State.regs[srcreg];
650 z = (State.regs[dstreg] == 0);
651 n = (State.regs[dstreg] & 0x80000000) != 0;
652 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
653 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
656 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
657 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
665 srcreg = translate_rreg (SD_, RM2);
666 dstreg = translate_rreg (SD_, RN0);
668 State.regs[dstreg] |= State.regs[srcreg];
669 z = (State.regs[dstreg] == 0);
670 n = (State.regs[dstreg] & 0x80000000) != 0;
671 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
672 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
675 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
676 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
684 srcreg = translate_rreg (SD_, RM2);
685 dstreg = translate_rreg (SD_, RN0);
687 State.regs[dstreg] ^= State.regs[srcreg];
688 z = (State.regs[dstreg] == 0);
689 n = (State.regs[dstreg] & 0x80000000) != 0;
690 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
691 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
694 // 1111 1001 0011 1001 Rn Rn; not Rn
695 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
703 dstreg = translate_rreg (SD_, RN0);
705 State.regs[dstreg] = ~State.regs[dstreg];
706 z = (State.regs[dstreg] == 0);
707 n = (State.regs[dstreg] & 0x80000000) != 0;
708 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
709 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
712 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
713 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
722 srcreg = translate_rreg (SD_, RM2);
723 dstreg = translate_rreg (SD_, RN0);
725 temp = State.regs[dstreg];
727 temp >>= State.regs[srcreg];
728 State.regs[dstreg] = temp;
729 z = (State.regs[dstreg] == 0);
730 n = (State.regs[dstreg] & 0x80000000) != 0;
731 PSW &= ~(PSW_Z | PSW_N | PSW_C);
732 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
735 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
736 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
745 srcreg = translate_rreg (SD_, RM2);
746 dstreg = translate_rreg (SD_, RN0);
748 c = State.regs[dstreg] & 1;
749 State.regs[dstreg] >>= State.regs[srcreg];
750 z = (State.regs[dstreg] == 0);
751 n = (State.regs[dstreg] & 0x80000000) != 0;
752 PSW &= ~(PSW_Z | PSW_N | PSW_C);
753 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
756 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
757 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
765 srcreg = translate_rreg (SD_, RM2);
766 dstreg = translate_rreg (SD_, RN0);
768 State.regs[dstreg] <<= State.regs[srcreg];
769 z = (State.regs[dstreg] == 0);
770 n = (State.regs[dstreg] & 0x80000000) != 0;
771 PSW &= ~(PSW_Z | PSW_N);
772 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
775 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
776 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
784 dstreg = translate_rreg (SD_, RN0);
786 State.regs[dstreg] <<= 2;
787 z = (State.regs[dstreg] == 0);
788 n = (State.regs[dstreg] & 0x80000000) != 0;
789 PSW &= ~(PSW_Z | PSW_N);
790 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
793 // 1111 1001 1000 1001 Rn Rn; ror Rn
794 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
803 dstreg = translate_rreg (SD_, RN0);
805 value = State.regs[dstreg];
809 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
810 State.regs[dstreg] = value;
812 n = (value & 0x80000000) != 0;
813 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
814 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
817 // 1111 1001 1001 1001 Rn Rn; rol Rn
818 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
827 dstreg = translate_rreg (SD_, RN0);
829 value = State.regs[dstreg];
830 c = (value & 0x80000000) ? 1 : 0;
833 value |= ((PSW & PSW_C) != 0);
834 State.regs[dstreg] = value;
836 n = (value & 0x80000000) != 0;
837 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
838 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
841 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
842 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
851 srcreg = translate_rreg (SD_, RM2);
852 dstreg = translate_rreg (SD_, RN0);
854 temp = ((signed64)(signed32)State.regs[dstreg]
855 * (signed64)(signed32)State.regs[srcreg]);
856 State.regs[dstreg] = temp & 0xffffffff;
857 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
858 z = (State.regs[dstreg] == 0);
859 n = (State.regs[dstreg] & 0x80000000) != 0;
860 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
861 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
864 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
865 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
874 srcreg = translate_rreg (SD_, RM2);
875 dstreg = translate_rreg (SD_, RN0);
877 temp = ((unsigned64)State.regs[dstreg]
878 * (unsigned64)State.regs[srcreg]);
879 State.regs[dstreg] = temp & 0xffffffff;
880 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
881 z = (State.regs[dstreg] == 0);
882 n = (State.regs[dstreg] & 0x80000000) != 0;
883 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
884 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
887 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
888 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
897 srcreg = translate_rreg (SD_, RM2);
898 dstreg = translate_rreg (SD_, RN0);
900 temp = State.regs[REG_MDR];
902 temp |= State.regs[dstreg];
903 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
904 temp /= (signed32)State.regs[srcreg];
905 State.regs[dstreg] = temp & 0xffffffff;
906 z = (State.regs[dstreg] == 0);
907 n = (State.regs[dstreg] & 0x80000000) != 0;
908 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
909 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
912 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
913 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
922 srcreg = translate_rreg (SD_, RM2);
923 dstreg = translate_rreg (SD_, RN0);
925 temp = State.regs[REG_MDR];
927 temp |= State.regs[dstreg];
928 State.regs[REG_MDR] = temp % State.regs[srcreg];
929 temp /= State.regs[srcreg];
930 State.regs[dstreg] = temp & 0xffffffff;
931 z = (State.regs[dstreg] == 0);
932 n = (State.regs[dstreg] & 0x80000000) != 0;
933 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
934 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
938 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
939 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
946 srcreg = translate_rreg (SD_, RM0);
947 dstreg = translate_rreg (SD_, RN2);
948 State.regs[dstreg] = load_word (State.regs[srcreg]);
951 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
952 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
959 srcreg = translate_rreg (SD_, RM2);
960 dstreg = translate_rreg (SD_, RN0);
961 store_word (State.regs[dstreg], State.regs[srcreg]);
964 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
965 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
972 srcreg = translate_rreg (SD_, RM0);
973 dstreg = translate_rreg (SD_, RN2);
974 State.regs[dstreg] = load_byte (State.regs[srcreg]);
977 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
978 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
985 srcreg = translate_rreg (SD_, RM2);
986 dstreg = translate_rreg (SD_, RN0);
987 store_byte (State.regs[dstreg], State.regs[srcreg]);
990 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
991 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
998 srcreg = translate_rreg (SD_, RM0);
999 dstreg = translate_rreg (SD_, RN2);
1000 State.regs[dstreg] = load_half (State.regs[srcreg]);
1003 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
1004 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1011 srcreg = translate_rreg (SD_, RM2);
1012 dstreg = translate_rreg (SD_, RN0);
1013 store_half (State.regs[dstreg], State.regs[srcreg]);
1016 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1017 8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
1024 srcreg = translate_rreg (SD_, RM0);
1025 dstreg = translate_rreg (SD_, RN2);
1026 State.regs[dstreg] = load_word (State.regs[srcreg]);
1027 State.regs[srcreg] += 4;
1030 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1031 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1038 srcreg = translate_rreg (SD_, RM2);
1039 dstreg = translate_rreg (SD_, RN0);
1040 store_word (State.regs[dstreg], State.regs[srcreg]);
1041 State.regs[dstreg] += 4;
1044 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1045 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1052 dstreg = translate_rreg (SD_, RN2);
1053 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1056 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1057 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1064 srcreg = translate_rreg (SD_, RM2);
1065 store_word (State.regs[REG_SP], State.regs[srcreg]);
1068 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1069 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1076 dstreg = translate_rreg (SD_, RN2);
1077 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1080 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1081 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1088 srcreg = translate_rreg (SD_, RM2);
1089 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1092 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1093 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1100 dstreg = translate_rreg (SD_, RN2);
1101 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1104 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1105 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1112 srcreg = translate_rreg (SD_, RM2);
1113 store_half (State.regs[REG_SP], State.regs[srcreg]);
1116 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1117 8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
1124 srcreg = translate_rreg (SD_, RM0);
1125 dstreg = translate_rreg (SD_, RN2);
1126 State.regs[dstreg] = load_half (State.regs[srcreg]);
1127 State.regs[srcreg] += 2;
1130 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1131 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1138 srcreg = translate_rreg (SD_, RM2);
1139 dstreg = translate_rreg (SD_, RN0);
1140 store_half (State.regs[dstreg], State.regs[srcreg]);
1141 State.regs[dstreg] += 2;
1145 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1146 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1150 int srcreg1, srcreg2;
1155 srcreg1 = translate_rreg (SD_, RM2);
1156 srcreg2 = translate_rreg (SD_, RN0);
1158 temp = ((signed64)(signed32)State.regs[srcreg2]
1159 * (signed64)(signed32)State.regs[srcreg1]);
1160 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1161 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1162 State.regs[REG_MCRL] = sum;
1165 sum = State.regs[REG_MCRH] + temp + c;
1166 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1167 && (temp & 0x80000000) != (sum & 0x80000000));
1168 State.regs[REG_MCRH] = sum;
1170 State.regs[REG_MCVF] = 1;
1173 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1174 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1178 int srcreg1, srcreg2;
1179 unsigned64 temp, sum;
1183 srcreg1 = translate_rreg (SD_, RM2);
1184 srcreg2 = translate_rreg (SD_, RN0);
1186 temp = ((unsigned64)State.regs[srcreg2]
1187 * (unsigned64)State.regs[srcreg1]);
1188 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1189 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1190 State.regs[REG_MCRL] = sum;
1193 sum = State.regs[REG_MCRH] + temp + c;
1194 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1195 && (temp & 0x80000000) != (sum & 0x80000000));
1196 State.regs[REG_MCRH] = sum;
1198 State.regs[REG_MCVF] = 1;
1201 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1202 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1206 int srcreg1, srcreg2;
1211 srcreg1 = translate_rreg (SD_, RM2);
1212 srcreg2 = translate_rreg (SD_, RN0);
1214 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1215 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
1216 sum = State.regs[REG_MCRL] + temp;
1217 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1218 && (temp & 0x80000000) != (sum & 0x80000000));
1219 State.regs[REG_MCRL] = sum;
1221 State.regs[REG_MCVF] = 1;
1224 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1225 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1229 int srcreg1, srcreg2;
1234 srcreg1 = translate_rreg (SD_, RM2);
1235 srcreg2 = translate_rreg (SD_, RN0);
1237 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1238 * (unsigned32)(State.regs[srcreg1] & 0xff));
1239 sum = State.regs[REG_MCRL] + temp;
1240 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1241 && (temp & 0x80000000) != (sum & 0x80000000));
1242 State.regs[REG_MCRL] = sum;
1244 State.regs[REG_MCVF] = 1;
1247 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1248 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1252 int srcreg1, srcreg2;
1257 srcreg1 = translate_rreg (SD_, RM2);
1258 srcreg2 = translate_rreg (SD_, RN0);
1260 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1261 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
1262 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1263 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1264 State.regs[REG_MCRL] = sum;
1267 sum = State.regs[REG_MCRH] + temp + c;
1268 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1269 && (temp & 0x80000000) != (sum & 0x80000000));
1270 State.regs[REG_MCRH] = sum;
1272 State.regs[REG_MCVF] = 1;
1275 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1276 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1280 int srcreg1, srcreg2;
1285 srcreg1 = translate_rreg (SD_, RM2);
1286 srcreg2 = translate_rreg (SD_, RN0);
1288 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1289 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1290 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1291 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1292 State.regs[REG_MCRL] = sum;
1295 sum = State.regs[REG_MCRH] + temp + c;
1296 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1297 && (temp & 0x80000000) != (sum & 0x80000000));
1298 State.regs[REG_MCRH] = sum;
1300 State.regs[REG_MCVF] = 1;
1303 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1304 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1308 int srcreg1, srcreg2;
1309 signed32 temp, temp2, sum;
1313 srcreg1 = translate_rreg (SD_, RM2);
1314 srcreg2 = translate_rreg (SD_, RN0);
1316 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1317 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1318 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1319 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
1320 sum = temp + temp2 + State.regs[REG_MCRL];
1321 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1322 && (temp & 0x80000000) != (sum & 0x80000000));
1323 State.regs[REG_MCRL] = sum;
1325 State.regs[REG_MCVF] = 1;
1328 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1329 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1333 int srcreg1, srcreg2;
1334 unsigned32 temp, temp2, sum;
1338 srcreg1 = translate_rreg (SD_, RM2);
1339 srcreg2 = translate_rreg (SD_, RN0);
1341 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1342 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1343 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1344 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1345 sum = temp + temp2 + State.regs[REG_MCRL];
1346 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1347 && (temp & 0x80000000) != (sum & 0x80000000));
1348 State.regs[REG_MCRL] = sum;
1350 State.regs[REG_MCVF] = 1;
1353 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1354 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1362 srcreg = translate_rreg (SD_, RM2);
1363 dstreg = translate_rreg (SD_, RN0);
1365 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1366 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
1367 State.regs[REG_MDRQ] = temp;
1368 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1369 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
1370 State.regs[dstreg] = temp;
1373 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1374 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1382 srcreg = translate_rreg (SD_, RM2);
1383 dstreg = translate_rreg (SD_, RN0);
1385 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1386 * (unsigned32)(State.regs[srcreg] & 0xffff));
1387 State.regs[REG_MDRQ] = temp;
1388 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1389 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1390 State.regs[dstreg] = temp;
1393 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1394 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1402 srcreg = translate_rreg (SD_, RM2);
1403 dstreg = translate_rreg (SD_, RN0);
1405 value = State.regs[srcreg];
1407 if (value >= 0x7fff)
1408 State.regs[dstreg] = 0x7fff;
1409 else if (value <= 0xffff8000)
1410 State.regs[dstreg] = 0xffff8000;
1412 State.regs[dstreg] = value;
1414 n = (State.regs[dstreg] & 0x8000) != 0;
1415 z = (State.regs[dstreg] == 0);
1416 PSW &= ~(PSW_Z | PSW_N);
1417 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1420 // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
1421 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1428 srcreg = translate_rreg (SD_, RM2);
1429 dstreg = translate_rreg (SD_, RN0);
1431 PSW &= ~(PSW_V | PSW_C);
1432 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1434 /* 32bit saturation. */
1435 if (State.regs[srcreg] == 0x20)
1439 tmp = State.regs[REG_MCRH];
1441 tmp += State.regs[REG_MCRL];
1443 if (tmp > 0x7fffffff)
1444 State.regs[dstreg] = 0x7fffffff;
1445 else if (tmp < 0xffffffff80000000LL)
1446 State.regs[dstreg] = 0x80000000;
1448 State.regs[dstreg] = tmp;
1450 /* 16bit saturation */
1451 else if (State.regs[srcreg] == 0x10)
1455 tmp = State.regs[REG_MCRH];
1457 tmp += State.regs[REG_MCRL];
1460 State.regs[dstreg] = 0x7fff;
1461 else if (tmp < 0xffffffffffff8000LL)
1462 State.regs[dstreg] = 0x8000;
1464 State.regs[dstreg] = tmp;
1466 /* 8 bit saturation */
1467 else if (State.regs[srcreg] == 0x8)
1471 tmp = State.regs[REG_MCRH];
1473 tmp += State.regs[REG_MCRL];
1476 State.regs[dstreg] = 0x7f;
1477 else if (tmp < 0xffffffffffffff80LL)
1478 State.regs[dstreg] = 0x80;
1480 State.regs[dstreg] = tmp;
1482 /* 9 bit saturation */
1483 else if (State.regs[srcreg] == 0x9)
1487 tmp = State.regs[REG_MCRH];
1489 tmp += State.regs[REG_MCRL];
1492 State.regs[dstreg] = 0x80;
1493 else if (tmp < 0xffffffffffffff81LL)
1494 State.regs[dstreg] = 0x81;
1496 State.regs[dstreg] = tmp;
1498 /* 9 bit saturation */
1499 else if (State.regs[srcreg] == 0x30)
1503 tmp = State.regs[REG_MCRH];
1505 tmp += State.regs[REG_MCRL];
1507 if (tmp > 0x7fffffffffffLL)
1508 tmp = 0x7fffffffffffLL;
1509 else if (tmp < 0xffff800000000000LL)
1510 tmp = 0xffff800000000000LL;
1513 State.regs[dstreg] = tmp;
1517 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1518 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1525 srcreg = translate_rreg (SD_, RM2);
1526 dstreg = translate_rreg (SD_, RN0);
1528 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1529 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1530 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1531 | ((State.regs[srcreg] >> 24) & 0xff));
1534 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1535 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1542 srcreg = translate_rreg (SD_, RM2);
1543 dstreg = translate_rreg (SD_, RN0);
1545 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1546 | ((State.regs[srcreg] >> 8) & 0xff)
1547 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1548 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1551 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1552 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1559 srcreg = translate_rreg (SD_, RM2);
1560 dstreg = translate_rreg (SD_, RN0);
1562 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1563 | ((State.regs[srcreg] >> 16) & 0xffff));
1566 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1567 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1576 srcreg = translate_rreg (SD_, RM2);
1577 dstreg = translate_rreg (SD_, RN0);
1579 temp = State.regs[srcreg];
1580 start = (State.regs[dstreg] & 0x1f) - 1;
1585 for (i = start; i >= 0; i--)
1587 if (temp & (1 << i))
1590 State.regs[dstreg] = i;
1598 State.regs[dstreg] = 0;
1601 PSW |= (c ? PSW_C : 0);
1605 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1606 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1613 dstreg = translate_rreg (SD_, RN0);
1614 State.regs[dstreg] = EXTEND8 (IMM8);
1617 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1618 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1625 dstreg = translate_rreg (SD_, RN0);
1626 State.regs[dstreg] = IMM8 & 0xff;
1629 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1630 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1637 dstreg = translate_rreg (SD_, RN0);
1638 genericAdd (EXTEND8 (IMM8), dstreg);
1641 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1642 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1648 unsigned32 reg2, sum;
1651 dstreg = translate_rreg (SD_, RN0);
1653 imm = EXTEND8 (IMM8);
1654 reg2 = State.regs[dstreg];
1655 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1656 State.regs[dstreg] = sum;
1658 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1659 n = (sum & 0x80000000);
1660 c = (sum < imm) || (sum < reg2);
1661 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1662 && (reg2 & 0x80000000) != (sum & 0x80000000));
1664 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1665 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1666 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1669 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1670 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1677 dstreg = translate_rreg (SD_, RN0);
1679 genericSub (EXTEND8 (IMM8), dstreg);
1682 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1683 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1689 unsigned32 reg2, difference;
1692 dstreg = translate_rreg (SD_, RN0);
1694 imm = EXTEND8 (IMM8);
1695 reg2 = State.regs[dstreg];
1696 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1697 State.regs[dstreg] = difference;
1699 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1700 n = (difference & 0x80000000);
1702 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1703 && (reg2 & 0x80000000) != (difference & 0x80000000));
1705 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1706 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1707 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1710 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1711 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1718 srcreg = translate_rreg (SD_, RN0);
1719 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1722 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1723 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1730 dstreg = translate_xreg (SD_, XRN0);
1732 State.regs[dstreg] = IMM8;
1735 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1736 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1744 dstreg = translate_rreg (SD_, RN0);
1746 State.regs[dstreg] &= (IMM8 & 0xff);
1747 z = (State.regs[dstreg] == 0);
1748 n = (State.regs[dstreg] & 0x80000000) != 0;
1749 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1750 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1753 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1754 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1762 dstreg = translate_rreg (SD_, RN0);
1764 State.regs[dstreg] |= (IMM8 & 0xff);
1765 z = (State.regs[dstreg] == 0);
1766 n = (State.regs[dstreg] & 0x80000000) != 0;
1767 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1768 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1771 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1772 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1780 dstreg = translate_rreg (SD_, RN0);
1782 State.regs[dstreg] ^= (IMM8 & 0xff);
1783 z = (State.regs[dstreg] == 0);
1784 n = (State.regs[dstreg] & 0x80000000) != 0;
1785 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1786 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1789 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1790 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1799 dstreg = translate_rreg (SD_, RN0);
1801 temp = State.regs[dstreg];
1803 temp >>= (IMM8 & 0xff);
1804 State.regs[dstreg] = temp;
1805 z = (State.regs[dstreg] == 0);
1806 n = (State.regs[dstreg] & 0x80000000) != 0;
1807 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1808 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1811 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1812 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1820 dstreg = translate_rreg (SD_, RN0);
1822 c = State.regs[dstreg] & 1;
1823 State.regs[dstreg] >>= (IMM8 & 0xff);
1824 z = (State.regs[dstreg] == 0);
1825 n = (State.regs[dstreg] & 0x80000000) != 0;
1826 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1827 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1830 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1831 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1839 dstreg = translate_rreg (SD_, RN0);
1841 State.regs[dstreg] <<= (IMM8 & 0xff);
1842 z = (State.regs[dstreg] == 0);
1843 n = (State.regs[dstreg] & 0x80000000) != 0;
1844 PSW &= ~(PSW_Z | PSW_N);
1845 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1848 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1849 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1858 dstreg = translate_rreg (SD_, RN0);
1860 temp = ((signed64)(signed32)State.regs[dstreg]
1861 * (signed64)(signed32)EXTEND8 (IMM8));
1862 State.regs[dstreg] = temp & 0xffffffff;
1863 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1864 z = (State.regs[dstreg] == 0);
1865 n = (State.regs[dstreg] & 0x80000000) != 0;
1866 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1867 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1870 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1871 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1880 dstreg = translate_rreg (SD_, RN0);
1882 temp = ((unsigned64)State.regs[dstreg]
1883 * (unsigned64)(IMM8 & 0xff));
1884 State.regs[dstreg] = temp & 0xffffffff;
1885 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1886 z = (State.regs[dstreg] == 0);
1887 n = (State.regs[dstreg] & 0x80000000) != 0;
1888 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1889 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1892 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1893 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1900 srcreg = translate_rreg (SD_, RM0);
1901 genericBtst(IMM8, State.regs[srcreg]);
1904 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1905 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1912 srcreg = translate_rreg (SD_, RM0);
1913 dstreg = translate_rreg (SD_, RN2);
1914 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1917 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1918 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1925 srcreg = translate_rreg (SD_, RM2);
1926 dstreg = translate_rreg (SD_, RN0);
1927 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1930 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1931 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1938 srcreg = translate_rreg (SD_, RM0);
1939 dstreg = translate_rreg (SD_, RN2);
1940 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1943 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1944 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1951 srcreg = translate_rreg (SD_, RM2);
1952 dstreg = translate_rreg (SD_, RN0);
1953 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1956 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1957 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1964 srcreg = translate_rreg (SD_, RM0);
1965 dstreg = translate_rreg (SD_, RN2);
1966 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1969 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1970 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1977 srcreg = translate_rreg (SD_, RM2);
1978 dstreg = translate_rreg (SD_, RN0);
1979 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1982 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1983 8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
1990 srcreg = translate_rreg (SD_, RM0);
1991 dstreg = translate_rreg (SD_, RN2);
1992 State.regs[dstreg] = load_word (State.regs[srcreg]);
1993 State.regs[srcreg] += EXTEND8 (IMM8);
1996 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1997 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
2004 srcreg = translate_rreg (SD_, RM2);
2005 dstreg = translate_rreg (SD_, RN0);
2006 store_word (State.regs[dstreg], State.regs[srcreg]);
2007 State.regs[dstreg] += EXTEND8 (IMM8);
2011 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
2012 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2019 dstreg = translate_rreg (SD_, RN2);
2020 State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8);
2023 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,sp)
2024 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2031 srcreg = translate_rreg (SD_, RM2);
2032 store_word (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
2035 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2036 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2043 dstreg = translate_rreg (SD_, RN2);
2044 State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8);
2047 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(d8,sp)
2048 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2055 srcreg = translate_rreg (SD_, RM2);
2056 store_byte (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
2059 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2060 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2067 dstreg = translate_rreg (SD_, RN2);
2068 State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8);
2071 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2072 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2079 srcreg = translate_rreg (SD_, RM2);
2080 store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
2083 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2084 8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
2091 srcreg = translate_rreg (SD_, RM0);
2092 dstreg = translate_rreg (SD_, RN2);
2093 State.regs[dstreg] = load_half (State.regs[srcreg]);
2094 State.regs[srcreg] += EXTEND8 (IMM8);
2097 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2098 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2105 srcreg = translate_rreg (SD_, RM2);
2106 dstreg = translate_rreg (SD_, RN0);
2107 store_half (State.regs[dstreg], State.regs[srcreg]);
2108 State.regs[dstreg] += EXTEND8 (IMM8);
2112 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2113 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2122 srcreg = translate_rreg (SD_, RN2);
2124 temp = ((signed64)(signed32)EXTEND8 (IMM8)
2125 * (signed64)(signed32)State.regs[srcreg]);
2126 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2127 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2128 State.regs[REG_MCRL] = sum;
2131 sum = State.regs[REG_MCRH] + temp + c;
2132 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2133 && (temp & 0x80000000) != (sum & 0x80000000));
2134 State.regs[REG_MCRH] = sum;
2136 State.regs[REG_MCVF] = 1;
2139 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2140 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2149 srcreg = translate_rreg (SD_, RN2);
2151 temp = ((unsigned64) (IMM8)
2152 * (unsigned64)State.regs[srcreg]);
2153 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2154 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2155 State.regs[REG_MCRL] = sum;
2158 sum = State.regs[REG_MCRH] + temp + c;
2159 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2160 && (temp & 0x80000000) != (sum & 0x80000000));
2161 State.regs[REG_MCRH] = sum;
2163 State.regs[REG_MCVF] = 1;
2166 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2167 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2176 srcreg = translate_rreg (SD_, RN2);
2178 temp = ((signed64)(signed8)EXTEND8 (IMM8)
2179 * (signed64)(signed8)State.regs[srcreg] & 0xff);
2180 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2181 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2182 State.regs[REG_MCRL] = sum;
2185 sum = State.regs[REG_MCRH] + temp + c;
2186 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2187 && (temp & 0x80000000) != (sum & 0x80000000));
2188 State.regs[REG_MCRH] = sum;
2190 State.regs[REG_MCVF] = 1;
2193 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2194 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2203 srcreg = translate_rreg (SD_, RN2);
2205 temp = ((unsigned64) (IMM8)
2206 * (unsigned64)State.regs[srcreg] & 0xff);
2207 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2208 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2209 State.regs[REG_MCRL] = sum;
2212 sum = State.regs[REG_MCRH] + temp + c;
2213 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2214 && (temp & 0x80000000) != (sum & 0x80000000));
2215 State.regs[REG_MCRH] = sum;
2217 State.regs[REG_MCVF] = 1;
2220 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2221 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2230 srcreg = translate_rreg (SD_, RN2);
2232 temp = ((signed64)(signed16)EXTEND8 (IMM8)
2233 * (signed64)(signed16)State.regs[srcreg] & 0xffff);
2234 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2235 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2236 State.regs[REG_MCRL] = sum;
2239 sum = State.regs[REG_MCRH] + temp + c;
2240 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2241 && (temp & 0x80000000) != (sum & 0x80000000));
2242 State.regs[REG_MCRH] = sum;
2244 State.regs[REG_MCVF] = 1;
2247 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2248 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2257 srcreg = translate_rreg (SD_, RN2);
2259 temp = ((unsigned64) (IMM8)
2260 * (unsigned64)State.regs[srcreg] & 0xffff);
2261 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2262 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2263 State.regs[REG_MCRL] = sum;
2266 sum = State.regs[REG_MCRH] + temp + c;
2267 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2268 && (temp & 0x80000000) != (sum & 0x80000000));
2269 State.regs[REG_MCRH] = sum;
2271 State.regs[REG_MCVF] = 1;
2274 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
2275 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2282 dstreg = translate_rreg (SD_, RN0);
2284 PSW &= ~(PSW_V | PSW_C);
2285 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2287 /* 32bit saturation. */
2292 tmp = State.regs[REG_MCRH];
2294 tmp += State.regs[REG_MCRL];
2296 if (tmp > 0x7fffffff)
2297 State.regs[dstreg] = 0x7fffffff;
2298 else if (tmp < 0xffffffff80000000LL)
2299 State.regs[dstreg] = 0x80000000;
2301 State.regs[dstreg] = tmp;
2303 /* 16bit saturation */
2304 else if (IMM8 == 0x10)
2308 tmp = State.regs[REG_MCRH];
2310 tmp += State.regs[REG_MCRL];
2313 State.regs[dstreg] = 0x7fff;
2314 else if (tmp < 0xffffffffffff8000LL)
2315 State.regs[dstreg] = 0x8000;
2317 State.regs[dstreg] = tmp;
2319 /* 8 bit saturation */
2320 else if (IMM8 == 0x8)
2324 tmp = State.regs[REG_MCRH];
2326 tmp += State.regs[REG_MCRL];
2329 State.regs[dstreg] = 0x7f;
2330 else if (tmp < 0xffffffffffffff80LL)
2331 State.regs[dstreg] = 0x80;
2333 State.regs[dstreg] = tmp;
2335 /* 9 bit saturation */
2336 else if (IMM8 == 0x9)
2340 tmp = State.regs[REG_MCRH];
2342 tmp += State.regs[REG_MCRL];
2345 State.regs[dstreg] = 0x80;
2346 else if (tmp < 0xffffffffffffff81LL)
2347 State.regs[dstreg] = 0x81;
2349 State.regs[dstreg] = tmp;
2351 /* 9 bit saturation */
2352 else if (IMM8 == 0x30)
2356 tmp = State.regs[REG_MCRH];
2358 tmp += State.regs[REG_MCRL];
2360 if (tmp > 0x7fffffffffffLL)
2361 tmp = 0x7fffffffffffLL;
2362 else if (tmp < 0xffff800000000000LL)
2363 tmp = 0xffff800000000000LL;
2366 State.regs[dstreg] = tmp;
2370 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2371 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2376 unsigned32 sum, source1, source2;
2377 int srcreg1, srcreg2, dstreg;
2380 srcreg1 = translate_rreg (SD_, RM2);
2381 srcreg2 = translate_rreg (SD_, RN0);
2382 dstreg = translate_rreg (SD_, RD0);
2384 source1 = State.regs[srcreg1];
2385 source2 = State.regs[srcreg2];
2386 sum = source1 + source2;
2387 State.regs[dstreg] = sum;
2390 n = (sum & 0x80000000);
2391 c = (sum < source1) || (sum < source2);
2392 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2393 && (source1 & 0x80000000) != (sum & 0x80000000));
2395 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2396 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2397 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2400 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2401 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2406 unsigned32 sum, source1, source2;
2407 int srcreg1, srcreg2, dstreg;
2410 srcreg1 = translate_rreg (SD_, RM2);
2411 srcreg2 = translate_rreg (SD_, RN0);
2412 dstreg = translate_rreg (SD_, RD0);
2414 source1 = State.regs[srcreg1];
2415 source2 = State.regs[srcreg2];
2416 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2417 State.regs[dstreg] = sum;
2419 z = ((PSW & PSW_Z) != 0) && (sum == 0);
2420 n = (sum & 0x80000000);
2421 c = (sum < source1) || (sum < source2);
2422 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2423 && (source1 & 0x80000000) != (sum & 0x80000000));
2425 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2426 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2427 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2430 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2431 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2436 unsigned32 difference, source1, source2;
2437 int srcreg1, srcreg2, dstreg;
2440 srcreg1 = translate_rreg (SD_, RM2);
2441 srcreg2 = translate_rreg (SD_, RN0);
2442 dstreg = translate_rreg (SD_, RD0);
2444 source1 = State.regs[srcreg1];
2445 source2 = State.regs[srcreg2];
2446 difference = source2 - source1;
2447 State.regs[dstreg] = difference;
2449 z = (difference == 0);
2450 n = (difference & 0x80000000);
2451 c = (source1 > source1);
2452 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2453 && (source1 & 0x80000000) != (difference & 0x80000000));
2455 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2456 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2457 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2460 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2461 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2466 unsigned32 difference, source1, source2;
2467 int srcreg1, srcreg2, dstreg;
2470 srcreg1 = translate_rreg (SD_, RM2);
2471 srcreg2 = translate_rreg (SD_, RN0);
2472 dstreg = translate_rreg (SD_, RD0);
2474 source1 = State.regs[srcreg1];
2475 source2 = State.regs[srcreg2];
2476 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2477 State.regs[dstreg] = difference;
2479 z = ((PSW & PSW_Z) != 0) && (difference == 0);
2480 n = (difference & 0x80000000);
2481 c = (source1 > source2);
2482 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2483 && (source1 & 0x80000000) != (difference & 0x80000000));
2485 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2486 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2487 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2490 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2491 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2496 int srcreg1, srcreg2, dstreg;
2499 srcreg1 = translate_rreg (SD_, RM2);
2500 srcreg2 = translate_rreg (SD_, RN0);
2501 dstreg = translate_rreg (SD_, RD0);
2503 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2505 z = (State.regs[dstreg] == 0);
2506 n = (State.regs[dstreg] & 0x80000000);
2508 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2509 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2512 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2513 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2518 int srcreg1, srcreg2, dstreg;
2521 srcreg1 = translate_rreg (SD_, RM2);
2522 srcreg2 = translate_rreg (SD_, RN0);
2523 dstreg = translate_rreg (SD_, RD0);
2525 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2527 z = (State.regs[dstreg] == 0);
2528 n = (State.regs[dstreg] & 0x80000000);
2530 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2531 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2534 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2535 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2540 int srcreg1, srcreg2, dstreg;
2543 srcreg1 = translate_rreg (SD_, RM2);
2544 srcreg2 = translate_rreg (SD_, RN0);
2545 dstreg = translate_rreg (SD_, RD0);
2547 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2549 z = (State.regs[dstreg] == 0);
2550 n = (State.regs[dstreg] & 0x80000000);
2552 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2553 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2556 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2557 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2563 int srcreg1, srcreg2, dstreg;
2566 srcreg1 = translate_rreg (SD_, RM2);
2567 srcreg2 = translate_rreg (SD_, RN0);
2568 dstreg = translate_rreg (SD_, RD0);
2570 temp = State.regs[srcreg2];
2572 temp >>= State.regs[srcreg1];
2573 State.regs[dstreg] = temp;
2575 z = (State.regs[dstreg] == 0);
2576 n = (State.regs[dstreg] & 0x80000000);
2578 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2579 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2582 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2583 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2588 int srcreg1, srcreg2, dstreg;
2591 srcreg1 = translate_rreg (SD_, RM2);
2592 srcreg2 = translate_rreg (SD_, RN0);
2593 dstreg = translate_rreg (SD_, RD0);
2595 c = State.regs[srcreg2] & 1;
2596 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2598 z = (State.regs[dstreg] == 0);
2599 n = (State.regs[dstreg] & 0x80000000);
2601 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2602 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2605 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2606 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2611 int srcreg1, srcreg2, dstreg;
2614 srcreg1 = translate_rreg (SD_, RM2);
2615 srcreg2 = translate_rreg (SD_, RN0);
2616 dstreg = translate_rreg (SD_, RD0);
2618 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
2620 z = (State.regs[dstreg] == 0);
2621 n = (State.regs[dstreg] & 0x80000000);
2623 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2624 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2627 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2628 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
2632 int srcreg1, srcreg2, dstreg1, dstreg2;
2637 srcreg1 = translate_rreg (SD_, RM2);
2638 srcreg2 = translate_rreg (SD_, RN0);
2639 dstreg1 = translate_rreg (SD_, RD0);
2640 dstreg2 = translate_rreg (SD_, RD2);
2642 temp = ((signed64)(signed32)State.regs[srcreg1]
2643 * (signed64)(signed32)State.regs[srcreg2]);
2644 State.regs[dstreg2] = temp & 0xffffffff;
2645 State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
2647 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2648 n = (State.regs[dstreg1] & 0x80000000);
2650 PSW &= ~(PSW_Z | PSW_N);
2651 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2654 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2655 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
2659 int srcreg1, srcreg2, dstreg1, dstreg2;
2664 srcreg1 = translate_rreg (SD_, RM2);
2665 srcreg2 = translate_rreg (SD_, RN0);
2666 dstreg1 = translate_rreg (SD_, RD0);
2667 dstreg2 = translate_rreg (SD_, RD2);
2669 temp = ((unsigned64)State.regs[srcreg1]
2670 * (unsigned64)State.regs[srcreg2]);
2671 State.regs[dstreg2] = temp & 0xffffffff;
2672 State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
2674 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2675 n = (State.regs[dstreg1] & 0x80000000);
2677 PSW &= ~(PSW_Z | PSW_N);
2678 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2681 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2682 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2689 dstreg = translate_rreg (SD_, RN2);
2690 State.regs[dstreg] = load_word (IMM8);
2693 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2694 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2701 srcreg = translate_rreg (SD_, RM2);
2702 store_word (IMM8, State.regs[srcreg]);
2705 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2706 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2713 dstreg = translate_rreg (SD_, RN2);
2714 State.regs[dstreg] = load_byte (IMM8);
2717 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2718 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2725 srcreg = translate_rreg (SD_, RM2);
2726 store_byte (IMM8, State.regs[srcreg]);
2729 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2730 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2737 dstreg = translate_rreg (SD_, RN2);
2738 State.regs[dstreg] = load_half (IMM8);
2741 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2742 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2749 srcreg = translate_rreg (SD_, RM2);
2750 store_half (IMM8, State.regs[srcreg]);
2753 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2754 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2758 int srcreg1, srcreg2, dstreg;
2761 srcreg1 = translate_rreg (SD_, RM0);
2762 srcreg2 = translate_rreg (SD_, RI0);
2763 dstreg = translate_rreg (SD_, RN0);
2764 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2767 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2768 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2772 int srcreg, dstreg1, dstreg2;
2775 srcreg = translate_rreg (SD_, RM0);
2776 dstreg1 = translate_rreg (SD_, RI0);
2777 dstreg2 = translate_rreg (SD_, RN0);
2778 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2781 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2782 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2786 int srcreg1, srcreg2, dstreg;
2789 srcreg1 = translate_rreg (SD_, RM0);
2790 srcreg2 = translate_rreg (SD_, RI0);
2791 dstreg = translate_rreg (SD_, RN0);
2792 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2795 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2796 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2800 int srcreg, dstreg1, dstreg2;
2803 srcreg = translate_rreg (SD_, RM0);
2804 dstreg1 = translate_rreg (SD_, RI0);
2805 dstreg2 = translate_rreg (SD_, RN0);
2806 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2809 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2810 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2814 int srcreg1, srcreg2, dstreg;
2817 srcreg1 = translate_rreg (SD_, RM0);
2818 srcreg2 = translate_rreg (SD_, RI0);
2819 dstreg = translate_rreg (SD_, RN0);
2820 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2823 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2824 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2828 int srcreg, dstreg1, dstreg2;
2831 srcreg = translate_rreg (SD_, RM0);
2832 dstreg1 = translate_rreg (SD_, RI0);
2833 dstreg2 = translate_rreg (SD_, RN0);
2834 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2837 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
2838 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
2842 int srcreg1, srcreg2, dstreg1, dstreg2;
2848 srcreg1 = translate_rreg (SD_, RM2);
2849 srcreg2 = translate_rreg (SD_, RN0);
2850 dstreg1 = translate_rreg (SD_, RD0);
2851 dstreg2 = translate_rreg (SD_, RD2);
2853 temp = ((signed64)(signed32)State.regs[srcreg1]
2854 * (signed64)(signed32)State.regs[srcreg2]);
2856 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2857 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2858 State.regs[dstreg2] = sum;
2861 sum = State.regs[dstreg1] + temp + c;
2862 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2863 && (temp & 0x80000000) != (sum & 0x80000000));
2864 State.regs[dstreg1] = sum;
2867 State.regs[REG_MCVF] = 1;
2869 PSW |= (( v ? PSW_V : 0));
2873 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
2874 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
2878 int srcreg1, srcreg2, dstreg1, dstreg2;
2884 srcreg1 = translate_rreg (SD_, RM2);
2885 srcreg2 = translate_rreg (SD_, RN0);
2886 dstreg1 = translate_rreg (SD_, RD0);
2887 dstreg2 = translate_rreg (SD_, RD2);
2889 temp = ((unsigned64)State.regs[srcreg1]
2890 * (unsigned64)State.regs[srcreg2]);
2892 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2893 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2894 State.regs[dstreg2] = sum;
2897 sum = State.regs[dstreg1] + temp + c;
2898 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2899 && (temp & 0x80000000) != (sum & 0x80000000));
2900 State.regs[dstreg1] = sum;
2903 State.regs[REG_MCVF] = 1;
2905 PSW |= (( v ? PSW_V : 0));
2909 // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
2910 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2914 int srcreg1, srcreg2, dstreg;
2919 srcreg1 = translate_rreg (SD_, RM2);
2920 srcreg2 = translate_rreg (SD_, RN0);
2921 dstreg = translate_rreg (SD_, RD0);
2923 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2924 * (signed32)(State.regs[srcreg1] & 0xff));
2925 sum = State.regs[dstreg] + temp;
2926 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2927 && (temp & 0x80000000) != (sum & 0x80000000));
2928 State.regs[dstreg] = sum;
2931 State.regs[REG_MCVF] = 1;
2933 PSW |= ((v ? PSW_V : 0));
2937 // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
2938 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2942 int srcreg1, srcreg2, dstreg;
2947 srcreg1 = translate_rreg (SD_, RM2);
2948 srcreg2 = translate_rreg (SD_, RN0);
2949 dstreg = translate_rreg (SD_, RD0);
2951 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2952 * (unsigned32)(State.regs[srcreg1] & 0xff));
2953 sum = State.regs[dstreg] + temp;
2954 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2955 && (temp & 0x80000000) != (sum & 0x80000000));
2956 State.regs[dstreg] = sum;
2959 State.regs[REG_MCVF] = 1;
2961 PSW |= ((v ? PSW_V : 0));
2965 // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
2966 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
2970 int srcreg1, srcreg2, dstreg1, dstreg2;
2975 srcreg1 = translate_rreg (SD_, RM2);
2976 srcreg2 = translate_rreg (SD_, RN0);
2977 dstreg1 = translate_rreg (SD_, RD0);
2978 dstreg2 = translate_rreg (SD_, RD0);
2980 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2981 * (signed32)(State.regs[srcreg1] & 0xffff));
2982 State.regs[dstreg2] += (temp & 0xffffffff);
2983 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
2984 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2985 && (temp & 0x80000000) != (sum & 0x80000000));
2986 State.regs[dstreg1] = sum;
2989 State.regs[REG_MCVF] = 1;
2991 PSW |= ((v ? PSW_V : 0));
2995 // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
2996 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
3000 int srcreg1, srcreg2, dstreg1, dstreg2;
3005 srcreg1 = translate_rreg (SD_, RM2);
3006 srcreg2 = translate_rreg (SD_, RN0);
3007 dstreg1 = translate_rreg (SD_, RD0);
3008 dstreg2 = translate_rreg (SD_, RD0);
3010 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3011 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3012 State.regs[dstreg2] += (temp & 0xffffffff);
3013 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
3014 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
3015 && (temp & 0x80000000) != (sum & 0x80000000));
3016 State.regs[dstreg1] = sum;
3019 State.regs[REG_MCVF] = 1;
3021 PSW |= ((v ? PSW_V : 0));
3025 // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
3026 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
3030 int srcreg1, srcreg2, dstreg;
3031 signed32 temp, temp2, sum;
3035 srcreg1 = translate_rreg (SD_, RM2);
3036 srcreg2 = translate_rreg (SD_, RN0);
3037 dstreg = translate_rreg (SD_, RD0);
3039 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
3040 * (signed32)(State.regs[srcreg1] & 0xffff));
3041 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3042 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
3043 sum = temp + temp2 + State.regs[dstreg];
3044 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3045 && (temp & 0x80000000) != (sum & 0x80000000));
3046 State.regs[dstreg] = sum;
3049 State.regs[REG_MCVF] = 1;
3051 PSW |= ((v ? PSW_V : 0));
3055 // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
3056 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
3060 int srcreg1, srcreg2, dstreg;
3061 signed32 temp, temp2, sum;
3065 srcreg1 = translate_rreg (SD_, RM2);
3066 srcreg2 = translate_rreg (SD_, RN0);
3067 dstreg = translate_rreg (SD_, RD0);
3069 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3070 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3071 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3072 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
3073 sum = temp + temp2 + State.regs[dstreg];
3074 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3075 && (temp & 0x80000000) != (sum & 0x80000000));
3076 State.regs[dstreg] = sum;
3079 State.regs[REG_MCVF] = 1;
3081 PSW |= ((v ? PSW_V : 0));
3085 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3086 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
3090 int srcreg1, srcreg2, dstreg1, dstreg2;
3094 srcreg1 = translate_rreg (SD_, RM2);
3095 srcreg2 = translate_rreg (SD_, RN0);
3096 dstreg1 = translate_rreg (SD_, RD0);
3097 dstreg2 = translate_rreg (SD_, RD2);
3099 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3100 * (signed32)(State.regs[srcreg1] & 0xffff));
3101 State.regs[dstreg2] = temp;
3102 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3103 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3104 State.regs[dstreg1] = temp;
3107 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3108 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
3112 int srcreg1, srcreg2, dstreg1, dstreg2;
3116 srcreg1 = translate_rreg (SD_, RM2);
3117 srcreg2 = translate_rreg (SD_, RN0);
3118 dstreg1 = translate_rreg (SD_, RD0);
3119 dstreg2 = translate_rreg (SD_, RD2);
3121 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3122 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3123 State.regs[dstreg2] = temp;
3124 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3125 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3126 State.regs[dstreg1] = temp;
3129 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3130 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3138 srcreg = translate_rreg (SD_, RM2);
3139 dstreg = translate_rreg (SD_, RN0);
3141 value = State.regs[srcreg];
3143 if (value >= 0x7fffff)
3144 State.regs[dstreg] = 0x7fffff;
3145 else if (value <= 0xff800000)
3146 State.regs[dstreg] = 0xff800000;
3148 State.regs[dstreg] = value;
3150 n = (State.regs[dstreg] & 0x800000) != 0;
3151 z = (State.regs[dstreg] == 0);
3152 PSW &= ~(PSW_Z | PSW_N);
3153 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3156 // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
3157 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3162 int srcreg1, srcreg2, dstreg;
3166 srcreg1 = translate_rreg (SD_, RM2);
3167 srcreg2 = translate_rreg (SD_, RN0);
3168 dstreg = translate_rreg (SD_, RD0);
3170 temp = State.regs[srcreg1];
3171 start = (State.regs[srcreg2] & 0x1f) - 1;
3176 for (i = start; i >= 0; i--)
3178 if (temp & (1 << i))
3181 State.regs[dstreg] = i;
3189 State.regs[dstreg] = 0;
3192 PSW |= (c ? PSW_C : 0);
3195 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3196 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3203 dstreg = translate_rreg (SD_, RN0);
3204 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3207 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
3208 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3215 dstreg = translate_rreg (SD_, RN0);
3216 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3219 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
3220 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3227 dstreg = translate_rreg (SD_, RN0);
3228 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3231 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
3232 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3236 int dstreg, z, n, c, v;
3237 unsigned32 sum, imm, reg2;
3240 dstreg = translate_rreg (SD_, RN0);
3242 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3243 reg2 = State.regs[dstreg];
3244 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3245 State.regs[dstreg] = sum;
3247 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3248 n = (sum & 0x80000000);
3249 c = (sum < imm) || (sum < reg2);
3250 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3251 && (reg2 & 0x80000000) != (sum & 0x80000000));
3253 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3254 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3255 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3258 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
3259 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3266 dstreg = translate_rreg (SD_, RN0);
3267 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3270 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
3271 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3275 int dstreg, z, n, c, v;
3276 unsigned32 difference, imm, reg2;
3279 dstreg = translate_rreg (SD_, RN0);
3281 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3282 reg2 = State.regs[dstreg];
3283 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3284 State.regs[dstreg] = difference;
3286 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3287 n = (difference & 0x80000000);
3289 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3290 && (reg2 & 0x80000000) != (difference & 0x80000000));
3292 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3293 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3294 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3297 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
3298 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3305 srcreg = translate_rreg (SD_, RN0);
3306 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3309 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
3310 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3317 dstreg = translate_xreg (SD_, XRN0);
3319 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3322 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3323 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3331 dstreg = translate_rreg (SD_, RN0);
3333 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3334 z = (State.regs[dstreg] == 0);
3335 n = (State.regs[dstreg] & 0x80000000) != 0;
3336 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3337 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3340 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3341 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3349 dstreg = translate_rreg (SD_, RN0);
3351 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3352 z = (State.regs[dstreg] == 0);
3353 n = (State.regs[dstreg] & 0x80000000) != 0;
3354 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3355 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3358 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3359 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3367 dstreg = translate_rreg (SD_, RN0);
3369 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3370 z = (State.regs[dstreg] == 0);
3371 n = (State.regs[dstreg] & 0x80000000) != 0;
3372 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3373 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3376 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3377 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3386 dstreg = translate_rreg (SD_, RN0);
3388 temp = State.regs[dstreg];
3390 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3391 State.regs[dstreg] = temp;
3392 z = (State.regs[dstreg] == 0);
3393 n = (State.regs[dstreg] & 0x80000000) != 0;
3394 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3395 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3399 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3400 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3408 dstreg = translate_rreg (SD_, RN0);
3410 c = State.regs[dstreg] & 1;
3411 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3412 z = (State.regs[dstreg] == 0);
3413 n = (State.regs[dstreg] & 0x80000000) != 0;
3414 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3415 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3418 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3419 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3427 dstreg = translate_rreg (SD_, RN0);
3429 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3430 z = (State.regs[dstreg] == 0);
3431 n = (State.regs[dstreg] & 0x80000000) != 0;
3432 PSW &= ~(PSW_Z | PSW_N);
3433 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3436 // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3437 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3446 dstreg = translate_rreg (SD_, RN0);
3448 temp = ((signed64)(signed32)State.regs[dstreg]
3449 * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3450 State.regs[dstreg] = temp & 0xffffffff;
3451 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
3452 z = (State.regs[dstreg] == 0);
3453 n = (State.regs[dstreg] & 0x80000000) != 0;
3454 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3455 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3458 // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3459 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3468 dstreg = translate_rreg (SD_, RN0);
3470 temp = ((unsigned64)State.regs[dstreg]
3471 * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3472 State.regs[dstreg] = temp & 0xffffffff;
3473 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
3474 z = (State.regs[dstreg] == 0);
3475 n = (State.regs[dstreg] & 0x80000000) != 0;
3476 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3477 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3480 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3481 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3488 srcreg = translate_rreg (SD_, RN0);
3489 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3492 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3493 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3500 srcreg = translate_rreg (SD_, RM0);
3501 dstreg = translate_rreg (SD_, RN2);
3502 State.regs[dstreg] = load_word (State.regs[srcreg]
3503 + EXTEND24 (FETCH24 (IMM24A,
3507 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3508 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3515 srcreg = translate_rreg (SD_, RM2);
3516 dstreg = translate_rreg (SD_, RN0);
3517 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3518 State.regs[srcreg]);
3521 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3522 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3529 srcreg = translate_rreg (SD_, RM0);
3530 dstreg = translate_rreg (SD_, RN2);
3531 State.regs[dstreg] = load_byte (State.regs[srcreg]
3532 + EXTEND24 (FETCH24 (IMM24A,
3536 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3537 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3544 srcreg = translate_rreg (SD_, RM2);
3545 dstreg = translate_rreg (SD_, RN0);
3546 store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3547 State.regs[srcreg]);
3550 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3551 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3558 srcreg = translate_rreg (SD_, RM0);
3559 dstreg = translate_rreg (SD_, RN2);
3560 State.regs[dstreg] = load_half (State.regs[srcreg]
3561 + EXTEND24 (FETCH24 (IMM24A,
3565 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3566 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3573 srcreg = translate_rreg (SD_, RM2);
3574 dstreg = translate_rreg (SD_, RN0);
3575 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3576 State.regs[srcreg]);
3579 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3580 8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3587 srcreg = translate_rreg (SD_, RM0);
3588 dstreg = translate_rreg (SD_, RN2);
3589 State.regs[dstreg] = load_word (State.regs[srcreg]);
3590 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3593 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3594 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3601 srcreg = translate_rreg (SD_, RM2);
3602 dstreg = translate_rreg (SD_, RN0);
3603 store_word (State.regs[dstreg], State.regs[srcreg]);
3604 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3608 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3609 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3616 dstreg = translate_rreg (SD_, RN2);
3617 State.regs[dstreg] = load_word (State.regs[REG_SP]
3618 + FETCH24 (IMM24A, IMM24B, IMM24C));
3621 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3622 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3629 srcreg = translate_rreg (SD_, RM2);
3630 store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3631 State.regs[srcreg]);
3634 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,sp),Rn
3635 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3642 dstreg = translate_rreg (SD_, RN2);
3643 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3644 + FETCH24 (IMM24A, IMM24B, IMM24C));
3647 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3648 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3655 srcreg = translate_rreg (SD_, RM2);
3656 store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3657 State.regs[srcreg]);
3660 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3661 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3668 dstreg = translate_rreg (SD_, RN2);
3669 State.regs[dstreg] = load_half (State.regs[REG_SP]
3670 + FETCH24 (IMM24A, IMM24B, IMM24C));
3673 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3674 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3681 srcreg = translate_rreg (SD_, RM2);
3682 store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3683 State.regs[srcreg]);
3686 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3687 8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3694 srcreg = translate_rreg (SD_, RM0);
3695 dstreg = translate_rreg (SD_, RN2);
3696 State.regs[dstreg] = load_half (State.regs[srcreg]);
3697 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3700 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3701 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3708 srcreg = translate_rreg (SD_, RM2);
3709 dstreg = translate_rreg (SD_, RN0);
3710 store_half (State.regs[dstreg], State.regs[srcreg]);
3711 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3714 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
3715 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3724 srcreg = translate_rreg (SD_, RN2);
3726 temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
3727 * (signed64)State.regs[srcreg]);
3728 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3729 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3730 State.regs[REG_MCRL] = sum;
3733 sum = State.regs[REG_MCRH] + temp + c;
3734 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3735 && (temp & 0x80000000) != (sum & 0x80000000));
3736 State.regs[REG_MCRH] = sum;
3738 State.regs[REG_MCVF] = 1;
3741 // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
3742 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3751 srcreg = translate_rreg (SD_, RN2);
3753 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3754 * (unsigned64)State.regs[srcreg]);
3755 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3756 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3757 State.regs[REG_MCRL] = sum;
3760 sum = State.regs[REG_MCRH] + temp + c;
3761 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3762 && (temp & 0x80000000) != (sum & 0x80000000));
3763 State.regs[REG_MCRH] = sum;
3765 State.regs[REG_MCVF] = 1;
3768 // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
3769 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3778 srcreg = translate_rreg (SD_, RN2);
3780 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3781 * (signed64)State.regs[srcreg] & 0xff);
3782 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3783 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3784 State.regs[REG_MCRL] = sum;
3787 sum = State.regs[REG_MCRH] + temp + c;
3788 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3789 && (temp & 0x80000000) != (sum & 0x80000000));
3790 State.regs[REG_MCRH] = sum;
3792 State.regs[REG_MCVF] = 1;
3795 // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
3796 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3805 srcreg = translate_rreg (SD_, RN2);
3807 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3808 * (unsigned64)State.regs[srcreg] & 0xff);
3809 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3810 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3811 State.regs[REG_MCRL] = sum;
3814 sum = State.regs[REG_MCRH] + temp + c;
3815 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3816 && (temp & 0x80000000) != (sum & 0x80000000));
3817 State.regs[REG_MCRH] = sum;
3819 State.regs[REG_MCVF] = 1;
3822 // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
3823 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3832 srcreg = translate_rreg (SD_, RN2);
3834 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3835 * (signed64)State.regs[srcreg] & 0xffff);
3836 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3837 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3838 State.regs[REG_MCRL] = sum;
3841 sum = State.regs[REG_MCRH] + temp + c;
3842 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3843 && (temp & 0x80000000) != (sum & 0x80000000));
3844 State.regs[REG_MCRH] = sum;
3846 State.regs[REG_MCVF] = 1;
3849 // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
3850 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3859 srcreg = translate_rreg (SD_, RN2);
3861 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3862 * (unsigned64)State.regs[srcreg] & 0xffff);
3863 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3864 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3865 State.regs[REG_MCRL] = sum;
3868 sum = State.regs[REG_MCRH] + temp + c;
3869 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3870 && (temp & 0x80000000) != (sum & 0x80000000));
3871 State.regs[REG_MCRH] = sum;
3873 State.regs[REG_MCVF] = 1;
3876 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3877 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3884 dstreg = translate_rreg (SD_, RN2);
3885 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3888 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3889 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3896 srcreg = translate_rreg (SD_, RM2);
3897 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3901 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3902 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3909 dstreg = translate_rreg (SD_, RN2);
3910 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3913 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3914 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3921 srcreg = translate_rreg (SD_, RM2);
3922 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3926 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3927 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3934 dstreg = translate_rreg (SD_, RN2);
3935 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3938 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3939 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3946 srcreg = translate_rreg (SD_, RM2);
3947 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3951 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3952 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3959 dstreg = translate_rreg (SD_, RN0);
3960 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3963 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3964 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3971 dstreg = translate_rreg (SD_, RN0);
3972 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3975 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3976 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3983 dstreg = translate_rreg (SD_, RN0);
3984 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3987 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3988 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3993 unsigned32 imm, reg2, sum;
3997 dstreg = translate_rreg (SD_, RN0);
3999 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4000 reg2 = State.regs[dstreg];
4001 sum = imm + reg2 + ((PSW & PSW_C) != 0);
4002 State.regs[dstreg] = sum;
4004 z = ((PSW & PSW_Z) != 0) && (sum == 0);
4005 n = (sum & 0x80000000);
4006 c = (sum < imm) || (sum < reg2);
4007 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4008 && (reg2 & 0x80000000) != (sum & 0x80000000));
4010 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4011 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4012 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4015 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
4016 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
4023 dstreg = translate_rreg (SD_, RN0);
4024 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
4027 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
4028 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4033 unsigned32 imm, reg2, difference;
4037 dstreg = translate_rreg (SD_, RN0);
4039 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4040 reg2 = State.regs[dstreg];
4041 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4042 State.regs[dstreg] = difference;
4044 z = ((PSW & PSW_Z) != 0) && (difference == 0);
4045 n = (difference & 0x80000000);
4047 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4048 && (reg2 & 0x80000000) != (difference & 0x80000000));
4050 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4051 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4052 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4055 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
4056 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4063 srcreg = translate_rreg (SD_, RN0);
4064 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4067 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
4068 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
4075 dstreg = translate_xreg (SD_, XRN0);
4077 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4080 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
4081 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4089 dstreg = translate_rreg (SD_, RN0);
4091 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4092 z = (State.regs[dstreg] == 0);
4093 n = (State.regs[dstreg] & 0x80000000) != 0;
4094 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4095 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4098 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
4099 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4107 dstreg = translate_rreg (SD_, RN0);
4109 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4110 z = (State.regs[dstreg] == 0);
4111 n = (State.regs[dstreg] & 0x80000000) != 0;
4112 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4113 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4116 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
4117 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4125 dstreg = translate_rreg (SD_, RN0);
4127 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4128 z = (State.regs[dstreg] == 0);
4129 n = (State.regs[dstreg] & 0x80000000) != 0;
4130 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4131 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4134 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
4135 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4144 dstreg = translate_rreg (SD_, RN0);
4146 temp = State.regs[dstreg];
4148 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4149 State.regs[dstreg] = temp;
4150 z = (State.regs[dstreg] == 0);
4151 n = (State.regs[dstreg] & 0x80000000) != 0;
4152 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4153 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4156 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
4157 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4165 dstreg = translate_rreg (SD_, RN0);
4167 c = State.regs[dstreg] & 1;
4168 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4169 z = (State.regs[dstreg] == 0);
4170 n = (State.regs[dstreg] & 0x80000000) != 0;
4171 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4172 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4175 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
4176 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4184 dstreg = translate_rreg (SD_, RN0);
4186 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4187 z = (State.regs[dstreg] == 0);
4188 n = (State.regs[dstreg] & 0x80000000) != 0;
4189 PSW &= ~(PSW_Z | PSW_N);
4190 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4193 // 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
4194 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
4203 dstreg = translate_rreg (SD_, RN0);
4205 temp = ((signed64)(signed32)State.regs[dstreg]
4206 * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4207 State.regs[dstreg] = temp & 0xffffffff;
4208 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
4209 z = (State.regs[dstreg] == 0);
4210 n = (State.regs[dstreg] & 0x80000000) != 0;
4211 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4212 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4215 // 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
4216 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
4225 dstreg = translate_rreg (SD_, RN0);
4227 temp = ((unsigned64)State.regs[dstreg]
4228 * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4229 State.regs[dstreg] = temp & 0xffffffff;
4230 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
4231 z = (State.regs[dstreg] == 0);
4232 n = (State.regs[dstreg] & 0x80000000) != 0;
4233 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4234 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4237 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
4238 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4245 srcreg = translate_rreg (SD_, RN0);
4246 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4249 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
4250 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4257 srcreg = translate_rreg (SD_, RM0);
4258 dstreg = translate_rreg (SD_, RN2);
4259 State.regs[dstreg] = load_word (State.regs[srcreg]
4260 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4263 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
4264 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4271 srcreg = translate_rreg (SD_, RM2);
4272 dstreg = translate_rreg (SD_, RN0);
4273 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4274 State.regs[srcreg]);
4277 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
4278 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4285 srcreg = translate_rreg (SD_, RM0);
4286 dstreg = translate_rreg (SD_, RN2);
4287 State.regs[dstreg] = load_byte (State.regs[srcreg]
4288 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4291 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
4292 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4299 srcreg = translate_rreg (SD_, RM2);
4300 dstreg = translate_rreg (SD_, RN0);
4301 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4302 State.regs[srcreg]);
4305 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
4306 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4313 srcreg = translate_rreg (SD_, RM0);
4314 dstreg = translate_rreg (SD_, RN2);
4315 State.regs[dstreg] = load_half (State.regs[srcreg]
4316 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4319 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
4320 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4327 srcreg = translate_rreg (SD_, RM2);
4328 dstreg = translate_rreg (SD_, RN0);
4329 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4330 State.regs[srcreg]);
4333 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
4334 8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4341 srcreg = translate_rreg (SD_, RM0);
4342 dstreg = translate_rreg (SD_, RN2);
4343 State.regs[dstreg] = load_word (State.regs[srcreg]);
4344 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4347 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
4348 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4355 srcreg = translate_rreg (SD_, RM2);
4356 dstreg = translate_rreg (SD_, RN0);
4357 store_word (State.regs[dstreg], State.regs[srcreg]);
4358 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4362 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
4363 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4370 dstreg = translate_rreg (SD_, RN2);
4371 State.regs[dstreg] = load_word (State.regs[REG_SP]
4372 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4375 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
4376 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4383 srcreg = translate_rreg (SD_, RM2);
4384 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4385 State.regs[srcreg]);
4388 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
4389 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4396 dstreg = translate_rreg (SD_, RN2);
4397 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4398 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4401 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
4402 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4409 srcreg = translate_rreg (SD_, RM2);
4410 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4411 State.regs[srcreg]);
4414 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4415 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4422 dstreg = translate_rreg (SD_, RN2);
4423 State.regs[dstreg] = load_half (State.regs[REG_SP]
4424 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4427 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4428 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4435 srcreg = translate_rreg (SD_, RM2);
4436 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4437 State.regs[srcreg]);
4441 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
4442 8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4449 srcreg = translate_rreg (SD_, RM0);
4450 dstreg = translate_rreg (SD_, RN2);
4451 State.regs[dstreg] = load_half (State.regs[srcreg]);
4452 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4455 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
4456 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4463 srcreg = translate_rreg (SD_, RM2);
4464 dstreg = translate_rreg (SD_, RN0);
4465 store_half (State.regs[dstreg], State.regs[srcreg]);
4466 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4470 // 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
4471 8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
4480 srcreg = translate_rreg (SD_, RN0);
4481 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4483 temp = ((signed64)(signed32)State.regs[srcreg]
4484 * (signed64)(signed32)imm);
4485 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4486 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4487 State.regs[REG_MCRL] = sum;
4490 sum = State.regs[REG_MCRH] + temp + c;
4491 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4492 && (temp & 0x80000000) != (sum & 0x80000000));
4493 State.regs[REG_MCRH] = sum;
4495 State.regs[REG_MCVF] = 1;
4498 // 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
4499 8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
4508 srcreg = translate_rreg (SD_, RN0);
4509 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4511 temp = ((unsigned64)State.regs[srcreg]
4513 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4514 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4515 State.regs[REG_MCRL] = sum;
4518 sum = State.regs[REG_MCRH] + temp + c;
4519 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4520 && (temp & 0x80000000) != (sum & 0x80000000));
4521 State.regs[REG_MCRH] = sum;
4523 State.regs[REG_MCVF] = 1;
4526 // 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
4527 8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
4536 srcreg = translate_rreg (SD_, RN0);
4537 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4539 temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
4540 * (signed32)(signed8)(imm & 0xff));
4541 sum = State.regs[REG_MCRL] + temp;
4542 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4543 && (temp & 0x80000000) != (sum & 0x80000000));
4544 State.regs[REG_MCRL] = sum;
4546 State.regs[REG_MCVF] = 1;
4549 // 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
4550 8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
4559 srcreg = translate_rreg (SD_, RN0);
4560 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4562 temp = ((unsigned32)(State.regs[srcreg] & 0xff)
4563 * (unsigned32)(imm & 0xff));
4564 sum = State.regs[REG_MCRL] + temp;
4565 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4566 && (temp & 0x80000000) != (sum & 0x80000000));
4567 State.regs[REG_MCRL] = sum;
4569 State.regs[REG_MCVF] = 1;
4572 // 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
4573 8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
4582 srcreg = translate_rreg (SD_, RN0);
4583 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4585 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4586 * (signed32)(signed16)(imm & 0xffff));
4587 sum = State.regs[REG_MCRL] + temp;
4588 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4589 && (temp & 0x80000000) != (sum & 0x80000000));
4590 State.regs[REG_MCRL] = sum;
4592 State.regs[REG_MCVF] = 1;
4595 // 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
4596 8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
4605 srcreg = translate_rreg (SD_, RN0);
4606 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4608 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4609 * (unsigned32)(imm & 0xffff));
4610 sum = State.regs[REG_MCRL] + temp;
4611 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4612 && (temp & 0x80000000) != (sum & 0x80000000));
4613 State.regs[REG_MCRL] = sum;
4615 State.regs[REG_MCVF] = 1;
4618 // 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
4619 8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
4624 signed32 temp, temp2, sum;
4628 srcreg = translate_rreg (SD_, RN0);
4629 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4631 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4632 * (signed32)(signed16)(imm & 0xffff));
4633 temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
4634 * (signed32)(signed16)((imm >> 16) & 0xffff));
4635 sum = temp + temp2 + State.regs[REG_MCRL];
4636 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4637 && (temp & 0x80000000) != (sum & 0x80000000));
4638 State.regs[REG_MCRL] = sum;
4640 State.regs[REG_MCVF] = 1;
4643 // 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
4644 8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
4649 signed32 temp, temp2, sum;
4653 srcreg = translate_rreg (SD_, RN0);
4654 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4656 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4657 * (unsigned32)(imm & 0xffff));
4658 temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
4659 * (unsigned32)((imm >> 16) & 0xffff));
4660 sum = temp + temp2 + State.regs[REG_MCRL];
4661 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4662 && (temp & 0x80000000) != (sum & 0x80000000));
4663 State.regs[REG_MCRL] = sum;
4665 State.regs[REG_MCVF] = 1;
4668 // 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
4669 8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
4677 dstreg = translate_rreg (SD_, RN0);
4678 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4680 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
4681 * (signed32)(signed16)(imm & 0xffff));
4682 State.regs[REG_MDRQ] = temp;
4683 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
4684 * (signed32)(signed16)((imm>>16) & 0xffff));
4685 State.regs[dstreg] = temp;
4688 // 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
4689 8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
4697 dstreg = translate_rreg (SD_, RN0);
4698 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4700 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
4701 * (unsigned32)(imm & 0xffff));
4702 State.regs[REG_MDRQ] = temp;
4703 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
4704 * (unsigned32)((imm >>16) & 0xffff));
4705 State.regs[dstreg] = temp;
4708 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4709 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4716 dstreg = translate_rreg (SD_, RN2);
4717 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4720 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4721 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4728 srcreg = translate_rreg (SD_, RM2);
4729 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4732 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4733 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4740 dstreg = translate_rreg (SD_, RN2);
4741 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4744 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4745 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4752 srcreg = translate_rreg (SD_, RM2);
4753 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4756 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4757 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4764 dstreg = translate_rreg (SD_, RN2);
4765 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4768 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4769 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4776 srcreg = translate_rreg (SD_, RM2);
4777 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4780 // 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
4781 8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
4785 int srcreg1, srcreg2, dstreg1, dstreg2;
4789 srcreg1 = translate_rreg (SD_, RM1);
4790 srcreg2 = translate_rreg (SD_, RM2);
4791 dstreg1 = translate_rreg (SD_, RN1);
4792 dstreg2 = translate_rreg (SD_, RN2);
4794 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4795 State.regs[dstreg2] += State.regs[srcreg2];
4796 State.regs[dstreg1] = result1;
4799 // 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
4800 8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
4804 int srcreg1, dstreg1, dstreg2;
4808 srcreg1 = translate_rreg (SD_, RM1);
4809 dstreg1 = translate_rreg (SD_, RN1);
4810 dstreg2 = translate_rreg (SD_, RN2);
4812 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4813 State.regs[dstreg2] += EXTEND4 (IMM4);
4814 State.regs[dstreg1] = result1;
4817 // 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
4818 8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
4822 int srcreg1, srcreg2, dstreg1, dstreg2;
4826 srcreg1 = translate_rreg (SD_, RM1);
4827 srcreg2 = translate_rreg (SD_, RM2);
4828 dstreg1 = translate_rreg (SD_, RN1);
4829 dstreg2 = translate_rreg (SD_, RN2);
4831 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4832 State.regs[dstreg2] -= State.regs[srcreg2];
4833 State.regs[dstreg1] = result1;
4836 // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
4837 8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
4841 int srcreg1, dstreg1, dstreg2;
4845 srcreg1 = translate_rreg (SD_, RM1);
4846 dstreg1 = translate_rreg (SD_, RN1);
4847 dstreg2 = translate_rreg (SD_, RN2);
4849 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4850 State.regs[dstreg2] -= EXTEND4 (IMM4);
4851 State.regs[dstreg1] = result1;
4854 // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
4855 8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
4859 int srcreg1, srcreg2, dstreg1, dstreg2;
4862 srcreg1 = translate_rreg (SD_, RM1);
4863 srcreg2 = translate_rreg (SD_, RM2);
4864 dstreg1 = translate_rreg (SD_, RN1);
4865 dstreg2 = translate_rreg (SD_, RN2);
4867 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
4868 State.regs[dstreg1] += State.regs[srcreg1];
4871 // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
4872 8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
4876 int srcreg1, dstreg1, dstreg2;
4879 srcreg1 = translate_rreg (SD_, RM1);
4880 dstreg1 = translate_rreg (SD_, RN1);
4881 dstreg2 = translate_rreg (SD_, RN2);
4883 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
4884 State.regs[dstreg1] += State.regs[srcreg1];
4887 // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
4888 8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
4892 int srcreg1, srcreg2, dstreg1, dstreg2;
4896 srcreg1 = translate_rreg (SD_, RM1);
4897 srcreg2 = translate_rreg (SD_, RM2);
4898 dstreg1 = translate_rreg (SD_, RN1);
4899 dstreg2 = translate_rreg (SD_, RN2);
4901 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4902 State.regs[dstreg2] = State.regs[srcreg2];
4903 State.regs[dstreg1] = result1;
4906 // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
4907 8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
4911 int srcreg1, dstreg1, dstreg2;
4915 srcreg1 = translate_rreg (SD_, RM1);
4916 dstreg1 = translate_rreg (SD_, RN1);
4917 dstreg2 = translate_rreg (SD_, RN2);
4919 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4920 State.regs[dstreg2] = EXTEND4 (IMM4);
4921 State.regs[dstreg1] = result1;
4924 // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
4925 8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
4929 int srcreg1, srcreg2, dstreg1, dstreg2;
4934 srcreg1 = translate_rreg (SD_, RM1);
4935 srcreg2 = translate_rreg (SD_, RM2);
4936 dstreg1 = translate_rreg (SD_, RN1);
4937 dstreg2 = translate_rreg (SD_, RN2);
4939 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4940 temp = State.regs[dstreg2];
4941 temp >>= State.regs[srcreg2];
4942 State.regs[dstreg2] = temp;
4943 State.regs[dstreg1] = result1;
4946 // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
4947 8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
4951 int srcreg1, dstreg1, dstreg2;
4956 srcreg1 = translate_rreg (SD_, RM1);
4957 dstreg1 = translate_rreg (SD_, RN1);
4958 dstreg2 = translate_rreg (SD_, RN2);
4960 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4961 temp = State.regs[dstreg2];
4963 State.regs[dstreg2] = temp;
4964 State.regs[dstreg1] = result1;
4967 // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
4968 8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
4972 int srcreg1, srcreg2, dstreg1, dstreg2;
4976 srcreg1 = translate_rreg (SD_, RM1);
4977 srcreg2 = translate_rreg (SD_, RM2);
4978 dstreg1 = translate_rreg (SD_, RN1);
4979 dstreg2 = translate_rreg (SD_, RN2);
4981 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4982 State.regs[dstreg2] >>= State.regs[srcreg2];
4983 State.regs[dstreg1] = result1;
4986 // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
4987 8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
4991 int srcreg1, dstreg1, dstreg2;
4995 srcreg1 = translate_rreg (SD_, RM1);
4996 dstreg1 = translate_rreg (SD_, RN1);
4997 dstreg2 = translate_rreg (SD_, RN2);
4999 result1 = State.regs[dstreg1] + State.regs[srcreg1];
5000 State.regs[dstreg2] >>= IMM4;
5001 State.regs[dstreg1] = result1;
5005 // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
5006 8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
5010 int srcreg1, srcreg2, dstreg1, dstreg2;
5014 srcreg1 = translate_rreg (SD_, RM1);
5015 srcreg2 = translate_rreg (SD_, RM2);
5016 dstreg1 = translate_rreg (SD_, RN1);
5017 dstreg2 = translate_rreg (SD_, RN2);
5019 result1 = State.regs[dstreg1] + State.regs[srcreg1];
5020 State.regs[dstreg2] <<= State.regs[srcreg2];
5021 State.regs[dstreg1] = result1;
5024 // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
5025 8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
5029 int srcreg1, dstreg1, dstreg2;
5033 srcreg1 = translate_rreg (SD_, RM1);
5034 dstreg1 = translate_rreg (SD_, RN1);
5035 dstreg2 = translate_rreg (SD_, RN2);
5037 result1 = State.regs[dstreg1] + State.regs[srcreg1];
5038 State.regs[dstreg2] <<= IMM4;
5039 State.regs[dstreg1] = result1;
5042 // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
5043 8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
5047 int srcreg1, srcreg2, dstreg1, dstreg2;
5050 srcreg1 = translate_rreg (SD_, RM1);
5051 srcreg2 = translate_rreg (SD_, RM2);
5052 dstreg1 = translate_rreg (SD_, RN1);
5053 dstreg2 = translate_rreg (SD_, RN2);
5055 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5056 State.regs[dstreg2] += State.regs[srcreg2];
5059 // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
5060 8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
5064 int srcreg1, dstreg1, dstreg2;
5067 srcreg1 = translate_rreg (SD_, RM1);
5068 dstreg1 = translate_rreg (SD_, RN1);
5069 dstreg2 = translate_rreg (SD_, RN2);
5071 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5072 State.regs[dstreg2] += EXTEND4 (IMM4);
5075 // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
5076 8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
5080 int srcreg1, srcreg2, dstreg1, dstreg2;
5083 srcreg1 = translate_rreg (SD_, RM1);
5084 srcreg2 = translate_rreg (SD_, RM2);
5085 dstreg1 = translate_rreg (SD_, RN1);
5086 dstreg2 = translate_rreg (SD_, RN2);
5088 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5089 State.regs[dstreg2] -= State.regs[srcreg2];
5092 // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
5093 8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
5097 int srcreg1, dstreg1, dstreg2;
5100 srcreg1 = translate_rreg (SD_, RM1);
5101 dstreg1 = translate_rreg (SD_, RN1);
5102 dstreg2 = translate_rreg (SD_, RN2);
5104 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5105 State.regs[dstreg2] -= EXTEND4 (IMM4);
5108 // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
5109 8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
5113 int srcreg1, srcreg2, dstreg1, dstreg2;
5116 srcreg1 = translate_rreg (SD_, RM1);
5117 srcreg2 = translate_rreg (SD_, RM2);
5118 dstreg1 = translate_rreg (SD_, RN1);
5119 dstreg2 = translate_rreg (SD_, RN2);
5121 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5122 State.regs[dstreg2] = State.regs[srcreg2];
5125 // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
5126 8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
5130 int srcreg1, dstreg1, dstreg2;
5133 srcreg1 = translate_rreg (SD_, RM1);
5134 dstreg1 = translate_rreg (SD_, RN1);
5135 dstreg2 = translate_rreg (SD_, RN2);
5137 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5138 State.regs[dstreg2] = EXTEND4 (IMM4);
5141 // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
5142 8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
5146 int srcreg1, srcreg2, dstreg1, dstreg2;
5150 srcreg1 = translate_rreg (SD_, RM1);
5151 srcreg2 = translate_rreg (SD_, RM2);
5152 dstreg1 = translate_rreg (SD_, RN1);
5153 dstreg2 = translate_rreg (SD_, RN2);
5155 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5156 temp = State.regs[dstreg2];
5157 temp >>= State.regs[srcreg2];
5158 State.regs[dstreg2] = temp;
5161 // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
5162 8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
5166 int srcreg1, dstreg1, dstreg2;
5170 srcreg1 = translate_rreg (SD_, RM1);
5171 dstreg1 = translate_rreg (SD_, RN1);
5172 dstreg2 = translate_rreg (SD_, RN2);
5174 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5175 temp = State.regs[dstreg2];
5177 State.regs[dstreg2] = temp;
5180 // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
5181 8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
5185 int srcreg1, srcreg2, dstreg1, dstreg2;
5188 srcreg1 = translate_rreg (SD_, RM1);
5189 srcreg2 = translate_rreg (SD_, RM2);
5190 dstreg1 = translate_rreg (SD_, RN1);
5191 dstreg2 = translate_rreg (SD_, RN2);
5193 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5194 State.regs[dstreg2] >>= State.regs[srcreg2];
5197 // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
5198 8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
5202 int srcreg1, dstreg1, dstreg2;
5205 srcreg1 = translate_rreg (SD_, RM1);
5206 dstreg1 = translate_rreg (SD_, RN1);
5207 dstreg2 = translate_rreg (SD_, RN2);
5209 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5210 State.regs[dstreg2] >>= IMM4;
5214 // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
5215 8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
5219 int srcreg1, srcreg2, dstreg1, dstreg2;
5222 srcreg1 = translate_rreg (SD_, RM1);
5223 srcreg2 = translate_rreg (SD_, RM2);
5224 dstreg1 = translate_rreg (SD_, RN1);
5225 dstreg2 = translate_rreg (SD_, RN2);
5227 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5228 State.regs[dstreg2] <<= State.regs[srcreg2];
5231 // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
5232 8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
5236 int srcreg1, dstreg1, dstreg2;
5239 srcreg1 = translate_rreg (SD_, RM1);
5240 dstreg1 = translate_rreg (SD_, RN1);
5241 dstreg2 = translate_rreg (SD_, RN2);
5243 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5244 State.regs[dstreg2] <<= IMM4;
5247 // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
5248 8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
5252 int srcreg1, srcreg2, dstreg1, dstreg2;
5256 srcreg1 = translate_rreg (SD_, RM1);
5257 srcreg2 = translate_rreg (SD_, RM2);
5258 dstreg1 = translate_rreg (SD_, RN1);
5259 dstreg2 = translate_rreg (SD_, RN2);
5261 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5262 State.regs[dstreg2] += State.regs[srcreg2];
5263 State.regs[dstreg1] = result1;
5266 // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
5267 8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
5271 int srcreg1, dstreg1, dstreg2;
5275 srcreg1 = translate_rreg (SD_, RM1);
5276 dstreg1 = translate_rreg (SD_, RN1);
5277 dstreg2 = translate_rreg (SD_, RN2);
5279 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5280 State.regs[dstreg2] += EXTEND4 (IMM4);
5281 State.regs[dstreg1] = result1;
5284 // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
5285 8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
5289 int srcreg1, srcreg2, dstreg1, dstreg2;
5293 srcreg1 = translate_rreg (SD_, RM1);
5294 srcreg2 = translate_rreg (SD_, RM2);
5295 dstreg1 = translate_rreg (SD_, RN1);
5296 dstreg2 = translate_rreg (SD_, RN2);
5298 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5299 State.regs[dstreg2] -= State.regs[srcreg2];
5300 State.regs[dstreg1] = result1;
5303 // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
5304 8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
5308 int srcreg1, dstreg1, dstreg2;
5312 srcreg1 = translate_rreg (SD_, RM1);
5313 dstreg1 = translate_rreg (SD_, RN1);
5314 dstreg2 = translate_rreg (SD_, RN2);
5316 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5317 State.regs[dstreg2] -= EXTEND4 (IMM4);
5318 State.regs[dstreg1] = result1;
5321 // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
5322 8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
5326 int srcreg1, srcreg2, dstreg1, dstreg2;
5329 srcreg1 = translate_rreg (SD_, RM1);
5330 srcreg2 = translate_rreg (SD_, RM2);
5331 dstreg1 = translate_rreg (SD_, RN1);
5332 dstreg2 = translate_rreg (SD_, RN2);
5334 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5335 State.regs[dstreg1] -= State.regs[srcreg1];
5338 // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
5339 8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
5343 int srcreg1, dstreg1, dstreg2;
5346 srcreg1 = translate_rreg (SD_, RM1);
5347 dstreg1 = translate_rreg (SD_, RN1);
5348 dstreg2 = translate_rreg (SD_, RN2);
5350 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5351 State.regs[dstreg1] -= State.regs[srcreg1];
5354 // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
5355 8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
5359 int srcreg1, srcreg2, dstreg1, dstreg2;
5363 srcreg1 = translate_rreg (SD_, RM1);
5364 srcreg2 = translate_rreg (SD_, RM2);
5365 dstreg1 = translate_rreg (SD_, RN1);
5366 dstreg2 = translate_rreg (SD_, RN2);
5368 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5369 State.regs[dstreg2] = State.regs[srcreg2];
5370 State.regs[dstreg1] = result1;
5373 // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
5374 8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
5378 int srcreg1, dstreg1, dstreg2;
5382 srcreg1 = translate_rreg (SD_, RM1);
5383 dstreg1 = translate_rreg (SD_, RN1);
5384 dstreg2 = translate_rreg (SD_, RN2);
5386 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5387 State.regs[dstreg2] = EXTEND4 (IMM4);
5388 State.regs[dstreg1] = result1;
5391 // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
5392 8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
5396 int srcreg1, srcreg2, dstreg1, dstreg2;
5401 srcreg1 = translate_rreg (SD_, RM1);
5402 srcreg2 = translate_rreg (SD_, RM2);
5403 dstreg1 = translate_rreg (SD_, RN1);
5404 dstreg2 = translate_rreg (SD_, RN2);
5406 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5407 temp = State.regs[dstreg2];
5408 temp >>= State.regs[srcreg2];
5409 State.regs[dstreg2] = temp;
5410 State.regs[dstreg1] = result1;
5413 // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
5414 8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
5418 int srcreg1, dstreg1, dstreg2;
5423 srcreg1 = translate_rreg (SD_, RM1);
5424 dstreg1 = translate_rreg (SD_, RN1);
5425 dstreg2 = translate_rreg (SD_, RN2);
5427 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5428 temp = State.regs[dstreg2];
5430 State.regs[dstreg2] = temp;
5431 State.regs[dstreg1] = result1;
5434 // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
5435 8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
5439 int srcreg1, srcreg2, dstreg1, dstreg2;
5443 srcreg1 = translate_rreg (SD_, RM1);
5444 srcreg2 = translate_rreg (SD_, RM2);
5445 dstreg1 = translate_rreg (SD_, RN1);
5446 dstreg2 = translate_rreg (SD_, RN2);
5448 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5449 State.regs[dstreg2] >>= State.regs[srcreg2];
5450 State.regs[dstreg1] = result1;
5453 // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
5454 8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
5458 int srcreg1, dstreg1, dstreg2;
5462 srcreg1 = translate_rreg (SD_, RM1);
5463 dstreg1 = translate_rreg (SD_, RN1);
5464 dstreg2 = translate_rreg (SD_, RN2);
5466 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5467 State.regs[dstreg2] >>= IMM4;
5468 State.regs[dstreg1] = result1;
5472 // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
5473 8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
5477 int srcreg1, srcreg2, dstreg1, dstreg2;
5481 srcreg1 = translate_rreg (SD_, RM1);
5482 srcreg2 = translate_rreg (SD_, RM2);
5483 dstreg1 = translate_rreg (SD_, RN1);
5484 dstreg2 = translate_rreg (SD_, RN2);
5486 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5487 State.regs[dstreg2] <<= State.regs[srcreg2];
5488 State.regs[dstreg1] = result1;
5491 // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
5492 8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
5496 int srcreg1, dstreg1, dstreg2;
5500 srcreg1 = translate_rreg (SD_, RM1);
5501 dstreg1 = translate_rreg (SD_, RN1);
5502 dstreg2 = translate_rreg (SD_, RN2);
5504 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5505 State.regs[dstreg2] <<= IMM4;
5506 State.regs[dstreg1] = result1;
5509 // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
5510 8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
5514 int srcreg1, srcreg2, dstreg1, dstreg2;
5518 srcreg1 = translate_rreg (SD_, RM1);
5519 srcreg2 = translate_rreg (SD_, RM2);
5520 dstreg1 = translate_rreg (SD_, RN1);
5521 dstreg2 = translate_rreg (SD_, RN2);
5523 result1 = State.regs[srcreg1];
5524 State.regs[dstreg2] += State.regs[srcreg2];
5525 State.regs[dstreg1] = result1;
5528 // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
5529 8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
5533 int srcreg1, dstreg1, dstreg2;
5537 srcreg1 = translate_rreg (SD_, RM1);
5538 dstreg1 = translate_rreg (SD_, RN1);
5539 dstreg2 = translate_rreg (SD_, RN2);
5541 result1 = State.regs[srcreg1];
5542 State.regs[dstreg2] += EXTEND4 (IMM4);
5543 State.regs[dstreg1] = result1;
5546 // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
5547 8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
5551 int srcreg1, srcreg2, dstreg1, dstreg2;
5555 srcreg1 = translate_rreg (SD_, RM1);
5556 srcreg2 = translate_rreg (SD_, RM2);
5557 dstreg1 = translate_rreg (SD_, RN1);
5558 dstreg2 = translate_rreg (SD_, RN2);
5560 result1 = State.regs[srcreg1];
5561 State.regs[dstreg2] -= State.regs[srcreg2];
5562 State.regs[dstreg1] = result1;
5565 // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
5566 8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
5570 int srcreg1, dstreg1, dstreg2;
5574 srcreg1 = translate_rreg (SD_, RM1);
5575 dstreg1 = translate_rreg (SD_, RN1);
5576 dstreg2 = translate_rreg (SD_, RN2);
5578 result1 = State.regs[srcreg1];
5579 State.regs[dstreg2] -= EXTEND4 (IMM4);
5580 State.regs[dstreg1] = result1;
5583 // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
5584 8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
5588 int srcreg1, srcreg2, dstreg1, dstreg2;
5591 srcreg1 = translate_rreg (SD_, RM1);
5592 srcreg2 = translate_rreg (SD_, RM2);
5593 dstreg1 = translate_rreg (SD_, RN1);
5594 dstreg2 = translate_rreg (SD_, RN2);
5596 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5597 State.regs[dstreg1] = State.regs[srcreg1];
5600 // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
5601 8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
5605 int srcreg1, dstreg1, dstreg2;
5608 srcreg1 = translate_rreg (SD_, RM1);
5609 dstreg1 = translate_rreg (SD_, RN1);
5610 dstreg2 = translate_rreg (SD_, RN2);
5612 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5613 State.regs[dstreg1] = State.regs[srcreg1];
5616 // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
5617 8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
5621 int srcreg1, srcreg2, dstreg1, dstreg2;
5625 srcreg1 = translate_rreg (SD_, RM1);
5626 srcreg2 = translate_rreg (SD_, RM2);
5627 dstreg1 = translate_rreg (SD_, RN1);
5628 dstreg2 = translate_rreg (SD_, RN2);
5630 result1 = State.regs[srcreg1];
5631 State.regs[dstreg2] = State.regs[srcreg2];
5632 State.regs[dstreg1] = result1;
5635 // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
5636 8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
5640 int srcreg1, dstreg1, dstreg2;
5644 srcreg1 = translate_rreg (SD_, RM1);
5645 dstreg1 = translate_rreg (SD_, RN1);
5646 dstreg2 = translate_rreg (SD_, RN2);
5648 result1 = State.regs[srcreg1];
5649 State.regs[dstreg2] = EXTEND4 (IMM4);
5650 State.regs[dstreg1] = result1;
5653 // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
5654 8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
5658 int srcreg1, srcreg2, dstreg1, dstreg2;
5663 srcreg1 = translate_rreg (SD_, RM1);
5664 srcreg2 = translate_rreg (SD_, RM2);
5665 dstreg1 = translate_rreg (SD_, RN1);
5666 dstreg2 = translate_rreg (SD_, RN2);
5668 result1 = State.regs[srcreg1];
5669 temp = State.regs[dstreg2];
5670 temp >>= State.regs[srcreg2];
5671 State.regs[dstreg2] = temp;
5672 State.regs[dstreg1] = result1;
5675 // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
5676 8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
5680 int srcreg1, dstreg1, dstreg2;
5685 srcreg1 = translate_rreg (SD_, RM1);
5686 dstreg1 = translate_rreg (SD_, RN1);
5687 dstreg2 = translate_rreg (SD_, RN2);
5689 result1 = State.regs[srcreg1];
5690 temp = State.regs[dstreg2];
5692 State.regs[dstreg2] = temp;
5693 State.regs[dstreg1] = result1;
5696 // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
5697 8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
5701 int srcreg1, srcreg2, dstreg1, dstreg2;
5705 srcreg1 = translate_rreg (SD_, RM1);
5706 srcreg2 = translate_rreg (SD_, RM2);
5707 dstreg1 = translate_rreg (SD_, RN1);
5708 dstreg2 = translate_rreg (SD_, RN2);
5710 result1 = State.regs[srcreg1];
5711 State.regs[dstreg2] >>= State.regs[srcreg2];
5712 State.regs[dstreg1] = result1;
5715 // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
5716 8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
5720 int srcreg1, dstreg1, dstreg2;
5724 srcreg1 = translate_rreg (SD_, RM1);
5725 dstreg1 = translate_rreg (SD_, RN1);
5726 dstreg2 = translate_rreg (SD_, RN2);
5728 result1 = State.regs[srcreg1];
5729 State.regs[dstreg2] >>= IMM4;
5730 State.regs[dstreg1] = result1;
5734 // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
5735 8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
5739 int srcreg1, srcreg2, dstreg1, dstreg2;
5743 srcreg1 = translate_rreg (SD_, RM1);
5744 srcreg2 = translate_rreg (SD_, RM2);
5745 dstreg1 = translate_rreg (SD_, RN1);
5746 dstreg2 = translate_rreg (SD_, RN2);
5748 result1 = State.regs[srcreg1];
5749 State.regs[dstreg2] <<= State.regs[srcreg2];
5750 State.regs[dstreg1] = result1;
5753 // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
5754 8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
5758 int srcreg1, dstreg1, dstreg2;
5762 srcreg1 = translate_rreg (SD_, RM1);
5763 dstreg1 = translate_rreg (SD_, RN1);
5764 dstreg2 = translate_rreg (SD_, RN2);
5766 result1 = State.regs[srcreg1];
5767 State.regs[dstreg2] <<= IMM4;
5768 State.regs[dstreg1] = result1;
5771 // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
5772 8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
5776 int srcreg2, dstreg1, dstreg2;
5780 srcreg2 = translate_rreg (SD_, RM2);
5781 dstreg1 = translate_rreg (SD_, RN1);
5782 dstreg2 = translate_rreg (SD_, RN2);
5784 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5785 State.regs[dstreg2] += State.regs[srcreg2];
5786 State.regs[dstreg1] = result1;
5789 // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
5790 8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
5794 int dstreg1, dstreg2;
5798 dstreg1 = translate_rreg (SD_, RN1);
5799 dstreg2 = translate_rreg (SD_, RN2);
5801 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5802 State.regs[dstreg2] += EXTEND4 (IMM4);
5803 State.regs[dstreg1] = result1;
5806 // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
5807 8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
5811 int srcreg2, dstreg1, dstreg2;
5815 srcreg2 = translate_rreg (SD_, RM2);
5816 dstreg1 = translate_rreg (SD_, RN1);
5817 dstreg2 = translate_rreg (SD_, RN2);
5819 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5820 State.regs[dstreg2] -= State.regs[srcreg2];
5821 State.regs[dstreg1] = result1;
5824 // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
5825 8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
5829 int dstreg1, dstreg2;
5833 dstreg1 = translate_rreg (SD_, RN1);
5834 dstreg2 = translate_rreg (SD_, RN2);
5836 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5837 State.regs[dstreg2] -= EXTEND4 (IMM4);
5838 State.regs[dstreg1] = result1;
5841 // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
5842 8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
5846 int srcreg2, dstreg1, dstreg2;
5849 srcreg2 = translate_rreg (SD_, RM2);
5850 dstreg1 = translate_rreg (SD_, RN1);
5851 dstreg2 = translate_rreg (SD_, RN2);
5853 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5854 State.regs[dstreg1] += EXTEND4 (IMM4A);
5857 // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
5858 8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
5862 int dstreg1, dstreg2;
5865 dstreg1 = translate_rreg (SD_, RN1);
5866 dstreg2 = translate_rreg (SD_, RN2);
5868 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5869 State.regs[dstreg1] += EXTEND4 (IMM4A);
5872 // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
5873 8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
5877 int srcreg2, dstreg1, dstreg2;
5881 srcreg2 = translate_rreg (SD_, RM2);
5882 dstreg1 = translate_rreg (SD_, RN1);
5883 dstreg2 = translate_rreg (SD_, RN2);
5885 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5886 State.regs[dstreg2] = State.regs[srcreg2];
5887 State.regs[dstreg1] = result1;
5890 // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
5891 8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
5895 int dstreg1, dstreg2;
5899 dstreg1 = translate_rreg (SD_, RN1);
5900 dstreg2 = translate_rreg (SD_, RN2);
5902 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5903 State.regs[dstreg2] = EXTEND4 (IMM4);
5904 State.regs[dstreg1] = result1;
5907 // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
5908 8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
5912 int srcreg2, dstreg1, dstreg2;
5917 srcreg2 = translate_rreg (SD_, RM2);
5918 dstreg1 = translate_rreg (SD_, RN1);
5919 dstreg2 = translate_rreg (SD_, RN2);
5921 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5922 temp = State.regs[dstreg2];
5923 temp >>= State.regs[srcreg2];
5924 State.regs[dstreg2] = temp;
5925 State.regs[dstreg1] = result1;
5928 // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
5929 8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
5933 int dstreg1, dstreg2;
5938 dstreg1 = translate_rreg (SD_, RN1);
5939 dstreg2 = translate_rreg (SD_, RN2);
5941 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5942 temp = State.regs[dstreg2];
5944 State.regs[dstreg2] = temp;
5945 State.regs[dstreg1] = result1;
5948 // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
5949 8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
5953 int srcreg2, dstreg1, dstreg2;
5957 srcreg2 = translate_rreg (SD_, RM2);
5958 dstreg1 = translate_rreg (SD_, RN1);
5959 dstreg2 = translate_rreg (SD_, RN2);
5961 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5962 State.regs[dstreg2] >>= State.regs[srcreg2];
5963 State.regs[dstreg1] = result1;
5966 // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
5967 8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
5971 int dstreg1, dstreg2;
5975 dstreg1 = translate_rreg (SD_, RN1);
5976 dstreg2 = translate_rreg (SD_, RN2);
5978 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5979 State.regs[dstreg2] >>= IMM4;
5980 State.regs[dstreg1] = result1;
5984 // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
5985 8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
5989 int srcreg2, dstreg1, dstreg2;
5993 srcreg2 = translate_rreg (SD_, RM2);
5994 dstreg1 = translate_rreg (SD_, RN1);
5995 dstreg2 = translate_rreg (SD_, RN2);
5997 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5998 State.regs[dstreg2] <<= State.regs[srcreg2];
5999 State.regs[dstreg1] = result1;
6002 // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
6003 8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
6007 int dstreg1, dstreg2;
6011 dstreg1 = translate_rreg (SD_, RN1);
6012 dstreg2 = translate_rreg (SD_, RN2);
6014 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
6015 State.regs[dstreg2] <<= IMM4;
6016 State.regs[dstreg1] = result1;
6019 // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
6020 8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
6024 int srcreg2, dstreg1, dstreg2;
6027 srcreg2 = translate_rreg (SD_, RM2);
6028 dstreg1 = translate_rreg (SD_, RN1);
6029 dstreg2 = translate_rreg (SD_, RN2);
6031 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6032 State.regs[dstreg2] += State.regs[srcreg2];
6035 // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
6036 8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
6040 int dstreg1, dstreg2;
6043 dstreg1 = translate_rreg (SD_, RN1);
6044 dstreg2 = translate_rreg (SD_, RN2);
6046 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6047 State.regs[dstreg2] += EXTEND4 (IMM4);
6050 // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
6051 8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
6055 int srcreg2, dstreg1, dstreg2;
6058 srcreg2 = translate_rreg (SD_, RM2);
6059 dstreg1 = translate_rreg (SD_, RN1);
6060 dstreg2 = translate_rreg (SD_, RN2);
6062 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6063 State.regs[dstreg2] -= State.regs[srcreg2];
6066 // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
6067 8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
6071 int dstreg1, dstreg2;
6074 dstreg1 = translate_rreg (SD_, RN1);
6075 dstreg2 = translate_rreg (SD_, RN2);
6077 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6078 State.regs[dstreg2] -= EXTEND4 (IMM4);
6081 // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
6082 8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
6086 int srcreg2, dstreg1, dstreg2;
6089 srcreg2 = translate_rreg (SD_, RM2);
6090 dstreg1 = translate_rreg (SD_, RN1);
6091 dstreg2 = translate_rreg (SD_, RN2);
6093 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6094 State.regs[dstreg2] = State.regs[srcreg2];
6097 // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
6098 8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
6102 int dstreg1, dstreg2;
6105 dstreg1 = translate_rreg (SD_, RN1);
6106 dstreg2 = translate_rreg (SD_, RN2);
6108 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6109 State.regs[dstreg2] = EXTEND4 (IMM4);
6112 // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
6113 8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
6117 int srcreg2, dstreg1, dstreg2;
6121 srcreg2 = translate_rreg (SD_, RM2);
6122 dstreg1 = translate_rreg (SD_, RN1);
6123 dstreg2 = translate_rreg (SD_, RN2);
6125 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6126 temp = State.regs[dstreg2];
6127 temp >>= State.regs[srcreg2];
6128 State.regs[dstreg2] = temp;
6131 // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
6132 8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
6136 int dstreg1, dstreg2;
6140 dstreg1 = translate_rreg (SD_, RN1);
6141 dstreg2 = translate_rreg (SD_, RN2);
6143 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6144 temp = State.regs[dstreg2];
6146 State.regs[dstreg2] = temp;
6149 // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
6150 8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
6154 int srcreg2, dstreg1, dstreg2;
6157 srcreg2 = translate_rreg (SD_, RM2);
6158 dstreg1 = translate_rreg (SD_, RN1);
6159 dstreg2 = translate_rreg (SD_, RN2);
6161 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6162 State.regs[dstreg2] >>= State.regs[srcreg2];
6165 // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
6166 8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
6170 int dstreg1, dstreg2;
6173 dstreg1 = translate_rreg (SD_, RN1);
6174 dstreg2 = translate_rreg (SD_, RN2);
6176 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6177 State.regs[dstreg2] >>= IMM4;
6181 // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
6182 8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
6186 int srcreg2, dstreg1, dstreg2;
6189 srcreg2 = translate_rreg (SD_, RM2);
6190 dstreg1 = translate_rreg (SD_, RN1);
6191 dstreg2 = translate_rreg (SD_, RN2);
6193 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6194 State.regs[dstreg2] <<= State.regs[srcreg2];
6197 // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
6198 8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
6202 int dstreg1, dstreg2;
6205 dstreg1 = translate_rreg (SD_, RN1);
6206 dstreg2 = translate_rreg (SD_, RN2);
6208 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6209 State.regs[dstreg2] <<= IMM4;
6212 // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
6213 8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
6217 int srcreg2, dstreg1, dstreg2;
6221 srcreg2 = translate_rreg (SD_, RM2);
6222 dstreg1 = translate_rreg (SD_, RN1);
6223 dstreg2 = translate_rreg (SD_, RN2);
6225 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6226 State.regs[dstreg2] += State.regs[srcreg2];
6227 State.regs[dstreg1] = result1;
6230 // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
6231 8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
6235 int dstreg1, dstreg2;
6239 dstreg1 = translate_rreg (SD_, RN1);
6240 dstreg2 = translate_rreg (SD_, RN2);
6242 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6243 State.regs[dstreg2] += EXTEND4 (IMM4);
6244 State.regs[dstreg1] = result1;
6247 // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
6248 8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
6252 int srcreg2, dstreg1, dstreg2;
6256 srcreg2 = translate_rreg (SD_, RM2);
6257 dstreg1 = translate_rreg (SD_, RN1);
6258 dstreg2 = translate_rreg (SD_, RN2);
6260 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6261 State.regs[dstreg2] -= State.regs[srcreg2];
6262 State.regs[dstreg1] = result1;
6265 // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
6266 8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
6270 int dstreg1, dstreg2;
6274 dstreg1 = translate_rreg (SD_, RN1);
6275 dstreg2 = translate_rreg (SD_, RN2);
6277 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6278 State.regs[dstreg2] -= EXTEND4 (IMM4);
6279 State.regs[dstreg1] = result1;
6282 // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
6283 8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
6287 int srcreg2, dstreg1, dstreg2;
6290 srcreg2 = translate_rreg (SD_, RM2);
6291 dstreg1 = translate_rreg (SD_, RN1);
6292 dstreg2 = translate_rreg (SD_, RN2);
6294 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6295 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6298 // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
6299 8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
6303 int dstreg1, dstreg2;
6306 dstreg1 = translate_rreg (SD_, RN1);
6307 dstreg2 = translate_rreg (SD_, RN2);
6309 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6310 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6313 // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
6314 8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
6318 int srcreg2, dstreg1, dstreg2;
6322 srcreg2 = translate_rreg (SD_, RM2);
6323 dstreg1 = translate_rreg (SD_, RN1);
6324 dstreg2 = translate_rreg (SD_, RN2);
6326 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6327 State.regs[dstreg2] = State.regs[srcreg2];
6328 State.regs[dstreg1] = result1;
6331 // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
6332 8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
6336 int dstreg1, dstreg2;
6340 dstreg1 = translate_rreg (SD_, RN1);
6341 dstreg2 = translate_rreg (SD_, RN2);
6343 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6344 State.regs[dstreg2] = EXTEND4 (IMM4);
6345 State.regs[dstreg1] = result1;
6348 // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
6349 8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
6353 int srcreg2, dstreg1, dstreg2;
6358 srcreg2 = translate_rreg (SD_, RM2);
6359 dstreg1 = translate_rreg (SD_, RN1);
6360 dstreg2 = translate_rreg (SD_, RN2);
6362 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6363 temp = State.regs[dstreg2];
6364 temp >>= State.regs[srcreg2];
6365 State.regs[dstreg2] = temp;
6366 State.regs[dstreg1] = result1;
6369 // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
6370 8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
6374 int dstreg1, dstreg2;
6379 dstreg1 = translate_rreg (SD_, RN1);
6380 dstreg2 = translate_rreg (SD_, RN2);
6382 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6383 temp = State.regs[dstreg2];
6385 State.regs[dstreg2] = temp;
6386 State.regs[dstreg1] = result1;
6389 // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
6390 8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
6394 int srcreg2, dstreg1, dstreg2;
6398 srcreg2 = translate_rreg (SD_, RM2);
6399 dstreg1 = translate_rreg (SD_, RN1);
6400 dstreg2 = translate_rreg (SD_, RN2);
6402 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6403 State.regs[dstreg2] >>= State.regs[srcreg2];
6404 State.regs[dstreg1] = result1;
6407 // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
6408 8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
6412 int dstreg1, dstreg2;
6416 dstreg1 = translate_rreg (SD_, RN1);
6417 dstreg2 = translate_rreg (SD_, RN2);
6419 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6420 State.regs[dstreg2] >>= IMM4;
6421 State.regs[dstreg1] = result1;
6425 // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
6426 8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
6430 int srcreg2, dstreg1, dstreg2;
6434 srcreg2 = translate_rreg (SD_, RM2);
6435 dstreg1 = translate_rreg (SD_, RN1);
6436 dstreg2 = translate_rreg (SD_, RN2);
6438 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6439 State.regs[dstreg2] <<= State.regs[srcreg2];
6440 State.regs[dstreg1] = result1;
6443 // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
6444 8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
6448 int dstreg1, dstreg2;
6452 dstreg1 = translate_rreg (SD_, RN1);
6453 dstreg2 = translate_rreg (SD_, RN2);
6455 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6456 State.regs[dstreg2] <<= IMM4;
6457 State.regs[dstreg1] = result1;
6460 // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
6461 8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
6465 int srcreg2, dstreg1, dstreg2;
6469 srcreg2 = translate_rreg (SD_, RM2);
6470 dstreg1 = translate_rreg (SD_, RN1);
6471 dstreg2 = translate_rreg (SD_, RN2);
6473 result1 = EXTEND4 (IMM4A);
6474 State.regs[dstreg2] += State.regs[srcreg2];
6475 State.regs[dstreg1] = result1;
6478 // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
6479 8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
6483 int dstreg1, dstreg2;
6487 dstreg1 = translate_rreg (SD_, RN1);
6488 dstreg2 = translate_rreg (SD_, RN2);
6490 result1 = EXTEND4 (IMM4A);
6491 State.regs[dstreg2] += EXTEND4 (IMM4);
6492 State.regs[dstreg1] = result1;
6495 // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
6496 8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
6500 int srcreg2, dstreg1, dstreg2;
6504 srcreg2 = translate_rreg (SD_, RM2);
6505 dstreg1 = translate_rreg (SD_, RN1);
6506 dstreg2 = translate_rreg (SD_, RN2);
6508 result1 = EXTEND4 (IMM4A);
6509 State.regs[dstreg2] -= State.regs[srcreg2];
6510 State.regs[dstreg1] = result1;
6513 // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
6514 8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
6518 int dstreg1, dstreg2;
6522 dstreg1 = translate_rreg (SD_, RN1);
6523 dstreg2 = translate_rreg (SD_, RN2);
6525 result1 = EXTEND4 (IMM4A);
6526 State.regs[dstreg2] -= EXTEND4 (IMM4);
6527 State.regs[dstreg1] = result1;
6530 // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
6531 8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
6535 int srcreg2, dstreg1, dstreg2;
6538 srcreg2 = translate_rreg (SD_, RM2);
6539 dstreg1 = translate_rreg (SD_, RN1);
6540 dstreg2 = translate_rreg (SD_, RN2);
6542 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6543 State.regs[dstreg1] = EXTEND4 (IMM4A);
6546 // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
6547 8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
6551 int dstreg1, dstreg2;
6554 dstreg1 = translate_rreg (SD_, RN1);
6555 dstreg2 = translate_rreg (SD_, RN2);
6557 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6558 State.regs[dstreg1] = EXTEND4 (IMM4A);
6561 // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
6562 8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
6566 int srcreg2, dstreg1, dstreg2;
6570 srcreg2 = translate_rreg (SD_, RM2);
6571 dstreg1 = translate_rreg (SD_, RN1);
6572 dstreg2 = translate_rreg (SD_, RN2);
6574 result1 = EXTEND4 (IMM4A);
6575 State.regs[dstreg2] = State.regs[srcreg2];
6576 State.regs[dstreg1] = result1;
6579 // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
6580 8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
6584 int dstreg1, dstreg2;
6588 dstreg1 = translate_rreg (SD_, RN1);
6589 dstreg2 = translate_rreg (SD_, RN2);
6591 result1 = EXTEND4 (IMM4A);
6592 State.regs[dstreg2] = EXTEND4 (IMM4);
6593 State.regs[dstreg1] = result1;
6596 // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
6597 8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
6601 int srcreg2, dstreg1, dstreg2;
6606 srcreg2 = translate_rreg (SD_, RM2);
6607 dstreg1 = translate_rreg (SD_, RN1);
6608 dstreg2 = translate_rreg (SD_, RN2);
6610 result1 = EXTEND4 (IMM4A);
6611 temp = State.regs[dstreg2];
6612 temp >>= State.regs[srcreg2];
6613 State.regs[dstreg2] = temp;
6614 State.regs[dstreg1] = result1;
6617 // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
6618 8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
6622 int dstreg1, dstreg2;
6627 dstreg1 = translate_rreg (SD_, RN1);
6628 dstreg2 = translate_rreg (SD_, RN2);
6630 result1 = EXTEND4 (IMM4A);
6631 temp = State.regs[dstreg2];
6633 State.regs[dstreg2] = temp;
6634 State.regs[dstreg1] = result1;
6637 // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
6638 8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
6642 int srcreg2, dstreg1, dstreg2;
6646 srcreg2 = translate_rreg (SD_, RM2);
6647 dstreg1 = translate_rreg (SD_, RN1);
6648 dstreg2 = translate_rreg (SD_, RN2);
6650 result1 = EXTEND4 (IMM4A);
6651 State.regs[dstreg2] >>= State.regs[srcreg2];
6652 State.regs[dstreg1] = result1;
6655 // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
6656 8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
6660 int dstreg1, dstreg2;
6664 dstreg1 = translate_rreg (SD_, RN1);
6665 dstreg2 = translate_rreg (SD_, RN2);
6667 result1 = EXTEND4 (IMM4A);
6668 State.regs[dstreg2] >>= IMM4;
6669 State.regs[dstreg1] = result1;
6673 // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
6674 8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
6678 int srcreg2, dstreg1, dstreg2;
6682 srcreg2 = translate_rreg (SD_, RM2);
6683 dstreg1 = translate_rreg (SD_, RN1);
6684 dstreg2 = translate_rreg (SD_, RN2);
6686 result1 = EXTEND4 (IMM4A);
6687 State.regs[dstreg2] <<= State.regs[srcreg2];
6688 State.regs[dstreg1] = result1;
6691 // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
6692 8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
6696 int dstreg1, dstreg2;
6700 dstreg1 = translate_rreg (SD_, RN1);
6701 dstreg2 = translate_rreg (SD_, RN2);
6703 result1 = EXTEND4 (IMM4A);
6704 State.regs[dstreg2] <<= IMM4;
6705 State.regs[dstreg1] = result1;
6708 // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
6709 8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
6713 int srcreg1, srcreg2, dstreg1, dstreg2;
6717 srcreg1 = translate_rreg (SD_, RM1);
6718 srcreg2 = translate_rreg (SD_, RM2);
6719 dstreg1 = translate_rreg (SD_, RN1);
6720 dstreg2 = translate_rreg (SD_, RN2);
6722 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6723 State.regs[dstreg2] += State.regs[srcreg2];
6724 State.regs[dstreg1] = result1;
6727 // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
6728 8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
6732 int srcreg1, dstreg1, dstreg2;
6736 srcreg1 = translate_rreg (SD_, RM1);
6737 dstreg1 = translate_rreg (SD_, RN1);
6738 dstreg2 = translate_rreg (SD_, RN2);
6740 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6741 State.regs[dstreg2] += EXTEND4 (IMM4);
6742 State.regs[dstreg1] = result1;
6745 // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
6746 8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
6750 int srcreg1, srcreg2, dstreg1, dstreg2;
6754 srcreg1 = translate_rreg (SD_, RM1);
6755 srcreg2 = translate_rreg (SD_, RM2);
6756 dstreg1 = translate_rreg (SD_, RN1);
6757 dstreg2 = translate_rreg (SD_, RN2);
6759 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6760 State.regs[dstreg2] -= State.regs[srcreg2];
6761 State.regs[dstreg1] = result1;
6764 // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
6765 8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
6769 int srcreg1, dstreg1, dstreg2;
6773 srcreg1 = translate_rreg (SD_, RM1);
6774 dstreg1 = translate_rreg (SD_, RN1);
6775 dstreg2 = translate_rreg (SD_, RN2);
6777 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6778 State.regs[dstreg2] -= EXTEND4 (IMM4);
6779 State.regs[dstreg1] = result1;
6782 // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
6783 8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
6787 int srcreg1, srcreg2, dstreg1, dstreg2;
6790 srcreg1 = translate_rreg (SD_, RM1);
6791 srcreg2 = translate_rreg (SD_, RM2);
6792 dstreg1 = translate_rreg (SD_, RN1);
6793 dstreg2 = translate_rreg (SD_, RN2);
6795 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6796 State.regs[dstreg1] &= State.regs[srcreg1];
6799 // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
6800 8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
6804 int srcreg1, dstreg1, dstreg2;
6807 srcreg1 = translate_rreg (SD_, RM1);
6808 dstreg1 = translate_rreg (SD_, RN1);
6809 dstreg2 = translate_rreg (SD_, RN2);
6811 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6812 State.regs[dstreg1] &= State.regs[srcreg1];
6815 // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
6816 8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
6820 int srcreg1, srcreg2, dstreg1, dstreg2;
6824 srcreg1 = translate_rreg (SD_, RM1);
6825 srcreg2 = translate_rreg (SD_, RM2);
6826 dstreg1 = translate_rreg (SD_, RN1);
6827 dstreg2 = translate_rreg (SD_, RN2);
6829 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6830 State.regs[dstreg2] = State.regs[srcreg2];
6831 State.regs[dstreg1] = result1;
6834 // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
6835 8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
6839 int srcreg1, dstreg1, dstreg2;
6843 srcreg1 = translate_rreg (SD_, RM1);
6844 dstreg1 = translate_rreg (SD_, RN1);
6845 dstreg2 = translate_rreg (SD_, RN2);
6847 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6848 State.regs[dstreg2] = EXTEND4 (IMM4);
6849 State.regs[dstreg1] = result1;
6852 // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
6853 8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
6857 int srcreg1, srcreg2, dstreg1, dstreg2;
6862 srcreg1 = translate_rreg (SD_, RM1);
6863 srcreg2 = translate_rreg (SD_, RM2);
6864 dstreg1 = translate_rreg (SD_, RN1);
6865 dstreg2 = translate_rreg (SD_, RN2);
6867 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6868 temp = State.regs[dstreg2];
6869 temp >>= State.regs[srcreg2];
6870 State.regs[dstreg2] = temp;
6871 State.regs[dstreg1] = result1;
6874 // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
6875 8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
6879 int srcreg1, dstreg1, dstreg2;
6884 srcreg1 = translate_rreg (SD_, RM1);
6885 dstreg1 = translate_rreg (SD_, RN1);
6886 dstreg2 = translate_rreg (SD_, RN2);
6888 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6889 temp = State.regs[dstreg2];
6891 State.regs[dstreg2] = temp;
6892 State.regs[dstreg1] = result1;
6895 // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
6896 8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
6900 int srcreg1, srcreg2, dstreg1, dstreg2;
6904 srcreg1 = translate_rreg (SD_, RM1);
6905 srcreg2 = translate_rreg (SD_, RM2);
6906 dstreg1 = translate_rreg (SD_, RN1);
6907 dstreg2 = translate_rreg (SD_, RN2);
6909 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6910 State.regs[dstreg2] >>= State.regs[srcreg2];
6911 State.regs[dstreg1] = result1;
6914 // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
6915 8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
6919 int srcreg1, dstreg1, dstreg2;
6923 srcreg1 = translate_rreg (SD_, RM1);
6924 dstreg1 = translate_rreg (SD_, RN1);
6925 dstreg2 = translate_rreg (SD_, RN2);
6927 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6928 State.regs[dstreg2] >>= IMM4;
6929 State.regs[dstreg1] = result1;
6933 // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
6934 8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
6938 int srcreg1, srcreg2, dstreg1, dstreg2;
6942 srcreg1 = translate_rreg (SD_, RM1);
6943 srcreg2 = translate_rreg (SD_, RM2);
6944 dstreg1 = translate_rreg (SD_, RN1);
6945 dstreg2 = translate_rreg (SD_, RN2);
6947 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6948 State.regs[dstreg2] <<= State.regs[srcreg2];
6949 State.regs[dstreg1] = result1;
6952 // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
6953 8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
6957 int srcreg1, dstreg1, dstreg2;
6961 srcreg1 = translate_rreg (SD_, RM1);
6962 dstreg1 = translate_rreg (SD_, RN1);
6963 dstreg2 = translate_rreg (SD_, RN2);
6965 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6966 State.regs[dstreg2] <<= IMM4;
6967 State.regs[dstreg1] = result1;
6970 // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
6971 8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
6975 int srcreg1, srcreg2, dstreg1, dstreg2;
6976 signed32 temp, temp2, sum;
6979 srcreg1 = translate_rreg (SD_, RM1);
6980 srcreg2 = translate_rreg (SD_, RM2);
6981 dstreg1 = translate_rreg (SD_, RN1);
6982 dstreg2 = translate_rreg (SD_, RN2);
6984 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6985 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6986 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6987 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6988 sum = temp + temp2 + State.regs[REG_MCRL];
6990 State.regs[dstreg2] += State.regs[srcreg2];
6991 State.regs[dstreg1] = sum;
6994 // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
6995 8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
6999 int srcreg1, dstreg1, dstreg2;
7000 signed32 temp, temp2, sum;
7003 srcreg1 = translate_rreg (SD_, RM1);
7004 dstreg1 = translate_rreg (SD_, RN1);
7005 dstreg2 = translate_rreg (SD_, RN2);
7007 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7008 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7009 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7010 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7011 sum = temp + temp2 + State.regs[REG_MCRL];
7013 State.regs[dstreg2] += EXTEND4 (IMM4);
7014 State.regs[dstreg1] = sum;
7017 // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
7018 8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
7022 int srcreg1, srcreg2, dstreg1, dstreg2;
7023 signed32 temp, temp2, sum;
7026 srcreg1 = translate_rreg (SD_, RM1);
7027 srcreg2 = translate_rreg (SD_, RM2);
7028 dstreg1 = translate_rreg (SD_, RN1);
7029 dstreg2 = translate_rreg (SD_, RN2);
7031 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7032 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7033 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7034 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7035 sum = temp + temp2 + State.regs[REG_MCRL];
7037 State.regs[dstreg2] -= State.regs[srcreg2];
7038 State.regs[dstreg1] = sum;
7041 // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
7042 8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
7046 int srcreg1, dstreg1, dstreg2;
7047 signed32 temp, temp2, sum;
7050 srcreg1 = translate_rreg (SD_, RM1);
7051 dstreg1 = translate_rreg (SD_, RN1);
7052 dstreg2 = translate_rreg (SD_, RN2);
7054 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7055 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7056 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7057 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7058 sum = temp + temp2 + State.regs[REG_MCRL];
7060 State.regs[dstreg2] -= EXTEND4 (IMM4);
7061 State.regs[dstreg1] = sum;
7064 // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
7065 8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
7069 int srcreg1, srcreg2, dstreg1, dstreg2;
7070 signed32 temp, temp2, sum;
7073 srcreg1 = translate_rreg (SD_, RM1);
7074 srcreg2 = translate_rreg (SD_, RM2);
7075 dstreg1 = translate_rreg (SD_, RN1);
7076 dstreg2 = translate_rreg (SD_, RN2);
7078 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7079 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7080 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7081 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7082 sum = temp + temp2 + State.regs[REG_MCRL];
7084 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7085 State.regs[dstreg1] = sum;
7088 // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
7089 8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
7093 int srcreg1, dstreg1, dstreg2;
7094 signed32 temp, temp2, sum;
7097 srcreg1 = translate_rreg (SD_, RM1);
7098 dstreg1 = translate_rreg (SD_, RN1);
7099 dstreg2 = translate_rreg (SD_, RN2);
7101 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7102 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7103 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7104 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7105 sum = temp + temp2 + State.regs[REG_MCRL];
7107 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7108 State.regs[dstreg1] = sum;
7111 // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
7112 8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
7116 int srcreg1, srcreg2, dstreg1, dstreg2;
7117 signed32 temp, temp2, sum;
7120 srcreg1 = translate_rreg (SD_, RM1);
7121 srcreg2 = translate_rreg (SD_, RM2);
7122 dstreg1 = translate_rreg (SD_, RN1);
7123 dstreg2 = translate_rreg (SD_, RN2);
7125 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7126 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7127 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7128 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7129 sum = temp + temp2 + State.regs[REG_MCRL];
7131 State.regs[dstreg2] = State.regs[srcreg2];
7132 State.regs[dstreg1] = sum;
7135 // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
7136 8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
7140 int srcreg1, dstreg1, dstreg2;
7141 signed32 temp, temp2, sum;
7144 srcreg1 = translate_rreg (SD_, RM1);
7145 dstreg1 = translate_rreg (SD_, RN1);
7146 dstreg2 = translate_rreg (SD_, RN2);
7148 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7149 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7150 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7151 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7152 sum = temp + temp2 + State.regs[REG_MCRL];
7154 State.regs[dstreg2] = EXTEND4 (IMM4);
7155 State.regs[dstreg1] = sum;
7158 // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
7159 8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
7163 int srcreg1, srcreg2, dstreg1, dstreg2;
7164 signed32 temp, temp2, sum;
7167 srcreg1 = translate_rreg (SD_, RM1);
7168 srcreg2 = translate_rreg (SD_, RM2);
7169 dstreg1 = translate_rreg (SD_, RN1);
7170 dstreg2 = translate_rreg (SD_, RN2);
7172 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7173 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7174 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7175 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7176 sum = temp + temp2 + State.regs[REG_MCRL];
7178 temp = State.regs[dstreg2];
7179 temp >>= State.regs[srcreg2];
7180 State.regs[dstreg2] = temp;
7181 State.regs[dstreg1] = sum;
7184 // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
7185 8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
7189 int srcreg1, dstreg1, dstreg2;
7190 signed32 temp, temp2, sum;
7193 srcreg1 = translate_rreg (SD_, RM1);
7194 dstreg1 = translate_rreg (SD_, RN1);
7195 dstreg2 = translate_rreg (SD_, RN2);
7197 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7198 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7199 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7200 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7201 sum = temp + temp2 + State.regs[REG_MCRL];
7203 temp = State.regs[dstreg2];
7205 State.regs[dstreg2] = temp;
7206 State.regs[dstreg1] = sum;
7209 // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
7210 8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
7214 int srcreg1, srcreg2, dstreg1, dstreg2;
7215 signed32 temp, temp2, sum;
7218 srcreg1 = translate_rreg (SD_, RM1);
7219 srcreg2 = translate_rreg (SD_, RM2);
7220 dstreg1 = translate_rreg (SD_, RN1);
7221 dstreg2 = translate_rreg (SD_, RN2);
7223 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7224 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7225 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7226 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7227 sum = temp + temp2 + State.regs[REG_MCRL];
7229 State.regs[dstreg2] >>= State.regs[srcreg2];
7230 State.regs[dstreg1] = sum;
7233 // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
7234 8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
7238 int srcreg1, dstreg1, dstreg2;
7239 signed32 temp, temp2, sum;
7242 srcreg1 = translate_rreg (SD_, RM1);
7243 dstreg1 = translate_rreg (SD_, RN1);
7244 dstreg2 = translate_rreg (SD_, RN2);
7246 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7247 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7248 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7249 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7250 sum = temp + temp2 + State.regs[REG_MCRL];
7252 State.regs[dstreg2] >>= IMM4;
7253 State.regs[dstreg1] = sum;
7257 // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
7258 8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
7262 int srcreg1, srcreg2, dstreg1, dstreg2;
7263 signed32 temp, temp2, sum;
7266 srcreg1 = translate_rreg (SD_, RM1);
7267 srcreg2 = translate_rreg (SD_, RM2);
7268 dstreg1 = translate_rreg (SD_, RN1);
7269 dstreg2 = translate_rreg (SD_, RN2);
7271 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7272 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7273 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7274 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7275 sum = temp + temp2 + State.regs[REG_MCRL];
7277 State.regs[dstreg2] <<= State.regs[srcreg2];
7278 State.regs[dstreg1] = sum;
7281 // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
7282 8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
7286 int srcreg1, dstreg1, dstreg2;
7287 signed32 temp, temp2, sum;
7290 srcreg1 = translate_rreg (SD_, RM1);
7291 dstreg1 = translate_rreg (SD_, RN1);
7292 dstreg2 = translate_rreg (SD_, RN2);
7294 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7295 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7296 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7297 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7298 sum = temp + temp2 + State.regs[REG_MCRL];
7300 State.regs[dstreg2] <<= IMM4;
7301 State.regs[dstreg1] = sum;
7304 // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
7305 8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
7309 int srcreg1, srcreg2, dstreg1, dstreg2;
7313 srcreg1 = translate_rreg (SD_, RM1);
7314 srcreg2 = translate_rreg (SD_, RM2);
7315 dstreg1 = translate_rreg (SD_, RN1);
7316 dstreg2 = translate_rreg (SD_, RN2);
7318 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7319 State.regs[dstreg2] += State.regs[srcreg2];
7320 State.regs[dstreg1] = result1;
7323 // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
7324 8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
7328 int srcreg1, dstreg1, dstreg2;
7332 srcreg1 = translate_rreg (SD_, RM1);
7333 dstreg1 = translate_rreg (SD_, RN1);
7334 dstreg2 = translate_rreg (SD_, RN2);
7336 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7337 State.regs[dstreg2] += EXTEND4 (IMM4);
7338 State.regs[dstreg1] = result1;
7341 // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
7342 8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
7346 int srcreg1, srcreg2, dstreg1, dstreg2;
7350 srcreg1 = translate_rreg (SD_, RM1);
7351 srcreg2 = translate_rreg (SD_, RM2);
7352 dstreg1 = translate_rreg (SD_, RN1);
7353 dstreg2 = translate_rreg (SD_, RN2);
7355 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7356 State.regs[dstreg2] -= State.regs[srcreg2];
7357 State.regs[dstreg1] = result1;
7360 // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
7361 8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
7365 int srcreg1, dstreg1, dstreg2;
7369 srcreg1 = translate_rreg (SD_, RM1);
7370 dstreg1 = translate_rreg (SD_, RN1);
7371 dstreg2 = translate_rreg (SD_, RN2);
7373 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7374 State.regs[dstreg2] -= EXTEND4 (IMM4);
7375 State.regs[dstreg1] = result1;
7378 // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
7379 8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
7383 int srcreg1, srcreg2, dstreg1, dstreg2;
7386 srcreg1 = translate_rreg (SD_, RM1);
7387 srcreg2 = translate_rreg (SD_, RM2);
7388 dstreg1 = translate_rreg (SD_, RN1);
7389 dstreg2 = translate_rreg (SD_, RN2);
7391 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7392 State.regs[dstreg1] ^= State.regs[srcreg1];
7395 // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
7396 8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
7400 int srcreg1, dstreg1, dstreg2;
7403 srcreg1 = translate_rreg (SD_, RM1);
7404 dstreg1 = translate_rreg (SD_, RN1);
7405 dstreg2 = translate_rreg (SD_, RN2);
7407 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7408 State.regs[dstreg1] ^= State.regs[srcreg1];
7411 // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
7412 8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
7416 int srcreg1, srcreg2, dstreg1, dstreg2;
7420 srcreg1 = translate_rreg (SD_, RM1);
7421 srcreg2 = translate_rreg (SD_, RM2);
7422 dstreg1 = translate_rreg (SD_, RN1);
7423 dstreg2 = translate_rreg (SD_, RN2);
7425 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7426 State.regs[dstreg2] = State.regs[srcreg2];
7427 State.regs[dstreg1] = result1;
7430 // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
7431 8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
7435 int srcreg1, dstreg1, dstreg2;
7439 srcreg1 = translate_rreg (SD_, RM1);
7440 dstreg1 = translate_rreg (SD_, RN1);
7441 dstreg2 = translate_rreg (SD_, RN2);
7443 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7444 State.regs[dstreg2] = EXTEND4 (IMM4);
7445 State.regs[dstreg1] = result1;
7448 // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
7449 8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
7453 int srcreg1, srcreg2, dstreg1, dstreg2;
7458 srcreg1 = translate_rreg (SD_, RM1);
7459 srcreg2 = translate_rreg (SD_, RM2);
7460 dstreg1 = translate_rreg (SD_, RN1);
7461 dstreg2 = translate_rreg (SD_, RN2);
7463 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7464 temp = State.regs[dstreg2];
7465 temp >>= State.regs[srcreg2];
7466 State.regs[dstreg2] = temp;
7467 State.regs[dstreg1] = result1;
7470 // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
7471 8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
7475 int srcreg1, dstreg1, dstreg2;
7480 srcreg1 = translate_rreg (SD_, RM1);
7481 dstreg1 = translate_rreg (SD_, RN1);
7482 dstreg2 = translate_rreg (SD_, RN2);
7484 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7485 temp = State.regs[dstreg2];
7487 State.regs[dstreg2] = temp;
7488 State.regs[dstreg1] = result1;
7491 // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
7492 8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
7496 int srcreg1, srcreg2, dstreg1, dstreg2;
7500 srcreg1 = translate_rreg (SD_, RM1);
7501 srcreg2 = translate_rreg (SD_, RM2);
7502 dstreg1 = translate_rreg (SD_, RN1);
7503 dstreg2 = translate_rreg (SD_, RN2);
7505 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7506 State.regs[dstreg2] >>= State.regs[srcreg2];
7507 State.regs[dstreg1] = result1;
7510 // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
7511 8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
7515 int srcreg1, dstreg1, dstreg2;
7519 srcreg1 = translate_rreg (SD_, RM1);
7520 dstreg1 = translate_rreg (SD_, RN1);
7521 dstreg2 = translate_rreg (SD_, RN2);
7523 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7524 State.regs[dstreg2] >>= IMM4;
7525 State.regs[dstreg1] = result1;
7529 // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
7530 8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
7534 int srcreg1, srcreg2, dstreg1, dstreg2;
7538 srcreg1 = translate_rreg (SD_, RM1);
7539 srcreg2 = translate_rreg (SD_, RM2);
7540 dstreg1 = translate_rreg (SD_, RN1);
7541 dstreg2 = translate_rreg (SD_, RN2);
7543 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7544 State.regs[dstreg2] <<= State.regs[srcreg2];
7545 State.regs[dstreg1] = result1;
7548 // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
7549 8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
7553 int srcreg1, dstreg1, dstreg2;
7557 srcreg1 = translate_rreg (SD_, RM1);
7558 dstreg1 = translate_rreg (SD_, RN1);
7559 dstreg2 = translate_rreg (SD_, RN2);
7561 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7562 State.regs[dstreg2] <<= IMM4;
7563 State.regs[dstreg1] = result1;
7566 // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
7567 8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
7571 int srcreg1, srcreg2, dstreg1, dstreg2;
7575 srcreg1 = translate_rreg (SD_, RM1);
7576 srcreg2 = translate_rreg (SD_, RM2);
7577 dstreg1 = translate_rreg (SD_, RN1);
7578 dstreg2 = translate_rreg (SD_, RN2);
7580 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7581 State.regs[dstreg2] += State.regs[srcreg2];
7582 State.regs[dstreg1] = result1;
7585 // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
7586 8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
7590 int srcreg1, dstreg1, dstreg2;
7594 srcreg1 = translate_rreg (SD_, RM1);
7595 dstreg1 = translate_rreg (SD_, RN1);
7596 dstreg2 = translate_rreg (SD_, RN2);
7598 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7599 | ((State.regs[srcreg1] >> 16) & 0xffff));
7600 State.regs[dstreg2] += EXTEND4 (IMM4);
7601 State.regs[dstreg1] = result1;
7604 // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
7605 8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
7609 int srcreg1, srcreg2, dstreg1, dstreg2;
7613 srcreg1 = translate_rreg (SD_, RM1);
7614 srcreg2 = translate_rreg (SD_, RM2);
7615 dstreg1 = translate_rreg (SD_, RN1);
7616 dstreg2 = translate_rreg (SD_, RN2);
7618 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7619 | ((State.regs[srcreg1] >> 16) & 0xffff));
7620 State.regs[dstreg2] -= State.regs[srcreg2];
7621 State.regs[dstreg1] = result1;
7624 // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
7625 8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
7629 int srcreg1, dstreg1, dstreg2;
7633 srcreg1 = translate_rreg (SD_, RM1);
7634 dstreg1 = translate_rreg (SD_, RN1);
7635 dstreg2 = translate_rreg (SD_, RN2);
7637 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7638 | ((State.regs[srcreg1] >> 16) & 0xffff));
7639 State.regs[dstreg2] -= EXTEND4 (IMM4);
7640 State.regs[dstreg1] = result1;
7643 // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
7644 8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
7648 int srcreg1, srcreg2, dstreg1, dstreg2;
7651 srcreg1 = translate_rreg (SD_, RM1);
7652 srcreg2 = translate_rreg (SD_, RM2);
7653 dstreg1 = translate_rreg (SD_, RN1);
7654 dstreg2 = translate_rreg (SD_, RN2);
7656 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7657 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7658 | ((State.regs[srcreg1] >> 16) & 0xffff));
7661 // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
7662 8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
7666 int srcreg1, dstreg1, dstreg2;
7669 srcreg1 = translate_rreg (SD_, RM1);
7670 dstreg1 = translate_rreg (SD_, RN1);
7671 dstreg2 = translate_rreg (SD_, RN2);
7673 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7674 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7675 | ((State.regs[srcreg1] >> 16) & 0xffff));
7678 // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
7679 8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
7683 int srcreg1, srcreg2, dstreg1, dstreg2;
7687 srcreg1 = translate_rreg (SD_, RM1);
7688 srcreg2 = translate_rreg (SD_, RM2);
7689 dstreg1 = translate_rreg (SD_, RN1);
7690 dstreg2 = translate_rreg (SD_, RN2);
7692 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7693 | ((State.regs[srcreg1] >> 16) & 0xffff));
7694 State.regs[dstreg2] = State.regs[srcreg2];
7695 State.regs[dstreg1] = result1;
7698 // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
7699 8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
7703 int srcreg1, dstreg1, dstreg2;
7707 srcreg1 = translate_rreg (SD_, RM1);
7708 dstreg1 = translate_rreg (SD_, RN1);
7709 dstreg2 = translate_rreg (SD_, RN2);
7711 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7712 | ((State.regs[srcreg1] >> 16) & 0xffff));
7713 State.regs[dstreg2] = EXTEND4 (IMM4);
7714 State.regs[dstreg1] = result1;
7717 // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
7718 8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
7722 int srcreg1, srcreg2, dstreg1, dstreg2;
7727 srcreg1 = translate_rreg (SD_, RM1);
7728 srcreg2 = translate_rreg (SD_, RM2);
7729 dstreg1 = translate_rreg (SD_, RN1);
7730 dstreg2 = translate_rreg (SD_, RN2);
7732 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7733 | ((State.regs[srcreg1] >> 16) & 0xffff));
7734 temp = State.regs[dstreg2];
7735 temp >>= State.regs[srcreg2];
7736 State.regs[dstreg2] = temp;
7737 State.regs[dstreg1] = result1;
7740 // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
7741 8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
7745 int srcreg1, dstreg1, dstreg2;
7750 srcreg1 = translate_rreg (SD_, RM1);
7751 dstreg1 = translate_rreg (SD_, RN1);
7752 dstreg2 = translate_rreg (SD_, RN2);
7754 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7755 | ((State.regs[srcreg1] >> 16) & 0xffff));
7756 temp = State.regs[dstreg2];
7758 State.regs[dstreg2] = temp;
7759 State.regs[dstreg1] = result1;
7762 // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
7763 8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
7767 int srcreg1, srcreg2, dstreg1, dstreg2;
7771 srcreg1 = translate_rreg (SD_, RM1);
7772 srcreg2 = translate_rreg (SD_, RM2);
7773 dstreg1 = translate_rreg (SD_, RN1);
7774 dstreg2 = translate_rreg (SD_, RN2);
7776 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7777 | ((State.regs[srcreg1] >> 16) & 0xffff));
7778 State.regs[dstreg2] >>= State.regs[srcreg2];
7779 State.regs[dstreg1] = result1;
7782 // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
7783 8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
7787 int srcreg1, dstreg1, dstreg2;
7791 srcreg1 = translate_rreg (SD_, RM1);
7792 dstreg1 = translate_rreg (SD_, RN1);
7793 dstreg2 = translate_rreg (SD_, RN2);
7795 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7796 | ((State.regs[srcreg1] >> 16) & 0xffff));
7797 State.regs[dstreg2] >>= IMM4;
7798 State.regs[dstreg1] = result1;
7802 // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
7803 8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
7807 int srcreg1, srcreg2, dstreg1, dstreg2;
7811 srcreg1 = translate_rreg (SD_, RM1);
7812 srcreg2 = translate_rreg (SD_, RM2);
7813 dstreg1 = translate_rreg (SD_, RN1);
7814 dstreg2 = translate_rreg (SD_, RN2);
7816 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7817 | ((State.regs[srcreg1] >> 16) & 0xffff));
7818 State.regs[dstreg2] <<= State.regs[srcreg2];
7819 State.regs[dstreg1] = result1;
7822 // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
7823 8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
7827 int srcreg1, dstreg1, dstreg2;
7831 srcreg1 = translate_rreg (SD_, RM1);
7832 dstreg1 = translate_rreg (SD_, RN1);
7833 dstreg2 = translate_rreg (SD_, RN2);
7835 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7836 | ((State.regs[srcreg1] >> 16) & 0xffff));
7837 State.regs[dstreg2] <<= IMM4;
7838 State.regs[dstreg1] = result1;
7841 // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
7842 8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
7846 int srcreg1, srcreg2, dstreg1, dstreg2;
7850 srcreg1 = translate_rreg (SD_, RM1);
7851 srcreg2 = translate_rreg (SD_, RM2);
7852 dstreg1 = translate_rreg (SD_, RN1);
7853 dstreg2 = translate_rreg (SD_, RN2);
7855 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7856 State.regs[dstreg2] += State.regs[srcreg2];
7857 State.regs[dstreg1] = result1;
7860 // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
7861 8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
7865 int srcreg1, dstreg1, dstreg2;
7869 srcreg1 = translate_rreg (SD_, RM1);
7870 dstreg1 = translate_rreg (SD_, RN1);
7871 dstreg2 = translate_rreg (SD_, RN2);
7873 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7874 State.regs[dstreg2] += EXTEND4 (IMM4);
7875 State.regs[dstreg1] = result1;
7878 // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
7879 8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
7883 int srcreg1, srcreg2, dstreg1, dstreg2;
7887 srcreg1 = translate_rreg (SD_, RM1);
7888 srcreg2 = translate_rreg (SD_, RM2);
7889 dstreg1 = translate_rreg (SD_, RN1);
7890 dstreg2 = translate_rreg (SD_, RN2);
7892 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7893 State.regs[dstreg2] -= State.regs[srcreg2];
7894 State.regs[dstreg1] = result1;
7897 // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
7898 8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
7902 int srcreg1, dstreg1, dstreg2;
7906 srcreg1 = translate_rreg (SD_, RM1);
7907 dstreg1 = translate_rreg (SD_, RN1);
7908 dstreg2 = translate_rreg (SD_, RN2);
7910 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7911 State.regs[dstreg2] -= EXTEND4 (IMM4);
7912 State.regs[dstreg1] = result1;
7915 // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
7916 8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
7920 int srcreg1, srcreg2, dstreg1, dstreg2;
7923 srcreg1 = translate_rreg (SD_, RM1);
7924 srcreg2 = translate_rreg (SD_, RM2);
7925 dstreg1 = translate_rreg (SD_, RN1);
7926 dstreg2 = translate_rreg (SD_, RN2);
7928 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7929 State.regs[dstreg1] |= State.regs[srcreg1];
7932 // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
7933 8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
7937 int srcreg1, dstreg1, dstreg2;
7940 srcreg1 = translate_rreg (SD_, RM1);
7941 dstreg1 = translate_rreg (SD_, RN1);
7942 dstreg2 = translate_rreg (SD_, RN2);
7944 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7945 State.regs[dstreg1] |= State.regs[srcreg1];
7948 // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
7949 8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
7953 int srcreg1, srcreg2, dstreg1, dstreg2;
7957 srcreg1 = translate_rreg (SD_, RM1);
7958 srcreg2 = translate_rreg (SD_, RM2);
7959 dstreg1 = translate_rreg (SD_, RN1);
7960 dstreg2 = translate_rreg (SD_, RN2);
7962 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7963 State.regs[dstreg2] = State.regs[srcreg2];
7964 State.regs[dstreg1] = result1;
7967 // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
7968 8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
7972 int srcreg1, dstreg1, dstreg2;
7976 srcreg1 = translate_rreg (SD_, RM1);
7977 dstreg1 = translate_rreg (SD_, RN1);
7978 dstreg2 = translate_rreg (SD_, RN2);
7980 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7981 State.regs[dstreg2] = EXTEND4 (IMM4);
7982 State.regs[dstreg1] = result1;
7985 // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
7986 8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
7990 int srcreg1, srcreg2, dstreg1, dstreg2;
7995 srcreg1 = translate_rreg (SD_, RM1);
7996 srcreg2 = translate_rreg (SD_, RM2);
7997 dstreg1 = translate_rreg (SD_, RN1);
7998 dstreg2 = translate_rreg (SD_, RN2);
8000 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8001 temp = State.regs[dstreg2];
8002 temp >>= State.regs[srcreg2];
8003 State.regs[dstreg2] = temp;
8004 State.regs[dstreg1] = result1;
8007 // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
8008 8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
8012 int srcreg1, dstreg1, dstreg2;
8017 srcreg1 = translate_rreg (SD_, RM1);
8018 dstreg1 = translate_rreg (SD_, RN1);
8019 dstreg2 = translate_rreg (SD_, RN2);
8021 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8022 temp = State.regs[dstreg2];
8024 State.regs[dstreg2] = temp;
8025 State.regs[dstreg1] = result1;
8028 // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
8029 8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
8033 int srcreg1, srcreg2, dstreg1, dstreg2;
8037 srcreg1 = translate_rreg (SD_, RM1);
8038 srcreg2 = translate_rreg (SD_, RM2);
8039 dstreg1 = translate_rreg (SD_, RN1);
8040 dstreg2 = translate_rreg (SD_, RN2);
8042 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8043 State.regs[dstreg2] >>= State.regs[srcreg2];
8044 State.regs[dstreg1] = result1;
8047 // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
8048 8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
8052 int srcreg1, dstreg1, dstreg2;
8056 srcreg1 = translate_rreg (SD_, RM1);
8057 dstreg1 = translate_rreg (SD_, RN1);
8058 dstreg2 = translate_rreg (SD_, RN2);
8060 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8061 State.regs[dstreg2] >>= IMM4;
8062 State.regs[dstreg1] = result1;
8066 // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
8067 8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
8071 int srcreg1, srcreg2, dstreg1, dstreg2;
8075 srcreg1 = translate_rreg (SD_, RM1);
8076 srcreg2 = translate_rreg (SD_, RM2);
8077 dstreg1 = translate_rreg (SD_, RN1);
8078 dstreg2 = translate_rreg (SD_, RN2);
8080 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8081 State.regs[dstreg2] <<= State.regs[srcreg2];
8082 State.regs[dstreg1] = result1;
8085 // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
8086 8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
8090 int srcreg1, dstreg1, dstreg2;
8094 srcreg1 = translate_rreg (SD_, RM1);
8095 dstreg1 = translate_rreg (SD_, RN1);
8096 dstreg2 = translate_rreg (SD_, RN2);
8098 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8099 State.regs[dstreg2] <<= IMM4;
8100 State.regs[dstreg1] = result1;
8103 // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
8104 8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
8108 int srcreg1, srcreg2, dstreg1, dstreg2;
8112 srcreg1 = translate_rreg (SD_, RM1);
8113 srcreg2 = translate_rreg (SD_, RM2);
8114 dstreg1 = translate_rreg (SD_, RN1);
8115 dstreg2 = translate_rreg (SD_, RN2);
8117 if (State.regs[srcreg1] >= 0x7fff)
8119 else if (State.regs[srcreg1] <= 0xffff8000)
8120 result1 = 0xffff8000;
8122 result1 = State.regs[srcreg1];
8124 State.regs[dstreg2] += State.regs[srcreg2];
8125 State.regs[dstreg1] = result1;
8128 // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
8129 8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
8133 int srcreg1, dstreg1, dstreg2;
8137 srcreg1 = translate_rreg (SD_, RM1);
8138 dstreg1 = translate_rreg (SD_, RN1);
8139 dstreg2 = translate_rreg (SD_, RN2);
8141 if (State.regs[srcreg1] >= 0x7fff)
8143 else if (State.regs[srcreg1] <= 0xffff8000)
8144 result1 = 0xffff8000;
8146 result1 = State.regs[srcreg1];
8148 State.regs[dstreg2] += EXTEND4 (IMM4);
8149 State.regs[dstreg1] = result1;
8152 // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
8153 8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
8157 int srcreg1, srcreg2, dstreg1, dstreg2;
8161 srcreg1 = translate_rreg (SD_, RM1);
8162 srcreg2 = translate_rreg (SD_, RM2);
8163 dstreg1 = translate_rreg (SD_, RN1);
8164 dstreg2 = translate_rreg (SD_, RN2);
8166 if (State.regs[srcreg1] >= 0x7fff)
8168 else if (State.regs[srcreg1] <= 0xffff8000)
8169 result1 = 0xffff8000;
8171 result1 = State.regs[srcreg1];
8173 State.regs[dstreg2] -= State.regs[srcreg2];
8174 State.regs[dstreg1] = result1;
8177 // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
8178 8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
8182 int srcreg1, dstreg1, dstreg2;
8186 srcreg1 = translate_rreg (SD_, RM1);
8187 dstreg1 = translate_rreg (SD_, RN1);
8188 dstreg2 = translate_rreg (SD_, RN2);
8190 if (State.regs[srcreg1] >= 0x7fff)
8192 else if (State.regs[srcreg1] <= 0xffff8000)
8193 result1 = 0xffff8000;
8195 result1 = State.regs[srcreg1];
8197 State.regs[dstreg2] -= EXTEND4 (IMM4);
8198 State.regs[dstreg1] = result1;
8201 // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
8202 8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
8206 int srcreg1, srcreg2, dstreg1, dstreg2;
8209 srcreg1 = translate_rreg (SD_, RM1);
8210 srcreg2 = translate_rreg (SD_, RM2);
8211 dstreg1 = translate_rreg (SD_, RN1);
8212 dstreg2 = translate_rreg (SD_, RN2);
8214 genericCmp (State.regs[dstreg2], State.regs[dstreg1]);
8215 if (State.regs[srcreg1] >= 0x7fff)
8216 State.regs[dstreg1] = 0x7fff;
8217 else if (State.regs[srcreg1] <= 0xffff8000)
8218 State.regs[dstreg1] = 0xffff8000;
8220 State.regs[dstreg1] = State.regs[srcreg1];
8223 // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
8224 8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
8228 int srcreg1, dstreg1, dstreg2;
8231 srcreg1 = translate_rreg (SD_, RM1);
8232 dstreg1 = translate_rreg (SD_, RN1);
8233 dstreg2 = translate_rreg (SD_, RN2);
8235 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
8236 if (State.regs[srcreg1] >= 0x7fff)
8237 State.regs[dstreg1] = 0x7fff;
8238 else if (State.regs[srcreg1] <= 0xffff8000)
8239 State.regs[dstreg1] = 0xffff8000;
8241 State.regs[dstreg1] = State.regs[srcreg1];
8244 // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
8245 8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
8249 int srcreg1, srcreg2, dstreg1, dstreg2;
8253 srcreg1 = translate_rreg (SD_, RM1);
8254 srcreg2 = translate_rreg (SD_, RM2);
8255 dstreg1 = translate_rreg (SD_, RN1);
8256 dstreg2 = translate_rreg (SD_, RN2);
8258 if (State.regs[srcreg1] >= 0x7fff)
8260 else if (State.regs[srcreg1] <= 0xffff8000)
8261 result1 = 0xffff8000;
8263 result1 = State.regs[srcreg1];
8265 State.regs[dstreg2] = State.regs[srcreg2];
8266 State.regs[dstreg1] = result1;
8269 // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
8270 8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
8274 int srcreg1, dstreg1, dstreg2;
8278 srcreg1 = translate_rreg (SD_, RM1);
8279 dstreg1 = translate_rreg (SD_, RN1);
8280 dstreg2 = translate_rreg (SD_, RN2);
8282 if (State.regs[srcreg1] >= 0x7fff)
8284 else if (State.regs[srcreg1] <= 0xffff8000)
8285 result1 = 0xffff8000;
8287 result1 = State.regs[srcreg1];
8289 State.regs[dstreg2] = EXTEND4 (IMM4);
8290 State.regs[dstreg1] = result1;
8293 // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
8294 8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
8298 int srcreg1, srcreg2, dstreg1, dstreg2;
8303 srcreg1 = translate_rreg (SD_, RM1);
8304 srcreg2 = translate_rreg (SD_, RM2);
8305 dstreg1 = translate_rreg (SD_, RN1);
8306 dstreg2 = translate_rreg (SD_, RN2);
8308 if (State.regs[srcreg1] >= 0x7fff)
8310 else if (State.regs[srcreg1] <= 0xffff8000)
8311 result1 = 0xffff8000;
8313 result1 = State.regs[srcreg1];
8315 temp = State.regs[dstreg2];
8316 temp >>= State.regs[srcreg2];
8317 State.regs[dstreg2] = temp;
8318 State.regs[dstreg1] = result1;
8321 // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
8322 8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
8326 int srcreg1, dstreg1, dstreg2;
8331 srcreg1 = translate_rreg (SD_, RM1);
8332 dstreg1 = translate_rreg (SD_, RN1);
8333 dstreg2 = translate_rreg (SD_, RN2);
8335 if (State.regs[srcreg1] >= 0x7fff)
8337 else if (State.regs[srcreg1] <= 0xffff8000)
8338 result1 = 0xffff8000;
8340 result1 = State.regs[srcreg1];
8342 temp = State.regs[dstreg2];
8344 State.regs[dstreg2] = temp;
8345 State.regs[dstreg1] = result1;
8348 // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
8349 8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
8353 int srcreg1, srcreg2, dstreg1, dstreg2;
8357 srcreg1 = translate_rreg (SD_, RM1);
8358 srcreg2 = translate_rreg (SD_, RM2);
8359 dstreg1 = translate_rreg (SD_, RN1);
8360 dstreg2 = translate_rreg (SD_, RN2);
8362 if (State.regs[srcreg1] >= 0x7fff)
8364 else if (State.regs[srcreg1] <= 0xffff8000)
8365 result1 = 0xffff8000;
8367 result1 = State.regs[srcreg1];
8369 State.regs[dstreg2] >>= State.regs[srcreg2];
8370 State.regs[dstreg1] = result1;
8373 // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
8374 8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
8378 int srcreg1, dstreg1, dstreg2;
8382 srcreg1 = translate_rreg (SD_, RM1);
8383 dstreg1 = translate_rreg (SD_, RN1);
8384 dstreg2 = translate_rreg (SD_, RN2);
8386 if (State.regs[srcreg1] >= 0x7fff)
8388 else if (State.regs[srcreg1] <= 0xffff8000)
8389 result1 = 0xffff8000;
8391 result1 = State.regs[srcreg1];
8393 State.regs[dstreg2] >>= IMM4;
8394 State.regs[dstreg1] = result1;
8398 // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
8399 8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
8403 int srcreg1, srcreg2, dstreg1, dstreg2;
8407 srcreg1 = translate_rreg (SD_, RM1);
8408 srcreg2 = translate_rreg (SD_, RM2);
8409 dstreg1 = translate_rreg (SD_, RN1);
8410 dstreg2 = translate_rreg (SD_, RN2);
8412 if (State.regs[srcreg1] >= 0x7fff)
8414 else if (State.regs[srcreg1] <= 0xffff8000)
8415 result1 = 0xffff8000;
8417 result1 = State.regs[srcreg1];
8419 State.regs[dstreg2] <<= State.regs[srcreg2];
8420 State.regs[dstreg1] = result1;
8423 // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
8424 8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
8428 int srcreg1, dstreg1, dstreg2;
8432 srcreg1 = translate_rreg (SD_, RM1);
8433 dstreg1 = translate_rreg (SD_, RN1);
8434 dstreg2 = translate_rreg (SD_, RN2);
8436 if (State.regs[srcreg1] >= 0x7fff)
8438 else if (State.regs[srcreg1] <= 0xffff8000)
8439 result1 = 0xffff8000;
8441 result1 = State.regs[srcreg1];
8443 State.regs[dstreg2] <<= IMM4;
8444 State.regs[dstreg1] = result1;
8447 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
8448 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
8455 srcreg = translate_rreg (SD_, RM);
8456 dstreg = translate_rreg (SD_, RN);
8458 State.regs[dstreg] = load_word (State.regs[srcreg]);
8459 State.regs[srcreg] += EXTEND4 (IMM4);
8461 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
8463 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8468 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
8469 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
8476 srcreg = translate_rreg (SD_, RM);
8477 dstreg = translate_rreg (SD_, RN);
8479 State.regs[dstreg] = load_word (State.regs[srcreg]);
8480 State.regs[srcreg] += EXTEND4 (IMM4);
8483 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
8485 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8490 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
8491 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
8498 srcreg = translate_rreg (SD_, RM);
8499 dstreg = translate_rreg (SD_, RN);
8501 State.regs[dstreg] = load_word (State.regs[srcreg]);
8502 State.regs[srcreg] += EXTEND4 (IMM4);
8504 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8506 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8511 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
8512 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
8519 srcreg = translate_rreg (SD_, RM);
8520 dstreg = translate_rreg (SD_, RN);
8522 State.regs[dstreg] = load_word (State.regs[srcreg]);
8523 State.regs[srcreg] += EXTEND4 (IMM4);
8526 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8528 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8533 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
8534 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
8541 srcreg = translate_rreg (SD_, RM);
8542 dstreg = translate_rreg (SD_, RN);
8544 State.regs[dstreg] = load_word (State.regs[srcreg]);
8545 State.regs[srcreg] += EXTEND4 (IMM4);
8549 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8554 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
8555 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
8562 srcreg = translate_rreg (SD_, RM);
8563 dstreg = translate_rreg (SD_, RN);
8565 State.regs[dstreg] = load_word (State.regs[srcreg]);
8566 State.regs[srcreg] += EXTEND4 (IMM4);
8568 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
8570 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8575 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
8576 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
8583 srcreg = translate_rreg (SD_, RM);
8584 dstreg = translate_rreg (SD_, RN);
8586 State.regs[dstreg] = load_word (State.regs[srcreg]);
8587 State.regs[srcreg] += EXTEND4 (IMM4);
8591 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8596 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
8597 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
8604 srcreg = translate_rreg (SD_, RM);
8605 dstreg = translate_rreg (SD_, RN);
8607 State.regs[dstreg] = load_word (State.regs[srcreg]);
8608 State.regs[srcreg] += EXTEND4 (IMM4);
8610 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
8612 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8617 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
8618 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
8625 srcreg = translate_rreg (SD_, RM);
8626 dstreg = translate_rreg (SD_, RN);
8628 State.regs[dstreg] = load_word (State.regs[srcreg]);
8629 State.regs[srcreg] += EXTEND4 (IMM4);
8633 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8638 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
8639 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
8646 srcreg = translate_rreg (SD_, RM);
8647 dstreg = translate_rreg (SD_, RN);
8649 State.regs[dstreg] = load_word (State.regs[srcreg]);
8650 State.regs[srcreg] += EXTEND4 (IMM4);
8654 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8659 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
8660 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
8667 srcreg = translate_rreg (SD_, RM);
8668 dstreg = translate_rreg (SD_, RN);
8670 State.regs[dstreg] = load_word (State.regs[srcreg]);
8671 State.regs[srcreg] += EXTEND4 (IMM4);
8673 State.regs[REG_PC] = State.regs[REG_LAR] - 4;