3 // Given an extended register number, translate it into an index into the
4 // register array. This is necessary as the upper 8 extended registers are
5 // actually synonyms for the d0-d3/a0-a3 registers.
9 :function:::int:translate_rreg:int rreg
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
22 // 1111 0000 0010 00An; mov USP,An
23 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
28 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
32 // 1111 0000 0010 01An; mov SSP,An
33 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
38 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
42 // 1111 0000 0010 10An; mov MSP,An
43 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
48 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
52 // 1111 0000 0010 11An; mov PC,An
53 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
58 State.regs[REG_A0 + AN0] = PC;
62 // 1111 0000 0011 Am00; mov Am,USP
63 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
68 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
71 // 1111 0000 0011 Am01; mov Am,SSP
72 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
77 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
80 // 1111 0000 0011 Am10; mov Am,MSP
81 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
86 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
90 // 1111 0000 1110 imm4; syscall
91 8.0xf0+4.0xe,IMM4:D0t:::syscall
95 unsigned int sp, next_pc;
98 sp = State.regs[REG_SP];
99 next_pc = State.regs[REG_PC] + 2;
100 store_word (sp - 4, next_pc);
101 store_word (sp - 8, PSW);
102 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
107 // 1111 0010 1110 11Dn; mov EPSW,Dn
108 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
113 State.regs[REG_D0 + DN0] = PSW;
117 // 1111 0010 1111 Dm01; mov Dm,EPSW
118 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
123 PSW = State.regs[REG_D0 + DM1];
126 // 1111 0101 00Am Rn; mov Am,Rn
127 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
131 int destreg = translate_rreg (SD_, RN0);
134 State.regs[destreg] = State.regs[REG_A0 + AM1];
137 // 1111 0101 01Dm Rn; mov Dm,Rn
138 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
142 int destreg = translate_rreg (SD_, RN0);
145 State.regs[destreg] = State.regs[REG_D0 + DM1];
148 // 1111 0101 10Rm An; mov Rm,An
149 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
153 int destreg = translate_rreg (SD_, RM1);
156 State.regs[REG_A0 + AN0] = State.regs[destreg];
159 // 1111 0101 11Rm Dn; mov Rm,Dn
160 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
164 int destreg = translate_rreg (SD_, RM1);
167 State.regs[REG_D0 + DN0] = State.regs[destreg];
171 // 1111 1000 1100 1110 regs....; movm (USP),regs
172 8.0xf8+8.0xce+8.REGS:D1a:::movm
176 unsigned long usp = State.regs[REG_USP];
185 State.regs[REG_LAR] = load_word (usp);
187 State.regs[REG_LIR] = load_word (usp);
189 State.regs[REG_MDR] = load_word (usp);
191 State.regs[REG_A0 + 1] = load_word (usp);
193 State.regs[REG_A0] = load_word (usp);
195 State.regs[REG_D0 + 1] = load_word (usp);
197 State.regs[REG_D0] = load_word (usp);
203 State.regs[REG_A0 + 3] = load_word (usp);
209 State.regs[REG_A0 + 2] = load_word (usp);
215 State.regs[REG_D0 + 3] = load_word (usp);
221 State.regs[REG_D0 + 2] = load_word (usp);
225 /* start-sanitize-am33 */
226 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
230 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
232 State.regs[REG_E0 + 1] = load_word (usp);
234 State.regs[REG_E0 + 0] = load_word (usp);
240 State.regs[REG_E0 + 7] = load_word (usp);
242 State.regs[REG_E0 + 6] = load_word (usp);
244 State.regs[REG_E0 + 5] = load_word (usp);
246 State.regs[REG_E0 + 4] = load_word (usp);
252 State.regs[REG_E0 + 3] = load_word (usp);
254 State.regs[REG_E0 + 2] = load_word (usp);
258 /* end-sanitize-am33 */
260 /* And make sure to update the stack pointer. */
261 State.regs[REG_USP] = usp;
264 // 1111 1000 1100 1111 regs....; movm (USP),regs
265 8.0xf8+8.0xcf+8.REGS:D1b:::movm
269 unsigned long usp = State.regs[REG_USP];
272 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
277 store_word (usp, State.regs[REG_E0 + 2]);
279 store_word (usp, State.regs[REG_E0 + 3]);
285 store_word (usp, State.regs[REG_E0 + 4]);
287 store_word (usp, State.regs[REG_E0 + 5]);
289 store_word (usp, State.regs[REG_E0 + 6]);
291 store_word (usp, State.regs[REG_E0 + 7]);
297 store_word (usp, State.regs[REG_E0 + 0]);
299 store_word (usp, State.regs[REG_E0 + 1]);
301 /* Need to save MDQR, MCRH, MCRL, and MCVF */
304 /* end-sanitize-am33 */
309 store_word (usp, State.regs[REG_D0 + 2]);
315 store_word (usp, State.regs[REG_D0 + 3]);
321 store_word (usp, State.regs[REG_A0 + 2]);
327 store_word (usp, State.regs[REG_A0 + 3]);
333 store_word (usp, State.regs[REG_D0]);
335 store_word (usp, State.regs[REG_D0 + 1]);
337 store_word (usp, State.regs[REG_A0]);
339 store_word (usp, State.regs[REG_A0 + 1]);
341 store_word (usp, State.regs[REG_MDR]);
343 store_word (usp, State.regs[REG_LIR]);
345 store_word (usp, State.regs[REG_LAR]);
349 /* And make sure to update the stack pointer. */
350 State.regs[REG_USP] = usp;
353 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
354 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
359 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
362 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
363 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
368 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
371 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
372 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
380 srcreg = translate_rreg (SD_, RM2);
381 dstreg = translate_rreg (SD_, RN0);
382 State.regs[dstreg] = State.regs[srcreg];
385 // 1111 1001 0001 1000 Rn Rn; ext Rn
386 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
393 srcreg = translate_rreg (SD_, RN0);
394 if (State.regs[srcreg] & 0x80000000)
395 State.regs[REG_MDR] = -1;
397 State.regs[REG_MDR] = 0;
400 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
401 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
408 srcreg = translate_rreg (SD_, RM2);
409 dstreg = translate_rreg (SD_, RN0);
410 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
413 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
414 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
421 srcreg = translate_rreg (SD_, RM2);
422 dstreg = translate_rreg (SD_, RN0);
423 State.regs[dstreg] = State.regs[srcreg] & 0xff;
426 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
427 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
434 srcreg = translate_rreg (SD_, RM2);
435 dstreg = translate_rreg (SD_, RN0);
436 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
439 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
440 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
447 srcreg = translate_rreg (SD_, RM2);
448 dstreg = translate_rreg (SD_, RN0);
449 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
452 // 1111 1001 0110 1000 Rn Rn; clr Rn
453 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
460 dstreg = translate_rreg (SD_, RN0);
461 State.regs[dstreg] = 0;
463 PSW &= ~(PSW_V | PSW_C | PSW_N);
466 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
467 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
474 srcreg = translate_rreg (SD_, RM2);
475 dstreg = translate_rreg (SD_, RN0);
476 genericAdd (State.regs[srcreg], dstreg);
479 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
480 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
486 unsigned long reg1, reg2, sum;
489 srcreg = translate_rreg (SD_, RM2);
490 dstreg = translate_rreg (SD_, RN0);
492 reg1 = State.regs[srcreg];
493 reg2 = State.regs[dstreg];
494 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
495 State.regs[dstreg] = sum;
498 n = (sum & 0x80000000);
499 c = (sum < reg1) || (sum < reg2);
500 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
501 && (reg2 & 0x80000000) != (sum & 0x80000000));
503 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
504 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
505 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
508 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
509 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
516 srcreg = translate_rreg (SD_, RM2);
517 dstreg = translate_rreg (SD_, RN0);
518 genericSub (State.regs[srcreg], dstreg);
521 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
522 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
528 unsigned long reg1, reg2, difference;
531 srcreg = translate_rreg (SD_, RM2);
532 dstreg = translate_rreg (SD_, RN0);
534 reg1 = State.regs[srcreg];
535 reg2 = State.regs[dstreg];
536 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
537 State.regs[dstreg] = difference;
539 z = (difference == 0);
540 n = (difference & 0x80000000);
542 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
543 && (reg2 & 0x80000000) != (difference & 0x80000000));
545 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
546 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
547 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
550 // 1111 1001 1011 1000 Rn Rn; inc Rn
551 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
558 dstreg = translate_rreg (SD_, RN0);
559 genericAdd (1, dstreg);
562 // 1111 1001 1101 1000 Rn Rn; inc Rn
563 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
570 dstreg = translate_rreg (SD_, RN0);
571 State.regs[dstreg] += 4;
574 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
575 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
579 int srcreg1, srcreg2;
582 srcreg1 = translate_rreg (SD_, RN0);
583 srcreg2 = translate_rreg (SD_, RM2);
584 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
587 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
588 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
595 dstreg = translate_rreg (SD_, RN0);
599 State.regs[dstreg] = State.regs[REG_SP];
605 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
606 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
613 srcreg = translate_rreg (SD_, RM2);
617 State.regs[REG_SP] = State.regs[srcreg];
623 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
624 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
633 srcreg = translate_rreg (SD_, RM2);
634 dstreg = translate_rreg (SD_, RN0);
636 State.regs[dstreg] &= State.regs[srcreg];
637 z = (State.regs[dstreg] == 0);
638 n = (State.regs[dstreg] & 0x80000000) != 0;
639 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
640 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
643 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
644 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
652 srcreg = translate_rreg (SD_, RM2);
653 dstreg = translate_rreg (SD_, RN0);
655 State.regs[dstreg] |= State.regs[srcreg];
656 z = (State.regs[dstreg] == 0);
657 n = (State.regs[dstreg] & 0x80000000) != 0;
658 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
659 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
662 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
663 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
671 srcreg = translate_rreg (SD_, RM2);
672 dstreg = translate_rreg (SD_, RN0);
674 State.regs[dstreg] ^= State.regs[srcreg];
675 z = (State.regs[dstreg] == 0);
676 n = (State.regs[dstreg] & 0x80000000) != 0;
677 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
678 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
681 // 1111 1001 0011 1001 Rn Rn; not Rn
682 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
690 dstreg = translate_rreg (SD_, RN0);
692 State.regs[dstreg] = ~State.regs[dstreg];
693 z = (State.regs[dstreg] == 0);
694 n = (State.regs[dstreg] & 0x80000000) != 0;
695 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
696 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
699 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
700 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
709 srcreg = translate_rreg (SD_, RM2);
710 dstreg = translate_rreg (SD_, RN0);
712 temp = State.regs[dstreg];
714 temp >>= State.regs[srcreg];
715 State.regs[dstreg] = temp;
716 z = (State.regs[dstreg] == 0);
717 n = (State.regs[dstreg] & 0x80000000) != 0;
718 PSW &= ~(PSW_Z | PSW_N | PSW_C);
719 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
722 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
723 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
732 srcreg = translate_rreg (SD_, RM2);
733 dstreg = translate_rreg (SD_, RN0);
735 c = State.regs[dstreg] & 1;
736 State.regs[dstreg] >>= State.regs[srcreg];
737 z = (State.regs[dstreg] == 0);
738 n = (State.regs[dstreg] & 0x80000000) != 0;
739 PSW &= ~(PSW_Z | PSW_N | PSW_C);
740 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
743 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
744 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
752 srcreg = translate_rreg (SD_, RM2);
753 dstreg = translate_rreg (SD_, RN0);
755 State.regs[dstreg] <<= State.regs[srcreg];
756 z = (State.regs[dstreg] == 0);
757 n = (State.regs[dstreg] & 0x80000000) != 0;
758 PSW &= ~(PSW_Z | PSW_N);
759 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
762 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
763 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
771 dstreg = translate_rreg (SD_, RN0);
773 State.regs[dstreg] <<= 2;
774 z = (State.regs[dstreg] == 0);
775 n = (State.regs[dstreg] & 0x80000000) != 0;
776 PSW &= ~(PSW_Z | PSW_N);
777 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
780 // 1111 1001 1000 1001 Rn Rn; ror Rn
781 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
790 dstreg = translate_rreg (SD_, RN0);
792 value = State.regs[dstreg];
796 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
797 State.regs[dstreg] = value;
799 n = (value & 0x80000000) != 0;
800 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
801 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
804 // 1111 1001 1001 1001 Rn Rn; rol Rn
805 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
814 dstreg = translate_rreg (SD_, RN0);
816 value = State.regs[dstreg];
817 c = (value & 0x80000000) ? 1 : 0;
820 value |= ((PSW & PSW_C) != 0);
821 State.regs[dstreg] = value;
823 n = (value & 0x80000000) != 0;
824 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
825 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
828 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
829 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
834 unsigned long long temp;
838 srcreg = translate_rreg (SD_, RM2);
839 dstreg = translate_rreg (SD_, RN0);
841 temp = ((signed64)(signed32)State.regs[dstreg]
842 * (signed64)(signed32)State.regs[srcreg]);
843 State.regs[dstreg] = temp & 0xffffffff;
844 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
845 z = (State.regs[dstreg] == 0);
846 n = (State.regs[dstreg] & 0x80000000) != 0;
847 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
848 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
851 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
852 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
857 unsigned long long temp;
861 srcreg = translate_rreg (SD_, RM2);
862 dstreg = translate_rreg (SD_, RN0);
864 temp = ((unsigned64)State.regs[dstreg]
865 * (unsigned64)State.regs[srcreg]);
866 State.regs[dstreg] = temp & 0xffffffff;
867 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
868 z = (State.regs[dstreg] == 0);
869 n = (State.regs[dstreg] & 0x80000000) != 0;
870 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
871 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
874 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
875 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
884 srcreg = translate_rreg (SD_, RM2);
885 dstreg = translate_rreg (SD_, RN0);
887 temp = State.regs[REG_MDR];
889 temp |= State.regs[dstreg];
890 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
891 temp /= (long)State.regs[srcreg];
892 State.regs[dstreg] = temp & 0xffffffff;
893 z = (State.regs[dstreg] == 0);
894 n = (State.regs[dstreg] & 0x80000000) != 0;
895 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
896 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
899 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
900 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
905 unsigned long long temp;
909 srcreg = translate_rreg (SD_, RM2);
910 dstreg = translate_rreg (SD_, RN0);
912 temp = State.regs[REG_MDR];
914 temp |= State.regs[dstreg];
915 State.regs[REG_MDR] = temp % State.regs[srcreg];
916 temp /= State.regs[srcreg];
917 State.regs[dstreg] = temp & 0xffffffff;
918 z = (State.regs[dstreg] == 0);
919 n = (State.regs[dstreg] & 0x80000000) != 0;
920 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
921 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
925 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
926 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
933 srcreg = translate_rreg (SD_, RM0);
934 dstreg = translate_rreg (SD_, RN2);
935 State.regs[dstreg] = load_word (State.regs[srcreg]);
938 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
939 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
946 srcreg = translate_rreg (SD_, RM2);
947 dstreg = translate_rreg (SD_, RN0);
948 store_word (State.regs[dstreg], State.regs[srcreg]);
951 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
952 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
959 srcreg = translate_rreg (SD_, RM0);
960 dstreg = translate_rreg (SD_, RN2);
961 State.regs[dstreg] = load_byte (State.regs[srcreg]);
964 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
965 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
972 srcreg = translate_rreg (SD_, RM2);
973 dstreg = translate_rreg (SD_, RN0);
974 store_byte (State.regs[dstreg], State.regs[srcreg]);
977 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
978 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
985 srcreg = translate_rreg (SD_, RM0);
986 dstreg = translate_rreg (SD_, RN2);
987 State.regs[dstreg] = load_half (State.regs[srcreg]);
990 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
991 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
998 srcreg = translate_rreg (SD_, RM2);
999 dstreg = translate_rreg (SD_, RN0);
1000 store_half (State.regs[dstreg], State.regs[srcreg]);
1003 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1004 8.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
1011 srcreg = translate_rreg (SD_, RM0);
1012 dstreg = translate_rreg (SD_, RN2);
1013 State.regs[dstreg] = load_word (State.regs[srcreg]);
1014 State.regs[srcreg] += 4;
1017 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1018 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1025 srcreg = translate_rreg (SD_, RM2);
1026 dstreg = translate_rreg (SD_, RN0);
1027 store_word (State.regs[dstreg], State.regs[srcreg]);
1028 State.regs[dstreg] += 4;
1031 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1032 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1039 dstreg = translate_rreg (SD_, RN2);
1040 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1043 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1044 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1051 srcreg = translate_rreg (SD_, RM2);
1052 store_word (State.regs[REG_SP], State.regs[srcreg]);
1055 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1056 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1063 dstreg = translate_rreg (SD_, RN2);
1064 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1067 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1068 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1075 srcreg = translate_rreg (SD_, RM2);
1076 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1079 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1080 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1087 dstreg = translate_rreg (SD_, RN2);
1088 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1091 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1092 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1099 srcreg = translate_rreg (SD_, RM2);
1100 store_half (State.regs[REG_SP], State.regs[srcreg]);
1103 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1104 8.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
1111 srcreg = translate_rreg (SD_, RM0);
1112 dstreg = translate_rreg (SD_, RN2);
1113 State.regs[dstreg] = load_half (State.regs[srcreg]);
1114 State.regs[srcreg] += 2;
1117 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1118 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1125 srcreg = translate_rreg (SD_, RM2);
1126 dstreg = translate_rreg (SD_, RN0);
1127 store_half (State.regs[dstreg], State.regs[srcreg]);
1128 State.regs[dstreg] += 2;
1132 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1133 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1137 int srcreg1, srcreg2;
1138 long long temp, sum;
1142 srcreg1 = translate_rreg (SD_, RM2);
1143 srcreg2 = translate_rreg (SD_, RN0);
1145 temp = ((signed64)State.regs[srcreg2]
1146 * (signed64)State.regs[srcreg1]);
1147 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1148 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1149 State.regs[REG_MCRL] = sum;
1152 sum = State.regs[REG_MCRH] + temp + c;
1153 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1154 && (temp & 0x80000000) != (sum & 0x80000000));
1155 State.regs[REG_MCRH] = sum;
1157 State.regs[REG_MCVF] = 1;
1160 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1161 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1165 int srcreg1, srcreg2;
1166 unsigned long long temp, sum;
1170 srcreg1 = translate_rreg (SD_, RM2);
1171 srcreg2 = translate_rreg (SD_, RN0);
1173 temp = ((unsigned64)State.regs[srcreg2]
1174 * (unsigned64)State.regs[srcreg1]);
1175 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1176 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1177 State.regs[REG_MCRL] = sum;
1180 sum = State.regs[REG_MCRH] + temp + c;
1181 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1182 && (temp & 0x80000000) != (sum & 0x80000000));
1183 State.regs[REG_MCRH] = sum;
1185 State.regs[REG_MCVF] = 1;
1188 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1189 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1193 int srcreg1, srcreg2;
1198 srcreg1 = translate_rreg (SD_, RM2);
1199 srcreg2 = translate_rreg (SD_, RN0);
1201 temp = ((signed32)(State.regs[srcreg2] & 0xff)
1202 * (signed32)(State.regs[srcreg1] & 0xff));
1203 sum = State.regs[REG_MCRL] + temp;
1204 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1205 && (temp & 0x80000000) != (sum & 0x80000000));
1206 State.regs[REG_MCRL] = sum;
1208 State.regs[REG_MCVF] = 1;
1211 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1212 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1216 int srcreg1, srcreg2;
1217 long long temp, sum;
1221 srcreg1 = translate_rreg (SD_, RM2);
1222 srcreg2 = translate_rreg (SD_, RN0);
1224 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1225 * (unsigned32)(State.regs[srcreg1] & 0xff));
1226 sum = State.regs[REG_MCRL] + temp;
1227 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1228 && (temp & 0x80000000) != (sum & 0x80000000));
1229 State.regs[REG_MCRL] = sum;
1231 State.regs[REG_MCVF] = 1;
1234 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1235 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1239 int srcreg1, srcreg2;
1240 long long temp, sum;
1244 srcreg1 = translate_rreg (SD_, RM2);
1245 srcreg2 = translate_rreg (SD_, RN0);
1247 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1248 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1249 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1250 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1251 State.regs[REG_MCRL] = sum;
1254 sum = State.regs[REG_MCRH] + temp + c;
1255 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1256 && (temp & 0x80000000) != (sum & 0x80000000));
1257 State.regs[REG_MCRH] = sum;
1259 State.regs[REG_MCVF] = 1;
1262 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1263 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1267 int srcreg1, srcreg2;
1268 long long temp, sum;
1272 srcreg1 = translate_rreg (SD_, RM2);
1273 srcreg2 = translate_rreg (SD_, RN0);
1275 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1276 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1277 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1278 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1279 State.regs[REG_MCRL] = sum;
1282 sum = State.regs[REG_MCRH] + temp + c;
1283 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1284 && (temp & 0x80000000) != (sum & 0x80000000));
1285 State.regs[REG_MCRH] = sum;
1287 State.regs[REG_MCVF] = 1;
1290 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1291 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1295 int srcreg1, srcreg2;
1296 long temp, temp2, sum;
1300 srcreg1 = translate_rreg (SD_, RM2);
1301 srcreg2 = translate_rreg (SD_, RN0);
1303 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
1304 * (signed32)(State.regs[srcreg1] & 0xffff));
1305 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
1306 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
1307 sum = temp + temp2 + State.regs[REG_MCRL];
1308 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1309 && (temp & 0x80000000) != (sum & 0x80000000));
1310 State.regs[REG_MCRL] = sum;
1312 State.regs[REG_MCVF] = 1;
1315 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1316 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1320 int srcreg1, srcreg2;
1321 unsigned long temp, temp2, sum;
1325 srcreg1 = translate_rreg (SD_, RM2);
1326 srcreg2 = translate_rreg (SD_, RN0);
1328 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1329 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1330 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1331 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1332 sum = temp + temp2 + State.regs[REG_MCRL];
1333 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1334 && (temp & 0x80000000) != (sum & 0x80000000));
1335 State.regs[REG_MCRL] = sum;
1337 State.regs[REG_MCVF] = 1;
1340 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1341 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1349 srcreg = translate_rreg (SD_, RM2);
1350 dstreg = translate_rreg (SD_, RN0);
1352 temp = ((signed32)(State.regs[dstreg] & 0xffff)
1353 * (signed32)(State.regs[srcreg] & 0xffff));
1354 State.regs[REG_MDRQ] = temp;
1355 temp = ((signed32)((State.regs[dstreg] >> 16) & 0xffff)
1356 * (signed32)((State.regs[srcreg] >>16) & 0xffff));
1357 State.regs[dstreg] = temp;
1360 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1361 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1369 srcreg = translate_rreg (SD_, RM2);
1370 dstreg = translate_rreg (SD_, RN0);
1372 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1373 * (unsigned32)(State.regs[srcreg] & 0xffff));
1374 State.regs[REG_MDRQ] = temp;
1375 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1376 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1377 State.regs[dstreg] = temp;
1380 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1381 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1389 srcreg = translate_rreg (SD_, RM2);
1390 dstreg = translate_rreg (SD_, RN0);
1392 value = State.regs[srcreg];
1394 if (value >= 0x7fff)
1395 State.regs[dstreg] = 0x7fff;
1396 else if (value <= 0xffff8000)
1397 State.regs[dstreg] = 0xffff8000;
1399 State.regs[dstreg] = value;
1402 // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
1403 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1410 srcreg = translate_rreg (SD_, RM2);
1411 dstreg = translate_rreg (SD_, RN0);
1413 PSW &= ~(PSW_V | PSW_C);
1414 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1416 /* 32bit saturation. */
1417 if (State.regs[srcreg] == 0x20)
1421 tmp = State.regs[REG_MCRH];
1423 tmp += State.regs[REG_MCRL];
1425 if (tmp > 0x7fffffff)
1426 State.regs[dstreg] = 0x7fffffff;
1427 else if (tmp < 0xffffffff80000000LL)
1428 State.regs[dstreg] = 0x80000000;
1430 State.regs[dstreg] = tmp;
1432 /* 16bit saturation */
1433 else if (State.regs[srcreg] == 0x10)
1437 tmp = State.regs[REG_MCRH];
1439 tmp += State.regs[REG_MCRL];
1442 State.regs[dstreg] = 0x7fff;
1443 else if (tmp < 0xffffffffffff8000LL)
1444 State.regs[dstreg] = 0x8000;
1446 State.regs[dstreg] = tmp;
1448 /* 8 bit saturation */
1449 else if (State.regs[srcreg] == 0x8)
1453 tmp = State.regs[REG_MCRH];
1455 tmp += State.regs[REG_MCRL];
1458 State.regs[dstreg] = 0x7f;
1459 else if (tmp < 0xffffffffffffff80LL)
1460 State.regs[dstreg] = 0x80;
1462 State.regs[dstreg] = tmp;
1464 /* 9 bit saturation */
1465 else if (State.regs[srcreg] == 0x9)
1469 tmp = State.regs[REG_MCRH];
1471 tmp += State.regs[REG_MCRL];
1474 State.regs[dstreg] = 0x80;
1475 else if (tmp < 0xffffffffffffff81LL)
1476 State.regs[dstreg] = 0x81;
1478 State.regs[dstreg] = tmp;
1480 /* 9 bit saturation */
1481 else if (State.regs[srcreg] == 0x30)
1485 tmp = State.regs[REG_MCRH];
1487 tmp += State.regs[REG_MCRL];
1489 if (tmp > 0x7fffffffffffLL)
1490 tmp = 0x7fffffffffffLL;
1491 else if (tmp < 0xffff800000000000LL)
1492 tmp = 0xffff800000000000LL;
1495 State.regs[dstreg] = tmp;
1499 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1500 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1507 srcreg = translate_rreg (SD_, RM2);
1508 dstreg = translate_rreg (SD_, RN0);
1510 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1511 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1512 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1513 | ((State.regs[srcreg] >> 24) & 0xff));
1516 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1517 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1524 srcreg = translate_rreg (SD_, RM2);
1525 dstreg = translate_rreg (SD_, RN0);
1527 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1528 | ((State.regs[srcreg] >> 8) & 0xff)
1529 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1530 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1533 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1534 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1541 srcreg = translate_rreg (SD_, RM2);
1542 dstreg = translate_rreg (SD_, RN0);
1544 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1545 | ((State.regs[srcreg] >> 16) & 0xffff));
1548 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1549 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1558 srcreg = translate_rreg (SD_, RM2);
1559 dstreg = translate_rreg (SD_, RN0);
1561 temp = State.regs[srcreg];
1562 start = (State.regs[dstreg] & 0x1f) - 1;
1566 for (i = start; i >= 0; i--)
1568 if (temp & (1 << i))
1571 State.regs[dstreg] = i;
1579 State.regs[dstreg] = 0;
1582 PSW |= (c ? PSW_C : 0);
1586 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1587 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1594 dstreg = translate_rreg (SD_, RN0);
1595 State.regs[dstreg] = EXTEND8 (IMM8);
1598 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1599 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1606 dstreg = translate_rreg (SD_, RN0);
1607 State.regs[dstreg] = IMM8 & 0xff;
1610 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1611 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1618 dstreg = translate_rreg (SD_, RN0);
1619 genericAdd (EXTEND8 (IMM8), dstreg);
1622 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1623 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1629 unsigned long reg1, reg2, sum;
1632 dstreg = translate_rreg (SD_, RN0);
1634 imm = EXTEND8 (IMM8);
1635 reg2 = State.regs[dstreg];
1636 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1637 State.regs[dstreg] = sum;
1640 n = (sum & 0x80000000);
1641 c = (sum < imm) || (sum < reg2);
1642 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1643 && (reg2 & 0x80000000) != (sum & 0x80000000));
1645 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1646 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1647 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1650 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1651 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1658 dstreg = translate_rreg (SD_, RN0);
1660 genericSub (EXTEND8 (IMM8), dstreg);
1663 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1664 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1670 unsigned long reg1, reg2, difference;
1673 dstreg = translate_rreg (SD_, RN0);
1675 imm = EXTEND8 (IMM8);
1676 reg2 = State.regs[dstreg];
1677 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1678 State.regs[dstreg] = difference;
1680 z = (difference == 0);
1681 n = (difference & 0x80000000);
1683 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1684 && (reg2 & 0x80000000) != (difference & 0x80000000));
1686 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1687 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1688 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1691 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1692 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1699 srcreg = translate_rreg (SD_, RN0);
1700 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1703 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1704 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1713 State.regs[REG_SP] = EXTEND8 (IMM8);
1718 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1719 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1727 dstreg = translate_rreg (SD_, RN0);
1729 State.regs[dstreg] &= (IMM8 & 0xff);
1730 z = (State.regs[dstreg] == 0);
1731 n = (State.regs[dstreg] & 0x80000000) != 0;
1732 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1733 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1736 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1737 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1745 dstreg = translate_rreg (SD_, RN0);
1747 State.regs[dstreg] |= (IMM8 & 0xff);
1748 z = (State.regs[dstreg] == 0);
1749 n = (State.regs[dstreg] & 0x80000000) != 0;
1750 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1751 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1754 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1755 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1763 dstreg = translate_rreg (SD_, RN0);
1765 State.regs[dstreg] ^= (IMM8 & 0xff);
1766 z = (State.regs[dstreg] == 0);
1767 n = (State.regs[dstreg] & 0x80000000) != 0;
1768 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1769 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1772 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1773 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1782 dstreg = translate_rreg (SD_, RN0);
1784 temp = State.regs[dstreg];
1786 temp >>= (IMM8 & 0xff);
1787 State.regs[dstreg] = temp;
1788 z = (State.regs[dstreg] == 0);
1789 n = (State.regs[dstreg] & 0x80000000) != 0;
1790 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1791 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1794 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1795 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1803 dstreg = translate_rreg (SD_, RN0);
1805 c = State.regs[dstreg] & 1;
1806 State.regs[dstreg] >>= (IMM8 & 0xff);
1807 z = (State.regs[dstreg] == 0);
1808 n = (State.regs[dstreg] & 0x80000000) != 0;
1809 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1810 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1813 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1814 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1822 dstreg = translate_rreg (SD_, RN0);
1824 State.regs[dstreg] <<= (IMM8 & 0xff);
1825 z = (State.regs[dstreg] == 0);
1826 n = (State.regs[dstreg] & 0x80000000) != 0;
1827 PSW &= ~(PSW_Z | PSW_N);
1828 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1831 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1832 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1837 unsigned long long temp;
1841 dstreg = translate_rreg (SD_, RN0);
1843 temp = ((signed64)(signed32)State.regs[dstreg]
1844 * (signed64)(signed32)EXTEND8 (IMM8));
1845 State.regs[dstreg] = temp & 0xffffffff;
1846 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1847 z = (State.regs[dstreg] == 0);
1848 n = (State.regs[dstreg] & 0x80000000) != 0;
1849 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1850 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1853 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1854 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1859 unsigned long long temp;
1863 dstreg = translate_rreg (SD_, RN0);
1865 temp = ((unsigned64)State.regs[dstreg]
1866 * (unsigned64)(IMM8 & 0xff));
1867 State.regs[dstreg] = temp & 0xffffffff;
1868 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1869 z = (State.regs[dstreg] == 0);
1870 n = (State.regs[dstreg] & 0x80000000) != 0;
1871 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1872 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1875 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1876 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1883 srcreg = translate_rreg (SD_, RM0);
1884 genericBtst(IMM8, State.regs[srcreg]);
1888 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1889 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1896 srcreg = translate_rreg (SD_, RM0);
1897 dstreg = translate_rreg (SD_, RN2);
1898 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1901 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1902 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1908 srcreg = translate_rreg (SD_, RM2);
1909 dstreg = translate_rreg (SD_, RN0);
1910 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1913 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1914 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1920 srcreg = translate_rreg (SD_, RM0);
1921 dstreg = translate_rreg (SD_, RN2);
1922 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1925 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1926 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1932 srcreg = translate_rreg (SD_, RM2);
1933 dstreg = translate_rreg (SD_, RN0);
1934 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1937 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1938 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1944 srcreg = translate_rreg (SD_, RM0);
1945 dstreg = translate_rreg (SD_, RN2);
1946 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1949 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1950 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1956 srcreg = translate_rreg (SD_, RM2);
1957 dstreg = translate_rreg (SD_, RN0);
1958 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1961 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1962 8.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
1969 srcreg = translate_rreg (SD_, RM0);
1970 dstreg = translate_rreg (SD_, RN2);
1971 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1972 State.regs[srcreg] += 4;
1975 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1976 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1982 srcreg = translate_rreg (SD_, RM2);
1983 dstreg = translate_rreg (SD_, RN0);
1984 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1985 State.regs[dstreg] += 4;
1989 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
1990 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
1996 dstreg = translate_rreg (SD_, RN2);
1997 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2000 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2001 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2007 srcreg = translate_rreg (SD_, RM2);
2008 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2011 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2012 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2018 dstreg = translate_rreg (SD_, RN2);
2019 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2022 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2023 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2029 srcreg = translate_rreg (SD_, RM2);
2030 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2033 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2034 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2040 dstreg = translate_rreg (SD_, RN2);
2041 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2044 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2045 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2051 srcreg = translate_rreg (SD_, RM2);
2052 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2055 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2056 8.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
2063 srcreg = translate_rreg (SD_, RM0);
2064 dstreg = translate_rreg (SD_, RN2);
2065 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
2066 State.regs[srcreg] += 2;
2069 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2070 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2076 srcreg = translate_rreg (SD_, RM2);
2077 dstreg = translate_rreg (SD_, RN0);
2078 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2079 State.regs[dstreg] += 2;
2083 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2084 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2088 long long temp, sum;
2092 srcreg = translate_rreg (SD_, RN2);
2094 temp = ((signed64)EXTEND8 (IMM8)
2095 * (signed64)State.regs[srcreg]);
2096 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2097 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2098 State.regs[REG_MCRL] = sum;
2101 sum = State.regs[REG_MCRH] + temp + c;
2102 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2103 && (temp & 0x80000000) != (sum & 0x80000000));
2104 State.regs[REG_MCRH] = sum;
2106 State.regs[REG_MCVF] = 1;
2109 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2110 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2114 long long temp, sum;
2118 srcreg = translate_rreg (SD_, RN2);
2120 temp = ((unsigned64) (IMM8)
2121 * (unsigned64)State.regs[srcreg]);
2122 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2123 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2124 State.regs[REG_MCRL] = sum;
2127 sum = State.regs[REG_MCRH] + temp + c;
2128 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2129 && (temp & 0x80000000) != (sum & 0x80000000));
2130 State.regs[REG_MCRH] = sum;
2132 State.regs[REG_MCVF] = 1;
2135 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2136 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2140 long long temp, sum;
2144 srcreg = translate_rreg (SD_, RN2);
2146 temp = ((signed64)EXTEND8 (IMM8)
2147 * (signed64)State.regs[srcreg] & 0xff);
2148 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2149 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2150 State.regs[REG_MCRL] = sum;
2153 sum = State.regs[REG_MCRH] + temp + c;
2154 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2155 && (temp & 0x80000000) != (sum & 0x80000000));
2156 State.regs[REG_MCRH] = sum;
2158 State.regs[REG_MCVF] = 1;
2161 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2162 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2166 long long temp, sum;
2170 srcreg = translate_rreg (SD_, RN2);
2172 temp = ((unsigned64) (IMM8)
2173 * (unsigned64)State.regs[srcreg] & 0xff);
2174 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2175 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2176 State.regs[REG_MCRL] = sum;
2179 sum = State.regs[REG_MCRH] + temp + c;
2180 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2181 && (temp & 0x80000000) != (sum & 0x80000000));
2182 State.regs[REG_MCRH] = sum;
2184 State.regs[REG_MCVF] = 1;
2187 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2188 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2192 long long temp, sum;
2196 srcreg = translate_rreg (SD_, RN2);
2198 temp = ((signed64)EXTEND8 (IMM8)
2199 * (signed64)State.regs[srcreg] & 0xffff);
2200 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2201 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2202 State.regs[REG_MCRL] = sum;
2205 sum = State.regs[REG_MCRH] + temp + c;
2206 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2207 && (temp & 0x80000000) != (sum & 0x80000000));
2208 State.regs[REG_MCRH] = sum;
2210 State.regs[REG_MCVF] = 1;
2213 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2214 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2218 long long temp, sum;
2222 srcreg = translate_rreg (SD_, RN2);
2224 temp = ((unsigned64) (IMM8)
2225 * (unsigned64)State.regs[srcreg] & 0xffff);
2226 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2227 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2228 State.regs[REG_MCRL] = sum;
2231 sum = State.regs[REG_MCRH] + temp + c;
2232 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2233 && (temp & 0x80000000) != (sum & 0x80000000));
2234 State.regs[REG_MCRH] = sum;
2236 State.regs[REG_MCVF] = 1;
2239 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
2240 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2246 dstreg = translate_rreg (SD_, RN0);
2248 PSW &= ~(PSW_V | PSW_C);
2249 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2251 /* 32bit saturation. */
2256 tmp = State.regs[REG_MCRH];
2258 tmp += State.regs[REG_MCRL];
2260 if (tmp > 0x7fffffff)
2261 State.regs[dstreg] = 0x7fffffff;
2262 else if (tmp < 0xffffffff80000000LL)
2263 State.regs[dstreg] = 0x80000000;
2265 State.regs[dstreg] = tmp;
2267 /* 16bit saturation */
2268 else if (IMM8 == 0x10)
2272 tmp = State.regs[REG_MCRH];
2274 tmp += State.regs[REG_MCRL];
2277 State.regs[dstreg] = 0x7fff;
2278 else if (tmp < 0xffffffffffff8000LL)
2279 State.regs[dstreg] = 0x8000;
2281 State.regs[dstreg] = tmp;
2283 /* 8 bit saturation */
2284 else if (IMM8 == 0x8)
2288 tmp = State.regs[REG_MCRH];
2290 tmp += State.regs[REG_MCRL];
2293 State.regs[dstreg] = 0x7f;
2294 else if (tmp < 0xffffffffffffff80LL)
2295 State.regs[dstreg] = 0x80;
2297 State.regs[dstreg] = tmp;
2299 /* 9 bit saturation */
2300 else if (IMM8 == 0x9)
2304 tmp = State.regs[REG_MCRH];
2306 tmp += State.regs[REG_MCRL];
2309 State.regs[dstreg] = 0x80;
2310 else if (tmp < 0xffffffffffffff81LL)
2311 State.regs[dstreg] = 0x81;
2313 State.regs[dstreg] = tmp;
2315 /* 9 bit saturation */
2316 else if (IMM8 == 0x30)
2320 tmp = State.regs[REG_MCRH];
2322 tmp += State.regs[REG_MCRL];
2324 if (tmp > 0x7fffffffffffLL)
2325 tmp = 0x7fffffffffffLL;
2326 else if (tmp < 0xffff800000000000LL)
2327 tmp = 0xffff800000000000LL;
2330 State.regs[dstreg] = tmp;
2334 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2335 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2340 unsigned long sum, source1, source2;
2341 int srcreg1, srcreg2, dstreg;
2344 srcreg1 = translate_rreg (SD_, RM2);
2345 srcreg2 = translate_rreg (SD_, RN0);
2346 dstreg = translate_rreg (SD_, RD0);
2348 source1 = State.regs[srcreg1];
2349 source2 = State.regs[srcreg2];
2350 sum = source1 + source2;
2351 State.regs[dstreg] = sum;
2354 n = (sum & 0x80000000);
2355 c = (sum < source1) || (sum < source2);
2356 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2357 && (source1 & 0x80000000) != (sum & 0x80000000));
2359 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2360 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2361 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2364 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2365 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2370 unsigned long sum, source1, source2;
2371 int srcreg1, srcreg2, dstreg;
2374 srcreg1 = translate_rreg (SD_, RM2);
2375 srcreg2 = translate_rreg (SD_, RN0);
2376 dstreg = translate_rreg (SD_, RD0);
2378 source1 = State.regs[srcreg1];
2379 source2 = State.regs[srcreg2];
2380 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2381 State.regs[dstreg] = sum;
2384 n = (sum & 0x80000000);
2385 c = (sum < source1) || (sum < source2);
2386 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2387 && (source1 & 0x80000000) != (sum & 0x80000000));
2389 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2390 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2391 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2394 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2395 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2400 unsigned long difference, source1, source2;
2401 int srcreg1, srcreg2, dstreg;
2404 srcreg1 = translate_rreg (SD_, RM2);
2405 srcreg2 = translate_rreg (SD_, RN0);
2406 dstreg = translate_rreg (SD_, RD0);
2408 source1 = State.regs[srcreg1];
2409 source2 = State.regs[srcreg2];
2410 difference = source2 - source1;
2411 State.regs[dstreg] = difference;
2413 z = (difference == 0);
2414 n = (difference & 0x80000000);
2415 c = (source1 > source1);
2416 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2417 && (source1 & 0x80000000) != (difference & 0x80000000));
2419 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2420 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2421 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2424 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2425 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2430 unsigned long difference, source1, source2;
2431 int srcreg1, srcreg2, dstreg;
2434 srcreg1 = translate_rreg (SD_, RM2);
2435 srcreg2 = translate_rreg (SD_, RN0);
2436 dstreg = translate_rreg (SD_, RD0);
2438 source1 = State.regs[srcreg1];
2439 source2 = State.regs[srcreg2];
2440 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2441 State.regs[dstreg] = difference;
2443 z = (difference == 0);
2444 n = (difference & 0x80000000);
2445 c = (source1 > source2);
2446 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2447 && (source1 & 0x80000000) != (difference & 0x80000000));
2449 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2450 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2451 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2454 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2455 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2460 int srcreg1, srcreg2, dstreg;
2463 srcreg1 = translate_rreg (SD_, RM2);
2464 srcreg2 = translate_rreg (SD_, RN0);
2465 dstreg = translate_rreg (SD_, RD0);
2467 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2469 z = (State.regs[dstreg] == 0);
2470 n = (State.regs[dstreg] & 0x80000000);
2472 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2473 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2476 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2477 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2482 int srcreg1, srcreg2, dstreg;
2485 srcreg1 = translate_rreg (SD_, RM2);
2486 srcreg2 = translate_rreg (SD_, RN0);
2487 dstreg = translate_rreg (SD_, RD0);
2489 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2491 z = (State.regs[dstreg] == 0);
2492 n = (State.regs[dstreg] & 0x80000000);
2494 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2495 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2498 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2499 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2504 int srcreg1, srcreg2, dstreg;
2507 srcreg1 = translate_rreg (SD_, RM2);
2508 srcreg2 = translate_rreg (SD_, RN0);
2509 dstreg = translate_rreg (SD_, RD0);
2511 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2513 z = (State.regs[dstreg] == 0);
2514 n = (State.regs[dstreg] & 0x80000000);
2516 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2517 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2520 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2521 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2527 int srcreg1, srcreg2, dstreg;
2530 srcreg1 = translate_rreg (SD_, RM2);
2531 srcreg2 = translate_rreg (SD_, RN0);
2532 dstreg = translate_rreg (SD_, RD0);
2534 temp = State.regs[srcreg2];
2536 temp >>= State.regs[srcreg1];
2537 State.regs[dstreg] = temp;
2539 z = (State.regs[dstreg] == 0);
2540 n = (State.regs[dstreg] & 0x80000000);
2542 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2543 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2546 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2547 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2552 int srcreg1, srcreg2, dstreg;
2555 srcreg1 = translate_rreg (SD_, RM2);
2556 srcreg2 = translate_rreg (SD_, RN0);
2557 dstreg = translate_rreg (SD_, RD0);
2559 c = State.regs[srcreg2] & 1;
2560 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2562 z = (State.regs[dstreg] == 0);
2563 n = (State.regs[dstreg] & 0x80000000);
2565 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2566 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2569 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2570 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2575 int srcreg1, srcreg2, dstreg;
2578 srcreg1 = translate_rreg (SD_, RM2);
2579 srcreg2 = translate_rreg (SD_, RN0);
2580 dstreg = translate_rreg (SD_, RD0);
2582 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2584 z = (State.regs[dstreg] == 0);
2585 n = (State.regs[dstreg] & 0x80000000);
2587 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2588 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2591 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2592 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
2596 int srcreg1, srcreg2, dstreg1, dstreg2;
2597 signed long long temp;
2600 srcreg1 = translate_rreg (SD_, RM2);
2601 srcreg2 = translate_rreg (SD_, RN0);
2602 dstreg1 = translate_rreg (SD_, RD0);
2603 dstreg2 = translate_rreg (SD_, RD2);
2605 temp = ((signed64)(signed32)State.regs[srcreg1]
2606 * (signed64)(signed32)State.regs[srcreg2]);
2607 State.regs[dstreg1] = temp & 0xffffffff;
2608 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2611 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2612 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
2616 int srcreg1, srcreg2, dstreg1, dstreg2;
2617 signed long long temp;
2620 srcreg1 = translate_rreg (SD_, RM2);
2621 srcreg2 = translate_rreg (SD_, RN0);
2622 dstreg1 = translate_rreg (SD_, RD0);
2623 dstreg2 = translate_rreg (SD_, RD2);
2625 temp = ((unsigned64)(unsigned32)State.regs[srcreg1]
2626 * (unsigned64)(unsigned32)State.regs[srcreg2]);
2627 State.regs[dstreg1] = temp & 0xffffffff;
2628 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2631 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2632 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2639 dstreg = translate_rreg (SD_, RN2);
2640 State.regs[dstreg] = load_word (IMM8);
2643 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2644 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2651 srcreg = translate_rreg (SD_, RM2);
2652 store_word (IMM8, State.regs[srcreg]);
2655 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2656 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2663 dstreg = translate_rreg (SD_, RN2);
2664 State.regs[dstreg] = load_byte (IMM8);
2667 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2668 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2675 srcreg = translate_rreg (SD_, RM2);
2676 store_byte (IMM8, State.regs[srcreg]);
2679 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2680 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2687 dstreg = translate_rreg (SD_, RN2);
2688 State.regs[dstreg] = load_half (IMM8);
2691 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2692 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2699 srcreg = translate_rreg (SD_, RM2);
2700 store_half (IMM8, State.regs[srcreg]);
2703 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2704 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2708 int srcreg1, srcreg2, dstreg;
2711 srcreg1 = translate_rreg (SD_, RM0);
2712 srcreg1 = translate_rreg (SD_, RI0);
2713 dstreg = translate_rreg (SD_, RN0);
2714 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2717 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2718 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2722 int srcreg, dstreg1, dstreg2;
2725 srcreg = translate_rreg (SD_, RM0);
2726 dstreg1 = translate_rreg (SD_, RI0);
2727 dstreg2 = translate_rreg (SD_, RN0);
2728 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2731 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2732 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2736 int srcreg1, srcreg2, dstreg;
2739 srcreg1 = translate_rreg (SD_, RM0);
2740 srcreg1 = translate_rreg (SD_, RI0);
2741 dstreg = translate_rreg (SD_, RN0);
2742 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2745 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2746 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2750 int srcreg, dstreg1, dstreg2;
2753 srcreg = translate_rreg (SD_, RM0);
2754 dstreg1 = translate_rreg (SD_, RI0);
2755 dstreg2 = translate_rreg (SD_, RN0);
2756 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2759 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2760 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2764 int srcreg1, srcreg2, dstreg;
2767 srcreg1 = translate_rreg (SD_, RM0);
2768 srcreg1 = translate_rreg (SD_, RI0);
2769 dstreg = translate_rreg (SD_, RN0);
2770 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2773 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2774 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2778 int srcreg, dstreg1, dstreg2;
2781 srcreg = translate_rreg (SD_, RM0);
2782 dstreg1 = translate_rreg (SD_, RI0);
2783 dstreg2 = translate_rreg (SD_, RN0);
2784 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2787 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
2788 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mac
2792 int srcreg1, srcreg2, dstreg1, dstreg2;
2793 signed long long temp;
2798 srcreg1 = translate_rreg (SD_, RM2);
2799 srcreg2 = translate_rreg (SD_, RN0);
2800 dstreg1 = translate_rreg (SD_, RD0);
2801 dstreg2 = translate_rreg (SD_, RD2);
2803 temp = ((signed64)(signed32)State.regs[srcreg1]
2804 * (signed64)(signed32)State.regs[srcreg2]);
2806 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2807 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2808 State.regs[dstreg2] = sum;
2811 sum = State.regs[dstreg1] + temp + c;
2812 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2813 && (temp & 0x80000000) != (sum & 0x80000000));
2814 State.regs[dstreg1] = sum;
2816 State.regs[REG_MCVF] = 1;
2819 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
2820 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::macu
2824 int srcreg1, srcreg2, dstreg1, dstreg2;
2825 signed long long temp;
2830 srcreg1 = translate_rreg (SD_, RM2);
2831 srcreg2 = translate_rreg (SD_, RN0);
2832 dstreg1 = translate_rreg (SD_, RD0);
2833 dstreg2 = translate_rreg (SD_, RD2);
2835 temp = ((unsigned64)State.regs[srcreg1]
2836 * (unsigned64)State.regs[srcreg2]);
2838 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2839 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2840 State.regs[dstreg2] = sum;
2843 sum = State.regs[dstreg1] + temp + c;
2844 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2845 && (temp & 0x80000000) != (sum & 0x80000000));
2846 State.regs[dstreg1] = sum;
2848 State.regs[REG_MCVF] = 1;
2851 // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
2852 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2856 int srcreg1, srcreg2, dstreg;
2861 srcreg1 = translate_rreg (SD_, RM2);
2862 srcreg2 = translate_rreg (SD_, RN0);
2863 dstreg = translate_rreg (SD_, RD0);
2865 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2866 * (signed32)(State.regs[srcreg1] & 0xff));
2867 sum = State.regs[dstreg] + temp;
2868 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2869 && (temp & 0x80000000) != (sum & 0x80000000));
2870 State.regs[dstreg] = sum;
2872 State.regs[REG_MCVF] = 1;
2875 // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
2876 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2880 int srcreg1, srcreg2, dstreg;
2885 srcreg1 = translate_rreg (SD_, RM2);
2886 srcreg2 = translate_rreg (SD_, RN0);
2887 dstreg = translate_rreg (SD_, RD0);
2889 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2890 * (unsigned32)(State.regs[srcreg1] & 0xff));
2891 sum = State.regs[dstreg] + temp;
2892 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2893 && (temp & 0x80000000) != (sum & 0x80000000));
2894 State.regs[dstreg] = sum;
2896 State.regs[REG_MCVF] = 1;
2899 // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1
2900 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::mach
2904 int srcreg1, srcreg2, dstreg;
2909 srcreg1 = translate_rreg (SD_, RM2);
2910 srcreg2 = translate_rreg (SD_, RN0);
2911 dstreg = translate_rreg (SD_, RD0);
2913 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2914 * (signed32)(State.regs[srcreg1] & 0xffff));
2915 sum = State.regs[dstreg] + temp;
2916 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2917 && (temp & 0x80000000) != (sum & 0x80000000));
2918 State.regs[dstreg] = sum;
2920 State.regs[REG_MCVF] = 1;
2923 // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1
2924 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::machu
2928 int srcreg1, srcreg2, dstreg;
2933 srcreg1 = translate_rreg (SD_, RM2);
2934 srcreg2 = translate_rreg (SD_, RN0);
2935 dstreg = translate_rreg (SD_, RD0);
2937 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2938 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2939 sum = State.regs[dstreg] + temp;
2940 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2941 && (temp & 0x80000000) != (sum & 0x80000000));
2942 State.regs[dstreg] = sum;
2944 State.regs[REG_MCVF] = 1;
2947 // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
2948 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
2952 int srcreg1, srcreg2, dstreg;
2953 long temp, temp2, sum;
2957 srcreg1 = translate_rreg (SD_, RM2);
2958 srcreg2 = translate_rreg (SD_, RN0);
2959 dstreg = translate_rreg (SD_, RD0);
2961 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2962 * (signed32)(State.regs[srcreg1] & 0xffff));
2963 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
2964 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
2965 sum = temp + temp2 + State.regs[dstreg];
2966 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2967 && (temp & 0x80000000) != (sum & 0x80000000));
2968 State.regs[dstreg] = sum;
2970 State.regs[REG_MCVF] = 1;
2973 // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
2974 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
2978 int srcreg1, srcreg2, dstreg;
2979 long temp, temp2, sum;
2983 srcreg1 = translate_rreg (SD_, RM2);
2984 srcreg2 = translate_rreg (SD_, RN0);
2985 dstreg = translate_rreg (SD_, RD0);
2987 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2988 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2989 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
2990 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
2991 sum = temp + temp2 + State.regs[dstreg];
2992 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2993 && (temp & 0x80000000) != (sum & 0x80000000));
2994 State.regs[dstreg] = sum;
2996 State.regs[REG_MCVF] = 1;
2999 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3000 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulh
3004 int srcreg1, srcreg2, dstreg1, dstreg2;
3005 signed long long temp;
3008 srcreg1 = translate_rreg (SD_, RM2);
3009 srcreg2 = translate_rreg (SD_, RN0);
3010 dstreg1 = translate_rreg (SD_, RD0);
3011 dstreg2 = translate_rreg (SD_, RD2);
3013 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3014 * (signed32)(State.regs[srcreg1] & 0xffff));
3015 State.regs[dstreg2] = temp;
3016 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3017 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3018 State.regs[dstreg1] = temp;
3021 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3022 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulhu
3026 int srcreg1, srcreg2, dstreg1, dstreg2;
3027 signed long long temp;
3030 srcreg1 = translate_rreg (SD_, RM2);
3031 srcreg2 = translate_rreg (SD_, RN0);
3032 dstreg1 = translate_rreg (SD_, RD0);
3033 dstreg2 = translate_rreg (SD_, RD2);
3035 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3036 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3037 State.regs[dstreg2] = temp;
3038 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3039 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3040 State.regs[dstreg1] = temp;
3043 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3044 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3052 srcreg = translate_rreg (SD_, RM2);
3053 dstreg = translate_rreg (SD_, RN0);
3055 value = State.regs[srcreg];
3057 if (value >= 0x7fffff)
3058 State.regs[dstreg] = 0x7fffff;
3059 else if (value <= 0xff800000)
3060 State.regs[dstreg] = 0xff800000;
3062 State.regs[dstreg] = value;
3065 // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
3066 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3071 int srcreg1, srcreg2, dstreg;
3075 srcreg1 = translate_rreg (SD_, RM2);
3076 srcreg2 = translate_rreg (SD_, RN0);
3077 dstreg = translate_rreg (SD_, RD0);
3079 temp = State.regs[srcreg1];
3080 start = (State.regs[srcreg2] & 0x1f) - 1;
3084 for (i = start; i >= 0; i--)
3086 if (temp & (1 << i))
3089 State.regs[dstreg] = i;
3097 State.regs[dstreg] = 0;
3100 PSW |= (c ? PSW_C : 0);
3103 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3104 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3111 dstreg = translate_rreg (SD_, RN0);
3112 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3115 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
3116 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3123 dstreg = translate_rreg (SD_, RN0);
3124 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3127 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
3128 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3135 dstreg = translate_rreg (SD_, RN0);
3136 genericAdd (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
3139 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
3140 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3144 int dstreg, z, n, c, v;
3145 unsigned long sum, imm, reg2;
3148 dstreg = translate_rreg (SD_, RN0);
3150 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3151 reg2 = State.regs[dstreg];
3152 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3153 State.regs[dstreg] = sum;
3156 n = (sum & 0x80000000);
3157 c = (sum < imm) || (sum < reg2);
3158 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3159 && (reg2 & 0x80000000) != (sum & 0x80000000));
3161 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3162 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3163 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3166 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
3167 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3174 dstreg = translate_rreg (SD_, RN0);
3175 genericSub (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
3178 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
3179 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3183 int dstreg, z, n, c, v;
3184 unsigned long difference, imm, reg2;
3187 dstreg = translate_rreg (SD_, RN0);
3189 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3190 reg2 = State.regs[dstreg];
3191 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3192 State.regs[dstreg] = difference;
3194 z = (difference == 0);
3195 n = (difference & 0x80000000);
3197 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3198 && (reg2 & 0x80000000) != (difference & 0x80000000));
3200 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3201 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3202 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3205 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
3206 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3213 srcreg = translate_rreg (SD_, RN0);
3214 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3217 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
3218 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3226 State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3232 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3233 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3241 dstreg = translate_rreg (SD_, RN0);
3243 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3244 z = (State.regs[dstreg] == 0);
3245 n = (State.regs[dstreg] & 0x80000000) != 0;
3246 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3247 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3250 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3251 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3259 dstreg = translate_rreg (SD_, RN0);
3261 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3262 z = (State.regs[dstreg] == 0);
3263 n = (State.regs[dstreg] & 0x80000000) != 0;
3264 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3265 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3268 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3269 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3277 dstreg = translate_rreg (SD_, RN0);
3279 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3280 z = (State.regs[dstreg] == 0);
3281 n = (State.regs[dstreg] & 0x80000000) != 0;
3282 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3283 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3286 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3287 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3296 dstreg = translate_rreg (SD_, RN0);
3298 temp = State.regs[dstreg];
3300 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3301 State.regs[dstreg] = temp;
3302 z = (State.regs[dstreg] == 0);
3303 n = (State.regs[dstreg] & 0x80000000) != 0;
3304 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3305 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3309 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3310 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3318 dstreg = translate_rreg (SD_, RN0);
3320 c = State.regs[dstreg] & 1;
3321 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3322 z = (State.regs[dstreg] == 0);
3323 n = (State.regs[dstreg] & 0x80000000) != 0;
3324 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3325 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3328 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3329 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3337 dstreg = translate_rreg (SD_, RN0);
3339 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3340 z = (State.regs[dstreg] == 0);
3341 n = (State.regs[dstreg] & 0x80000000) != 0;
3342 PSW &= ~(PSW_Z | PSW_N);
3343 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3346 // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3347 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3352 unsigned long long temp;
3356 dstreg = translate_rreg (SD_, RN0);
3358 temp = ((signed64)(signed32)State.regs[dstreg]
3359 * (signed64)(signed32)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3360 State.regs[dstreg] = temp & 0xffffffff;
3361 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3362 z = (State.regs[dstreg] == 0);
3363 n = (State.regs[dstreg] & 0x80000000) != 0;
3364 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3365 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3368 // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3369 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3374 unsigned long long temp;
3378 dstreg = translate_rreg (SD_, RN0);
3380 temp = ((unsigned64)State.regs[dstreg]
3381 * (unsigned64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3382 State.regs[dstreg] = temp & 0xffffffff;
3383 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3384 z = (State.regs[dstreg] == 0);
3385 n = (State.regs[dstreg] & 0x80000000) != 0;
3386 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3387 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3390 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3391 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3398 srcreg = translate_rreg (SD_, RN0);
3399 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3402 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3403 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3410 srcreg = translate_rreg (SD_, RM0);
3411 dstreg = translate_rreg (SD_, RN2);
3412 State.regs[dstreg] = load_word (State.regs[srcreg]
3413 + FETCH24 (IMM24A, IMM24B, IMM24C));
3416 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3417 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3424 srcreg = translate_rreg (SD_, RM2);
3425 dstreg = translate_rreg (SD_, RN0);
3426 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3427 State.regs[srcreg]);
3430 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3431 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3438 srcreg = translate_rreg (SD_, RM0);
3439 dstreg = translate_rreg (SD_, RN2);
3440 State.regs[dstreg] = load_byte (State.regs[srcreg]
3441 + FETCH24 (IMM24A, IMM24B, IMM24C));
3444 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3445 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3452 srcreg = translate_rreg (SD_, RM2);
3453 dstreg = translate_rreg (SD_, RN0);
3454 store_byte (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3455 State.regs[srcreg]);
3458 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3459 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3466 srcreg = translate_rreg (SD_, RM0);
3467 dstreg = translate_rreg (SD_, RN2);
3468 State.regs[dstreg] = load_half (State.regs[srcreg]
3469 + FETCH24 (IMM24A, IMM24B, IMM24C));
3472 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3473 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3480 srcreg = translate_rreg (SD_, RM2);
3481 dstreg = translate_rreg (SD_, RN0);
3482 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3483 State.regs[srcreg]);
3486 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3487 8.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3494 srcreg = translate_rreg (SD_, RM0);
3495 dstreg = translate_rreg (SD_, RN2);
3496 State.regs[dstreg] = load_word (State.regs[srcreg]
3497 + FETCH24 (IMM24A, IMM24B, IMM24C));
3498 State.regs[srcreg] += 4;
3501 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3502 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3509 srcreg = translate_rreg (SD_, RM2);
3510 dstreg = translate_rreg (SD_, RN0);
3511 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3512 State.regs[srcreg]);
3513 State.regs[dstreg] += 4;
3517 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3518 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3525 dstreg = translate_rreg (SD_, RN2);
3526 State.regs[dstreg] = load_word (State.regs[REG_SP]
3527 + FETCH24 (IMM24A, IMM24B, IMM24C));
3530 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3531 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3538 srcreg = translate_rreg (SD_, RM2);
3539 store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3540 State.regs[srcreg]);
3543 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
3544 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3551 dstreg = translate_rreg (SD_, RN2);
3552 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3553 + FETCH24 (IMM24A, IMM24B, IMM24C));
3556 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3557 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3564 srcreg = translate_rreg (SD_, RM2);
3565 store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3566 State.regs[srcreg]);
3569 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3570 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3577 dstreg = translate_rreg (SD_, RN2);
3578 State.regs[dstreg] = load_half (State.regs[REG_SP]
3579 + FETCH24 (IMM24A, IMM24B, IMM24C));
3582 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3583 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3590 srcreg = translate_rreg (SD_, RM2);
3591 store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3592 State.regs[srcreg]);
3595 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3596 8.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3603 srcreg = translate_rreg (SD_, RM0);
3604 dstreg = translate_rreg (SD_, RN2);
3605 State.regs[dstreg] = load_half (State.regs[srcreg]
3606 + FETCH24 (IMM24A, IMM24B, IMM24C));
3607 State.regs[dstreg] += 2;
3610 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3611 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3618 srcreg = translate_rreg (SD_, RM2);
3619 dstreg = translate_rreg (SD_, RN0);
3620 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3621 State.regs[srcreg]);
3622 State.regs[srcreg] += 2;
3625 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
3626 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3631 long long temp, sum;
3635 srcreg = translate_rreg (SD_, RN2);
3637 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3638 * (signed64)State.regs[srcreg]);
3639 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3640 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3641 State.regs[REG_MCRL] = sum;
3644 sum = State.regs[REG_MCRH] + temp + c;
3645 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3646 && (temp & 0x80000000) != (sum & 0x80000000));
3647 State.regs[REG_MCRH] = sum;
3649 State.regs[REG_MCVF] = 1;
3652 // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
3653 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3658 long long temp, sum;
3662 srcreg = translate_rreg (SD_, RN2);
3664 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3665 * (unsigned64)State.regs[srcreg]);
3666 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3667 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3668 State.regs[REG_MCRL] = sum;
3671 sum = State.regs[REG_MCRH] + temp + c;
3672 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3673 && (temp & 0x80000000) != (sum & 0x80000000));
3674 State.regs[REG_MCRH] = sum;
3676 State.regs[REG_MCVF] = 1;
3679 // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
3680 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3685 long long temp, sum;
3689 srcreg = translate_rreg (SD_, RN2);
3691 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3692 * (signed64)State.regs[srcreg] & 0xff);
3693 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3694 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3695 State.regs[REG_MCRL] = sum;
3698 sum = State.regs[REG_MCRH] + temp + c;
3699 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3700 && (temp & 0x80000000) != (sum & 0x80000000));
3701 State.regs[REG_MCRH] = sum;
3703 State.regs[REG_MCVF] = 1;
3706 // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
3707 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3712 long long temp, sum;
3716 srcreg = translate_rreg (SD_, RN2);
3718 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3719 * (unsigned64)State.regs[srcreg] & 0xff);
3720 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3721 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3722 State.regs[REG_MCRL] = sum;
3725 sum = State.regs[REG_MCRH] + temp + c;
3726 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3727 && (temp & 0x80000000) != (sum & 0x80000000));
3728 State.regs[REG_MCRH] = sum;
3730 State.regs[REG_MCVF] = 1;
3733 // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
3734 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3739 long long temp, sum;
3743 srcreg = translate_rreg (SD_, RN2);
3745 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3746 * (signed64)State.regs[srcreg] & 0xffff);
3747 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3748 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3749 State.regs[REG_MCRL] = sum;
3752 sum = State.regs[REG_MCRH] + temp + c;
3753 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3754 && (temp & 0x80000000) != (sum & 0x80000000));
3755 State.regs[REG_MCRH] = sum;
3757 State.regs[REG_MCVF] = 1;
3760 // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
3761 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3766 long long temp, sum;
3770 srcreg = translate_rreg (SD_, RN2);
3772 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3773 * (unsigned64)State.regs[srcreg] & 0xffff);
3774 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3775 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3776 State.regs[REG_MCRL] = sum;
3779 sum = State.regs[REG_MCRH] + temp + c;
3780 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3781 && (temp & 0x80000000) != (sum & 0x80000000));
3782 State.regs[REG_MCRH] = sum;
3784 State.regs[REG_MCVF] = 1;
3787 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3788 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3795 dstreg = translate_rreg (SD_, RN2);
3796 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3799 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3800 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3807 srcreg = translate_rreg (SD_, RM2);
3808 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3812 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3813 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3820 dstreg = translate_rreg (SD_, RN2);
3821 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3824 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3825 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3832 srcreg = translate_rreg (SD_, RM2);
3833 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3837 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3838 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3845 dstreg = translate_rreg (SD_, RN2);
3846 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3849 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3850 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3857 srcreg = translate_rreg (SD_, RM2);
3858 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3862 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3863 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3870 dstreg = translate_rreg (SD_, RN0);
3871 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3874 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3875 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3882 dstreg = translate_rreg (SD_, RN0);
3883 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3886 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3887 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3894 dstreg = translate_rreg (SD_, RN0);
3895 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3898 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3899 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3904 unsigned int imm, reg2, sum;
3908 dstreg = translate_rreg (SD_, RN0);
3910 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3911 reg2 = State.regs[dstreg];
3912 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3913 State.regs[dstreg] = sum;
3916 n = (sum & 0x80000000);
3917 c = (sum < imm) || (sum < reg2);
3918 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3919 && (reg2 & 0x80000000) != (sum & 0x80000000));
3921 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3922 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3923 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3926 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
3927 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3934 dstreg = translate_rreg (SD_, RN0);
3935 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3938 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
3939 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
3944 unsigned int imm, reg2, difference;
3948 dstreg = translate_rreg (SD_, RN0);
3950 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3951 reg2 = State.regs[dstreg];
3952 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3953 State.regs[dstreg] = difference;
3955 z = (difference == 0);
3956 n = (difference & 0x80000000);
3958 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3959 && (reg2 & 0x80000000) != (difference & 0x80000000));
3961 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3962 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3963 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3966 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
3967 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
3974 srcreg = translate_rreg (SD_, RN0);
3975 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3978 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
3979 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
3986 State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3991 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
3992 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4000 dstreg = translate_rreg (SD_, RN0);
4002 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4003 z = (State.regs[dstreg] == 0);
4004 n = (State.regs[dstreg] & 0x80000000) != 0;
4005 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4006 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4009 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
4010 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4018 dstreg = translate_rreg (SD_, RN0);
4020 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4021 z = (State.regs[dstreg] == 0);
4022 n = (State.regs[dstreg] & 0x80000000) != 0;
4023 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4024 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4027 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
4028 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4036 dstreg = translate_rreg (SD_, RN0);
4038 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4039 z = (State.regs[dstreg] == 0);
4040 n = (State.regs[dstreg] & 0x80000000) != 0;
4041 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4042 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4045 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
4046 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4055 dstreg = translate_rreg (SD_, RN0);
4057 temp = State.regs[dstreg];
4059 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4060 State.regs[dstreg] = temp;
4061 z = (State.regs[dstreg] == 0);
4062 n = (State.regs[dstreg] & 0x80000000) != 0;
4063 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4064 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4067 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
4068 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4076 dstreg = translate_rreg (SD_, RN0);
4078 c = State.regs[dstreg] & 1;
4079 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4080 z = (State.regs[dstreg] == 0);
4081 n = (State.regs[dstreg] & 0x80000000) != 0;
4082 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4083 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4086 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
4087 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4095 dstreg = translate_rreg (SD_, RN0);
4097 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4098 z = (State.regs[dstreg] == 0);
4099 n = (State.regs[dstreg] & 0x80000000) != 0;
4100 PSW &= ~(PSW_Z | PSW_N);
4101 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4107 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
4108 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4115 srcreg = translate_rreg (SD_, RN0);
4116 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4119 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
4120 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4127 srcreg = translate_rreg (SD_, RM0);
4128 dstreg = translate_rreg (SD_, RN2);
4129 State.regs[dstreg] = load_word (State.regs[srcreg]
4130 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4133 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
4134 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4141 srcreg = translate_rreg (SD_, RM2);
4142 dstreg = translate_rreg (SD_, RN0);
4143 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4144 State.regs[srcreg]);
4147 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
4148 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4155 srcreg = translate_rreg (SD_, RM0);
4156 dstreg = translate_rreg (SD_, RN2);
4157 State.regs[dstreg] = load_byte (State.regs[srcreg]
4158 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4161 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
4162 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4169 srcreg = translate_rreg (SD_, RM2);
4170 dstreg = translate_rreg (SD_, RN0);
4171 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4172 State.regs[srcreg]);
4175 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
4176 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4183 srcreg = translate_rreg (SD_, RM0);
4184 dstreg = translate_rreg (SD_, RN2);
4185 State.regs[dstreg] = load_half (State.regs[srcreg]
4186 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4189 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
4190 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4197 srcreg = translate_rreg (SD_, RM2);
4198 dstreg = translate_rreg (SD_, RN0);
4199 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4200 State.regs[srcreg]);
4203 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
4204 8.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4211 srcreg = translate_rreg (SD_, RM0);
4212 dstreg = translate_rreg (SD_, RN2);
4213 State.regs[dstreg] = load_word (State.regs[srcreg]
4214 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4215 State.regs[srcreg] += 4;
4218 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
4219 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4226 srcreg = translate_rreg (SD_, RM2);
4227 dstreg = translate_rreg (SD_, RN0);
4228 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4229 State.regs[srcreg]);
4230 State.regs[dstreg] += 4;
4234 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
4235 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4242 dstreg = translate_rreg (SD_, RN2);
4243 State.regs[dstreg] = load_word (State.regs[REG_SP]
4244 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4247 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
4248 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4255 srcreg = translate_rreg (SD_, RM2);
4256 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4257 State.regs[srcreg]);
4260 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
4261 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4268 dstreg = translate_rreg (SD_, RN2);
4269 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4270 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4273 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
4274 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4281 srcreg = translate_rreg (SD_, RM2);
4282 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4283 State.regs[srcreg]);
4286 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4287 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4294 dstreg = translate_rreg (SD_, RN2);
4295 State.regs[dstreg] = load_half (State.regs[REG_SP]
4296 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4299 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4300 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4307 srcreg = translate_rreg (SD_, RM2);
4308 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4309 State.regs[srcreg]);
4313 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
4314 8.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4321 srcreg = translate_rreg (SD_, RM0);
4322 dstreg = translate_rreg (SD_, RN2);
4323 State.regs[dstreg] = load_half (State.regs[srcreg]
4324 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4325 State.regs[srcreg] += 2;
4328 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
4329 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4336 srcreg = translate_rreg (SD_, RM2);
4337 dstreg = translate_rreg (SD_, RN0);
4338 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4339 State.regs[srcreg]);
4340 State.regs[dstreg] += 2;
4355 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4356 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4363 dstreg = translate_rreg (SD_, RN2);
4364 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4367 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4368 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4375 srcreg = translate_rreg (SD_, RM2);
4376 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4379 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4380 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4387 dstreg = translate_rreg (SD_, RN2);
4388 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4391 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4392 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4399 srcreg = translate_rreg (SD_, RM2);
4400 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4403 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4404 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4411 dstreg = translate_rreg (SD_, RN2);
4412 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4415 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4416 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4423 srcreg = translate_rreg (SD_, RM2);
4424 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);