3 // Given an extended register number, translate it into an index into the
4 // register array. This is necessary as the upper 8 extended registers are
5 // actually synonyms for the d0-d3/a0-a3 registers.
9 :function:::int:translate_rreg:int rreg
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
22 :function:::int:translate_xreg:int xreg
41 // 1111 0000 0010 00An; mov USP,An
42 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
47 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
51 // 1111 0000 0010 01An; mov SSP,An
52 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
57 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
61 // 1111 0000 0010 10An; mov MSP,An
62 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
67 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
71 // 1111 0000 0010 11An; mov PC,An
72 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
77 State.regs[REG_A0 + AN0] = PC;
81 // 1111 0000 0011 Am00; mov Am,USP
82 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
87 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
90 // 1111 0000 0011 Am01; mov Am,SSP
91 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
96 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
99 // 1111 0000 0011 Am10; mov Am,MSP
100 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
105 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
109 // 1111 0000 1110 imm4; syscall
110 8.0xf0+4.0xe,IMM4:D0t:::syscall
114 unsigned32 sp, next_pc;
117 sp = State.regs[REG_SP];
118 next_pc = State.regs[REG_PC] + 2;
119 store_word (sp - 4, next_pc);
120 store_word (sp - 8, PSW);
121 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
126 // 1111 0010 1110 11Dn; mov EPSW,Dn
127 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
132 State.regs[REG_D0 + DN0] = PSW;
136 // 1111 0010 1111 Dm01; mov Dm,EPSW
137 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
142 PSW = State.regs[REG_D0 + DM1];
145 // 1111 0101 00Am Rn; mov Am,Rn
146 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
150 int destreg = translate_rreg (SD_, RN0);
153 State.regs[destreg] = State.regs[REG_A0 + AM1];
156 // 1111 0101 01Dm Rn; mov Dm,Rn
157 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
161 int destreg = translate_rreg (SD_, RN0);
164 State.regs[destreg] = State.regs[REG_D0 + DM1];
167 // 1111 0101 10Rm An; mov Rm,An
168 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
172 int destreg = translate_rreg (SD_, RM1);
175 State.regs[REG_A0 + AN0] = State.regs[destreg];
178 // 1111 0101 11Rm Dn; mov Rm,Dn
179 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
183 int destreg = translate_rreg (SD_, RM1);
186 State.regs[REG_D0 + DN0] = State.regs[destreg];
190 // 1111 1000 1100 1110 regs....; movm (USP),regs
191 8.0xf8+8.0xce+8.REGS:D1a:::movm
195 unsigned32 usp = State.regs[REG_USP];
204 State.regs[REG_LAR] = load_word (usp);
206 State.regs[REG_LIR] = load_word (usp);
208 State.regs[REG_MDR] = load_word (usp);
210 State.regs[REG_A0 + 1] = load_word (usp);
212 State.regs[REG_A0] = load_word (usp);
214 State.regs[REG_D0 + 1] = load_word (usp);
216 State.regs[REG_D0] = load_word (usp);
222 State.regs[REG_A0 + 3] = load_word (usp);
228 State.regs[REG_A0 + 2] = load_word (usp);
234 State.regs[REG_D0 + 3] = load_word (usp);
240 State.regs[REG_D0 + 2] = load_word (usp);
244 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
249 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
251 State.regs[REG_E0 + 1] = load_word (usp);
253 State.regs[REG_E0 + 0] = load_word (usp);
259 State.regs[REG_E0 + 7] = load_word (usp);
261 State.regs[REG_E0 + 6] = load_word (usp);
263 State.regs[REG_E0 + 5] = load_word (usp);
265 State.regs[REG_E0 + 4] = load_word (usp);
271 State.regs[REG_E0 + 3] = load_word (usp);
273 State.regs[REG_E0 + 2] = load_word (usp);
278 /* And make sure to update the stack pointer. */
279 State.regs[REG_USP] = usp;
282 // 1111 1000 1100 1111 regs....; movm (USP),regs
283 8.0xf8+8.0xcf+8.REGS:D1b:::movm
287 unsigned32 usp = State.regs[REG_USP];
290 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
296 store_word (usp, State.regs[REG_E0 + 2]);
298 store_word (usp, State.regs[REG_E0 + 3]);
304 store_word (usp, State.regs[REG_E0 + 4]);
306 store_word (usp, State.regs[REG_E0 + 5]);
308 store_word (usp, State.regs[REG_E0 + 6]);
310 store_word (usp, State.regs[REG_E0 + 7]);
316 store_word (usp, State.regs[REG_E0 + 0]);
318 store_word (usp, State.regs[REG_E0 + 1]);
320 /* Need to save MDQR, MCRH, MCRL, and MCVF */
327 store_word (usp, State.regs[REG_D0 + 2]);
333 store_word (usp, State.regs[REG_D0 + 3]);
339 store_word (usp, State.regs[REG_A0 + 2]);
345 store_word (usp, State.regs[REG_A0 + 3]);
351 store_word (usp, State.regs[REG_D0]);
353 store_word (usp, State.regs[REG_D0 + 1]);
355 store_word (usp, State.regs[REG_A0]);
357 store_word (usp, State.regs[REG_A0 + 1]);
359 store_word (usp, State.regs[REG_MDR]);
361 store_word (usp, State.regs[REG_LIR]);
363 store_word (usp, State.regs[REG_LAR]);
367 /* And make sure to update the stack pointer. */
368 State.regs[REG_USP] = usp;
371 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
372 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
377 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
380 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
381 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
386 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
389 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
390 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
398 srcreg = translate_rreg (SD_, RM2);
399 dstreg = translate_rreg (SD_, RN0);
400 State.regs[dstreg] = State.regs[srcreg];
403 // 1111 1001 0001 1000 Rn Rn; ext Rn
404 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
411 srcreg = translate_rreg (SD_, RN0);
412 if (State.regs[srcreg] & 0x80000000)
413 State.regs[REG_MDR] = -1;
415 State.regs[REG_MDR] = 0;
418 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
419 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
426 srcreg = translate_rreg (SD_, RM2);
427 dstreg = translate_rreg (SD_, RN0);
428 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
431 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
432 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
439 srcreg = translate_rreg (SD_, RM2);
440 dstreg = translate_rreg (SD_, RN0);
441 State.regs[dstreg] = State.regs[srcreg] & 0xff;
444 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
445 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
452 srcreg = translate_rreg (SD_, RM2);
453 dstreg = translate_rreg (SD_, RN0);
454 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
457 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
458 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
465 srcreg = translate_rreg (SD_, RM2);
466 dstreg = translate_rreg (SD_, RN0);
467 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
470 // 1111 1001 0110 1000 Rn Rn; clr Rn
471 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
478 dstreg = translate_rreg (SD_, RN0);
479 State.regs[dstreg] = 0;
481 PSW &= ~(PSW_V | PSW_C | PSW_N);
484 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
485 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
492 srcreg = translate_rreg (SD_, RM2);
493 dstreg = translate_rreg (SD_, RN0);
494 genericAdd (State.regs[srcreg], dstreg);
497 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
498 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
504 unsigned32 reg1, reg2, sum;
507 srcreg = translate_rreg (SD_, RM2);
508 dstreg = translate_rreg (SD_, RN0);
510 reg1 = State.regs[srcreg];
511 reg2 = State.regs[dstreg];
512 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
513 State.regs[dstreg] = sum;
515 z = ((PSW & PSW_Z) != 0) && (sum == 0);
516 n = (sum & 0x80000000);
517 c = (sum < reg1) || (sum < reg2);
518 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
519 && (reg2 & 0x80000000) != (sum & 0x80000000));
521 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
522 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
523 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
526 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
527 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
534 srcreg = translate_rreg (SD_, RM2);
535 dstreg = translate_rreg (SD_, RN0);
536 genericSub (State.regs[srcreg], dstreg);
539 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
540 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
546 unsigned32 reg1, reg2, difference;
549 srcreg = translate_rreg (SD_, RM2);
550 dstreg = translate_rreg (SD_, RN0);
552 reg1 = State.regs[srcreg];
553 reg2 = State.regs[dstreg];
554 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
555 State.regs[dstreg] = difference;
557 z = ((PSW & PSW_Z) != 0) && (difference == 0);
558 n = (difference & 0x80000000);
560 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
561 && (reg2 & 0x80000000) != (difference & 0x80000000));
563 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
564 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
565 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
568 // 1111 1001 1011 1000 Rn Rn; inc Rn
569 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
576 dstreg = translate_rreg (SD_, RN0);
577 genericAdd (1, dstreg);
580 // 1111 1001 1101 1000 Rn Rn; inc Rn
581 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
588 dstreg = translate_rreg (SD_, RN0);
589 genericAdd (4, dstreg);
592 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
593 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
597 int srcreg1, srcreg2;
600 srcreg1 = translate_rreg (SD_, RN0);
601 srcreg2 = translate_rreg (SD_, RM2);
602 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
605 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
606 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
613 dstreg = translate_rreg (SD_, RN0);
614 srcreg = translate_xreg (SD_, XRM2);
616 State.regs[dstreg] = State.regs[srcreg];
619 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
620 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
627 srcreg = translate_rreg (SD_, RM2);
628 dstreg = translate_xreg (SD_, XRN0);
630 State.regs[dstreg] = State.regs[srcreg];
633 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
634 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
643 srcreg = translate_rreg (SD_, RM2);
644 dstreg = translate_rreg (SD_, RN0);
646 State.regs[dstreg] &= State.regs[srcreg];
647 z = (State.regs[dstreg] == 0);
648 n = (State.regs[dstreg] & 0x80000000) != 0;
649 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
650 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
653 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
654 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
662 srcreg = translate_rreg (SD_, RM2);
663 dstreg = translate_rreg (SD_, RN0);
665 State.regs[dstreg] |= State.regs[srcreg];
666 z = (State.regs[dstreg] == 0);
667 n = (State.regs[dstreg] & 0x80000000) != 0;
668 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
669 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
672 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
673 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
681 srcreg = translate_rreg (SD_, RM2);
682 dstreg = translate_rreg (SD_, RN0);
684 State.regs[dstreg] ^= State.regs[srcreg];
685 z = (State.regs[dstreg] == 0);
686 n = (State.regs[dstreg] & 0x80000000) != 0;
687 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
688 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
691 // 1111 1001 0011 1001 Rn Rn; not Rn
692 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
700 dstreg = translate_rreg (SD_, RN0);
702 State.regs[dstreg] = ~State.regs[dstreg];
703 z = (State.regs[dstreg] == 0);
704 n = (State.regs[dstreg] & 0x80000000) != 0;
705 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
706 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
709 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
710 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
719 srcreg = translate_rreg (SD_, RM2);
720 dstreg = translate_rreg (SD_, RN0);
722 temp = State.regs[dstreg];
724 temp >>= State.regs[srcreg];
725 State.regs[dstreg] = temp;
726 z = (State.regs[dstreg] == 0);
727 n = (State.regs[dstreg] & 0x80000000) != 0;
728 PSW &= ~(PSW_Z | PSW_N | PSW_C);
729 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
732 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
733 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
742 srcreg = translate_rreg (SD_, RM2);
743 dstreg = translate_rreg (SD_, RN0);
745 c = State.regs[dstreg] & 1;
746 State.regs[dstreg] >>= State.regs[srcreg];
747 z = (State.regs[dstreg] == 0);
748 n = (State.regs[dstreg] & 0x80000000) != 0;
749 PSW &= ~(PSW_Z | PSW_N | PSW_C);
750 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
753 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
754 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
762 srcreg = translate_rreg (SD_, RM2);
763 dstreg = translate_rreg (SD_, RN0);
765 State.regs[dstreg] <<= State.regs[srcreg];
766 z = (State.regs[dstreg] == 0);
767 n = (State.regs[dstreg] & 0x80000000) != 0;
768 PSW &= ~(PSW_Z | PSW_N);
769 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
772 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
773 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
781 dstreg = translate_rreg (SD_, RN0);
783 State.regs[dstreg] <<= 2;
784 z = (State.regs[dstreg] == 0);
785 n = (State.regs[dstreg] & 0x80000000) != 0;
786 PSW &= ~(PSW_Z | PSW_N);
787 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
790 // 1111 1001 1000 1001 Rn Rn; ror Rn
791 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
800 dstreg = translate_rreg (SD_, RN0);
802 value = State.regs[dstreg];
806 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
807 State.regs[dstreg] = value;
809 n = (value & 0x80000000) != 0;
810 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
811 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
814 // 1111 1001 1001 1001 Rn Rn; rol Rn
815 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
824 dstreg = translate_rreg (SD_, RN0);
826 value = State.regs[dstreg];
827 c = (value & 0x80000000) ? 1 : 0;
830 value |= ((PSW & PSW_C) != 0);
831 State.regs[dstreg] = value;
833 n = (value & 0x80000000) != 0;
834 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
835 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
838 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
839 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
848 srcreg = translate_rreg (SD_, RM2);
849 dstreg = translate_rreg (SD_, RN0);
851 temp = ((signed64)(signed32)State.regs[dstreg]
852 * (signed64)(signed32)State.regs[srcreg]);
853 State.regs[dstreg] = temp & 0xffffffff;
854 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
855 z = (State.regs[dstreg] == 0);
856 n = (State.regs[dstreg] & 0x80000000) != 0;
857 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
858 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
861 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
862 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
871 srcreg = translate_rreg (SD_, RM2);
872 dstreg = translate_rreg (SD_, RN0);
874 temp = ((unsigned64)State.regs[dstreg]
875 * (unsigned64)State.regs[srcreg]);
876 State.regs[dstreg] = temp & 0xffffffff;
877 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
878 z = (State.regs[dstreg] == 0);
879 n = (State.regs[dstreg] & 0x80000000) != 0;
880 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
881 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
884 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
885 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
894 srcreg = translate_rreg (SD_, RM2);
895 dstreg = translate_rreg (SD_, RN0);
897 temp = State.regs[REG_MDR];
899 temp |= State.regs[dstreg];
900 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
901 temp /= (signed32)State.regs[srcreg];
902 State.regs[dstreg] = temp & 0xffffffff;
903 z = (State.regs[dstreg] == 0);
904 n = (State.regs[dstreg] & 0x80000000) != 0;
905 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
906 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
909 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
910 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
919 srcreg = translate_rreg (SD_, RM2);
920 dstreg = translate_rreg (SD_, RN0);
922 temp = State.regs[REG_MDR];
924 temp |= State.regs[dstreg];
925 State.regs[REG_MDR] = temp % State.regs[srcreg];
926 temp /= State.regs[srcreg];
927 State.regs[dstreg] = temp & 0xffffffff;
928 z = (State.regs[dstreg] == 0);
929 n = (State.regs[dstreg] & 0x80000000) != 0;
930 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
931 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
935 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
936 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
943 srcreg = translate_rreg (SD_, RM0);
944 dstreg = translate_rreg (SD_, RN2);
945 State.regs[dstreg] = load_word (State.regs[srcreg]);
948 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
949 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
956 srcreg = translate_rreg (SD_, RM2);
957 dstreg = translate_rreg (SD_, RN0);
958 store_word (State.regs[dstreg], State.regs[srcreg]);
961 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
962 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
969 srcreg = translate_rreg (SD_, RM0);
970 dstreg = translate_rreg (SD_, RN2);
971 State.regs[dstreg] = load_byte (State.regs[srcreg]);
974 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
975 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
982 srcreg = translate_rreg (SD_, RM2);
983 dstreg = translate_rreg (SD_, RN0);
984 store_byte (State.regs[dstreg], State.regs[srcreg]);
987 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
988 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
995 srcreg = translate_rreg (SD_, RM0);
996 dstreg = translate_rreg (SD_, RN2);
997 State.regs[dstreg] = load_half (State.regs[srcreg]);
1000 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
1001 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1008 srcreg = translate_rreg (SD_, RM2);
1009 dstreg = translate_rreg (SD_, RN0);
1010 store_half (State.regs[dstreg], State.regs[srcreg]);
1013 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1014 8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
1021 srcreg = translate_rreg (SD_, RM0);
1022 dstreg = translate_rreg (SD_, RN2);
1023 State.regs[dstreg] = load_word (State.regs[srcreg]);
1024 State.regs[srcreg] += 4;
1027 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1028 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1035 srcreg = translate_rreg (SD_, RM2);
1036 dstreg = translate_rreg (SD_, RN0);
1037 store_word (State.regs[dstreg], State.regs[srcreg]);
1038 State.regs[dstreg] += 4;
1041 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1042 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1049 dstreg = translate_rreg (SD_, RN2);
1050 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1053 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1054 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1061 srcreg = translate_rreg (SD_, RM2);
1062 store_word (State.regs[REG_SP], State.regs[srcreg]);
1065 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1066 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1073 dstreg = translate_rreg (SD_, RN2);
1074 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1077 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1078 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1085 srcreg = translate_rreg (SD_, RM2);
1086 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1089 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1090 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1097 dstreg = translate_rreg (SD_, RN2);
1098 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1101 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1102 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1109 srcreg = translate_rreg (SD_, RM2);
1110 store_half (State.regs[REG_SP], State.regs[srcreg]);
1113 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1114 8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
1121 srcreg = translate_rreg (SD_, RM0);
1122 dstreg = translate_rreg (SD_, RN2);
1123 State.regs[dstreg] = load_half (State.regs[srcreg]);
1124 State.regs[srcreg] += 2;
1127 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1128 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1135 srcreg = translate_rreg (SD_, RM2);
1136 dstreg = translate_rreg (SD_, RN0);
1137 store_half (State.regs[dstreg], State.regs[srcreg]);
1138 State.regs[dstreg] += 2;
1142 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1143 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1147 int srcreg1, srcreg2;
1152 srcreg1 = translate_rreg (SD_, RM2);
1153 srcreg2 = translate_rreg (SD_, RN0);
1155 temp = ((signed64)(signed32)State.regs[srcreg2]
1156 * (signed64)(signed32)State.regs[srcreg1]);
1157 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1158 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1159 State.regs[REG_MCRL] = sum;
1162 sum = State.regs[REG_MCRH] + temp + c;
1163 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1164 && (temp & 0x80000000) != (sum & 0x80000000));
1165 State.regs[REG_MCRH] = sum;
1167 State.regs[REG_MCVF] = 1;
1170 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1171 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1175 int srcreg1, srcreg2;
1176 unsigned64 temp, sum;
1180 srcreg1 = translate_rreg (SD_, RM2);
1181 srcreg2 = translate_rreg (SD_, RN0);
1183 temp = ((unsigned64)State.regs[srcreg2]
1184 * (unsigned64)State.regs[srcreg1]);
1185 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1186 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1187 State.regs[REG_MCRL] = sum;
1190 sum = State.regs[REG_MCRH] + temp + c;
1191 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1192 && (temp & 0x80000000) != (sum & 0x80000000));
1193 State.regs[REG_MCRH] = sum;
1195 State.regs[REG_MCVF] = 1;
1198 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1199 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1203 int srcreg1, srcreg2;
1208 srcreg1 = translate_rreg (SD_, RM2);
1209 srcreg2 = translate_rreg (SD_, RN0);
1211 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1212 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
1213 sum = State.regs[REG_MCRL] + temp;
1214 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1215 && (temp & 0x80000000) != (sum & 0x80000000));
1216 State.regs[REG_MCRL] = sum;
1218 State.regs[REG_MCVF] = 1;
1221 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1222 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1226 int srcreg1, srcreg2;
1231 srcreg1 = translate_rreg (SD_, RM2);
1232 srcreg2 = translate_rreg (SD_, RN0);
1234 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1235 * (unsigned32)(State.regs[srcreg1] & 0xff));
1236 sum = State.regs[REG_MCRL] + temp;
1237 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1238 && (temp & 0x80000000) != (sum & 0x80000000));
1239 State.regs[REG_MCRL] = sum;
1241 State.regs[REG_MCVF] = 1;
1244 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1245 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1249 int srcreg1, srcreg2;
1254 srcreg1 = translate_rreg (SD_, RM2);
1255 srcreg2 = translate_rreg (SD_, RN0);
1257 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1258 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
1259 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1260 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1261 State.regs[REG_MCRL] = sum;
1264 sum = State.regs[REG_MCRH] + temp + c;
1265 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1266 && (temp & 0x80000000) != (sum & 0x80000000));
1267 State.regs[REG_MCRH] = sum;
1269 State.regs[REG_MCVF] = 1;
1272 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1273 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1277 int srcreg1, srcreg2;
1282 srcreg1 = translate_rreg (SD_, RM2);
1283 srcreg2 = translate_rreg (SD_, RN0);
1285 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1286 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1287 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1288 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1289 State.regs[REG_MCRL] = sum;
1292 sum = State.regs[REG_MCRH] + temp + c;
1293 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1294 && (temp & 0x80000000) != (sum & 0x80000000));
1295 State.regs[REG_MCRH] = sum;
1297 State.regs[REG_MCVF] = 1;
1300 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1301 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1305 int srcreg1, srcreg2;
1306 signed32 temp, temp2, sum;
1310 srcreg1 = translate_rreg (SD_, RM2);
1311 srcreg2 = translate_rreg (SD_, RN0);
1313 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1314 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1315 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1316 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
1317 sum = temp + temp2 + State.regs[REG_MCRL];
1318 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1319 && (temp & 0x80000000) != (sum & 0x80000000));
1320 State.regs[REG_MCRL] = sum;
1322 State.regs[REG_MCVF] = 1;
1325 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1326 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1330 int srcreg1, srcreg2;
1331 unsigned32 temp, temp2, sum;
1335 srcreg1 = translate_rreg (SD_, RM2);
1336 srcreg2 = translate_rreg (SD_, RN0);
1338 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1339 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1340 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1341 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1342 sum = temp + temp2 + State.regs[REG_MCRL];
1343 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1344 && (temp & 0x80000000) != (sum & 0x80000000));
1345 State.regs[REG_MCRL] = sum;
1347 State.regs[REG_MCVF] = 1;
1350 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1351 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1359 srcreg = translate_rreg (SD_, RM2);
1360 dstreg = translate_rreg (SD_, RN0);
1362 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1363 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
1364 State.regs[REG_MDRQ] = temp;
1365 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1366 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
1367 State.regs[dstreg] = temp;
1370 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1371 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1379 srcreg = translate_rreg (SD_, RM2);
1380 dstreg = translate_rreg (SD_, RN0);
1382 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1383 * (unsigned32)(State.regs[srcreg] & 0xffff));
1384 State.regs[REG_MDRQ] = temp;
1385 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1386 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1387 State.regs[dstreg] = temp;
1390 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1391 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1399 srcreg = translate_rreg (SD_, RM2);
1400 dstreg = translate_rreg (SD_, RN0);
1402 value = State.regs[srcreg];
1404 if (value >= 0x7fff)
1405 State.regs[dstreg] = 0x7fff;
1406 else if (value <= 0xffff8000)
1407 State.regs[dstreg] = 0xffff8000;
1409 State.regs[dstreg] = value;
1411 n = (State.regs[dstreg] & 0x8000) != 0;
1412 z = (State.regs[dstreg] == 0);
1413 PSW &= ~(PSW_Z | PSW_N);
1414 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1417 // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
1418 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1425 srcreg = translate_rreg (SD_, RM2);
1426 dstreg = translate_rreg (SD_, RN0);
1428 PSW &= ~(PSW_V | PSW_C);
1429 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1431 /* 32bit saturation. */
1432 if (State.regs[srcreg] == 0x20)
1436 tmp = State.regs[REG_MCRH];
1438 tmp += State.regs[REG_MCRL];
1440 if (tmp > 0x7fffffff)
1441 State.regs[dstreg] = 0x7fffffff;
1442 else if (tmp < 0xffffffff80000000LL)
1443 State.regs[dstreg] = 0x80000000;
1445 State.regs[dstreg] = tmp;
1447 /* 16bit saturation */
1448 else if (State.regs[srcreg] == 0x10)
1452 tmp = State.regs[REG_MCRH];
1454 tmp += State.regs[REG_MCRL];
1457 State.regs[dstreg] = 0x7fff;
1458 else if (tmp < 0xffffffffffff8000LL)
1459 State.regs[dstreg] = 0x8000;
1461 State.regs[dstreg] = tmp;
1463 /* 8 bit saturation */
1464 else if (State.regs[srcreg] == 0x8)
1468 tmp = State.regs[REG_MCRH];
1470 tmp += State.regs[REG_MCRL];
1473 State.regs[dstreg] = 0x7f;
1474 else if (tmp < 0xffffffffffffff80LL)
1475 State.regs[dstreg] = 0x80;
1477 State.regs[dstreg] = tmp;
1479 /* 9 bit saturation */
1480 else if (State.regs[srcreg] == 0x9)
1484 tmp = State.regs[REG_MCRH];
1486 tmp += State.regs[REG_MCRL];
1489 State.regs[dstreg] = 0x80;
1490 else if (tmp < 0xffffffffffffff81LL)
1491 State.regs[dstreg] = 0x81;
1493 State.regs[dstreg] = tmp;
1495 /* 9 bit saturation */
1496 else if (State.regs[srcreg] == 0x30)
1500 tmp = State.regs[REG_MCRH];
1502 tmp += State.regs[REG_MCRL];
1504 if (tmp > 0x7fffffffffffLL)
1505 tmp = 0x7fffffffffffLL;
1506 else if (tmp < 0xffff800000000000LL)
1507 tmp = 0xffff800000000000LL;
1510 State.regs[dstreg] = tmp;
1514 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1515 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1522 srcreg = translate_rreg (SD_, RM2);
1523 dstreg = translate_rreg (SD_, RN0);
1525 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1526 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1527 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1528 | ((State.regs[srcreg] >> 24) & 0xff));
1531 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1532 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1539 srcreg = translate_rreg (SD_, RM2);
1540 dstreg = translate_rreg (SD_, RN0);
1542 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1543 | ((State.regs[srcreg] >> 8) & 0xff)
1544 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1545 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1548 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1549 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1556 srcreg = translate_rreg (SD_, RM2);
1557 dstreg = translate_rreg (SD_, RN0);
1559 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1560 | ((State.regs[srcreg] >> 16) & 0xffff));
1563 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1564 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1573 srcreg = translate_rreg (SD_, RM2);
1574 dstreg = translate_rreg (SD_, RN0);
1576 temp = State.regs[srcreg];
1577 start = (State.regs[dstreg] & 0x1f) - 1;
1581 for (i = start; i >= 0; i--)
1583 if (temp & (1 << i))
1586 State.regs[dstreg] = i;
1594 State.regs[dstreg] = 0;
1597 PSW |= (c ? PSW_C : 0);
1601 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1602 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1609 dstreg = translate_rreg (SD_, RN0);
1610 State.regs[dstreg] = EXTEND8 (IMM8);
1613 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1614 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1621 dstreg = translate_rreg (SD_, RN0);
1622 State.regs[dstreg] = IMM8 & 0xff;
1625 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1626 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1633 dstreg = translate_rreg (SD_, RN0);
1634 genericAdd (EXTEND8 (IMM8), dstreg);
1637 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1638 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1644 unsigned32 reg1, reg2, sum;
1647 dstreg = translate_rreg (SD_, RN0);
1649 imm = EXTEND8 (IMM8);
1650 reg2 = State.regs[dstreg];
1651 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1652 State.regs[dstreg] = sum;
1654 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1655 n = (sum & 0x80000000);
1656 c = (sum < imm) || (sum < reg2);
1657 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1658 && (reg2 & 0x80000000) != (sum & 0x80000000));
1660 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1661 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1662 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1665 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1666 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1673 dstreg = translate_rreg (SD_, RN0);
1675 genericSub (EXTEND8 (IMM8), dstreg);
1678 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1679 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1685 unsigned32 reg1, reg2, difference;
1688 dstreg = translate_rreg (SD_, RN0);
1690 imm = EXTEND8 (IMM8);
1691 reg2 = State.regs[dstreg];
1692 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1693 State.regs[dstreg] = difference;
1695 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1696 n = (difference & 0x80000000);
1698 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1699 && (reg2 & 0x80000000) != (difference & 0x80000000));
1701 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1702 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1703 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1706 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1707 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1714 srcreg = translate_rreg (SD_, RN0);
1715 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1718 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1719 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1726 dstreg = translate_xreg (SD_, XRN0);
1728 State.regs[dstreg] = IMM8;
1731 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1732 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1740 dstreg = translate_rreg (SD_, RN0);
1742 State.regs[dstreg] &= (IMM8 & 0xff);
1743 z = (State.regs[dstreg] == 0);
1744 n = (State.regs[dstreg] & 0x80000000) != 0;
1745 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1746 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1749 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1750 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1758 dstreg = translate_rreg (SD_, RN0);
1760 State.regs[dstreg] |= (IMM8 & 0xff);
1761 z = (State.regs[dstreg] == 0);
1762 n = (State.regs[dstreg] & 0x80000000) != 0;
1763 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1764 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1767 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1768 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1776 dstreg = translate_rreg (SD_, RN0);
1778 State.regs[dstreg] ^= (IMM8 & 0xff);
1779 z = (State.regs[dstreg] == 0);
1780 n = (State.regs[dstreg] & 0x80000000) != 0;
1781 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1782 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1785 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1786 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1795 dstreg = translate_rreg (SD_, RN0);
1797 temp = State.regs[dstreg];
1799 temp >>= (IMM8 & 0xff);
1800 State.regs[dstreg] = temp;
1801 z = (State.regs[dstreg] == 0);
1802 n = (State.regs[dstreg] & 0x80000000) != 0;
1803 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1804 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1807 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1808 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1816 dstreg = translate_rreg (SD_, RN0);
1818 c = State.regs[dstreg] & 1;
1819 State.regs[dstreg] >>= (IMM8 & 0xff);
1820 z = (State.regs[dstreg] == 0);
1821 n = (State.regs[dstreg] & 0x80000000) != 0;
1822 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1823 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1826 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1827 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1835 dstreg = translate_rreg (SD_, RN0);
1837 State.regs[dstreg] <<= (IMM8 & 0xff);
1838 z = (State.regs[dstreg] == 0);
1839 n = (State.regs[dstreg] & 0x80000000) != 0;
1840 PSW &= ~(PSW_Z | PSW_N);
1841 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1844 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1845 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1854 dstreg = translate_rreg (SD_, RN0);
1856 temp = ((signed64)(signed32)State.regs[dstreg]
1857 * (signed64)(signed32)EXTEND8 (IMM8));
1858 State.regs[dstreg] = temp & 0xffffffff;
1859 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1860 z = (State.regs[dstreg] == 0);
1861 n = (State.regs[dstreg] & 0x80000000) != 0;
1862 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1863 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1866 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1867 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1876 dstreg = translate_rreg (SD_, RN0);
1878 temp = ((unsigned64)State.regs[dstreg]
1879 * (unsigned64)(IMM8 & 0xff));
1880 State.regs[dstreg] = temp & 0xffffffff;
1881 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1882 z = (State.regs[dstreg] == 0);
1883 n = (State.regs[dstreg] & 0x80000000) != 0;
1884 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1885 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1888 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1889 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1896 srcreg = translate_rreg (SD_, RM0);
1897 genericBtst(IMM8, State.regs[srcreg]);
1900 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1901 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1908 srcreg = translate_rreg (SD_, RM0);
1909 dstreg = translate_rreg (SD_, RN2);
1910 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1913 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1914 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1921 srcreg = translate_rreg (SD_, RM2);
1922 dstreg = translate_rreg (SD_, RN0);
1923 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1926 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1927 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1934 srcreg = translate_rreg (SD_, RM0);
1935 dstreg = translate_rreg (SD_, RN2);
1936 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1939 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1940 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1947 srcreg = translate_rreg (SD_, RM2);
1948 dstreg = translate_rreg (SD_, RN0);
1949 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1952 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1953 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1960 srcreg = translate_rreg (SD_, RM0);
1961 dstreg = translate_rreg (SD_, RN2);
1962 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1965 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1966 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1973 srcreg = translate_rreg (SD_, RM2);
1974 dstreg = translate_rreg (SD_, RN0);
1975 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1978 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1979 8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
1986 srcreg = translate_rreg (SD_, RM0);
1987 dstreg = translate_rreg (SD_, RN2);
1988 State.regs[dstreg] = load_word (State.regs[srcreg]);
1989 State.regs[srcreg] += EXTEND8 (IMM8);
1992 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1993 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
2000 srcreg = translate_rreg (SD_, RM2);
2001 dstreg = translate_rreg (SD_, RN0);
2002 store_word (State.regs[dstreg], State.regs[srcreg]);
2003 State.regs[dstreg] += EXTEND8 (IMM8);
2007 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
2008 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2015 dstreg = translate_rreg (SD_, RN2);
2016 State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8);
2019 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,sp)
2020 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2027 srcreg = translate_rreg (SD_, RM2);
2028 store_word (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
2031 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2032 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2039 dstreg = translate_rreg (SD_, RN2);
2040 State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8);
2043 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(d8,sp)
2044 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2051 srcreg = translate_rreg (SD_, RM2);
2052 store_byte (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
2055 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2056 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2063 dstreg = translate_rreg (SD_, RN2);
2064 State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8);
2067 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2068 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2075 srcreg = translate_rreg (SD_, RM2);
2076 store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
2079 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2080 8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
2087 srcreg = translate_rreg (SD_, RM0);
2088 dstreg = translate_rreg (SD_, RN2);
2089 State.regs[dstreg] = load_half (State.regs[srcreg]);
2090 State.regs[srcreg] += EXTEND8 (IMM8);
2093 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2094 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2101 srcreg = translate_rreg (SD_, RM2);
2102 dstreg = translate_rreg (SD_, RN0);
2103 store_half (State.regs[dstreg], State.regs[srcreg]);
2104 State.regs[dstreg] += EXTEND8 (IMM8);
2108 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2109 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2118 srcreg = translate_rreg (SD_, RN2);
2120 temp = ((signed64)(signed32)EXTEND8 (IMM8)
2121 * (signed64)(signed32)State.regs[srcreg]);
2122 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2123 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2124 State.regs[REG_MCRL] = sum;
2127 sum = State.regs[REG_MCRH] + temp + c;
2128 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2129 && (temp & 0x80000000) != (sum & 0x80000000));
2130 State.regs[REG_MCRH] = sum;
2132 State.regs[REG_MCVF] = 1;
2135 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2136 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2145 srcreg = translate_rreg (SD_, RN2);
2147 temp = ((unsigned64) (IMM8)
2148 * (unsigned64)State.regs[srcreg]);
2149 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2150 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2151 State.regs[REG_MCRL] = sum;
2154 sum = State.regs[REG_MCRH] + temp + c;
2155 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2156 && (temp & 0x80000000) != (sum & 0x80000000));
2157 State.regs[REG_MCRH] = sum;
2159 State.regs[REG_MCVF] = 1;
2162 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2163 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2172 srcreg = translate_rreg (SD_, RN2);
2174 temp = ((signed64)(signed8)EXTEND8 (IMM8)
2175 * (signed64)(signed8)State.regs[srcreg] & 0xff);
2176 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2177 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2178 State.regs[REG_MCRL] = sum;
2181 sum = State.regs[REG_MCRH] + temp + c;
2182 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2183 && (temp & 0x80000000) != (sum & 0x80000000));
2184 State.regs[REG_MCRH] = sum;
2186 State.regs[REG_MCVF] = 1;
2189 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2190 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2199 srcreg = translate_rreg (SD_, RN2);
2201 temp = ((unsigned64) (IMM8)
2202 * (unsigned64)State.regs[srcreg] & 0xff);
2203 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2204 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2205 State.regs[REG_MCRL] = sum;
2208 sum = State.regs[REG_MCRH] + temp + c;
2209 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2210 && (temp & 0x80000000) != (sum & 0x80000000));
2211 State.regs[REG_MCRH] = sum;
2213 State.regs[REG_MCVF] = 1;
2216 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2217 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2226 srcreg = translate_rreg (SD_, RN2);
2228 temp = ((signed64)(signed16)EXTEND8 (IMM8)
2229 * (signed64)(signed16)State.regs[srcreg] & 0xffff);
2230 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2231 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2232 State.regs[REG_MCRL] = sum;
2235 sum = State.regs[REG_MCRH] + temp + c;
2236 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2237 && (temp & 0x80000000) != (sum & 0x80000000));
2238 State.regs[REG_MCRH] = sum;
2240 State.regs[REG_MCVF] = 1;
2243 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2244 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2253 srcreg = translate_rreg (SD_, RN2);
2255 temp = ((unsigned64) (IMM8)
2256 * (unsigned64)State.regs[srcreg] & 0xffff);
2257 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2258 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2259 State.regs[REG_MCRL] = sum;
2262 sum = State.regs[REG_MCRH] + temp + c;
2263 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2264 && (temp & 0x80000000) != (sum & 0x80000000));
2265 State.regs[REG_MCRH] = sum;
2267 State.regs[REG_MCVF] = 1;
2270 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
2271 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2278 dstreg = translate_rreg (SD_, RN0);
2280 PSW &= ~(PSW_V | PSW_C);
2281 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2283 /* 32bit saturation. */
2288 tmp = State.regs[REG_MCRH];
2290 tmp += State.regs[REG_MCRL];
2292 if (tmp > 0x7fffffff)
2293 State.regs[dstreg] = 0x7fffffff;
2294 else if (tmp < 0xffffffff80000000LL)
2295 State.regs[dstreg] = 0x80000000;
2297 State.regs[dstreg] = tmp;
2299 /* 16bit saturation */
2300 else if (IMM8 == 0x10)
2304 tmp = State.regs[REG_MCRH];
2306 tmp += State.regs[REG_MCRL];
2309 State.regs[dstreg] = 0x7fff;
2310 else if (tmp < 0xffffffffffff8000LL)
2311 State.regs[dstreg] = 0x8000;
2313 State.regs[dstreg] = tmp;
2315 /* 8 bit saturation */
2316 else if (IMM8 == 0x8)
2320 tmp = State.regs[REG_MCRH];
2322 tmp += State.regs[REG_MCRL];
2325 State.regs[dstreg] = 0x7f;
2326 else if (tmp < 0xffffffffffffff80LL)
2327 State.regs[dstreg] = 0x80;
2329 State.regs[dstreg] = tmp;
2331 /* 9 bit saturation */
2332 else if (IMM8 == 0x9)
2336 tmp = State.regs[REG_MCRH];
2338 tmp += State.regs[REG_MCRL];
2341 State.regs[dstreg] = 0x80;
2342 else if (tmp < 0xffffffffffffff81LL)
2343 State.regs[dstreg] = 0x81;
2345 State.regs[dstreg] = tmp;
2347 /* 9 bit saturation */
2348 else if (IMM8 == 0x30)
2352 tmp = State.regs[REG_MCRH];
2354 tmp += State.regs[REG_MCRL];
2356 if (tmp > 0x7fffffffffffLL)
2357 tmp = 0x7fffffffffffLL;
2358 else if (tmp < 0xffff800000000000LL)
2359 tmp = 0xffff800000000000LL;
2362 State.regs[dstreg] = tmp;
2366 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2367 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2372 unsigned32 sum, source1, source2;
2373 int srcreg1, srcreg2, dstreg;
2376 srcreg1 = translate_rreg (SD_, RM2);
2377 srcreg2 = translate_rreg (SD_, RN0);
2378 dstreg = translate_rreg (SD_, RD0);
2380 source1 = State.regs[srcreg1];
2381 source2 = State.regs[srcreg2];
2382 sum = source1 + source2;
2383 State.regs[dstreg] = sum;
2386 n = (sum & 0x80000000);
2387 c = (sum < source1) || (sum < source2);
2388 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2389 && (source1 & 0x80000000) != (sum & 0x80000000));
2391 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2392 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2393 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2396 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2397 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2402 unsigned32 sum, source1, source2;
2403 int srcreg1, srcreg2, dstreg;
2406 srcreg1 = translate_rreg (SD_, RM2);
2407 srcreg2 = translate_rreg (SD_, RN0);
2408 dstreg = translate_rreg (SD_, RD0);
2410 source1 = State.regs[srcreg1];
2411 source2 = State.regs[srcreg2];
2412 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2413 State.regs[dstreg] = sum;
2415 z = ((PSW & PSW_Z) != 0) && (sum == 0);
2416 n = (sum & 0x80000000);
2417 c = (sum < source1) || (sum < source2);
2418 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2419 && (source1 & 0x80000000) != (sum & 0x80000000));
2421 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2422 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2423 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2426 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2427 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2432 unsigned32 difference, source1, source2;
2433 int srcreg1, srcreg2, dstreg;
2436 srcreg1 = translate_rreg (SD_, RM2);
2437 srcreg2 = translate_rreg (SD_, RN0);
2438 dstreg = translate_rreg (SD_, RD0);
2440 source1 = State.regs[srcreg1];
2441 source2 = State.regs[srcreg2];
2442 difference = source2 - source1;
2443 State.regs[dstreg] = difference;
2445 z = (difference == 0);
2446 n = (difference & 0x80000000);
2447 c = (source1 > source1);
2448 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2449 && (source1 & 0x80000000) != (difference & 0x80000000));
2451 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2452 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2453 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2456 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2457 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2462 unsigned32 difference, source1, source2;
2463 int srcreg1, srcreg2, dstreg;
2466 srcreg1 = translate_rreg (SD_, RM2);
2467 srcreg2 = translate_rreg (SD_, RN0);
2468 dstreg = translate_rreg (SD_, RD0);
2470 source1 = State.regs[srcreg1];
2471 source2 = State.regs[srcreg2];
2472 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2473 State.regs[dstreg] = difference;
2475 z = ((PSW & PSW_Z) != 0) && (difference == 0);
2476 n = (difference & 0x80000000);
2477 c = (source1 > source2);
2478 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2479 && (source1 & 0x80000000) != (difference & 0x80000000));
2481 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2482 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2483 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2486 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2487 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2492 int srcreg1, srcreg2, dstreg;
2495 srcreg1 = translate_rreg (SD_, RM2);
2496 srcreg2 = translate_rreg (SD_, RN0);
2497 dstreg = translate_rreg (SD_, RD0);
2499 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2501 z = (State.regs[dstreg] == 0);
2502 n = (State.regs[dstreg] & 0x80000000);
2504 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2505 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2508 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2509 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2514 int srcreg1, srcreg2, dstreg;
2517 srcreg1 = translate_rreg (SD_, RM2);
2518 srcreg2 = translate_rreg (SD_, RN0);
2519 dstreg = translate_rreg (SD_, RD0);
2521 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2523 z = (State.regs[dstreg] == 0);
2524 n = (State.regs[dstreg] & 0x80000000);
2526 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2527 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2530 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2531 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2536 int srcreg1, srcreg2, dstreg;
2539 srcreg1 = translate_rreg (SD_, RM2);
2540 srcreg2 = translate_rreg (SD_, RN0);
2541 dstreg = translate_rreg (SD_, RD0);
2543 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2545 z = (State.regs[dstreg] == 0);
2546 n = (State.regs[dstreg] & 0x80000000);
2548 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2549 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2552 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2553 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2559 int srcreg1, srcreg2, dstreg;
2562 srcreg1 = translate_rreg (SD_, RM2);
2563 srcreg2 = translate_rreg (SD_, RN0);
2564 dstreg = translate_rreg (SD_, RD0);
2566 temp = State.regs[srcreg2];
2568 temp >>= State.regs[srcreg1];
2569 State.regs[dstreg] = temp;
2571 z = (State.regs[dstreg] == 0);
2572 n = (State.regs[dstreg] & 0x80000000);
2574 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2575 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2578 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2579 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2584 int srcreg1, srcreg2, dstreg;
2587 srcreg1 = translate_rreg (SD_, RM2);
2588 srcreg2 = translate_rreg (SD_, RN0);
2589 dstreg = translate_rreg (SD_, RD0);
2591 c = State.regs[srcreg2] & 1;
2592 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2594 z = (State.regs[dstreg] == 0);
2595 n = (State.regs[dstreg] & 0x80000000);
2597 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2598 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2601 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2602 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2607 int srcreg1, srcreg2, dstreg;
2610 srcreg1 = translate_rreg (SD_, RM2);
2611 srcreg2 = translate_rreg (SD_, RN0);
2612 dstreg = translate_rreg (SD_, RD0);
2614 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
2616 z = (State.regs[dstreg] == 0);
2617 n = (State.regs[dstreg] & 0x80000000);
2619 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2620 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2623 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2624 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
2628 int srcreg1, srcreg2, dstreg1, dstreg2;
2633 srcreg1 = translate_rreg (SD_, RM2);
2634 srcreg2 = translate_rreg (SD_, RN0);
2635 dstreg1 = translate_rreg (SD_, RD0);
2636 dstreg2 = translate_rreg (SD_, RD2);
2638 temp = ((signed64)(signed32)State.regs[srcreg1]
2639 * (signed64)(signed32)State.regs[srcreg2]);
2640 State.regs[dstreg2] = temp & 0xffffffff;
2641 State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
2643 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2644 n = (State.regs[dstreg1] & 0x80000000);
2646 PSW &= ~(PSW_Z | PSW_N);
2647 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2650 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2651 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
2655 int srcreg1, srcreg2, dstreg1, dstreg2;
2660 srcreg1 = translate_rreg (SD_, RM2);
2661 srcreg2 = translate_rreg (SD_, RN0);
2662 dstreg1 = translate_rreg (SD_, RD0);
2663 dstreg2 = translate_rreg (SD_, RD2);
2665 temp = ((unsigned64)State.regs[srcreg1]
2666 * (unsigned64)State.regs[srcreg2]);
2667 State.regs[dstreg2] = temp & 0xffffffff;
2668 State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
2670 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2671 n = (State.regs[dstreg1] & 0x80000000);
2673 PSW &= ~(PSW_Z | PSW_N);
2674 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2677 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2678 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2685 dstreg = translate_rreg (SD_, RN2);
2686 State.regs[dstreg] = load_word (IMM8);
2689 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2690 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2697 srcreg = translate_rreg (SD_, RM2);
2698 store_word (IMM8, State.regs[srcreg]);
2701 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2702 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2709 dstreg = translate_rreg (SD_, RN2);
2710 State.regs[dstreg] = load_byte (IMM8);
2713 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2714 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2721 srcreg = translate_rreg (SD_, RM2);
2722 store_byte (IMM8, State.regs[srcreg]);
2725 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2726 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2733 dstreg = translate_rreg (SD_, RN2);
2734 State.regs[dstreg] = load_half (IMM8);
2737 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2738 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2745 srcreg = translate_rreg (SD_, RM2);
2746 store_half (IMM8, State.regs[srcreg]);
2749 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2750 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2754 int srcreg1, srcreg2, dstreg;
2757 srcreg1 = translate_rreg (SD_, RM0);
2758 srcreg1 = translate_rreg (SD_, RI0);
2759 dstreg = translate_rreg (SD_, RN0);
2760 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2763 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2764 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2768 int srcreg, dstreg1, dstreg2;
2771 srcreg = translate_rreg (SD_, RM0);
2772 dstreg1 = translate_rreg (SD_, RI0);
2773 dstreg2 = translate_rreg (SD_, RN0);
2774 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2777 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2778 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2782 int srcreg1, srcreg2, dstreg;
2785 srcreg1 = translate_rreg (SD_, RM0);
2786 srcreg1 = translate_rreg (SD_, RI0);
2787 dstreg = translate_rreg (SD_, RN0);
2788 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2791 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2792 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2796 int srcreg, dstreg1, dstreg2;
2799 srcreg = translate_rreg (SD_, RM0);
2800 dstreg1 = translate_rreg (SD_, RI0);
2801 dstreg2 = translate_rreg (SD_, RN0);
2802 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2805 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2806 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2810 int srcreg1, srcreg2, dstreg;
2813 srcreg1 = translate_rreg (SD_, RM0);
2814 srcreg1 = translate_rreg (SD_, RI0);
2815 dstreg = translate_rreg (SD_, RN0);
2816 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2819 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2820 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2824 int srcreg, dstreg1, dstreg2;
2827 srcreg = translate_rreg (SD_, RM0);
2828 dstreg1 = translate_rreg (SD_, RI0);
2829 dstreg2 = translate_rreg (SD_, RN0);
2830 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2833 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
2834 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
2838 int srcreg1, srcreg2, dstreg1, dstreg2;
2844 srcreg1 = translate_rreg (SD_, RM2);
2845 srcreg2 = translate_rreg (SD_, RN0);
2846 dstreg1 = translate_rreg (SD_, RD0);
2847 dstreg2 = translate_rreg (SD_, RD2);
2849 temp = ((signed64)(signed32)State.regs[srcreg1]
2850 * (signed64)(signed32)State.regs[srcreg2]);
2852 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2853 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2854 State.regs[dstreg2] = sum;
2857 sum = State.regs[dstreg1] + temp + c;
2858 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2859 && (temp & 0x80000000) != (sum & 0x80000000));
2860 State.regs[dstreg1] = sum;
2863 State.regs[REG_MCVF] = 1;
2865 PSW |= (( v ? PSW_V : 0));
2869 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
2870 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
2874 int srcreg1, srcreg2, dstreg1, dstreg2;
2880 srcreg1 = translate_rreg (SD_, RM2);
2881 srcreg2 = translate_rreg (SD_, RN0);
2882 dstreg1 = translate_rreg (SD_, RD0);
2883 dstreg2 = translate_rreg (SD_, RD2);
2885 temp = ((unsigned64)State.regs[srcreg1]
2886 * (unsigned64)State.regs[srcreg2]);
2888 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2889 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2890 State.regs[dstreg2] = sum;
2893 sum = State.regs[dstreg1] + temp + c;
2894 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2895 && (temp & 0x80000000) != (sum & 0x80000000));
2896 State.regs[dstreg1] = sum;
2899 State.regs[REG_MCVF] = 1;
2901 PSW |= (( v ? PSW_V : 0));
2905 // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
2906 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2910 int srcreg1, srcreg2, dstreg;
2915 srcreg1 = translate_rreg (SD_, RM2);
2916 srcreg2 = translate_rreg (SD_, RN0);
2917 dstreg = translate_rreg (SD_, RD0);
2919 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2920 * (signed32)(State.regs[srcreg1] & 0xff));
2921 sum = State.regs[dstreg] + temp;
2922 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2923 && (temp & 0x80000000) != (sum & 0x80000000));
2924 State.regs[dstreg] = sum;
2927 State.regs[REG_MCVF] = 1;
2929 PSW |= ((v ? PSW_V : 0));
2933 // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
2934 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2938 int srcreg1, srcreg2, dstreg;
2943 srcreg1 = translate_rreg (SD_, RM2);
2944 srcreg2 = translate_rreg (SD_, RN0);
2945 dstreg = translate_rreg (SD_, RD0);
2947 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2948 * (unsigned32)(State.regs[srcreg1] & 0xff));
2949 sum = State.regs[dstreg] + temp;
2950 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2951 && (temp & 0x80000000) != (sum & 0x80000000));
2952 State.regs[dstreg] = sum;
2955 State.regs[REG_MCVF] = 1;
2957 PSW |= ((v ? PSW_V : 0));
2961 // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
2962 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
2966 int srcreg1, srcreg2, dstreg1, dstreg2;
2971 srcreg1 = translate_rreg (SD_, RM2);
2972 srcreg2 = translate_rreg (SD_, RN0);
2973 dstreg1 = translate_rreg (SD_, RD0);
2974 dstreg2 = translate_rreg (SD_, RD0);
2976 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2977 * (signed32)(State.regs[srcreg1] & 0xffff));
2978 State.regs[dstreg2] += (temp & 0xffffffff);
2979 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
2980 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2981 && (temp & 0x80000000) != (sum & 0x80000000));
2982 State.regs[dstreg1] = sum;
2985 State.regs[REG_MCVF] = 1;
2987 PSW |= ((v ? PSW_V : 0));
2991 // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
2992 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
2996 int srcreg1, srcreg2, dstreg1, dstreg2;
3001 srcreg1 = translate_rreg (SD_, RM2);
3002 srcreg2 = translate_rreg (SD_, RN0);
3003 dstreg1 = translate_rreg (SD_, RD0);
3004 dstreg2 = translate_rreg (SD_, RD0);
3006 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3007 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3008 State.regs[dstreg2] += (temp & 0xffffffff);
3009 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
3010 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
3011 && (temp & 0x80000000) != (sum & 0x80000000));
3012 State.regs[dstreg1] = sum;
3015 State.regs[REG_MCVF] = 1;
3017 PSW |= ((v ? PSW_V : 0));
3021 // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
3022 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
3026 int srcreg1, srcreg2, dstreg;
3027 signed32 temp, temp2, sum;
3031 srcreg1 = translate_rreg (SD_, RM2);
3032 srcreg2 = translate_rreg (SD_, RN0);
3033 dstreg = translate_rreg (SD_, RD0);
3035 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
3036 * (signed32)(State.regs[srcreg1] & 0xffff));
3037 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3038 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
3039 sum = temp + temp2 + State.regs[dstreg];
3040 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3041 && (temp & 0x80000000) != (sum & 0x80000000));
3042 State.regs[dstreg] = sum;
3045 State.regs[REG_MCVF] = 1;
3047 PSW |= ((v ? PSW_V : 0));
3051 // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
3052 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
3056 int srcreg1, srcreg2, dstreg;
3057 signed32 temp, temp2, sum;
3061 srcreg1 = translate_rreg (SD_, RM2);
3062 srcreg2 = translate_rreg (SD_, RN0);
3063 dstreg = translate_rreg (SD_, RD0);
3065 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3066 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3067 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3068 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
3069 sum = temp + temp2 + State.regs[dstreg];
3070 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3071 && (temp & 0x80000000) != (sum & 0x80000000));
3072 State.regs[dstreg] = sum;
3075 State.regs[REG_MCVF] = 1;
3077 PSW |= ((v ? PSW_V : 0));
3081 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3082 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
3086 int srcreg1, srcreg2, dstreg1, dstreg2;
3090 srcreg1 = translate_rreg (SD_, RM2);
3091 srcreg2 = translate_rreg (SD_, RN0);
3092 dstreg1 = translate_rreg (SD_, RD0);
3093 dstreg2 = translate_rreg (SD_, RD2);
3095 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3096 * (signed32)(State.regs[srcreg1] & 0xffff));
3097 State.regs[dstreg2] = temp;
3098 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3099 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3100 State.regs[dstreg1] = temp;
3103 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3104 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
3108 int srcreg1, srcreg2, dstreg1, dstreg2;
3112 srcreg1 = translate_rreg (SD_, RM2);
3113 srcreg2 = translate_rreg (SD_, RN0);
3114 dstreg1 = translate_rreg (SD_, RD0);
3115 dstreg2 = translate_rreg (SD_, RD2);
3117 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3118 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3119 State.regs[dstreg2] = temp;
3120 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3121 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3122 State.regs[dstreg1] = temp;
3125 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3126 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3134 srcreg = translate_rreg (SD_, RM2);
3135 dstreg = translate_rreg (SD_, RN0);
3137 value = State.regs[srcreg];
3139 if (value >= 0x7fffff)
3140 State.regs[dstreg] = 0x7fffff;
3141 else if (value <= 0xff800000)
3142 State.regs[dstreg] = 0xff800000;
3144 State.regs[dstreg] = value;
3146 n = (State.regs[dstreg] & 0x800000) != 0;
3147 z = (State.regs[dstreg] == 0);
3148 PSW &= ~(PSW_Z | PSW_N);
3149 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3152 // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
3153 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3158 int srcreg1, srcreg2, dstreg;
3162 srcreg1 = translate_rreg (SD_, RM2);
3163 srcreg2 = translate_rreg (SD_, RN0);
3164 dstreg = translate_rreg (SD_, RD0);
3166 temp = State.regs[srcreg1];
3167 start = (State.regs[srcreg2] & 0x1f) - 1;
3171 for (i = start; i >= 0; i--)
3173 if (temp & (1 << i))
3176 State.regs[dstreg] = i;
3184 State.regs[dstreg] = 0;
3187 PSW |= (c ? PSW_C : 0);
3190 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3191 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3198 dstreg = translate_rreg (SD_, RN0);
3199 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3202 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
3203 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3210 dstreg = translate_rreg (SD_, RN0);
3211 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3214 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
3215 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3222 dstreg = translate_rreg (SD_, RN0);
3223 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3226 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
3227 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3231 int dstreg, z, n, c, v;
3232 unsigned32 sum, imm, reg2;
3235 dstreg = translate_rreg (SD_, RN0);
3237 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3238 reg2 = State.regs[dstreg];
3239 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3240 State.regs[dstreg] = sum;
3242 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3243 n = (sum & 0x80000000);
3244 c = (sum < imm) || (sum < reg2);
3245 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3246 && (reg2 & 0x80000000) != (sum & 0x80000000));
3248 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3249 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3250 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3253 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
3254 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3261 dstreg = translate_rreg (SD_, RN0);
3262 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3265 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
3266 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3270 int dstreg, z, n, c, v;
3271 unsigned32 difference, imm, reg2;
3274 dstreg = translate_rreg (SD_, RN0);
3276 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3277 reg2 = State.regs[dstreg];
3278 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3279 State.regs[dstreg] = difference;
3281 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3282 n = (difference & 0x80000000);
3284 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3285 && (reg2 & 0x80000000) != (difference & 0x80000000));
3287 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3288 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3289 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3292 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
3293 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3300 srcreg = translate_rreg (SD_, RN0);
3301 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3304 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
3305 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3312 dstreg = translate_xreg (SD_, XRN0);
3314 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3317 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3318 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3326 dstreg = translate_rreg (SD_, RN0);
3328 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3329 z = (State.regs[dstreg] == 0);
3330 n = (State.regs[dstreg] & 0x80000000) != 0;
3331 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3332 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3335 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3336 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3344 dstreg = translate_rreg (SD_, RN0);
3346 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3347 z = (State.regs[dstreg] == 0);
3348 n = (State.regs[dstreg] & 0x80000000) != 0;
3349 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3350 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3353 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3354 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3362 dstreg = translate_rreg (SD_, RN0);
3364 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3365 z = (State.regs[dstreg] == 0);
3366 n = (State.regs[dstreg] & 0x80000000) != 0;
3367 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3368 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3371 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3372 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3381 dstreg = translate_rreg (SD_, RN0);
3383 temp = State.regs[dstreg];
3385 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3386 State.regs[dstreg] = temp;
3387 z = (State.regs[dstreg] == 0);
3388 n = (State.regs[dstreg] & 0x80000000) != 0;
3389 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3390 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3394 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3395 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3403 dstreg = translate_rreg (SD_, RN0);
3405 c = State.regs[dstreg] & 1;
3406 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3407 z = (State.regs[dstreg] == 0);
3408 n = (State.regs[dstreg] & 0x80000000) != 0;
3409 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3410 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3413 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3414 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3422 dstreg = translate_rreg (SD_, RN0);
3424 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3425 z = (State.regs[dstreg] == 0);
3426 n = (State.regs[dstreg] & 0x80000000) != 0;
3427 PSW &= ~(PSW_Z | PSW_N);
3428 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3431 // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3432 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3441 dstreg = translate_rreg (SD_, RN0);
3443 temp = ((signed64)(signed32)State.regs[dstreg]
3444 * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3445 State.regs[dstreg] = temp & 0xffffffff;
3446 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
3447 z = (State.regs[dstreg] == 0);
3448 n = (State.regs[dstreg] & 0x80000000) != 0;
3449 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3450 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3453 // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3454 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3463 dstreg = translate_rreg (SD_, RN0);
3465 temp = ((unsigned64)State.regs[dstreg]
3466 * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3467 State.regs[dstreg] = temp & 0xffffffff;
3468 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
3469 z = (State.regs[dstreg] == 0);
3470 n = (State.regs[dstreg] & 0x80000000) != 0;
3471 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3472 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3475 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3476 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3483 srcreg = translate_rreg (SD_, RN0);
3484 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3487 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3488 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3495 srcreg = translate_rreg (SD_, RM0);
3496 dstreg = translate_rreg (SD_, RN2);
3497 State.regs[dstreg] = load_word (State.regs[srcreg]
3498 + EXTEND24 (FETCH24 (IMM24A,
3502 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3503 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3510 srcreg = translate_rreg (SD_, RM2);
3511 dstreg = translate_rreg (SD_, RN0);
3512 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3513 State.regs[srcreg]);
3516 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3517 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3524 srcreg = translate_rreg (SD_, RM0);
3525 dstreg = translate_rreg (SD_, RN2);
3526 State.regs[dstreg] = load_byte (State.regs[srcreg]
3527 + EXTEND24 (FETCH24 (IMM24A,
3531 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3532 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3539 srcreg = translate_rreg (SD_, RM2);
3540 dstreg = translate_rreg (SD_, RN0);
3541 store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3542 State.regs[srcreg]);
3545 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3546 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3553 srcreg = translate_rreg (SD_, RM0);
3554 dstreg = translate_rreg (SD_, RN2);
3555 State.regs[dstreg] = load_half (State.regs[srcreg]
3556 + EXTEND24 (FETCH24 (IMM24A,
3560 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3561 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3568 srcreg = translate_rreg (SD_, RM2);
3569 dstreg = translate_rreg (SD_, RN0);
3570 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3571 State.regs[srcreg]);
3574 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3575 8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3582 srcreg = translate_rreg (SD_, RM0);
3583 dstreg = translate_rreg (SD_, RN2);
3584 State.regs[dstreg] = load_word (State.regs[srcreg]);
3585 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3588 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3589 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3596 srcreg = translate_rreg (SD_, RM2);
3597 dstreg = translate_rreg (SD_, RN0);
3598 store_word (State.regs[dstreg], State.regs[srcreg]);
3599 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3603 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3604 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3611 dstreg = translate_rreg (SD_, RN2);
3612 State.regs[dstreg] = load_word (State.regs[REG_SP]
3613 + FETCH24 (IMM24A, IMM24B, IMM24C));
3616 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3617 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3624 srcreg = translate_rreg (SD_, RM2);
3625 store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3626 State.regs[srcreg]);
3629 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,sp),Rn
3630 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3637 dstreg = translate_rreg (SD_, RN2);
3638 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3639 + FETCH24 (IMM24A, IMM24B, IMM24C));
3642 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3643 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3650 srcreg = translate_rreg (SD_, RM2);
3651 store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3652 State.regs[srcreg]);
3655 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3656 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3663 dstreg = translate_rreg (SD_, RN2);
3664 State.regs[dstreg] = load_half (State.regs[REG_SP]
3665 + FETCH24 (IMM24A, IMM24B, IMM24C));
3668 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3669 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3676 srcreg = translate_rreg (SD_, RM2);
3677 store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3678 State.regs[srcreg]);
3681 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3682 8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3689 srcreg = translate_rreg (SD_, RM0);
3690 dstreg = translate_rreg (SD_, RN2);
3691 State.regs[dstreg] = load_half (State.regs[srcreg]);
3692 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3695 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3696 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3703 srcreg = translate_rreg (SD_, RM2);
3704 dstreg = translate_rreg (SD_, RN0);
3705 store_half (State.regs[dstreg], State.regs[srcreg]);
3706 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3709 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
3710 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3719 srcreg = translate_rreg (SD_, RN2);
3721 temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
3722 * (signed64)State.regs[srcreg]);
3723 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3724 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3725 State.regs[REG_MCRL] = sum;
3728 sum = State.regs[REG_MCRH] + temp + c;
3729 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3730 && (temp & 0x80000000) != (sum & 0x80000000));
3731 State.regs[REG_MCRH] = sum;
3733 State.regs[REG_MCVF] = 1;
3736 // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
3737 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3746 srcreg = translate_rreg (SD_, RN2);
3748 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3749 * (unsigned64)State.regs[srcreg]);
3750 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3751 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3752 State.regs[REG_MCRL] = sum;
3755 sum = State.regs[REG_MCRH] + temp + c;
3756 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3757 && (temp & 0x80000000) != (sum & 0x80000000));
3758 State.regs[REG_MCRH] = sum;
3760 State.regs[REG_MCVF] = 1;
3763 // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
3764 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3773 srcreg = translate_rreg (SD_, RN2);
3775 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3776 * (signed64)State.regs[srcreg] & 0xff);
3777 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3778 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3779 State.regs[REG_MCRL] = sum;
3782 sum = State.regs[REG_MCRH] + temp + c;
3783 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3784 && (temp & 0x80000000) != (sum & 0x80000000));
3785 State.regs[REG_MCRH] = sum;
3787 State.regs[REG_MCVF] = 1;
3790 // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
3791 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3800 srcreg = translate_rreg (SD_, RN2);
3802 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3803 * (unsigned64)State.regs[srcreg] & 0xff);
3804 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3805 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3806 State.regs[REG_MCRL] = sum;
3809 sum = State.regs[REG_MCRH] + temp + c;
3810 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3811 && (temp & 0x80000000) != (sum & 0x80000000));
3812 State.regs[REG_MCRH] = sum;
3814 State.regs[REG_MCVF] = 1;
3817 // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
3818 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3827 srcreg = translate_rreg (SD_, RN2);
3829 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3830 * (signed64)State.regs[srcreg] & 0xffff);
3831 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3832 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3833 State.regs[REG_MCRL] = sum;
3836 sum = State.regs[REG_MCRH] + temp + c;
3837 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3838 && (temp & 0x80000000) != (sum & 0x80000000));
3839 State.regs[REG_MCRH] = sum;
3841 State.regs[REG_MCVF] = 1;
3844 // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
3845 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3854 srcreg = translate_rreg (SD_, RN2);
3856 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3857 * (unsigned64)State.regs[srcreg] & 0xffff);
3858 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3859 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3860 State.regs[REG_MCRL] = sum;
3863 sum = State.regs[REG_MCRH] + temp + c;
3864 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3865 && (temp & 0x80000000) != (sum & 0x80000000));
3866 State.regs[REG_MCRH] = sum;
3868 State.regs[REG_MCVF] = 1;
3871 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3872 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3879 dstreg = translate_rreg (SD_, RN2);
3880 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3883 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3884 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3891 srcreg = translate_rreg (SD_, RM2);
3892 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3896 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3897 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3904 dstreg = translate_rreg (SD_, RN2);
3905 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3908 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3909 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3916 srcreg = translate_rreg (SD_, RM2);
3917 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3921 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3922 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3929 dstreg = translate_rreg (SD_, RN2);
3930 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3933 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3934 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3941 srcreg = translate_rreg (SD_, RM2);
3942 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3946 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3947 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3954 dstreg = translate_rreg (SD_, RN0);
3955 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3958 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3959 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3966 dstreg = translate_rreg (SD_, RN0);
3967 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3970 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3971 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3978 dstreg = translate_rreg (SD_, RN0);
3979 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3982 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3983 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3988 unsigned32 imm, reg2, sum;
3992 dstreg = translate_rreg (SD_, RN0);
3994 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3995 reg2 = State.regs[dstreg];
3996 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3997 State.regs[dstreg] = sum;
3999 z = ((PSW & PSW_Z) != 0) && (sum == 0);
4000 n = (sum & 0x80000000);
4001 c = (sum < imm) || (sum < reg2);
4002 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4003 && (reg2 & 0x80000000) != (sum & 0x80000000));
4005 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4006 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4007 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4010 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
4011 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
4018 dstreg = translate_rreg (SD_, RN0);
4019 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
4022 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
4023 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4028 unsigned32 imm, reg2, difference;
4032 dstreg = translate_rreg (SD_, RN0);
4034 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4035 reg2 = State.regs[dstreg];
4036 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4037 State.regs[dstreg] = difference;
4039 z = ((PSW & PSW_Z) != 0) && (difference == 0);
4040 n = (difference & 0x80000000);
4042 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4043 && (reg2 & 0x80000000) != (difference & 0x80000000));
4045 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4046 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4047 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4050 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
4051 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4058 srcreg = translate_rreg (SD_, RN0);
4059 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4062 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
4063 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
4070 dstreg = translate_xreg (SD_, XRN0);
4072 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4075 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
4076 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4084 dstreg = translate_rreg (SD_, RN0);
4086 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4087 z = (State.regs[dstreg] == 0);
4088 n = (State.regs[dstreg] & 0x80000000) != 0;
4089 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4090 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4093 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
4094 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4102 dstreg = translate_rreg (SD_, RN0);
4104 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4105 z = (State.regs[dstreg] == 0);
4106 n = (State.regs[dstreg] & 0x80000000) != 0;
4107 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4108 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4111 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
4112 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4120 dstreg = translate_rreg (SD_, RN0);
4122 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4123 z = (State.regs[dstreg] == 0);
4124 n = (State.regs[dstreg] & 0x80000000) != 0;
4125 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4126 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4129 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
4130 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4139 dstreg = translate_rreg (SD_, RN0);
4141 temp = State.regs[dstreg];
4143 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4144 State.regs[dstreg] = temp;
4145 z = (State.regs[dstreg] == 0);
4146 n = (State.regs[dstreg] & 0x80000000) != 0;
4147 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4148 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4151 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
4152 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4160 dstreg = translate_rreg (SD_, RN0);
4162 c = State.regs[dstreg] & 1;
4163 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4164 z = (State.regs[dstreg] == 0);
4165 n = (State.regs[dstreg] & 0x80000000) != 0;
4166 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4167 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4170 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
4171 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4179 dstreg = translate_rreg (SD_, RN0);
4181 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4182 z = (State.regs[dstreg] == 0);
4183 n = (State.regs[dstreg] & 0x80000000) != 0;
4184 PSW &= ~(PSW_Z | PSW_N);
4185 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4188 // 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
4189 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
4198 dstreg = translate_rreg (SD_, RN0);
4200 temp = ((signed64)(signed32)State.regs[dstreg]
4201 * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4202 State.regs[dstreg] = temp & 0xffffffff;
4203 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
4204 z = (State.regs[dstreg] == 0);
4205 n = (State.regs[dstreg] & 0x80000000) != 0;
4206 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4207 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4210 // 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
4211 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
4220 dstreg = translate_rreg (SD_, RN0);
4222 temp = ((unsigned64)State.regs[dstreg]
4223 * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4224 State.regs[dstreg] = temp & 0xffffffff;
4225 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
4226 z = (State.regs[dstreg] == 0);
4227 n = (State.regs[dstreg] & 0x80000000) != 0;
4228 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4229 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4232 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
4233 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4240 srcreg = translate_rreg (SD_, RN0);
4241 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4244 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
4245 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4252 srcreg = translate_rreg (SD_, RM0);
4253 dstreg = translate_rreg (SD_, RN2);
4254 State.regs[dstreg] = load_word (State.regs[srcreg]
4255 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4258 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
4259 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4266 srcreg = translate_rreg (SD_, RM2);
4267 dstreg = translate_rreg (SD_, RN0);
4268 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4269 State.regs[srcreg]);
4272 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
4273 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4280 srcreg = translate_rreg (SD_, RM0);
4281 dstreg = translate_rreg (SD_, RN2);
4282 State.regs[dstreg] = load_byte (State.regs[srcreg]
4283 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4286 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
4287 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4294 srcreg = translate_rreg (SD_, RM2);
4295 dstreg = translate_rreg (SD_, RN0);
4296 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4297 State.regs[srcreg]);
4300 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
4301 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4308 srcreg = translate_rreg (SD_, RM0);
4309 dstreg = translate_rreg (SD_, RN2);
4310 State.regs[dstreg] = load_half (State.regs[srcreg]
4311 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4314 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
4315 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4322 srcreg = translate_rreg (SD_, RM2);
4323 dstreg = translate_rreg (SD_, RN0);
4324 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4325 State.regs[srcreg]);
4328 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
4329 8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4336 srcreg = translate_rreg (SD_, RM0);
4337 dstreg = translate_rreg (SD_, RN2);
4338 State.regs[dstreg] = load_word (State.regs[srcreg]);
4339 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4342 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
4343 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4350 srcreg = translate_rreg (SD_, RM2);
4351 dstreg = translate_rreg (SD_, RN0);
4352 store_word (State.regs[dstreg], State.regs[srcreg]);
4353 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4357 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
4358 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4365 dstreg = translate_rreg (SD_, RN2);
4366 State.regs[dstreg] = load_word (State.regs[REG_SP]
4367 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4370 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
4371 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4378 srcreg = translate_rreg (SD_, RM2);
4379 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4380 State.regs[srcreg]);
4383 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
4384 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4391 dstreg = translate_rreg (SD_, RN2);
4392 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4393 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4396 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
4397 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4404 srcreg = translate_rreg (SD_, RM2);
4405 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4406 State.regs[srcreg]);
4409 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4410 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4417 dstreg = translate_rreg (SD_, RN2);
4418 State.regs[dstreg] = load_half (State.regs[REG_SP]
4419 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4422 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4423 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4430 srcreg = translate_rreg (SD_, RM2);
4431 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4432 State.regs[srcreg]);
4436 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
4437 8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4444 srcreg = translate_rreg (SD_, RM0);
4445 dstreg = translate_rreg (SD_, RN2);
4446 State.regs[dstreg] = load_half (State.regs[srcreg]);
4447 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4450 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
4451 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4458 srcreg = translate_rreg (SD_, RM2);
4459 dstreg = translate_rreg (SD_, RN0);
4460 store_half (State.regs[dstreg], State.regs[srcreg]);
4461 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4465 // 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
4466 8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
4475 srcreg = translate_rreg (SD_, RN0);
4476 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4478 temp = ((signed64)(signed32)State.regs[srcreg]
4479 * (signed64)(signed32)imm);
4480 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4481 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4482 State.regs[REG_MCRL] = sum;
4485 sum = State.regs[REG_MCRH] + temp + c;
4486 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4487 && (temp & 0x80000000) != (sum & 0x80000000));
4488 State.regs[REG_MCRH] = sum;
4490 State.regs[REG_MCVF] = 1;
4493 // 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
4494 8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
4503 srcreg = translate_rreg (SD_, RN0);
4504 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4506 temp = ((unsigned64)State.regs[srcreg]
4508 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4509 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4510 State.regs[REG_MCRL] = sum;
4513 sum = State.regs[REG_MCRH] + temp + c;
4514 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4515 && (temp & 0x80000000) != (sum & 0x80000000));
4516 State.regs[REG_MCRH] = sum;
4518 State.regs[REG_MCVF] = 1;
4521 // 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
4522 8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
4531 srcreg = translate_rreg (SD_, RN0);
4532 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4534 temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
4535 * (signed32)(signed8)(imm & 0xff));
4536 sum = State.regs[REG_MCRL] + temp;
4537 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4538 && (temp & 0x80000000) != (sum & 0x80000000));
4539 State.regs[REG_MCRL] = sum;
4541 State.regs[REG_MCVF] = 1;
4544 // 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
4545 8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
4554 srcreg = translate_rreg (SD_, RN0);
4555 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4557 temp = ((unsigned32)(State.regs[srcreg] & 0xff)
4558 * (unsigned32)(imm & 0xff));
4559 sum = State.regs[REG_MCRL] + temp;
4560 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4561 && (temp & 0x80000000) != (sum & 0x80000000));
4562 State.regs[REG_MCRL] = sum;
4564 State.regs[REG_MCVF] = 1;
4567 // 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
4568 8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
4577 srcreg = translate_rreg (SD_, RN0);
4578 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4580 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4581 * (signed32)(signed16)(imm & 0xffff));
4582 sum = State.regs[REG_MCRL] + temp;
4583 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4584 && (temp & 0x80000000) != (sum & 0x80000000));
4585 State.regs[REG_MCRL] = sum;
4587 State.regs[REG_MCVF] = 1;
4590 // 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
4591 8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
4600 srcreg = translate_rreg (SD_, RN0);
4601 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4603 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4604 * (unsigned32)(imm & 0xffff));
4605 sum = State.regs[REG_MCRL] + temp;
4606 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4607 && (temp & 0x80000000) != (sum & 0x80000000));
4608 State.regs[REG_MCRL] = sum;
4610 State.regs[REG_MCVF] = 1;
4613 // 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
4614 8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
4619 signed32 temp, temp2, sum;
4623 srcreg = translate_rreg (SD_, RN0);
4624 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4626 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4627 * (signed32)(signed16)(imm & 0xffff));
4628 temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
4629 * (signed32)(signed16)((imm >> 16) & 0xffff));
4630 sum = temp + temp2 + State.regs[REG_MCRL];
4631 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4632 && (temp & 0x80000000) != (sum & 0x80000000));
4633 State.regs[REG_MCRL] = sum;
4635 State.regs[REG_MCVF] = 1;
4638 // 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
4639 8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
4644 signed32 temp, temp2, sum;
4648 srcreg = translate_rreg (SD_, RN0);
4649 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4651 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4652 * (unsigned32)(imm & 0xffff));
4653 temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
4654 * (unsigned32)((imm >> 16) & 0xffff));
4655 sum = temp + temp2 + State.regs[REG_MCRL];
4656 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4657 && (temp & 0x80000000) != (sum & 0x80000000));
4658 State.regs[REG_MCRL] = sum;
4660 State.regs[REG_MCVF] = 1;
4663 // 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
4664 8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
4672 dstreg = translate_rreg (SD_, RN0);
4673 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4675 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
4676 * (signed32)(signed16)(imm & 0xffff));
4677 State.regs[REG_MDRQ] = temp;
4678 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
4679 * (signed32)(signed16)((imm>>16) & 0xffff));
4680 State.regs[dstreg] = temp;
4683 // 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
4684 8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
4692 dstreg = translate_rreg (SD_, RN0);
4693 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4695 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
4696 * (unsigned32)(imm & 0xffff));
4697 State.regs[REG_MDRQ] = temp;
4698 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
4699 * (unsigned32)((imm >>16) & 0xffff));
4700 State.regs[dstreg] = temp;
4703 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4704 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4711 dstreg = translate_rreg (SD_, RN2);
4712 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4715 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4716 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4723 srcreg = translate_rreg (SD_, RM2);
4724 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4727 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4728 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4735 dstreg = translate_rreg (SD_, RN2);
4736 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4739 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4740 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4747 srcreg = translate_rreg (SD_, RM2);
4748 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4751 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4752 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4759 dstreg = translate_rreg (SD_, RN2);
4760 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4763 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4764 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4771 srcreg = translate_rreg (SD_, RM2);
4772 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4775 // 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
4776 8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
4780 int srcreg1, srcreg2, dstreg1, dstreg2;
4784 srcreg1 = translate_rreg (SD_, RM1);
4785 srcreg2 = translate_rreg (SD_, RM2);
4786 dstreg1 = translate_rreg (SD_, RN1);
4787 dstreg2 = translate_rreg (SD_, RN2);
4789 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4790 State.regs[dstreg2] += State.regs[srcreg2];
4791 State.regs[dstreg1] = result1;
4794 // 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
4795 8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
4799 int srcreg1, dstreg1, dstreg2;
4803 srcreg1 = translate_rreg (SD_, RM1);
4804 dstreg1 = translate_rreg (SD_, RN1);
4805 dstreg2 = translate_rreg (SD_, RN2);
4807 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4808 State.regs[dstreg2] += EXTEND4 (IMM4);
4809 State.regs[dstreg1] = result1;
4812 // 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
4813 8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
4817 int srcreg1, srcreg2, dstreg1, dstreg2;
4821 srcreg1 = translate_rreg (SD_, RM1);
4822 srcreg2 = translate_rreg (SD_, RM2);
4823 dstreg1 = translate_rreg (SD_, RN1);
4824 dstreg2 = translate_rreg (SD_, RN2);
4826 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4827 State.regs[dstreg2] -= State.regs[srcreg2];
4828 State.regs[dstreg1] = result1;
4831 // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
4832 8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
4836 int srcreg1, dstreg1, dstreg2;
4840 srcreg1 = translate_rreg (SD_, RM1);
4841 dstreg1 = translate_rreg (SD_, RN1);
4842 dstreg2 = translate_rreg (SD_, RN2);
4844 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4845 State.regs[dstreg2] -= EXTEND4 (IMM4);
4846 State.regs[dstreg1] = result1;
4849 // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
4850 8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
4854 int srcreg1, srcreg2, dstreg1, dstreg2;
4857 srcreg1 = translate_rreg (SD_, RM1);
4858 srcreg2 = translate_rreg (SD_, RM2);
4859 dstreg1 = translate_rreg (SD_, RN1);
4860 dstreg2 = translate_rreg (SD_, RN2);
4862 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
4863 State.regs[dstreg1] += State.regs[srcreg1];
4866 // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
4867 8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
4871 int srcreg1, dstreg1, dstreg2;
4874 srcreg1 = translate_rreg (SD_, RM1);
4875 dstreg1 = translate_rreg (SD_, RN1);
4876 dstreg2 = translate_rreg (SD_, RN2);
4878 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
4879 State.regs[dstreg1] += State.regs[srcreg1];
4882 // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
4883 8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
4887 int srcreg1, srcreg2, dstreg1, dstreg2;
4891 srcreg1 = translate_rreg (SD_, RM1);
4892 srcreg2 = translate_rreg (SD_, RM2);
4893 dstreg1 = translate_rreg (SD_, RN1);
4894 dstreg2 = translate_rreg (SD_, RN2);
4896 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4897 State.regs[dstreg2] = State.regs[srcreg2];
4898 State.regs[dstreg1] = result1;
4901 // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
4902 8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
4906 int srcreg1, dstreg1, dstreg2;
4910 srcreg1 = translate_rreg (SD_, RM1);
4911 dstreg1 = translate_rreg (SD_, RN1);
4912 dstreg2 = translate_rreg (SD_, RN2);
4914 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4915 State.regs[dstreg2] = EXTEND4 (IMM4);
4916 State.regs[dstreg1] = result1;
4919 // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
4920 8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
4924 int srcreg1, srcreg2, dstreg1, dstreg2;
4929 srcreg1 = translate_rreg (SD_, RM1);
4930 srcreg2 = translate_rreg (SD_, RM2);
4931 dstreg1 = translate_rreg (SD_, RN1);
4932 dstreg2 = translate_rreg (SD_, RN2);
4934 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4935 temp = State.regs[dstreg2];
4936 temp >>= State.regs[srcreg2];
4937 State.regs[dstreg2] = temp;
4938 State.regs[dstreg1] = result1;
4941 // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
4942 8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
4946 int srcreg1, dstreg1, dstreg2;
4951 srcreg1 = translate_rreg (SD_, RM1);
4952 dstreg1 = translate_rreg (SD_, RN1);
4953 dstreg2 = translate_rreg (SD_, RN2);
4955 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4956 temp = State.regs[dstreg2];
4958 State.regs[dstreg2] = temp;
4959 State.regs[dstreg1] = result1;
4962 // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
4963 8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
4967 int srcreg1, srcreg2, dstreg1, dstreg2;
4971 srcreg1 = translate_rreg (SD_, RM1);
4972 srcreg2 = translate_rreg (SD_, RM2);
4973 dstreg1 = translate_rreg (SD_, RN1);
4974 dstreg2 = translate_rreg (SD_, RN2);
4976 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4977 State.regs[dstreg2] >>= State.regs[srcreg2];
4978 State.regs[dstreg1] = result1;
4981 // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
4982 8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
4986 int srcreg1, dstreg1, dstreg2;
4991 srcreg1 = translate_rreg (SD_, RM1);
4992 dstreg1 = translate_rreg (SD_, RN1);
4993 dstreg2 = translate_rreg (SD_, RN2);
4995 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4996 State.regs[dstreg2] >>= IMM4;
4997 State.regs[dstreg1] = result1;
5001 // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
5002 8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
5006 int srcreg1, srcreg2, dstreg1, dstreg2;
5010 srcreg1 = translate_rreg (SD_, RM1);
5011 srcreg2 = translate_rreg (SD_, RM2);
5012 dstreg1 = translate_rreg (SD_, RN1);
5013 dstreg2 = translate_rreg (SD_, RN2);
5015 result1 = State.regs[dstreg1] + State.regs[srcreg1];
5016 State.regs[dstreg2] <<= State.regs[srcreg2];
5017 State.regs[dstreg1] = result1;
5020 // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
5021 8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
5025 int srcreg1, dstreg1, dstreg2;
5030 srcreg1 = translate_rreg (SD_, RM1);
5031 dstreg1 = translate_rreg (SD_, RN1);
5032 dstreg2 = translate_rreg (SD_, RN2);
5034 result1 = State.regs[dstreg1] + State.regs[srcreg1];
5035 State.regs[dstreg2] <<= IMM4;
5036 State.regs[dstreg1] = result1;
5039 // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
5040 8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
5044 int srcreg1, srcreg2, dstreg1, dstreg2;
5047 srcreg1 = translate_rreg (SD_, RM1);
5048 srcreg2 = translate_rreg (SD_, RM2);
5049 dstreg1 = translate_rreg (SD_, RN1);
5050 dstreg2 = translate_rreg (SD_, RN2);
5052 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5053 State.regs[dstreg2] += State.regs[srcreg2];
5056 // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
5057 8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
5061 int srcreg1, dstreg1, dstreg2;
5064 srcreg1 = translate_rreg (SD_, RM1);
5065 dstreg1 = translate_rreg (SD_, RN1);
5066 dstreg2 = translate_rreg (SD_, RN2);
5068 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5069 State.regs[dstreg2] += EXTEND4 (IMM4);
5072 // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
5073 8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
5077 int srcreg1, srcreg2, dstreg1, dstreg2;
5080 srcreg1 = translate_rreg (SD_, RM1);
5081 srcreg2 = translate_rreg (SD_, RM2);
5082 dstreg1 = translate_rreg (SD_, RN1);
5083 dstreg2 = translate_rreg (SD_, RN2);
5085 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5086 State.regs[dstreg2] -= State.regs[srcreg2];
5089 // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
5090 8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
5094 int srcreg1, dstreg1, dstreg2;
5097 srcreg1 = translate_rreg (SD_, RM1);
5098 dstreg1 = translate_rreg (SD_, RN1);
5099 dstreg2 = translate_rreg (SD_, RN2);
5101 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5102 State.regs[dstreg2] -= EXTEND4 (IMM4);
5105 // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
5106 8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
5110 int srcreg1, srcreg2, dstreg1, dstreg2;
5113 srcreg1 = translate_rreg (SD_, RM1);
5114 srcreg2 = translate_rreg (SD_, RM2);
5115 dstreg1 = translate_rreg (SD_, RN1);
5116 dstreg2 = translate_rreg (SD_, RN2);
5118 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5119 State.regs[dstreg2] = State.regs[srcreg2];
5122 // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
5123 8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
5127 int srcreg1, dstreg1, dstreg2;
5130 srcreg1 = translate_rreg (SD_, RM1);
5131 dstreg1 = translate_rreg (SD_, RN1);
5132 dstreg2 = translate_rreg (SD_, RN2);
5134 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5135 State.regs[dstreg2] = EXTEND4 (IMM4);
5138 // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
5139 8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
5143 int srcreg1, srcreg2, dstreg1, dstreg2;
5147 srcreg1 = translate_rreg (SD_, RM1);
5148 srcreg2 = translate_rreg (SD_, RM2);
5149 dstreg1 = translate_rreg (SD_, RN1);
5150 dstreg2 = translate_rreg (SD_, RN2);
5152 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5153 temp = State.regs[dstreg2];
5154 temp >>= State.regs[srcreg2];
5155 State.regs[dstreg2] = temp;
5158 // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
5159 8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
5163 int srcreg1, dstreg1, dstreg2;
5167 srcreg1 = translate_rreg (SD_, RM1);
5168 dstreg1 = translate_rreg (SD_, RN1);
5169 dstreg2 = translate_rreg (SD_, RN2);
5171 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5172 temp = State.regs[dstreg2];
5174 State.regs[dstreg2] = temp;
5177 // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
5178 8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
5182 int srcreg1, srcreg2, dstreg1, dstreg2;
5185 srcreg1 = translate_rreg (SD_, RM1);
5186 srcreg2 = translate_rreg (SD_, RM2);
5187 dstreg1 = translate_rreg (SD_, RN1);
5188 dstreg2 = translate_rreg (SD_, RN2);
5190 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5191 State.regs[dstreg2] >>= State.regs[srcreg2];
5194 // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
5195 8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
5199 int srcreg1, dstreg1, dstreg2;
5203 srcreg1 = translate_rreg (SD_, RM1);
5204 dstreg1 = translate_rreg (SD_, RN1);
5205 dstreg2 = translate_rreg (SD_, RN2);
5207 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5208 State.regs[dstreg2] >>= IMM4;
5212 // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
5213 8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
5217 int srcreg1, srcreg2, dstreg1, dstreg2;
5220 srcreg1 = translate_rreg (SD_, RM1);
5221 srcreg2 = translate_rreg (SD_, RM2);
5222 dstreg1 = translate_rreg (SD_, RN1);
5223 dstreg2 = translate_rreg (SD_, RN2);
5225 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5226 State.regs[dstreg2] <<= State.regs[srcreg2];
5229 // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
5230 8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
5234 int srcreg1, dstreg1, dstreg2;
5238 srcreg1 = translate_rreg (SD_, RM1);
5239 dstreg1 = translate_rreg (SD_, RN1);
5240 dstreg2 = translate_rreg (SD_, RN2);
5242 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5243 State.regs[dstreg2] <<= IMM4;
5246 // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
5247 8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
5251 int srcreg1, srcreg2, dstreg1, dstreg2;
5255 srcreg1 = translate_rreg (SD_, RM1);
5256 srcreg2 = translate_rreg (SD_, RM2);
5257 dstreg1 = translate_rreg (SD_, RN1);
5258 dstreg2 = translate_rreg (SD_, RN2);
5260 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5261 State.regs[dstreg2] += State.regs[srcreg2];
5262 State.regs[dstreg1] = result1;
5265 // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
5266 8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
5270 int srcreg1, dstreg1, dstreg2;
5274 srcreg1 = translate_rreg (SD_, RM1);
5275 dstreg1 = translate_rreg (SD_, RN1);
5276 dstreg2 = translate_rreg (SD_, RN2);
5278 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5279 State.regs[dstreg2] += EXTEND4 (IMM4);
5280 State.regs[dstreg1] = result1;
5283 // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
5284 8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
5288 int srcreg1, srcreg2, dstreg1, dstreg2;
5292 srcreg1 = translate_rreg (SD_, RM1);
5293 srcreg2 = translate_rreg (SD_, RM2);
5294 dstreg1 = translate_rreg (SD_, RN1);
5295 dstreg2 = translate_rreg (SD_, RN2);
5297 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5298 State.regs[dstreg2] -= State.regs[srcreg2];
5299 State.regs[dstreg1] = result1;
5302 // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
5303 8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
5307 int srcreg1, dstreg1, dstreg2;
5311 srcreg1 = translate_rreg (SD_, RM1);
5312 dstreg1 = translate_rreg (SD_, RN1);
5313 dstreg2 = translate_rreg (SD_, RN2);
5315 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5316 State.regs[dstreg2] -= EXTEND4 (IMM4);
5317 State.regs[dstreg1] = result1;
5320 // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
5321 8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
5325 int srcreg1, srcreg2, dstreg1, dstreg2;
5328 srcreg1 = translate_rreg (SD_, RM1);
5329 srcreg2 = translate_rreg (SD_, RM2);
5330 dstreg1 = translate_rreg (SD_, RN1);
5331 dstreg2 = translate_rreg (SD_, RN2);
5333 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5334 State.regs[dstreg1] -= State.regs[srcreg1];
5337 // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
5338 8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
5342 int srcreg1, dstreg1, dstreg2;
5346 srcreg1 = translate_rreg (SD_, RM1);
5347 dstreg1 = translate_rreg (SD_, RN1);
5348 dstreg2 = translate_rreg (SD_, RN2);
5350 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5351 State.regs[dstreg1] -= State.regs[srcreg1];
5354 // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
5355 8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
5359 int srcreg1, srcreg2, dstreg1, dstreg2;
5363 srcreg1 = translate_rreg (SD_, RM1);
5364 srcreg2 = translate_rreg (SD_, RM2);
5365 dstreg1 = translate_rreg (SD_, RN1);
5366 dstreg2 = translate_rreg (SD_, RN2);
5368 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5369 State.regs[dstreg2] = State.regs[srcreg2];
5370 State.regs[dstreg1] = result1;
5373 // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
5374 8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
5378 int srcreg1, dstreg1, dstreg2;
5382 srcreg1 = translate_rreg (SD_, RM1);
5383 dstreg1 = translate_rreg (SD_, RN1);
5384 dstreg2 = translate_rreg (SD_, RN2);
5386 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5387 State.regs[dstreg2] = EXTEND4 (IMM4);
5388 State.regs[dstreg1] = result1;
5391 // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
5392 8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
5396 int srcreg1, srcreg2, dstreg1, dstreg2;
5401 srcreg1 = translate_rreg (SD_, RM1);
5402 srcreg2 = translate_rreg (SD_, RM2);
5403 dstreg1 = translate_rreg (SD_, RN1);
5404 dstreg2 = translate_rreg (SD_, RN2);
5406 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5407 temp = State.regs[dstreg2];
5408 temp >>= State.regs[srcreg2];
5409 State.regs[dstreg2] = temp;
5410 State.regs[dstreg1] = result1;
5413 // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
5414 8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
5418 int srcreg1, dstreg1, dstreg2;
5423 srcreg1 = translate_rreg (SD_, RM1);
5424 dstreg1 = translate_rreg (SD_, RN1);
5425 dstreg2 = translate_rreg (SD_, RN2);
5427 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5428 temp = State.regs[dstreg2];
5430 State.regs[dstreg2] = temp;
5431 State.regs[dstreg1] = result1;
5434 // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
5435 8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
5439 int srcreg1, srcreg2, dstreg1, dstreg2;
5443 srcreg1 = translate_rreg (SD_, RM1);
5444 srcreg2 = translate_rreg (SD_, RM2);
5445 dstreg1 = translate_rreg (SD_, RN1);
5446 dstreg2 = translate_rreg (SD_, RN2);
5448 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5449 State.regs[dstreg2] >>= State.regs[srcreg2];
5450 State.regs[dstreg1] = result1;
5453 // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
5454 8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
5458 int srcreg1, dstreg1, dstreg2;
5463 srcreg1 = translate_rreg (SD_, RM1);
5464 dstreg1 = translate_rreg (SD_, RN1);
5465 dstreg2 = translate_rreg (SD_, RN2);
5467 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5468 State.regs[dstreg2] >>= IMM4;
5469 State.regs[dstreg1] = result1;
5473 // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
5474 8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
5478 int srcreg1, srcreg2, dstreg1, dstreg2;
5482 srcreg1 = translate_rreg (SD_, RM1);
5483 srcreg2 = translate_rreg (SD_, RM2);
5484 dstreg1 = translate_rreg (SD_, RN1);
5485 dstreg2 = translate_rreg (SD_, RN2);
5487 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5488 State.regs[dstreg2] <<= State.regs[srcreg2];
5489 State.regs[dstreg1] = result1;
5492 // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
5493 8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
5497 int srcreg1, dstreg1, dstreg2;
5502 srcreg1 = translate_rreg (SD_, RM1);
5503 dstreg1 = translate_rreg (SD_, RN1);
5504 dstreg2 = translate_rreg (SD_, RN2);
5506 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5507 State.regs[dstreg2] <<= IMM4;
5508 State.regs[dstreg1] = result1;
5511 // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
5512 8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
5516 int srcreg1, srcreg2, dstreg1, dstreg2;
5520 srcreg1 = translate_rreg (SD_, RM1);
5521 srcreg2 = translate_rreg (SD_, RM2);
5522 dstreg1 = translate_rreg (SD_, RN1);
5523 dstreg2 = translate_rreg (SD_, RN2);
5525 result1 = State.regs[srcreg1];
5526 State.regs[dstreg2] += State.regs[srcreg2];
5527 State.regs[dstreg1] = result1;
5530 // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
5531 8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
5535 int srcreg1, dstreg1, dstreg2;
5539 srcreg1 = translate_rreg (SD_, RM1);
5540 dstreg1 = translate_rreg (SD_, RN1);
5541 dstreg2 = translate_rreg (SD_, RN2);
5543 result1 = State.regs[srcreg1];
5544 State.regs[dstreg2] += EXTEND4 (IMM4);
5545 State.regs[dstreg1] = result1;
5548 // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
5549 8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
5553 int srcreg1, srcreg2, dstreg1, dstreg2;
5557 srcreg1 = translate_rreg (SD_, RM1);
5558 srcreg2 = translate_rreg (SD_, RM2);
5559 dstreg1 = translate_rreg (SD_, RN1);
5560 dstreg2 = translate_rreg (SD_, RN2);
5562 result1 = State.regs[srcreg1];
5563 State.regs[dstreg2] -= State.regs[srcreg2];
5564 State.regs[dstreg1] = result1;
5567 // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
5568 8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
5572 int srcreg1, dstreg1, dstreg2;
5576 srcreg1 = translate_rreg (SD_, RM1);
5577 dstreg1 = translate_rreg (SD_, RN1);
5578 dstreg2 = translate_rreg (SD_, RN2);
5580 result1 = State.regs[srcreg1];
5581 State.regs[dstreg2] -= EXTEND4 (IMM4);
5582 State.regs[dstreg1] = result1;
5585 // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
5586 8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
5590 int srcreg1, srcreg2, dstreg1, dstreg2;
5593 srcreg1 = translate_rreg (SD_, RM1);
5594 srcreg2 = translate_rreg (SD_, RM2);
5595 dstreg1 = translate_rreg (SD_, RN1);
5596 dstreg2 = translate_rreg (SD_, RN2);
5598 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5599 State.regs[dstreg1] = State.regs[srcreg1];
5602 // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
5603 8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
5607 int srcreg1, dstreg1, dstreg2;
5610 srcreg1 = translate_rreg (SD_, RM1);
5611 dstreg1 = translate_rreg (SD_, RN1);
5612 dstreg2 = translate_rreg (SD_, RN2);
5614 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5615 State.regs[dstreg1] = State.regs[srcreg1];
5618 // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
5619 8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
5623 int srcreg1, srcreg2, dstreg1, dstreg2;
5627 srcreg1 = translate_rreg (SD_, RM1);
5628 srcreg2 = translate_rreg (SD_, RM2);
5629 dstreg1 = translate_rreg (SD_, RN1);
5630 dstreg2 = translate_rreg (SD_, RN2);
5632 result1 = State.regs[srcreg1];
5633 State.regs[dstreg2] = State.regs[srcreg2];
5634 State.regs[dstreg1] = result1;
5637 // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
5638 8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
5642 int srcreg1, dstreg1, dstreg2;
5646 srcreg1 = translate_rreg (SD_, RM1);
5647 dstreg1 = translate_rreg (SD_, RN1);
5648 dstreg2 = translate_rreg (SD_, RN2);
5650 result1 = State.regs[srcreg1];
5651 State.regs[dstreg2] = EXTEND4 (IMM4);
5652 State.regs[dstreg1] = result1;
5655 // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
5656 8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
5660 int srcreg1, srcreg2, dstreg1, dstreg2;
5665 srcreg1 = translate_rreg (SD_, RM1);
5666 srcreg2 = translate_rreg (SD_, RM2);
5667 dstreg1 = translate_rreg (SD_, RN1);
5668 dstreg2 = translate_rreg (SD_, RN2);
5670 result1 = State.regs[srcreg1];
5671 temp = State.regs[dstreg2];
5672 temp >>= State.regs[srcreg2];
5673 State.regs[dstreg2] = temp;
5674 State.regs[dstreg1] = result1;
5677 // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
5678 8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
5682 int srcreg1, dstreg1, dstreg2;
5687 srcreg1 = translate_rreg (SD_, RM1);
5688 dstreg1 = translate_rreg (SD_, RN1);
5689 dstreg2 = translate_rreg (SD_, RN2);
5691 result1 = State.regs[srcreg1];
5692 temp = State.regs[dstreg2];
5694 State.regs[dstreg2] = temp;
5695 State.regs[dstreg1] = result1;
5698 // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
5699 8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
5703 int srcreg1, srcreg2, dstreg1, dstreg2;
5707 srcreg1 = translate_rreg (SD_, RM1);
5708 srcreg2 = translate_rreg (SD_, RM2);
5709 dstreg1 = translate_rreg (SD_, RN1);
5710 dstreg2 = translate_rreg (SD_, RN2);
5712 result1 = State.regs[srcreg1];
5713 State.regs[dstreg2] >>= State.regs[srcreg2];
5714 State.regs[dstreg1] = result1;
5717 // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
5718 8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
5722 int srcreg1, dstreg1, dstreg2;
5727 srcreg1 = translate_rreg (SD_, RM1);
5728 dstreg1 = translate_rreg (SD_, RN1);
5729 dstreg2 = translate_rreg (SD_, RN2);
5731 result1 = State.regs[srcreg1];
5732 State.regs[dstreg2] >>= IMM4;
5733 State.regs[dstreg1] = result1;
5737 // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
5738 8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
5742 int srcreg1, srcreg2, dstreg1, dstreg2;
5746 srcreg1 = translate_rreg (SD_, RM1);
5747 srcreg2 = translate_rreg (SD_, RM2);
5748 dstreg1 = translate_rreg (SD_, RN1);
5749 dstreg2 = translate_rreg (SD_, RN2);
5751 result1 = State.regs[srcreg1];
5752 State.regs[dstreg2] <<= State.regs[srcreg2];
5753 State.regs[dstreg1] = result1;
5756 // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
5757 8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
5761 int srcreg1, dstreg1, dstreg2;
5766 srcreg1 = translate_rreg (SD_, RM1);
5767 dstreg1 = translate_rreg (SD_, RN1);
5768 dstreg2 = translate_rreg (SD_, RN2);
5770 result1 = State.regs[srcreg1];
5771 State.regs[dstreg2] <<= IMM4;
5772 State.regs[dstreg1] = result1;
5775 // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
5776 8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
5780 int srcreg2, dstreg1, dstreg2;
5784 srcreg2 = translate_rreg (SD_, RM2);
5785 dstreg1 = translate_rreg (SD_, RN1);
5786 dstreg2 = translate_rreg (SD_, RN2);
5788 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5789 State.regs[dstreg2] += State.regs[srcreg2];
5790 State.regs[dstreg1] = result1;
5793 // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
5794 8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
5798 int dstreg1, dstreg2;
5802 dstreg1 = translate_rreg (SD_, RN1);
5803 dstreg2 = translate_rreg (SD_, RN2);
5805 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5806 State.regs[dstreg2] += EXTEND4 (IMM4);
5807 State.regs[dstreg1] = result1;
5810 // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
5811 8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
5815 int srcreg2, dstreg1, dstreg2;
5819 srcreg2 = translate_rreg (SD_, RM2);
5820 dstreg1 = translate_rreg (SD_, RN1);
5821 dstreg2 = translate_rreg (SD_, RN2);
5823 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5824 State.regs[dstreg2] -= State.regs[srcreg2];
5825 State.regs[dstreg1] = result1;
5828 // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
5829 8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
5833 int dstreg1, dstreg2;
5837 dstreg1 = translate_rreg (SD_, RN1);
5838 dstreg2 = translate_rreg (SD_, RN2);
5840 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5841 State.regs[dstreg2] -= EXTEND4 (IMM4);
5842 State.regs[dstreg1] = result1;
5845 // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
5846 8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
5850 int srcreg2, dstreg1, dstreg2;
5853 srcreg2 = translate_rreg (SD_, RM2);
5854 dstreg1 = translate_rreg (SD_, RN1);
5855 dstreg2 = translate_rreg (SD_, RN2);
5857 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5858 State.regs[dstreg1] += EXTEND4 (IMM4A);
5861 // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
5862 8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
5866 int dstreg1, dstreg2;
5869 dstreg1 = translate_rreg (SD_, RN1);
5870 dstreg2 = translate_rreg (SD_, RN2);
5872 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5873 State.regs[dstreg1] += EXTEND4 (IMM4A);
5876 // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
5877 8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
5881 int srcreg2, dstreg1, dstreg2;
5885 srcreg2 = translate_rreg (SD_, RM2);
5886 dstreg1 = translate_rreg (SD_, RN1);
5887 dstreg2 = translate_rreg (SD_, RN2);
5889 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5890 State.regs[dstreg2] = State.regs[srcreg2];
5891 State.regs[dstreg1] = result1;
5894 // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
5895 8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
5899 int dstreg1, dstreg2;
5903 dstreg1 = translate_rreg (SD_, RN1);
5904 dstreg2 = translate_rreg (SD_, RN2);
5906 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5907 State.regs[dstreg2] = EXTEND4 (IMM4);
5908 State.regs[dstreg1] = result1;
5911 // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
5912 8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
5916 int srcreg2, dstreg1, dstreg2;
5921 srcreg2 = translate_rreg (SD_, RM2);
5922 dstreg1 = translate_rreg (SD_, RN1);
5923 dstreg2 = translate_rreg (SD_, RN2);
5925 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5926 temp = State.regs[dstreg2];
5927 temp >>= State.regs[srcreg2];
5928 State.regs[dstreg2] = temp;
5929 State.regs[dstreg1] = result1;
5932 // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
5933 8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
5937 int dstreg1, dstreg2;
5942 dstreg1 = translate_rreg (SD_, RN1);
5943 dstreg2 = translate_rreg (SD_, RN2);
5945 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5946 temp = State.regs[dstreg2];
5948 State.regs[dstreg2] = temp;
5949 State.regs[dstreg1] = result1;
5952 // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
5953 8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
5957 int srcreg2, dstreg1, dstreg2;
5961 srcreg2 = translate_rreg (SD_, RM2);
5962 dstreg1 = translate_rreg (SD_, RN1);
5963 dstreg2 = translate_rreg (SD_, RN2);
5965 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5966 State.regs[dstreg2] >>= State.regs[srcreg2];
5967 State.regs[dstreg1] = result1;
5970 // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
5971 8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
5975 int dstreg1, dstreg2;
5980 dstreg1 = translate_rreg (SD_, RN1);
5981 dstreg2 = translate_rreg (SD_, RN2);
5983 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5984 State.regs[dstreg2] >>= IMM4;
5985 State.regs[dstreg1] = result1;
5989 // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
5990 8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
5994 int srcreg2, dstreg1, dstreg2;
5998 srcreg2 = translate_rreg (SD_, RM2);
5999 dstreg1 = translate_rreg (SD_, RN1);
6000 dstreg2 = translate_rreg (SD_, RN2);
6002 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
6003 State.regs[dstreg2] <<= State.regs[srcreg2];
6004 State.regs[dstreg1] = result1;
6007 // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
6008 8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
6012 int dstreg1, dstreg2;
6017 dstreg1 = translate_rreg (SD_, RN1);
6018 dstreg2 = translate_rreg (SD_, RN2);
6020 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
6021 State.regs[dstreg2] <<= IMM4;
6022 State.regs[dstreg1] = result1;
6025 // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
6026 8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
6030 int srcreg2, dstreg1, dstreg2;
6033 srcreg2 = translate_rreg (SD_, RM2);
6034 dstreg1 = translate_rreg (SD_, RN1);
6035 dstreg2 = translate_rreg (SD_, RN2);
6037 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6038 State.regs[dstreg2] += State.regs[srcreg2];
6041 // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
6042 8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
6046 int dstreg1, dstreg2;
6049 dstreg1 = translate_rreg (SD_, RN1);
6050 dstreg2 = translate_rreg (SD_, RN2);
6052 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6053 State.regs[dstreg2] += EXTEND4 (IMM4);
6056 // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
6057 8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
6061 int srcreg2, dstreg1, dstreg2;
6064 srcreg2 = translate_rreg (SD_, RM2);
6065 dstreg1 = translate_rreg (SD_, RN1);
6066 dstreg2 = translate_rreg (SD_, RN2);
6068 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6069 State.regs[dstreg2] -= State.regs[srcreg2];
6072 // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
6073 8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
6077 int dstreg1, dstreg2;
6080 dstreg1 = translate_rreg (SD_, RN1);
6081 dstreg2 = translate_rreg (SD_, RN2);
6083 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6084 State.regs[dstreg2] -= EXTEND4 (IMM4);
6087 // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
6088 8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
6092 int srcreg2, dstreg1, dstreg2;
6095 srcreg2 = translate_rreg (SD_, RM2);
6096 dstreg1 = translate_rreg (SD_, RN1);
6097 dstreg2 = translate_rreg (SD_, RN2);
6099 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6100 State.regs[dstreg2] = State.regs[srcreg2];
6103 // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
6104 8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
6108 int dstreg1, dstreg2;
6111 dstreg1 = translate_rreg (SD_, RN1);
6112 dstreg2 = translate_rreg (SD_, RN2);
6114 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6115 State.regs[dstreg2] = EXTEND4 (IMM4);
6118 // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
6119 8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
6123 int srcreg2, dstreg1, dstreg2;
6127 srcreg2 = translate_rreg (SD_, RM2);
6128 dstreg1 = translate_rreg (SD_, RN1);
6129 dstreg2 = translate_rreg (SD_, RN2);
6131 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6132 temp = State.regs[dstreg2];
6133 temp >>= State.regs[srcreg2];
6134 State.regs[dstreg2] = temp;
6137 // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
6138 8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
6142 int dstreg1, dstreg2;
6146 dstreg1 = translate_rreg (SD_, RN1);
6147 dstreg2 = translate_rreg (SD_, RN2);
6149 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6150 temp = State.regs[dstreg2];
6152 State.regs[dstreg2] = temp;
6155 // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
6156 8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
6160 int srcreg2, dstreg1, dstreg2;
6163 srcreg2 = translate_rreg (SD_, RM2);
6164 dstreg1 = translate_rreg (SD_, RN1);
6165 dstreg2 = translate_rreg (SD_, RN2);
6167 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6168 State.regs[dstreg2] >>= State.regs[srcreg2];
6171 // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
6172 8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
6176 int dstreg1, dstreg2;
6180 dstreg1 = translate_rreg (SD_, RN1);
6181 dstreg2 = translate_rreg (SD_, RN2);
6183 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6184 State.regs[dstreg2] >>= IMM4;
6188 // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
6189 8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
6193 int srcreg2, dstreg1, dstreg2;
6196 srcreg2 = translate_rreg (SD_, RM2);
6197 dstreg1 = translate_rreg (SD_, RN1);
6198 dstreg2 = translate_rreg (SD_, RN2);
6200 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6201 State.regs[dstreg2] <<= State.regs[srcreg2];
6204 // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
6205 8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
6209 int dstreg1, dstreg2;
6213 dstreg1 = translate_rreg (SD_, RN1);
6214 dstreg2 = translate_rreg (SD_, RN2);
6216 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6217 State.regs[dstreg2] <<= IMM4;
6220 // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
6221 8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
6225 int srcreg2, dstreg1, dstreg2;
6229 srcreg2 = translate_rreg (SD_, RM2);
6230 dstreg1 = translate_rreg (SD_, RN1);
6231 dstreg2 = translate_rreg (SD_, RN2);
6233 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6234 State.regs[dstreg2] += State.regs[srcreg2];
6235 State.regs[dstreg1] = result1;
6238 // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
6239 8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
6243 int dstreg1, dstreg2;
6247 dstreg1 = translate_rreg (SD_, RN1);
6248 dstreg2 = translate_rreg (SD_, RN2);
6250 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6251 State.regs[dstreg2] += EXTEND4 (IMM4);
6252 State.regs[dstreg1] = result1;
6255 // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
6256 8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
6260 int srcreg2, dstreg1, dstreg2;
6264 srcreg2 = translate_rreg (SD_, RM2);
6265 dstreg1 = translate_rreg (SD_, RN1);
6266 dstreg2 = translate_rreg (SD_, RN2);
6268 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6269 State.regs[dstreg2] -= State.regs[srcreg2];
6270 State.regs[dstreg1] = result1;
6273 // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
6274 8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
6278 int dstreg1, dstreg2;
6282 dstreg1 = translate_rreg (SD_, RN1);
6283 dstreg2 = translate_rreg (SD_, RN2);
6285 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6286 State.regs[dstreg2] -= EXTEND4 (IMM4);
6287 State.regs[dstreg1] = result1;
6290 // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
6291 8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
6295 int srcreg2, dstreg1, dstreg2;
6299 srcreg2 = translate_rreg (SD_, RM2);
6300 dstreg1 = translate_rreg (SD_, RN1);
6301 dstreg2 = translate_rreg (SD_, RN2);
6303 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6304 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6307 // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
6308 8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
6312 int dstreg1, dstreg2;
6316 dstreg1 = translate_rreg (SD_, RN1);
6317 dstreg2 = translate_rreg (SD_, RN2);
6319 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6320 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6323 // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
6324 8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
6328 int srcreg2, dstreg1, dstreg2;
6332 srcreg2 = translate_rreg (SD_, RM2);
6333 dstreg1 = translate_rreg (SD_, RN1);
6334 dstreg2 = translate_rreg (SD_, RN2);
6336 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6337 State.regs[dstreg2] = State.regs[srcreg2];
6338 State.regs[dstreg1] = result1;
6341 // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
6342 8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
6346 int dstreg1, dstreg2;
6350 dstreg1 = translate_rreg (SD_, RN1);
6351 dstreg2 = translate_rreg (SD_, RN2);
6353 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6354 State.regs[dstreg2] = EXTEND4 (IMM4);
6355 State.regs[dstreg1] = result1;
6358 // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
6359 8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
6363 int srcreg2, dstreg1, dstreg2;
6368 srcreg2 = translate_rreg (SD_, RM2);
6369 dstreg1 = translate_rreg (SD_, RN1);
6370 dstreg2 = translate_rreg (SD_, RN2);
6372 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6373 temp = State.regs[dstreg2];
6374 temp >>= State.regs[srcreg2];
6375 State.regs[dstreg2] = temp;
6376 State.regs[dstreg1] = result1;
6379 // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
6380 8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
6384 int dstreg1, dstreg2;
6389 dstreg1 = translate_rreg (SD_, RN1);
6390 dstreg2 = translate_rreg (SD_, RN2);
6392 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6393 temp = State.regs[dstreg2];
6395 State.regs[dstreg2] = temp;
6396 State.regs[dstreg1] = result1;
6399 // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
6400 8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
6404 int srcreg2, dstreg1, dstreg2;
6408 srcreg2 = translate_rreg (SD_, RM2);
6409 dstreg1 = translate_rreg (SD_, RN1);
6410 dstreg2 = translate_rreg (SD_, RN2);
6412 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6413 State.regs[dstreg2] >>= State.regs[srcreg2];
6414 State.regs[dstreg1] = result1;
6417 // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
6418 8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
6422 int dstreg1, dstreg2;
6427 dstreg1 = translate_rreg (SD_, RN1);
6428 dstreg2 = translate_rreg (SD_, RN2);
6430 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6431 State.regs[dstreg2] >>= IMM4;
6432 State.regs[dstreg1] = result1;
6436 // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
6437 8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
6441 int srcreg2, dstreg1, dstreg2;
6445 srcreg2 = translate_rreg (SD_, RM2);
6446 dstreg1 = translate_rreg (SD_, RN1);
6447 dstreg2 = translate_rreg (SD_, RN2);
6449 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6450 State.regs[dstreg2] <<= State.regs[srcreg2];
6451 State.regs[dstreg1] = result1;
6454 // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
6455 8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
6459 int dstreg1, dstreg2;
6464 dstreg1 = translate_rreg (SD_, RN1);
6465 dstreg2 = translate_rreg (SD_, RN2);
6467 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6468 State.regs[dstreg2] <<= IMM4;
6469 State.regs[dstreg1] = result1;
6472 // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
6473 8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
6477 int srcreg2, dstreg1, dstreg2;
6481 srcreg2 = translate_rreg (SD_, RM2);
6482 dstreg1 = translate_rreg (SD_, RN1);
6483 dstreg2 = translate_rreg (SD_, RN2);
6485 result1 = EXTEND4 (IMM4A);
6486 State.regs[dstreg2] += State.regs[srcreg2];
6487 State.regs[dstreg1] = result1;
6490 // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
6491 8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
6495 int dstreg1, dstreg2;
6499 dstreg1 = translate_rreg (SD_, RN1);
6500 dstreg2 = translate_rreg (SD_, RN2);
6502 result1 = EXTEND4 (IMM4A);
6503 State.regs[dstreg2] += EXTEND4 (IMM4);
6504 State.regs[dstreg1] = result1;
6507 // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
6508 8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
6512 int srcreg2, dstreg1, dstreg2;
6516 srcreg2 = translate_rreg (SD_, RM2);
6517 dstreg1 = translate_rreg (SD_, RN1);
6518 dstreg2 = translate_rreg (SD_, RN2);
6520 result1 = EXTEND4 (IMM4A);
6521 State.regs[dstreg2] -= State.regs[srcreg2];
6522 State.regs[dstreg1] = result1;
6525 // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
6526 8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
6530 int dstreg1, dstreg2;
6534 dstreg1 = translate_rreg (SD_, RN1);
6535 dstreg2 = translate_rreg (SD_, RN2);
6537 result1 = EXTEND4 (IMM4A);
6538 State.regs[dstreg2] -= EXTEND4 (IMM4);
6539 State.regs[dstreg1] = result1;
6542 // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
6543 8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
6547 int srcreg2, dstreg1, dstreg2;
6550 srcreg2 = translate_rreg (SD_, RM2);
6551 dstreg1 = translate_rreg (SD_, RN1);
6552 dstreg2 = translate_rreg (SD_, RN2);
6554 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6555 State.regs[dstreg1] = EXTEND4 (IMM4A);
6558 // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
6559 8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
6563 int dstreg1, dstreg2;
6566 dstreg1 = translate_rreg (SD_, RN1);
6567 dstreg2 = translate_rreg (SD_, RN2);
6569 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6570 State.regs[dstreg1] = EXTEND4 (IMM4A);
6573 // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
6574 8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
6578 int srcreg2, dstreg1, dstreg2;
6582 srcreg2 = translate_rreg (SD_, RM2);
6583 dstreg1 = translate_rreg (SD_, RN1);
6584 dstreg2 = translate_rreg (SD_, RN2);
6586 result1 = EXTEND4 (IMM4A);
6587 State.regs[dstreg2] = State.regs[srcreg2];
6588 State.regs[dstreg1] = result1;
6591 // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
6592 8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
6596 int dstreg1, dstreg2;
6600 dstreg1 = translate_rreg (SD_, RN1);
6601 dstreg2 = translate_rreg (SD_, RN2);
6603 result1 = EXTEND4 (IMM4A);
6604 State.regs[dstreg2] = EXTEND4 (IMM4);
6605 State.regs[dstreg1] = result1;
6608 // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
6609 8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
6613 int srcreg2, dstreg1, dstreg2;
6618 srcreg2 = translate_rreg (SD_, RM2);
6619 dstreg1 = translate_rreg (SD_, RN1);
6620 dstreg2 = translate_rreg (SD_, RN2);
6622 result1 = EXTEND4 (IMM4A);
6623 temp = State.regs[dstreg2];
6624 temp >>= State.regs[srcreg2];
6625 State.regs[dstreg2] = temp;
6626 State.regs[dstreg1] = result1;
6629 // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
6630 8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
6634 int dstreg1, dstreg2;
6639 dstreg1 = translate_rreg (SD_, RN1);
6640 dstreg2 = translate_rreg (SD_, RN2);
6642 result1 = EXTEND4 (IMM4A);
6643 temp = State.regs[dstreg2];
6645 State.regs[dstreg2] = temp;
6646 State.regs[dstreg1] = result1;
6649 // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
6650 8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
6654 int srcreg2, dstreg1, dstreg2;
6658 srcreg2 = translate_rreg (SD_, RM2);
6659 dstreg1 = translate_rreg (SD_, RN1);
6660 dstreg2 = translate_rreg (SD_, RN2);
6662 result1 = EXTEND4 (IMM4A);
6663 State.regs[dstreg2] >>= State.regs[srcreg2];
6664 State.regs[dstreg1] = result1;
6667 // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
6668 8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
6672 int dstreg1, dstreg2;
6677 dstreg1 = translate_rreg (SD_, RN1);
6678 dstreg2 = translate_rreg (SD_, RN2);
6680 result1 = EXTEND4 (IMM4A);
6681 State.regs[dstreg2] >>= IMM4;
6682 State.regs[dstreg1] = result1;
6686 // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
6687 8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
6691 int srcreg2, dstreg1, dstreg2;
6695 srcreg2 = translate_rreg (SD_, RM2);
6696 dstreg1 = translate_rreg (SD_, RN1);
6697 dstreg2 = translate_rreg (SD_, RN2);
6699 result1 = EXTEND4 (IMM4A);
6700 State.regs[dstreg2] <<= State.regs[srcreg2];
6701 State.regs[dstreg1] = result1;
6704 // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
6705 8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
6709 int dstreg1, dstreg2;
6714 dstreg1 = translate_rreg (SD_, RN1);
6715 dstreg2 = translate_rreg (SD_, RN2);
6717 result1 = EXTEND4 (IMM4A);
6718 State.regs[dstreg2] <<= IMM4;
6719 State.regs[dstreg1] = result1;
6722 // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
6723 8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
6727 int srcreg1, srcreg2, dstreg1, dstreg2;
6731 srcreg1 = translate_rreg (SD_, RM1);
6732 srcreg2 = translate_rreg (SD_, RM2);
6733 dstreg1 = translate_rreg (SD_, RN1);
6734 dstreg2 = translate_rreg (SD_, RN2);
6736 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6737 State.regs[dstreg2] += State.regs[srcreg2];
6738 State.regs[dstreg1] = result1;
6741 // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
6742 8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
6746 int srcreg1, dstreg1, dstreg2;
6750 srcreg1 = translate_rreg (SD_, RM1);
6751 dstreg1 = translate_rreg (SD_, RN1);
6752 dstreg2 = translate_rreg (SD_, RN2);
6754 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6755 State.regs[dstreg2] += EXTEND4 (IMM4);
6756 State.regs[dstreg1] = result1;
6759 // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
6760 8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
6764 int srcreg1, srcreg2, dstreg1, dstreg2;
6768 srcreg1 = translate_rreg (SD_, RM1);
6769 srcreg2 = translate_rreg (SD_, RM2);
6770 dstreg1 = translate_rreg (SD_, RN1);
6771 dstreg2 = translate_rreg (SD_, RN2);
6773 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6774 State.regs[dstreg2] -= State.regs[srcreg2];
6775 State.regs[dstreg1] = result1;
6778 // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
6779 8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
6783 int srcreg1, dstreg1, dstreg2;
6787 srcreg1 = translate_rreg (SD_, RM1);
6788 dstreg1 = translate_rreg (SD_, RN1);
6789 dstreg2 = translate_rreg (SD_, RN2);
6791 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6792 State.regs[dstreg2] -= EXTEND4 (IMM4);
6793 State.regs[dstreg1] = result1;
6796 // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
6797 8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
6801 int srcreg1, srcreg2, dstreg1, dstreg2;
6804 srcreg1 = translate_rreg (SD_, RM1);
6805 srcreg2 = translate_rreg (SD_, RM2);
6806 dstreg1 = translate_rreg (SD_, RN1);
6807 dstreg2 = translate_rreg (SD_, RN2);
6809 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6810 State.regs[dstreg1] &= State.regs[srcreg1];
6813 // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
6814 8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
6818 int srcreg1, dstreg1, dstreg2;
6821 srcreg1 = translate_rreg (SD_, RM1);
6822 dstreg1 = translate_rreg (SD_, RN1);
6823 dstreg2 = translate_rreg (SD_, RN2);
6825 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6826 State.regs[dstreg1] &= State.regs[srcreg1];
6829 // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
6830 8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
6834 int srcreg1, srcreg2, dstreg1, dstreg2;
6838 srcreg1 = translate_rreg (SD_, RM1);
6839 srcreg2 = translate_rreg (SD_, RM2);
6840 dstreg1 = translate_rreg (SD_, RN1);
6841 dstreg2 = translate_rreg (SD_, RN2);
6843 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6844 State.regs[dstreg2] = State.regs[srcreg2];
6845 State.regs[dstreg1] = result1;
6848 // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
6849 8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
6853 int srcreg1, dstreg1, dstreg2;
6857 srcreg1 = translate_rreg (SD_, RM1);
6858 dstreg1 = translate_rreg (SD_, RN1);
6859 dstreg2 = translate_rreg (SD_, RN2);
6861 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6862 State.regs[dstreg2] = EXTEND4 (IMM4);
6863 State.regs[dstreg1] = result1;
6866 // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
6867 8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
6871 int srcreg1, srcreg2, dstreg1, dstreg2;
6876 srcreg1 = translate_rreg (SD_, RM1);
6877 srcreg2 = translate_rreg (SD_, RM2);
6878 dstreg1 = translate_rreg (SD_, RN1);
6879 dstreg2 = translate_rreg (SD_, RN2);
6881 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6882 temp = State.regs[dstreg2];
6883 temp >>= State.regs[srcreg2];
6884 State.regs[dstreg2] = temp;
6885 State.regs[dstreg1] = result1;
6888 // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
6889 8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
6893 int srcreg1, dstreg1, dstreg2;
6898 srcreg1 = translate_rreg (SD_, RM1);
6899 dstreg1 = translate_rreg (SD_, RN1);
6900 dstreg2 = translate_rreg (SD_, RN2);
6902 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6903 temp = State.regs[dstreg2];
6905 State.regs[dstreg2] = temp;
6906 State.regs[dstreg1] = result1;
6909 // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
6910 8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
6914 int srcreg1, srcreg2, dstreg1, dstreg2;
6918 srcreg1 = translate_rreg (SD_, RM1);
6919 srcreg2 = translate_rreg (SD_, RM2);
6920 dstreg1 = translate_rreg (SD_, RN1);
6921 dstreg2 = translate_rreg (SD_, RN2);
6923 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6924 State.regs[dstreg2] >>= State.regs[srcreg2];
6925 State.regs[dstreg1] = result1;
6928 // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
6929 8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
6933 int srcreg1, dstreg1, dstreg2;
6938 srcreg1 = translate_rreg (SD_, RM1);
6939 dstreg1 = translate_rreg (SD_, RN1);
6940 dstreg2 = translate_rreg (SD_, RN2);
6942 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6943 State.regs[dstreg2] >>= IMM4;
6944 State.regs[dstreg1] = result1;
6948 // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
6949 8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
6953 int srcreg1, srcreg2, dstreg1, dstreg2;
6957 srcreg1 = translate_rreg (SD_, RM1);
6958 srcreg2 = translate_rreg (SD_, RM2);
6959 dstreg1 = translate_rreg (SD_, RN1);
6960 dstreg2 = translate_rreg (SD_, RN2);
6962 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6963 State.regs[dstreg2] <<= State.regs[srcreg2];
6964 State.regs[dstreg1] = result1;
6967 // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
6968 8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
6972 int srcreg1, dstreg1, dstreg2;
6977 srcreg1 = translate_rreg (SD_, RM1);
6978 dstreg1 = translate_rreg (SD_, RN1);
6979 dstreg2 = translate_rreg (SD_, RN2);
6981 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6982 State.regs[dstreg2] <<= IMM4;
6983 State.regs[dstreg1] = result1;
6986 // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
6987 8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
6991 int srcreg1, srcreg2, dstreg1, dstreg2;
6992 signed32 temp, temp2, sum;
6995 srcreg1 = translate_rreg (SD_, RM1);
6996 srcreg2 = translate_rreg (SD_, RM2);
6997 dstreg1 = translate_rreg (SD_, RN1);
6998 dstreg2 = translate_rreg (SD_, RN2);
7000 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7001 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7002 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7003 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7004 sum = temp + temp2 + State.regs[REG_MCRL];
7006 State.regs[dstreg2] += State.regs[srcreg2];
7007 State.regs[dstreg1] = sum;
7010 // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
7011 8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
7015 int srcreg1, dstreg1, dstreg2;
7016 signed32 temp, temp2, sum;
7019 srcreg1 = translate_rreg (SD_, RM1);
7020 dstreg1 = translate_rreg (SD_, RN1);
7021 dstreg2 = translate_rreg (SD_, RN2);
7023 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7024 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7025 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7026 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7027 sum = temp + temp2 + State.regs[REG_MCRL];
7029 State.regs[dstreg2] += EXTEND4 (IMM4);
7030 State.regs[dstreg1] = sum;
7033 // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
7034 8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
7038 int srcreg1, srcreg2, dstreg1, dstreg2;
7039 signed32 temp, temp2, sum;
7042 srcreg1 = translate_rreg (SD_, RM1);
7043 srcreg2 = translate_rreg (SD_, RM2);
7044 dstreg1 = translate_rreg (SD_, RN1);
7045 dstreg2 = translate_rreg (SD_, RN2);
7047 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7048 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7049 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7050 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7051 sum = temp + temp2 + State.regs[REG_MCRL];
7053 State.regs[dstreg2] -= State.regs[srcreg2];
7054 State.regs[dstreg1] = sum;
7057 // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
7058 8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
7062 int srcreg1, dstreg1, dstreg2;
7063 signed32 temp, temp2, sum;
7066 srcreg1 = translate_rreg (SD_, RM1);
7067 dstreg1 = translate_rreg (SD_, RN1);
7068 dstreg2 = translate_rreg (SD_, RN2);
7070 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7071 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7072 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7073 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7074 sum = temp + temp2 + State.regs[REG_MCRL];
7076 State.regs[dstreg2] -= EXTEND4 (IMM4);
7077 State.regs[dstreg1] = sum;
7080 // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
7081 8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
7085 int srcreg1, srcreg2, dstreg1, dstreg2;
7086 signed32 temp, temp2, sum;
7089 srcreg1 = translate_rreg (SD_, RM1);
7090 srcreg2 = translate_rreg (SD_, RM2);
7091 dstreg1 = translate_rreg (SD_, RN1);
7092 dstreg2 = translate_rreg (SD_, RN2);
7094 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7095 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7096 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7097 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7098 sum = temp + temp2 + State.regs[REG_MCRL];
7100 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7101 State.regs[dstreg1] = sum;
7104 // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
7105 8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
7109 int srcreg1, dstreg1, dstreg2;
7110 signed32 temp, temp2, sum;
7113 srcreg1 = translate_rreg (SD_, RM1);
7114 dstreg1 = translate_rreg (SD_, RN1);
7115 dstreg2 = translate_rreg (SD_, RN2);
7117 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7118 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7119 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7120 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7121 sum = temp + temp2 + State.regs[REG_MCRL];
7123 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7124 State.regs[dstreg1] = sum;
7127 // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
7128 8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
7132 int srcreg1, srcreg2, dstreg1, dstreg2;
7133 signed32 temp, temp2, sum;
7136 srcreg1 = translate_rreg (SD_, RM1);
7137 srcreg2 = translate_rreg (SD_, RM2);
7138 dstreg1 = translate_rreg (SD_, RN1);
7139 dstreg2 = translate_rreg (SD_, RN2);
7141 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7142 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7143 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7144 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7145 sum = temp + temp2 + State.regs[REG_MCRL];
7147 State.regs[dstreg2] = State.regs[srcreg2];
7148 State.regs[dstreg1] = sum;
7151 // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
7152 8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
7156 int srcreg1, dstreg1, dstreg2;
7157 signed32 temp, temp2, sum;
7160 srcreg1 = translate_rreg (SD_, RM1);
7161 dstreg1 = translate_rreg (SD_, RN1);
7162 dstreg2 = translate_rreg (SD_, RN2);
7164 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7165 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7166 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7167 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7168 sum = temp + temp2 + State.regs[REG_MCRL];
7170 State.regs[dstreg2] = EXTEND4 (IMM4);
7171 State.regs[dstreg1] = sum;
7174 // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
7175 8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
7179 int srcreg1, srcreg2, dstreg1, dstreg2;
7180 signed32 temp, temp2, sum;
7183 srcreg1 = translate_rreg (SD_, RM1);
7184 srcreg2 = translate_rreg (SD_, RM2);
7185 dstreg1 = translate_rreg (SD_, RN1);
7186 dstreg2 = translate_rreg (SD_, RN2);
7188 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7189 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7190 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7191 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7192 sum = temp + temp2 + State.regs[REG_MCRL];
7194 temp = State.regs[dstreg2];
7195 temp >>= State.regs[srcreg2];
7196 State.regs[dstreg2] = temp;
7197 State.regs[dstreg1] = sum;
7200 // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
7201 8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
7205 int srcreg1, dstreg1, dstreg2;
7206 signed32 temp, temp2, sum;
7209 srcreg1 = translate_rreg (SD_, RM1);
7210 dstreg1 = translate_rreg (SD_, RN1);
7211 dstreg2 = translate_rreg (SD_, RN2);
7213 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7214 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7215 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7216 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7217 sum = temp + temp2 + State.regs[REG_MCRL];
7219 temp = State.regs[dstreg2];
7221 State.regs[dstreg2] = temp;
7222 State.regs[dstreg1] = sum;
7225 // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
7226 8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
7230 int srcreg1, srcreg2, dstreg1, dstreg2;
7231 signed32 temp, temp2, sum;
7234 srcreg1 = translate_rreg (SD_, RM1);
7235 srcreg2 = translate_rreg (SD_, RM2);
7236 dstreg1 = translate_rreg (SD_, RN1);
7237 dstreg2 = translate_rreg (SD_, RN2);
7239 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7240 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7241 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7242 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7243 sum = temp + temp2 + State.regs[REG_MCRL];
7245 State.regs[dstreg2] >>= State.regs[srcreg2];
7246 State.regs[dstreg1] = sum;
7249 // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
7250 8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
7254 int srcreg1, dstreg1, dstreg2;
7255 signed32 temp, temp2, sum;
7258 srcreg1 = translate_rreg (SD_, RM1);
7259 dstreg1 = translate_rreg (SD_, RN1);
7260 dstreg2 = translate_rreg (SD_, RN2);
7262 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7263 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7264 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7265 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7266 sum = temp + temp2 + State.regs[REG_MCRL];
7268 State.regs[dstreg2] >>= IMM4;
7269 State.regs[dstreg1] = sum;
7273 // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
7274 8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
7278 int srcreg1, srcreg2, dstreg1, dstreg2;
7279 signed32 temp, temp2, sum;
7282 srcreg1 = translate_rreg (SD_, RM1);
7283 srcreg2 = translate_rreg (SD_, RM2);
7284 dstreg1 = translate_rreg (SD_, RN1);
7285 dstreg2 = translate_rreg (SD_, RN2);
7287 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7288 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7289 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7290 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7291 sum = temp + temp2 + State.regs[REG_MCRL];
7293 State.regs[dstreg2] <<= State.regs[srcreg2];
7294 State.regs[dstreg1] = sum;
7297 // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
7298 8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
7302 int srcreg1, dstreg1, dstreg2;
7303 signed32 temp, temp2, sum;
7306 srcreg1 = translate_rreg (SD_, RM1);
7307 dstreg1 = translate_rreg (SD_, RN1);
7308 dstreg2 = translate_rreg (SD_, RN2);
7310 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7311 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7312 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7313 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7314 sum = temp + temp2 + State.regs[REG_MCRL];
7316 State.regs[dstreg2] <<= IMM4;
7317 State.regs[dstreg1] = sum;
7320 // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
7321 8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
7325 int srcreg1, srcreg2, dstreg1, dstreg2;
7329 srcreg1 = translate_rreg (SD_, RM1);
7330 srcreg2 = translate_rreg (SD_, RM2);
7331 dstreg1 = translate_rreg (SD_, RN1);
7332 dstreg2 = translate_rreg (SD_, RN2);
7334 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7335 State.regs[dstreg2] += State.regs[srcreg2];
7336 State.regs[dstreg1] = result1;
7339 // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
7340 8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
7344 int srcreg1, dstreg1, dstreg2;
7348 srcreg1 = translate_rreg (SD_, RM1);
7349 dstreg1 = translate_rreg (SD_, RN1);
7350 dstreg2 = translate_rreg (SD_, RN2);
7352 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7353 State.regs[dstreg2] += EXTEND4 (IMM4);
7354 State.regs[dstreg1] = result1;
7357 // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
7358 8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
7362 int srcreg1, srcreg2, dstreg1, dstreg2;
7366 srcreg1 = translate_rreg (SD_, RM1);
7367 srcreg2 = translate_rreg (SD_, RM2);
7368 dstreg1 = translate_rreg (SD_, RN1);
7369 dstreg2 = translate_rreg (SD_, RN2);
7371 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7372 State.regs[dstreg2] -= State.regs[srcreg2];
7373 State.regs[dstreg1] = result1;
7376 // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
7377 8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
7381 int srcreg1, dstreg1, dstreg2;
7385 srcreg1 = translate_rreg (SD_, RM1);
7386 dstreg1 = translate_rreg (SD_, RN1);
7387 dstreg2 = translate_rreg (SD_, RN2);
7389 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7390 State.regs[dstreg2] -= EXTEND4 (IMM4);
7391 State.regs[dstreg1] = result1;
7394 // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
7395 8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
7399 int srcreg1, srcreg2, dstreg1, dstreg2;
7402 srcreg1 = translate_rreg (SD_, RM1);
7403 srcreg2 = translate_rreg (SD_, RM2);
7404 dstreg1 = translate_rreg (SD_, RN1);
7405 dstreg2 = translate_rreg (SD_, RN2);
7407 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7408 State.regs[dstreg1] ^= State.regs[srcreg1];
7411 // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
7412 8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
7416 int srcreg1, dstreg1, dstreg2;
7419 srcreg1 = translate_rreg (SD_, RM1);
7420 dstreg1 = translate_rreg (SD_, RN1);
7421 dstreg2 = translate_rreg (SD_, RN2);
7423 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7424 State.regs[dstreg1] ^= State.regs[srcreg1];
7427 // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
7428 8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
7432 int srcreg1, srcreg2, dstreg1, dstreg2;
7436 srcreg1 = translate_rreg (SD_, RM1);
7437 srcreg2 = translate_rreg (SD_, RM2);
7438 dstreg1 = translate_rreg (SD_, RN1);
7439 dstreg2 = translate_rreg (SD_, RN2);
7441 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7442 State.regs[dstreg2] = State.regs[srcreg2];
7443 State.regs[dstreg1] = result1;
7446 // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
7447 8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
7451 int srcreg1, dstreg1, dstreg2;
7455 srcreg1 = translate_rreg (SD_, RM1);
7456 dstreg1 = translate_rreg (SD_, RN1);
7457 dstreg2 = translate_rreg (SD_, RN2);
7459 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7460 State.regs[dstreg2] = EXTEND4 (IMM4);
7461 State.regs[dstreg1] = result1;
7464 // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
7465 8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
7469 int srcreg1, srcreg2, dstreg1, dstreg2;
7474 srcreg1 = translate_rreg (SD_, RM1);
7475 srcreg2 = translate_rreg (SD_, RM2);
7476 dstreg1 = translate_rreg (SD_, RN1);
7477 dstreg2 = translate_rreg (SD_, RN2);
7479 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7480 temp = State.regs[dstreg2];
7481 temp >>= State.regs[srcreg2];
7482 State.regs[dstreg2] = temp;
7483 State.regs[dstreg1] = result1;
7486 // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
7487 8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
7491 int srcreg1, dstreg1, dstreg2;
7496 srcreg1 = translate_rreg (SD_, RM1);
7497 dstreg1 = translate_rreg (SD_, RN1);
7498 dstreg2 = translate_rreg (SD_, RN2);
7500 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7501 temp = State.regs[dstreg2];
7503 State.regs[dstreg2] = temp;
7504 State.regs[dstreg1] = result1;
7507 // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
7508 8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
7512 int srcreg1, srcreg2, dstreg1, dstreg2;
7516 srcreg1 = translate_rreg (SD_, RM1);
7517 srcreg2 = translate_rreg (SD_, RM2);
7518 dstreg1 = translate_rreg (SD_, RN1);
7519 dstreg2 = translate_rreg (SD_, RN2);
7521 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7522 State.regs[dstreg2] >>= State.regs[srcreg2];
7523 State.regs[dstreg1] = result1;
7526 // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
7527 8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
7531 int srcreg1, dstreg1, dstreg2;
7536 srcreg1 = translate_rreg (SD_, RM1);
7537 dstreg1 = translate_rreg (SD_, RN1);
7538 dstreg2 = translate_rreg (SD_, RN2);
7540 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7541 State.regs[dstreg2] >>= IMM4;
7542 State.regs[dstreg1] = result1;
7546 // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
7547 8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
7551 int srcreg1, srcreg2, dstreg1, dstreg2;
7555 srcreg1 = translate_rreg (SD_, RM1);
7556 srcreg2 = translate_rreg (SD_, RM2);
7557 dstreg1 = translate_rreg (SD_, RN1);
7558 dstreg2 = translate_rreg (SD_, RN2);
7560 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7561 State.regs[dstreg2] <<= State.regs[srcreg2];
7562 State.regs[dstreg1] = result1;
7565 // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
7566 8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
7570 int srcreg1, dstreg1, dstreg2;
7575 srcreg1 = translate_rreg (SD_, RM1);
7576 dstreg1 = translate_rreg (SD_, RN1);
7577 dstreg2 = translate_rreg (SD_, RN2);
7579 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7580 State.regs[dstreg2] <<= IMM4;
7581 State.regs[dstreg1] = result1;
7584 // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
7585 8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
7589 int srcreg1, srcreg2, dstreg1, dstreg2;
7593 srcreg1 = translate_rreg (SD_, RM1);
7594 srcreg2 = translate_rreg (SD_, RM2);
7595 dstreg1 = translate_rreg (SD_, RN1);
7596 dstreg2 = translate_rreg (SD_, RN2);
7598 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7599 State.regs[dstreg2] += State.regs[srcreg2];
7600 State.regs[dstreg1] = result1;
7603 // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
7604 8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
7608 int srcreg1, dstreg1, dstreg2;
7612 srcreg1 = translate_rreg (SD_, RM1);
7613 dstreg1 = translate_rreg (SD_, RN1);
7614 dstreg2 = translate_rreg (SD_, RN2);
7616 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7617 | ((State.regs[srcreg1] >> 16) & 0xffff));
7618 State.regs[dstreg2] += EXTEND4 (IMM4);
7619 State.regs[dstreg1] = result1;
7622 // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
7623 8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
7627 int srcreg1, srcreg2, dstreg1, dstreg2;
7631 srcreg1 = translate_rreg (SD_, RM1);
7632 srcreg2 = translate_rreg (SD_, RM2);
7633 dstreg1 = translate_rreg (SD_, RN1);
7634 dstreg2 = translate_rreg (SD_, RN2);
7636 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7637 | ((State.regs[srcreg1] >> 16) & 0xffff));
7638 State.regs[dstreg2] -= State.regs[srcreg2];
7639 State.regs[dstreg1] = result1;
7642 // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
7643 8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
7647 int srcreg1, dstreg1, dstreg2;
7651 srcreg1 = translate_rreg (SD_, RM1);
7652 dstreg1 = translate_rreg (SD_, RN1);
7653 dstreg2 = translate_rreg (SD_, RN2);
7655 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7656 | ((State.regs[srcreg1] >> 16) & 0xffff));
7657 State.regs[dstreg2] -= EXTEND4 (IMM4);
7658 State.regs[dstreg1] = result1;
7661 // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
7662 8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
7666 int srcreg1, srcreg2, dstreg1, dstreg2;
7669 srcreg1 = translate_rreg (SD_, RM1);
7670 srcreg2 = translate_rreg (SD_, RM2);
7671 dstreg1 = translate_rreg (SD_, RN1);
7672 dstreg2 = translate_rreg (SD_, RN2);
7674 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7675 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7676 | ((State.regs[srcreg1] >> 16) & 0xffff));
7679 // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
7680 8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
7684 int srcreg1, dstreg1, dstreg2;
7687 srcreg1 = translate_rreg (SD_, RM1);
7688 dstreg1 = translate_rreg (SD_, RN1);
7689 dstreg2 = translate_rreg (SD_, RN2);
7691 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7692 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7693 | ((State.regs[srcreg1] >> 16) & 0xffff));
7696 // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
7697 8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
7701 int srcreg1, srcreg2, dstreg1, dstreg2;
7705 srcreg1 = translate_rreg (SD_, RM1);
7706 srcreg2 = translate_rreg (SD_, RM2);
7707 dstreg1 = translate_rreg (SD_, RN1);
7708 dstreg2 = translate_rreg (SD_, RN2);
7710 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7711 | ((State.regs[srcreg1] >> 16) & 0xffff));
7712 State.regs[dstreg2] = State.regs[srcreg2];
7713 State.regs[dstreg1] = result1;
7716 // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
7717 8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
7721 int srcreg1, dstreg1, dstreg2;
7725 srcreg1 = translate_rreg (SD_, RM1);
7726 dstreg1 = translate_rreg (SD_, RN1);
7727 dstreg2 = translate_rreg (SD_, RN2);
7729 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7730 | ((State.regs[srcreg1] >> 16) & 0xffff));
7731 State.regs[dstreg2] = EXTEND4 (IMM4);
7732 State.regs[dstreg1] = result1;
7735 // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
7736 8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
7740 int srcreg1, srcreg2, dstreg1, dstreg2;
7745 srcreg1 = translate_rreg (SD_, RM1);
7746 srcreg2 = translate_rreg (SD_, RM2);
7747 dstreg1 = translate_rreg (SD_, RN1);
7748 dstreg2 = translate_rreg (SD_, RN2);
7750 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7751 | ((State.regs[srcreg1] >> 16) & 0xffff));
7752 temp = State.regs[dstreg2];
7753 temp >>= State.regs[srcreg2];
7754 State.regs[dstreg2] = temp;
7755 State.regs[dstreg1] = result1;
7758 // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
7759 8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
7763 int srcreg1, dstreg1, dstreg2;
7768 srcreg1 = translate_rreg (SD_, RM1);
7769 dstreg1 = translate_rreg (SD_, RN1);
7770 dstreg2 = translate_rreg (SD_, RN2);
7772 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7773 | ((State.regs[srcreg1] >> 16) & 0xffff));
7774 temp = State.regs[dstreg2];
7776 State.regs[dstreg2] = temp;
7777 State.regs[dstreg1] = result1;
7780 // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
7781 8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
7785 int srcreg1, srcreg2, dstreg1, dstreg2;
7789 srcreg1 = translate_rreg (SD_, RM1);
7790 srcreg2 = translate_rreg (SD_, RM2);
7791 dstreg1 = translate_rreg (SD_, RN1);
7792 dstreg2 = translate_rreg (SD_, RN2);
7794 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7795 | ((State.regs[srcreg1] >> 16) & 0xffff));
7796 State.regs[dstreg2] >>= State.regs[srcreg2];
7797 State.regs[dstreg1] = result1;
7800 // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
7801 8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
7805 int srcreg1, dstreg1, dstreg2;
7810 srcreg1 = translate_rreg (SD_, RM1);
7811 dstreg1 = translate_rreg (SD_, RN1);
7812 dstreg2 = translate_rreg (SD_, RN2);
7814 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7815 | ((State.regs[srcreg1] >> 16) & 0xffff));
7816 State.regs[dstreg2] >>= IMM4;
7817 State.regs[dstreg1] = result1;
7821 // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
7822 8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
7826 int srcreg1, srcreg2, dstreg1, dstreg2;
7830 srcreg1 = translate_rreg (SD_, RM1);
7831 srcreg2 = translate_rreg (SD_, RM2);
7832 dstreg1 = translate_rreg (SD_, RN1);
7833 dstreg2 = translate_rreg (SD_, RN2);
7835 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7836 | ((State.regs[srcreg1] >> 16) & 0xffff));
7837 State.regs[dstreg2] <<= State.regs[srcreg2];
7838 State.regs[dstreg1] = result1;
7841 // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
7842 8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
7846 int srcreg1, dstreg1, dstreg2;
7851 srcreg1 = translate_rreg (SD_, RM1);
7852 dstreg1 = translate_rreg (SD_, RN1);
7853 dstreg2 = translate_rreg (SD_, RN2);
7855 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7856 | ((State.regs[srcreg1] >> 16) & 0xffff));
7857 State.regs[dstreg2] <<= IMM4;
7858 State.regs[dstreg1] = result1;
7861 // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
7862 8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
7866 int srcreg1, srcreg2, dstreg1, dstreg2;
7870 srcreg1 = translate_rreg (SD_, RM1);
7871 srcreg2 = translate_rreg (SD_, RM2);
7872 dstreg1 = translate_rreg (SD_, RN1);
7873 dstreg2 = translate_rreg (SD_, RN2);
7875 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7876 State.regs[dstreg2] += State.regs[srcreg2];
7877 State.regs[dstreg1] = result1;
7880 // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
7881 8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
7885 int srcreg1, dstreg1, dstreg2;
7889 srcreg1 = translate_rreg (SD_, RM1);
7890 dstreg1 = translate_rreg (SD_, RN1);
7891 dstreg2 = translate_rreg (SD_, RN2);
7893 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7894 State.regs[dstreg2] += EXTEND4 (IMM4);
7895 State.regs[dstreg1] = result1;
7898 // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
7899 8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
7903 int srcreg1, srcreg2, dstreg1, dstreg2;
7907 srcreg1 = translate_rreg (SD_, RM1);
7908 srcreg2 = translate_rreg (SD_, RM2);
7909 dstreg1 = translate_rreg (SD_, RN1);
7910 dstreg2 = translate_rreg (SD_, RN2);
7912 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7913 State.regs[dstreg2] -= State.regs[srcreg2];
7914 State.regs[dstreg1] = result1;
7917 // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
7918 8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
7922 int srcreg1, dstreg1, dstreg2;
7926 srcreg1 = translate_rreg (SD_, RM1);
7927 dstreg1 = translate_rreg (SD_, RN1);
7928 dstreg2 = translate_rreg (SD_, RN2);
7930 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7931 State.regs[dstreg2] -= EXTEND4 (IMM4);
7932 State.regs[dstreg1] = result1;
7935 // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
7936 8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
7940 int srcreg1, srcreg2, dstreg1, dstreg2;
7943 srcreg1 = translate_rreg (SD_, RM1);
7944 srcreg2 = translate_rreg (SD_, RM2);
7945 dstreg1 = translate_rreg (SD_, RN1);
7946 dstreg2 = translate_rreg (SD_, RN2);
7948 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7949 State.regs[dstreg1] |= State.regs[srcreg1];
7952 // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
7953 8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
7957 int srcreg1, dstreg1, dstreg2;
7960 srcreg1 = translate_rreg (SD_, RM1);
7961 dstreg1 = translate_rreg (SD_, RN1);
7962 dstreg2 = translate_rreg (SD_, RN2);
7964 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7965 State.regs[dstreg1] |= State.regs[srcreg1];
7968 // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
7969 8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
7973 int srcreg1, srcreg2, dstreg1, dstreg2;
7977 srcreg1 = translate_rreg (SD_, RM1);
7978 srcreg2 = translate_rreg (SD_, RM2);
7979 dstreg1 = translate_rreg (SD_, RN1);
7980 dstreg2 = translate_rreg (SD_, RN2);
7982 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7983 State.regs[dstreg2] = State.regs[srcreg2];
7984 State.regs[dstreg1] = result1;
7987 // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
7988 8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
7992 int srcreg1, dstreg1, dstreg2;
7996 srcreg1 = translate_rreg (SD_, RM1);
7997 dstreg1 = translate_rreg (SD_, RN1);
7998 dstreg2 = translate_rreg (SD_, RN2);
8000 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8001 State.regs[dstreg2] = EXTEND4 (IMM4);
8002 State.regs[dstreg1] = result1;
8005 // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
8006 8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
8010 int srcreg1, srcreg2, dstreg1, dstreg2;
8015 srcreg1 = translate_rreg (SD_, RM1);
8016 srcreg2 = translate_rreg (SD_, RM2);
8017 dstreg1 = translate_rreg (SD_, RN1);
8018 dstreg2 = translate_rreg (SD_, RN2);
8020 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8021 temp = State.regs[dstreg2];
8022 temp >>= State.regs[srcreg2];
8023 State.regs[dstreg2] = temp;
8024 State.regs[dstreg1] = result1;
8027 // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
8028 8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
8032 int srcreg1, dstreg1, dstreg2;
8037 srcreg1 = translate_rreg (SD_, RM1);
8038 dstreg1 = translate_rreg (SD_, RN1);
8039 dstreg2 = translate_rreg (SD_, RN2);
8041 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8042 temp = State.regs[dstreg2];
8044 State.regs[dstreg2] = temp;
8045 State.regs[dstreg1] = result1;
8048 // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
8049 8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
8053 int srcreg1, srcreg2, dstreg1, dstreg2;
8057 srcreg1 = translate_rreg (SD_, RM1);
8058 srcreg2 = translate_rreg (SD_, RM2);
8059 dstreg1 = translate_rreg (SD_, RN1);
8060 dstreg2 = translate_rreg (SD_, RN2);
8062 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8063 State.regs[dstreg2] >>= State.regs[srcreg2];
8064 State.regs[dstreg1] = result1;
8067 // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
8068 8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
8072 int srcreg1, dstreg1, dstreg2;
8077 srcreg1 = translate_rreg (SD_, RM1);
8078 dstreg1 = translate_rreg (SD_, RN1);
8079 dstreg2 = translate_rreg (SD_, RN2);
8081 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8082 State.regs[dstreg2] >>= IMM4;
8083 State.regs[dstreg1] = result1;
8087 // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
8088 8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
8092 int srcreg1, srcreg2, dstreg1, dstreg2;
8096 srcreg1 = translate_rreg (SD_, RM1);
8097 srcreg2 = translate_rreg (SD_, RM2);
8098 dstreg1 = translate_rreg (SD_, RN1);
8099 dstreg2 = translate_rreg (SD_, RN2);
8101 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8102 State.regs[dstreg2] <<= State.regs[srcreg2];
8103 State.regs[dstreg1] = result1;
8106 // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
8107 8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
8111 int srcreg1, dstreg1, dstreg2;
8116 srcreg1 = translate_rreg (SD_, RM1);
8117 dstreg1 = translate_rreg (SD_, RN1);
8118 dstreg2 = translate_rreg (SD_, RN2);
8120 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8121 State.regs[dstreg2] <<= IMM4;
8122 State.regs[dstreg1] = result1;
8125 // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
8126 8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
8130 int srcreg1, srcreg2, dstreg1, dstreg2;
8134 srcreg1 = translate_rreg (SD_, RM1);
8135 srcreg2 = translate_rreg (SD_, RM2);
8136 dstreg1 = translate_rreg (SD_, RN1);
8137 dstreg2 = translate_rreg (SD_, RN2);
8139 if (State.regs[srcreg1] >= 0x7fff)
8141 else if (State.regs[srcreg1] <= 0xffff8000)
8142 result1 = 0xffff8000;
8144 result1 = State.regs[srcreg1];
8146 State.regs[dstreg2] += State.regs[srcreg2];
8147 State.regs[dstreg1] = result1;
8150 // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
8151 8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
8155 int srcreg1, dstreg1, dstreg2;
8159 srcreg1 = translate_rreg (SD_, RM1);
8160 dstreg1 = translate_rreg (SD_, RN1);
8161 dstreg2 = translate_rreg (SD_, RN2);
8163 if (State.regs[srcreg1] >= 0x7fff)
8165 else if (State.regs[srcreg1] <= 0xffff8000)
8166 result1 = 0xffff8000;
8168 result1 = State.regs[srcreg1];
8170 State.regs[dstreg2] += EXTEND4 (IMM4);
8171 State.regs[dstreg1] = result1;
8174 // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
8175 8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
8179 int srcreg1, srcreg2, dstreg1, dstreg2;
8183 srcreg1 = translate_rreg (SD_, RM1);
8184 srcreg2 = translate_rreg (SD_, RM2);
8185 dstreg1 = translate_rreg (SD_, RN1);
8186 dstreg2 = translate_rreg (SD_, RN2);
8188 if (State.regs[srcreg1] >= 0x7fff)
8190 else if (State.regs[srcreg1] <= 0xffff8000)
8191 result1 = 0xffff8000;
8193 result1 = State.regs[srcreg1];
8195 State.regs[dstreg2] -= State.regs[srcreg2];
8196 State.regs[dstreg1] = result1;
8199 // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
8200 8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
8204 int srcreg1, dstreg1, dstreg2;
8208 srcreg1 = translate_rreg (SD_, RM1);
8209 dstreg1 = translate_rreg (SD_, RN1);
8210 dstreg2 = translate_rreg (SD_, RN2);
8212 if (State.regs[srcreg1] >= 0x7fff)
8214 else if (State.regs[srcreg1] <= 0xffff8000)
8215 result1 = 0xffff8000;
8217 result1 = State.regs[srcreg1];
8219 State.regs[dstreg2] -= EXTEND4 (IMM4);
8220 State.regs[dstreg1] = result1;
8223 // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
8224 8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
8228 int srcreg1, srcreg2, dstreg1, dstreg2;
8232 srcreg1 = translate_rreg (SD_, RM1);
8233 srcreg2 = translate_rreg (SD_, RM2);
8234 dstreg1 = translate_rreg (SD_, RN1);
8235 dstreg2 = translate_rreg (SD_, RN2);
8237 State.regs[dstreg1] = result1;
8238 if (State.regs[srcreg1] >= 0x7fff)
8239 State.regs[dstreg1] = 0x7fff;
8240 else if (State.regs[srcreg1] <= 0xffff8000)
8241 State.regs[dstreg1] = 0xffff8000;
8243 State.regs[dstreg1] = State.regs[srcreg1];
8246 // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
8247 8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
8251 int srcreg1, dstreg1, dstreg2;
8254 srcreg1 = translate_rreg (SD_, RM1);
8255 dstreg1 = translate_rreg (SD_, RN1);
8256 dstreg2 = translate_rreg (SD_, RN2);
8258 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
8259 if (State.regs[srcreg1] >= 0x7fff)
8260 State.regs[dstreg1] = 0x7fff;
8261 else if (State.regs[srcreg1] <= 0xffff8000)
8262 State.regs[dstreg1] = 0xffff8000;
8264 State.regs[dstreg1] = State.regs[srcreg1];
8267 // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
8268 8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
8272 int srcreg1, srcreg2, dstreg1, dstreg2;
8276 srcreg1 = translate_rreg (SD_, RM1);
8277 srcreg2 = translate_rreg (SD_, RM2);
8278 dstreg1 = translate_rreg (SD_, RN1);
8279 dstreg2 = translate_rreg (SD_, RN2);
8281 if (State.regs[srcreg1] >= 0x7fff)
8283 else if (State.regs[srcreg1] <= 0xffff8000)
8284 result1 = 0xffff8000;
8286 result1 = State.regs[srcreg1];
8288 State.regs[dstreg2] = State.regs[srcreg2];
8289 State.regs[dstreg1] = result1;
8292 // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
8293 8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
8297 int srcreg1, dstreg1, dstreg2;
8301 srcreg1 = translate_rreg (SD_, RM1);
8302 dstreg1 = translate_rreg (SD_, RN1);
8303 dstreg2 = translate_rreg (SD_, RN2);
8305 if (State.regs[srcreg1] >= 0x7fff)
8307 else if (State.regs[srcreg1] <= 0xffff8000)
8308 result1 = 0xffff8000;
8310 result1 = State.regs[srcreg1];
8312 State.regs[dstreg2] = EXTEND4 (IMM4);
8313 State.regs[dstreg1] = result1;
8316 // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
8317 8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
8321 int srcreg1, srcreg2, dstreg1, dstreg2;
8326 srcreg1 = translate_rreg (SD_, RM1);
8327 srcreg2 = translate_rreg (SD_, RM2);
8328 dstreg1 = translate_rreg (SD_, RN1);
8329 dstreg2 = translate_rreg (SD_, RN2);
8331 if (State.regs[srcreg1] >= 0x7fff)
8333 else if (State.regs[srcreg1] <= 0xffff8000)
8334 result1 = 0xffff8000;
8336 result1 = State.regs[srcreg1];
8338 temp = State.regs[dstreg2];
8339 temp >>= State.regs[srcreg2];
8340 State.regs[dstreg2] = temp;
8341 State.regs[dstreg1] = result1;
8344 // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
8345 8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
8349 int srcreg1, dstreg1, dstreg2;
8354 srcreg1 = translate_rreg (SD_, RM1);
8355 dstreg1 = translate_rreg (SD_, RN1);
8356 dstreg2 = translate_rreg (SD_, RN2);
8358 if (State.regs[srcreg1] >= 0x7fff)
8360 else if (State.regs[srcreg1] <= 0xffff8000)
8361 result1 = 0xffff8000;
8363 result1 = State.regs[srcreg1];
8365 temp = State.regs[dstreg2];
8367 State.regs[dstreg2] = temp;
8368 State.regs[dstreg1] = result1;
8371 // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
8372 8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
8376 int srcreg1, srcreg2, dstreg1, dstreg2;
8380 srcreg1 = translate_rreg (SD_, RM1);
8381 srcreg2 = translate_rreg (SD_, RM2);
8382 dstreg1 = translate_rreg (SD_, RN1);
8383 dstreg2 = translate_rreg (SD_, RN2);
8385 if (State.regs[srcreg1] >= 0x7fff)
8387 else if (State.regs[srcreg1] <= 0xffff8000)
8388 result1 = 0xffff8000;
8390 result1 = State.regs[srcreg1];
8392 State.regs[dstreg2] >>= State.regs[srcreg2];
8393 State.regs[dstreg1] = result1;
8396 // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
8397 8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
8401 int srcreg1, dstreg1, dstreg2;
8406 srcreg1 = translate_rreg (SD_, RM1);
8407 dstreg1 = translate_rreg (SD_, RN1);
8408 dstreg2 = translate_rreg (SD_, RN2);
8410 if (State.regs[srcreg1] >= 0x7fff)
8412 else if (State.regs[srcreg1] <= 0xffff8000)
8413 result1 = 0xffff8000;
8415 result1 = State.regs[srcreg1];
8417 State.regs[dstreg2] >>= IMM4;
8418 State.regs[dstreg1] = result1;
8422 // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
8423 8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
8427 int srcreg1, srcreg2, dstreg1, dstreg2;
8431 srcreg1 = translate_rreg (SD_, RM1);
8432 srcreg2 = translate_rreg (SD_, RM2);
8433 dstreg1 = translate_rreg (SD_, RN1);
8434 dstreg2 = translate_rreg (SD_, RN2);
8436 if (State.regs[srcreg1] >= 0x7fff)
8438 else if (State.regs[srcreg1] <= 0xffff8000)
8439 result1 = 0xffff8000;
8441 result1 = State.regs[srcreg1];
8443 State.regs[dstreg2] <<= State.regs[srcreg2];
8444 State.regs[dstreg1] = result1;
8447 // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
8448 8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
8452 int srcreg1, dstreg1, dstreg2;
8457 srcreg1 = translate_rreg (SD_, RM1);
8458 dstreg1 = translate_rreg (SD_, RN1);
8459 dstreg2 = translate_rreg (SD_, RN2);
8461 if (State.regs[srcreg1] >= 0x7fff)
8463 else if (State.regs[srcreg1] <= 0xffff8000)
8464 result1 = 0xffff8000;
8466 result1 = State.regs[srcreg1];
8468 State.regs[dstreg2] <<= IMM4;
8469 State.regs[dstreg1] = result1;
8472 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
8473 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
8481 srcreg = translate_rreg (SD_, RM);
8482 dstreg = translate_rreg (SD_, RN);
8484 State.regs[dstreg] = load_word (State.regs[srcreg]);
8485 State.regs[srcreg] += EXTEND4 (IMM4);
8487 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
8489 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8492 State.regs[dstreg] = result1;
8495 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
8496 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
8503 srcreg = translate_rreg (SD_, RM);
8504 dstreg = translate_rreg (SD_, RN);
8506 State.regs[dstreg] = load_word (State.regs[srcreg]);
8507 State.regs[srcreg] += EXTEND4 (IMM4);
8510 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
8512 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8517 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
8518 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
8525 srcreg = translate_rreg (SD_, RM);
8526 dstreg = translate_rreg (SD_, RN);
8528 State.regs[dstreg] = load_word (State.regs[srcreg]);
8529 State.regs[srcreg] += EXTEND4 (IMM4);
8531 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8533 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8538 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
8539 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
8546 srcreg = translate_rreg (SD_, RM);
8547 dstreg = translate_rreg (SD_, RN);
8549 State.regs[dstreg] = load_word (State.regs[srcreg]);
8550 State.regs[srcreg] += EXTEND4 (IMM4);
8553 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8555 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8560 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
8561 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
8568 srcreg = translate_rreg (SD_, RM);
8569 dstreg = translate_rreg (SD_, RN);
8571 State.regs[dstreg] = load_word (State.regs[srcreg]);
8572 State.regs[srcreg] += EXTEND4 (IMM4);
8576 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8581 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
8582 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
8589 srcreg = translate_rreg (SD_, RM);
8590 dstreg = translate_rreg (SD_, RN);
8592 State.regs[dstreg] = load_word (State.regs[srcreg]);
8593 State.regs[srcreg] += EXTEND4 (IMM4);
8595 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
8597 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8602 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
8603 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
8610 srcreg = translate_rreg (SD_, RM);
8611 dstreg = translate_rreg (SD_, RN);
8613 State.regs[dstreg] = load_word (State.regs[srcreg]);
8614 State.regs[srcreg] += EXTEND4 (IMM4);
8618 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8623 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
8624 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
8631 srcreg = translate_rreg (SD_, RM);
8632 dstreg = translate_rreg (SD_, RN);
8634 State.regs[dstreg] = load_word (State.regs[srcreg]);
8635 State.regs[srcreg] += EXTEND4 (IMM4);
8637 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
8639 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8644 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
8645 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
8652 srcreg = translate_rreg (SD_, RM);
8653 dstreg = translate_rreg (SD_, RN);
8655 State.regs[dstreg] = load_word (State.regs[srcreg]);
8656 State.regs[srcreg] += EXTEND4 (IMM4);
8660 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8665 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
8666 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
8673 srcreg = translate_rreg (SD_, RM);
8674 dstreg = translate_rreg (SD_, RN);
8676 State.regs[dstreg] = load_word (State.regs[srcreg]);
8677 State.regs[srcreg] += EXTEND4 (IMM4);
8681 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8686 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
8687 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
8694 srcreg = translate_rreg (SD_, RM);
8695 dstreg = translate_rreg (SD_, RN);
8697 State.regs[dstreg] = load_word (State.regs[srcreg]);
8698 State.regs[srcreg] += EXTEND4 (IMM4);
8700 State.regs[REG_PC] = State.regs[REG_LAR] - 4;