3 // Given an extended register number, translate it into an index into the
4 // register array. This is necessary as the upper 8 extended registers are
5 // actually synonyms for the d0-d3/a0-a3 registers.
9 :function:::int:translate_rreg:int rreg
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
22 // 1111 0000 0010 00An; mov USP,An
23 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
28 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
32 // 1111 0000 0010 01An; mov SSP,An
33 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
38 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
42 // 1111 0000 0010 10An; mov MSP,An
43 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
48 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
52 // 1111 0000 0010 11An; mov PC,An
53 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
58 State.regs[REG_A0 + AN0] = PC;
62 // 1111 0000 0011 Am00; mov Am,USP
63 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
68 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
71 // 1111 0000 0011 Am01; mov Am,SSP
72 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
77 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
80 // 1111 0000 0011 Am10; mov Am,MSP
81 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
86 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
90 // 1111 0000 1110 imm4; syscall
91 8.0xf0+4.0xe,IMM4:D0t:::syscall
95 unsigned int sp, next_pc;
98 sp = State.regs[REG_SP];
99 next_pc = State.regs[REG_PC] + 2;
100 store_word (sp - 4, next_pc);
101 store_word (sp - 8, PSW);
102 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
107 // 1111 0010 1110 11Dn; mov EPSW,Dn
108 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
113 State.regs[REG_D0 + DN0] = PSW;
117 // 1111 0010 1111 Dm01; mov Dm,EPSW
118 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
123 PSW = State.regs[REG_D0 + DM1];
126 // 1111 0101 00Am Rn; mov Am,Rn
127 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
131 int destreg = translate_rreg (SD_, RN0);
134 State.regs[destreg] = State.regs[REG_A0 + AM1];
137 // 1111 0101 01Dm Rn; mov Dm,Rn
138 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
142 int destreg = translate_rreg (SD_, RN0);
145 State.regs[destreg] = State.regs[REG_D0 + DM1];
148 // 1111 0101 10Rm An; mov Rm,An
149 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
153 int destreg = translate_rreg (SD_, RM1);
156 State.regs[REG_A0 + AN0] = State.regs[destreg];
159 // 1111 0101 11Rm Dn; mov Rm,Dn
160 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
164 int destreg = translate_rreg (SD_, RM1);
167 State.regs[REG_D0 + DN0] = State.regs[destreg];
171 // 1111 1000 1100 1110 regs....; movm (USP),regs
172 8.0xf8+8.0xce+8.REGS:D1a:::movm
176 unsigned long usp = State.regs[REG_USP];
185 State.regs[REG_LAR] = load_word (usp);
187 State.regs[REG_LIR] = load_word (usp);
189 State.regs[REG_MDR] = load_word (usp);
191 State.regs[REG_A0 + 1] = load_word (usp);
193 State.regs[REG_A0] = load_word (usp);
195 State.regs[REG_D0 + 1] = load_word (usp);
197 State.regs[REG_D0] = load_word (usp);
203 State.regs[REG_A0 + 3] = load_word (usp);
209 State.regs[REG_A0 + 2] = load_word (usp);
215 State.regs[REG_D0 + 3] = load_word (usp);
221 State.regs[REG_D0 + 2] = load_word (usp);
225 /* start-sanitize-am33 */
226 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
230 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
232 State.regs[REG_E0 + 1] = load_word (usp);
234 State.regs[REG_E0 + 0] = load_word (usp);
240 State.regs[REG_E0 + 7] = load_word (usp);
242 State.regs[REG_E0 + 6] = load_word (usp);
244 State.regs[REG_E0 + 5] = load_word (usp);
246 State.regs[REG_E0 + 4] = load_word (usp);
252 State.regs[REG_E0 + 3] = load_word (usp);
254 State.regs[REG_E0 + 2] = load_word (usp);
258 /* end-sanitize-am33 */
260 /* And make sure to update the stack pointer. */
261 State.regs[REG_USP] = usp;
264 // 1111 1000 1100 1111 regs....; movm (USP),regs
265 8.0xf8+8.0xcf+8.REGS:D1b:::movm
269 unsigned long usp = State.regs[REG_USP];
272 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
277 store_word (usp, State.regs[REG_E0 + 2]);
279 store_word (usp, State.regs[REG_E0 + 3]);
285 store_word (usp, State.regs[REG_E0 + 4]);
287 store_word (usp, State.regs[REG_E0 + 5]);
289 store_word (usp, State.regs[REG_E0 + 6]);
291 store_word (usp, State.regs[REG_E0 + 7]);
297 store_word (usp, State.regs[REG_E0 + 0]);
299 store_word (usp, State.regs[REG_E0 + 1]);
301 /* Need to save MDQR, MCRH, MCRL, and MCVF */
304 /* end-sanitize-am33 */
309 store_word (usp, State.regs[REG_D0 + 2]);
315 store_word (usp, State.regs[REG_D0 + 3]);
321 store_word (usp, State.regs[REG_A0 + 2]);
327 store_word (usp, State.regs[REG_A0 + 3]);
333 store_word (usp, State.regs[REG_D0]);
335 store_word (usp, State.regs[REG_D0 + 1]);
337 store_word (usp, State.regs[REG_A0]);
339 store_word (usp, State.regs[REG_A0 + 1]);
341 store_word (usp, State.regs[REG_MDR]);
343 store_word (usp, State.regs[REG_LIR]);
345 store_word (usp, State.regs[REG_LAR]);
349 /* And make sure to update the stack pointer. */
350 State.regs[REG_USP] = usp;
353 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
354 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
359 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
362 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
363 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
368 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
371 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
372 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
380 srcreg = translate_rreg (SD_, RM2);
381 dstreg = translate_rreg (SD_, RN0);
382 State.regs[dstreg] = State.regs[srcreg];
385 // 1111 1001 0001 1000 Rn Rn; ext Rn
386 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
393 srcreg = translate_rreg (SD_, RN0);
394 if (State.regs[srcreg] & 0x80000000)
395 State.regs[REG_MDR] = -1;
397 State.regs[REG_MDR] = 0;
400 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
401 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
408 srcreg = translate_rreg (SD_, RM2);
409 dstreg = translate_rreg (SD_, RN0);
410 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
413 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
414 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
421 srcreg = translate_rreg (SD_, RM2);
422 dstreg = translate_rreg (SD_, RN0);
423 State.regs[dstreg] = State.regs[srcreg] & 0xff;
426 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
427 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
434 srcreg = translate_rreg (SD_, RM2);
435 dstreg = translate_rreg (SD_, RN0);
436 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
439 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
440 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
447 srcreg = translate_rreg (SD_, RM2);
448 dstreg = translate_rreg (SD_, RN0);
449 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
452 // 1111 1001 0110 1000 Rn Rn; clr Rn
453 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
460 dstreg = translate_rreg (SD_, RN0);
461 State.regs[dstreg] = 0;
463 PSW &= ~(PSW_V | PSW_C | PSW_N);
466 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
467 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
474 srcreg = translate_rreg (SD_, RM2);
475 dstreg = translate_rreg (SD_, RN0);
476 genericAdd (State.regs[srcreg], dstreg);
479 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
480 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
486 unsigned long reg1, reg2, sum;
489 srcreg = translate_rreg (SD_, RM2);
490 dstreg = translate_rreg (SD_, RN0);
492 reg1 = State.regs[srcreg];
493 reg2 = State.regs[dstreg];
494 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
495 State.regs[dstreg] = sum;
497 z = ((PSW & PSW_Z) != 0) && (sum == 0);
498 n = (sum & 0x80000000);
499 c = (sum < reg1) || (sum < reg2);
500 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
501 && (reg2 & 0x80000000) != (sum & 0x80000000));
503 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
504 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
505 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
508 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
509 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
516 srcreg = translate_rreg (SD_, RM2);
517 dstreg = translate_rreg (SD_, RN0);
518 genericSub (State.regs[srcreg], dstreg);
521 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
522 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
528 unsigned long reg1, reg2, difference;
531 srcreg = translate_rreg (SD_, RM2);
532 dstreg = translate_rreg (SD_, RN0);
534 reg1 = State.regs[srcreg];
535 reg2 = State.regs[dstreg];
536 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
537 State.regs[dstreg] = difference;
539 z = ((PSW & PSW_Z) != 0) && (difference == 0);
540 n = (difference & 0x80000000);
542 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
543 && (reg2 & 0x80000000) != (difference & 0x80000000));
545 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
546 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
547 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
550 // 1111 1001 1011 1000 Rn Rn; inc Rn
551 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
558 dstreg = translate_rreg (SD_, RN0);
559 genericAdd (1, dstreg);
562 // 1111 1001 1101 1000 Rn Rn; inc Rn
563 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
570 dstreg = translate_rreg (SD_, RN0);
571 State.regs[dstreg] += 4;
574 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
575 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
579 int srcreg1, srcreg2;
582 srcreg1 = translate_rreg (SD_, RN0);
583 srcreg2 = translate_rreg (SD_, RM2);
584 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
587 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
588 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
595 dstreg = translate_rreg (SD_, RN0);
599 State.regs[dstreg] = State.regs[REG_SP];
605 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
606 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
613 srcreg = translate_rreg (SD_, RM2);
617 State.regs[REG_SP] = State.regs[srcreg];
623 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
624 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
633 srcreg = translate_rreg (SD_, RM2);
634 dstreg = translate_rreg (SD_, RN0);
636 State.regs[dstreg] &= State.regs[srcreg];
637 z = (State.regs[dstreg] == 0);
638 n = (State.regs[dstreg] & 0x80000000) != 0;
639 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
640 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
643 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
644 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
652 srcreg = translate_rreg (SD_, RM2);
653 dstreg = translate_rreg (SD_, RN0);
655 State.regs[dstreg] |= State.regs[srcreg];
656 z = (State.regs[dstreg] == 0);
657 n = (State.regs[dstreg] & 0x80000000) != 0;
658 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
659 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
662 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
663 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
671 srcreg = translate_rreg (SD_, RM2);
672 dstreg = translate_rreg (SD_, RN0);
674 State.regs[dstreg] ^= State.regs[srcreg];
675 z = (State.regs[dstreg] == 0);
676 n = (State.regs[dstreg] & 0x80000000) != 0;
677 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
678 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
681 // 1111 1001 0011 1001 Rn Rn; not Rn
682 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
690 dstreg = translate_rreg (SD_, RN0);
692 State.regs[dstreg] = ~State.regs[dstreg];
693 z = (State.regs[dstreg] == 0);
694 n = (State.regs[dstreg] & 0x80000000) != 0;
695 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
696 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
699 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
700 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
709 srcreg = translate_rreg (SD_, RM2);
710 dstreg = translate_rreg (SD_, RN0);
712 temp = State.regs[dstreg];
714 temp >>= State.regs[srcreg];
715 State.regs[dstreg] = temp;
716 z = (State.regs[dstreg] == 0);
717 n = (State.regs[dstreg] & 0x80000000) != 0;
718 PSW &= ~(PSW_Z | PSW_N | PSW_C);
719 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
722 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
723 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
732 srcreg = translate_rreg (SD_, RM2);
733 dstreg = translate_rreg (SD_, RN0);
735 c = State.regs[dstreg] & 1;
736 State.regs[dstreg] >>= State.regs[srcreg];
737 z = (State.regs[dstreg] == 0);
738 n = (State.regs[dstreg] & 0x80000000) != 0;
739 PSW &= ~(PSW_Z | PSW_N | PSW_C);
740 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
743 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
744 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
752 srcreg = translate_rreg (SD_, RM2);
753 dstreg = translate_rreg (SD_, RN0);
755 State.regs[dstreg] <<= State.regs[srcreg];
756 z = (State.regs[dstreg] == 0);
757 n = (State.regs[dstreg] & 0x80000000) != 0;
758 PSW &= ~(PSW_Z | PSW_N);
759 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
762 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
763 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
771 dstreg = translate_rreg (SD_, RN0);
773 State.regs[dstreg] <<= 2;
774 z = (State.regs[dstreg] == 0);
775 n = (State.regs[dstreg] & 0x80000000) != 0;
776 PSW &= ~(PSW_Z | PSW_N);
777 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
780 // 1111 1001 1000 1001 Rn Rn; ror Rn
781 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
790 dstreg = translate_rreg (SD_, RN0);
792 value = State.regs[dstreg];
796 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
797 State.regs[dstreg] = value;
799 n = (value & 0x80000000) != 0;
800 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
801 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
804 // 1111 1001 1001 1001 Rn Rn; rol Rn
805 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
814 dstreg = translate_rreg (SD_, RN0);
816 value = State.regs[dstreg];
817 c = (value & 0x80000000) ? 1 : 0;
820 value |= ((PSW & PSW_C) != 0);
821 State.regs[dstreg] = value;
823 n = (value & 0x80000000) != 0;
824 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
825 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
828 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
829 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
834 unsigned long long temp;
838 srcreg = translate_rreg (SD_, RM2);
839 dstreg = translate_rreg (SD_, RN0);
841 temp = ((signed64)(signed32)State.regs[dstreg]
842 * (signed64)(signed32)State.regs[srcreg]);
843 State.regs[dstreg] = temp & 0xffffffff;
844 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
845 z = (State.regs[dstreg] == 0);
846 n = (State.regs[dstreg] & 0x80000000) != 0;
847 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
848 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
851 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
852 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
857 unsigned long long temp;
861 srcreg = translate_rreg (SD_, RM2);
862 dstreg = translate_rreg (SD_, RN0);
864 temp = ((unsigned64)State.regs[dstreg]
865 * (unsigned64)State.regs[srcreg]);
866 State.regs[dstreg] = temp & 0xffffffff;
867 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
868 z = (State.regs[dstreg] == 0);
869 n = (State.regs[dstreg] & 0x80000000) != 0;
870 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
871 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
874 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
875 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
884 srcreg = translate_rreg (SD_, RM2);
885 dstreg = translate_rreg (SD_, RN0);
887 temp = State.regs[REG_MDR];
889 temp |= State.regs[dstreg];
890 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
891 temp /= (signed32)State.regs[srcreg];
892 State.regs[dstreg] = temp & 0xffffffff;
893 z = (State.regs[dstreg] == 0);
894 n = (State.regs[dstreg] & 0x80000000) != 0;
895 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
896 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
899 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
900 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
905 unsigned long long temp;
909 srcreg = translate_rreg (SD_, RM2);
910 dstreg = translate_rreg (SD_, RN0);
912 temp = State.regs[REG_MDR];
914 temp |= State.regs[dstreg];
915 State.regs[REG_MDR] = temp % State.regs[srcreg];
916 temp /= State.regs[srcreg];
917 State.regs[dstreg] = temp & 0xffffffff;
918 z = (State.regs[dstreg] == 0);
919 n = (State.regs[dstreg] & 0x80000000) != 0;
920 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
921 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
925 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
926 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
933 srcreg = translate_rreg (SD_, RM0);
934 dstreg = translate_rreg (SD_, RN2);
935 State.regs[dstreg] = load_word (State.regs[srcreg]);
938 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
939 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
946 srcreg = translate_rreg (SD_, RM2);
947 dstreg = translate_rreg (SD_, RN0);
948 store_word (State.regs[dstreg], State.regs[srcreg]);
951 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
952 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
959 srcreg = translate_rreg (SD_, RM0);
960 dstreg = translate_rreg (SD_, RN2);
961 State.regs[dstreg] = load_byte (State.regs[srcreg]);
964 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
965 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
972 srcreg = translate_rreg (SD_, RM2);
973 dstreg = translate_rreg (SD_, RN0);
974 store_byte (State.regs[dstreg], State.regs[srcreg]);
977 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
978 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
985 srcreg = translate_rreg (SD_, RM0);
986 dstreg = translate_rreg (SD_, RN2);
987 State.regs[dstreg] = load_half (State.regs[srcreg]);
990 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
991 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
998 srcreg = translate_rreg (SD_, RM2);
999 dstreg = translate_rreg (SD_, RN0);
1000 store_half (State.regs[dstreg], State.regs[srcreg]);
1003 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1004 8.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
1011 srcreg = translate_rreg (SD_, RM0);
1012 dstreg = translate_rreg (SD_, RN2);
1013 State.regs[dstreg] = load_word (State.regs[srcreg]);
1014 State.regs[srcreg] += 4;
1017 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1018 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1025 srcreg = translate_rreg (SD_, RM2);
1026 dstreg = translate_rreg (SD_, RN0);
1027 store_word (State.regs[dstreg], State.regs[srcreg]);
1028 State.regs[dstreg] += 4;
1031 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1032 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1039 dstreg = translate_rreg (SD_, RN2);
1040 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1043 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1044 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1051 srcreg = translate_rreg (SD_, RM2);
1052 store_word (State.regs[REG_SP], State.regs[srcreg]);
1055 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1056 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1063 dstreg = translate_rreg (SD_, RN2);
1064 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1067 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1068 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1075 srcreg = translate_rreg (SD_, RM2);
1076 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1079 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1080 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1087 dstreg = translate_rreg (SD_, RN2);
1088 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1091 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1092 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1099 srcreg = translate_rreg (SD_, RM2);
1100 store_half (State.regs[REG_SP], State.regs[srcreg]);
1103 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1104 8.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
1111 srcreg = translate_rreg (SD_, RM0);
1112 dstreg = translate_rreg (SD_, RN2);
1113 State.regs[dstreg] = load_half (State.regs[srcreg]);
1114 State.regs[srcreg] += 2;
1117 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1118 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1125 srcreg = translate_rreg (SD_, RM2);
1126 dstreg = translate_rreg (SD_, RN0);
1127 store_half (State.regs[dstreg], State.regs[srcreg]);
1128 State.regs[dstreg] += 2;
1132 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1133 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1137 int srcreg1, srcreg2;
1138 long long temp, sum;
1142 srcreg1 = translate_rreg (SD_, RM2);
1143 srcreg2 = translate_rreg (SD_, RN0);
1145 temp = ((signed64)(signed32)State.regs[srcreg2]
1146 * (signed64)(signed32)State.regs[srcreg1]);
1147 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1148 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1149 State.regs[REG_MCRL] = sum;
1152 sum = State.regs[REG_MCRH] + temp + c;
1153 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1154 && (temp & 0x80000000) != (sum & 0x80000000));
1155 State.regs[REG_MCRH] = sum;
1157 State.regs[REG_MCVF] = 1;
1160 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1161 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1165 int srcreg1, srcreg2;
1166 unsigned long long temp, sum;
1170 srcreg1 = translate_rreg (SD_, RM2);
1171 srcreg2 = translate_rreg (SD_, RN0);
1173 temp = ((unsigned64)State.regs[srcreg2]
1174 * (unsigned64)State.regs[srcreg1]);
1175 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1176 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1177 State.regs[REG_MCRL] = sum;
1180 sum = State.regs[REG_MCRH] + temp + c;
1181 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1182 && (temp & 0x80000000) != (sum & 0x80000000));
1183 State.regs[REG_MCRH] = sum;
1185 State.regs[REG_MCVF] = 1;
1188 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1189 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1193 int srcreg1, srcreg2;
1198 srcreg1 = translate_rreg (SD_, RM2);
1199 srcreg2 = translate_rreg (SD_, RN0);
1201 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1202 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
1203 sum = State.regs[REG_MCRL] + temp;
1204 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1205 && (temp & 0x80000000) != (sum & 0x80000000));
1206 State.regs[REG_MCRL] = sum;
1208 State.regs[REG_MCVF] = 1;
1211 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1212 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1216 int srcreg1, srcreg2;
1217 long long temp, sum;
1221 srcreg1 = translate_rreg (SD_, RM2);
1222 srcreg2 = translate_rreg (SD_, RN0);
1224 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1225 * (unsigned32)(State.regs[srcreg1] & 0xff));
1226 sum = State.regs[REG_MCRL] + temp;
1227 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1228 && (temp & 0x80000000) != (sum & 0x80000000));
1229 State.regs[REG_MCRL] = sum;
1231 State.regs[REG_MCVF] = 1;
1234 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1235 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1239 int srcreg1, srcreg2;
1240 long long temp, sum;
1244 srcreg1 = translate_rreg (SD_, RM2);
1245 srcreg2 = translate_rreg (SD_, RN0);
1247 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1248 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
1249 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1250 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1251 State.regs[REG_MCRL] = sum;
1254 sum = State.regs[REG_MCRH] + temp + c;
1255 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1256 && (temp & 0x80000000) != (sum & 0x80000000));
1257 State.regs[REG_MCRH] = sum;
1259 State.regs[REG_MCVF] = 1;
1262 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1263 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1267 int srcreg1, srcreg2;
1268 long long temp, sum;
1272 srcreg1 = translate_rreg (SD_, RM2);
1273 srcreg2 = translate_rreg (SD_, RN0);
1275 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1276 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1277 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1278 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1279 State.regs[REG_MCRL] = sum;
1282 sum = State.regs[REG_MCRH] + temp + c;
1283 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1284 && (temp & 0x80000000) != (sum & 0x80000000));
1285 State.regs[REG_MCRH] = sum;
1287 State.regs[REG_MCVF] = 1;
1290 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1291 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1295 int srcreg1, srcreg2;
1296 long temp, temp2, sum;
1300 srcreg1 = translate_rreg (SD_, RM2);
1301 srcreg2 = translate_rreg (SD_, RN0);
1303 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1304 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1305 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1306 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
1307 sum = temp + temp2 + State.regs[REG_MCRL];
1308 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1309 && (temp & 0x80000000) != (sum & 0x80000000));
1310 State.regs[REG_MCRL] = sum;
1312 State.regs[REG_MCVF] = 1;
1315 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1316 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1320 int srcreg1, srcreg2;
1321 unsigned long temp, temp2, sum;
1325 srcreg1 = translate_rreg (SD_, RM2);
1326 srcreg2 = translate_rreg (SD_, RN0);
1328 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1329 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1330 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1331 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1332 sum = temp + temp2 + State.regs[REG_MCRL];
1333 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1334 && (temp & 0x80000000) != (sum & 0x80000000));
1335 State.regs[REG_MCRL] = sum;
1337 State.regs[REG_MCVF] = 1;
1340 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1341 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1349 srcreg = translate_rreg (SD_, RM2);
1350 dstreg = translate_rreg (SD_, RN0);
1352 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1353 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
1354 State.regs[REG_MDRQ] = temp;
1355 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1356 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
1357 State.regs[dstreg] = temp;
1360 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1361 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1369 srcreg = translate_rreg (SD_, RM2);
1370 dstreg = translate_rreg (SD_, RN0);
1372 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1373 * (unsigned32)(State.regs[srcreg] & 0xffff));
1374 State.regs[REG_MDRQ] = temp;
1375 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1376 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1377 State.regs[dstreg] = temp;
1380 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1381 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1389 srcreg = translate_rreg (SD_, RM2);
1390 dstreg = translate_rreg (SD_, RN0);
1392 value = State.regs[srcreg];
1394 if (value >= 0x7fff)
1395 State.regs[dstreg] = 0x7fff;
1396 else if (value <= 0xffff8000)
1397 State.regs[dstreg] = 0xffff8000;
1399 State.regs[dstreg] = value;
1401 n = (State.regs[dstreg] & 0x8000) != 0;
1402 z = (State.regs[dstreg] == 0);
1403 PSW &= ~(PSW_Z | PSW_N);
1404 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1407 // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
1408 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1415 srcreg = translate_rreg (SD_, RM2);
1416 dstreg = translate_rreg (SD_, RN0);
1418 PSW &= ~(PSW_V | PSW_C);
1419 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1421 /* 32bit saturation. */
1422 if (State.regs[srcreg] == 0x20)
1426 tmp = State.regs[REG_MCRH];
1428 tmp += State.regs[REG_MCRL];
1430 if (tmp > 0x7fffffff)
1431 State.regs[dstreg] = 0x7fffffff;
1432 else if (tmp < 0xffffffff80000000LL)
1433 State.regs[dstreg] = 0x80000000;
1435 State.regs[dstreg] = tmp;
1437 /* 16bit saturation */
1438 else if (State.regs[srcreg] == 0x10)
1442 tmp = State.regs[REG_MCRH];
1444 tmp += State.regs[REG_MCRL];
1447 State.regs[dstreg] = 0x7fff;
1448 else if (tmp < 0xffffffffffff8000LL)
1449 State.regs[dstreg] = 0x8000;
1451 State.regs[dstreg] = tmp;
1453 /* 8 bit saturation */
1454 else if (State.regs[srcreg] == 0x8)
1458 tmp = State.regs[REG_MCRH];
1460 tmp += State.regs[REG_MCRL];
1463 State.regs[dstreg] = 0x7f;
1464 else if (tmp < 0xffffffffffffff80LL)
1465 State.regs[dstreg] = 0x80;
1467 State.regs[dstreg] = tmp;
1469 /* 9 bit saturation */
1470 else if (State.regs[srcreg] == 0x9)
1474 tmp = State.regs[REG_MCRH];
1476 tmp += State.regs[REG_MCRL];
1479 State.regs[dstreg] = 0x80;
1480 else if (tmp < 0xffffffffffffff81LL)
1481 State.regs[dstreg] = 0x81;
1483 State.regs[dstreg] = tmp;
1485 /* 9 bit saturation */
1486 else if (State.regs[srcreg] == 0x30)
1490 tmp = State.regs[REG_MCRH];
1492 tmp += State.regs[REG_MCRL];
1494 if (tmp > 0x7fffffffffffLL)
1495 tmp = 0x7fffffffffffLL;
1496 else if (tmp < 0xffff800000000000LL)
1497 tmp = 0xffff800000000000LL;
1500 State.regs[dstreg] = tmp;
1504 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1505 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1512 srcreg = translate_rreg (SD_, RM2);
1513 dstreg = translate_rreg (SD_, RN0);
1515 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1516 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1517 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1518 | ((State.regs[srcreg] >> 24) & 0xff));
1521 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1522 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1529 srcreg = translate_rreg (SD_, RM2);
1530 dstreg = translate_rreg (SD_, RN0);
1532 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1533 | ((State.regs[srcreg] >> 8) & 0xff)
1534 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1535 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1538 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1539 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1546 srcreg = translate_rreg (SD_, RM2);
1547 dstreg = translate_rreg (SD_, RN0);
1549 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1550 | ((State.regs[srcreg] >> 16) & 0xffff));
1553 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1554 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1563 srcreg = translate_rreg (SD_, RM2);
1564 dstreg = translate_rreg (SD_, RN0);
1566 temp = State.regs[srcreg];
1567 start = (State.regs[dstreg] & 0x1f) - 1;
1571 for (i = start; i >= 0; i--)
1573 if (temp & (1 << i))
1576 State.regs[dstreg] = i;
1584 State.regs[dstreg] = 0;
1587 PSW |= (c ? PSW_C : 0);
1591 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1592 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1599 dstreg = translate_rreg (SD_, RN0);
1600 State.regs[dstreg] = EXTEND8 (IMM8);
1603 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1604 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1611 dstreg = translate_rreg (SD_, RN0);
1612 State.regs[dstreg] = IMM8 & 0xff;
1615 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1616 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1623 dstreg = translate_rreg (SD_, RN0);
1624 genericAdd (EXTEND8 (IMM8), dstreg);
1627 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1628 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1634 unsigned long reg1, reg2, sum;
1637 dstreg = translate_rreg (SD_, RN0);
1639 imm = EXTEND8 (IMM8);
1640 reg2 = State.regs[dstreg];
1641 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1642 State.regs[dstreg] = sum;
1645 n = (sum & 0x80000000);
1646 c = (sum < imm) || (sum < reg2);
1647 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1648 && (reg2 & 0x80000000) != (sum & 0x80000000));
1650 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1651 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1652 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1655 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1656 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1663 dstreg = translate_rreg (SD_, RN0);
1665 genericSub (EXTEND8 (IMM8), dstreg);
1668 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1669 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1675 unsigned long reg1, reg2, difference;
1678 dstreg = translate_rreg (SD_, RN0);
1680 imm = EXTEND8 (IMM8);
1681 reg2 = State.regs[dstreg];
1682 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1683 State.regs[dstreg] = difference;
1685 z = (difference == 0);
1686 n = (difference & 0x80000000);
1688 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1689 && (reg2 & 0x80000000) != (difference & 0x80000000));
1691 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1692 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1693 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1696 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1697 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1704 srcreg = translate_rreg (SD_, RN0);
1705 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1708 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1709 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1718 State.regs[REG_SP] = EXTEND8 (IMM8);
1723 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1724 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1732 dstreg = translate_rreg (SD_, RN0);
1734 State.regs[dstreg] &= (IMM8 & 0xff);
1735 z = (State.regs[dstreg] == 0);
1736 n = (State.regs[dstreg] & 0x80000000) != 0;
1737 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1738 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1741 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1742 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1750 dstreg = translate_rreg (SD_, RN0);
1752 State.regs[dstreg] |= (IMM8 & 0xff);
1753 z = (State.regs[dstreg] == 0);
1754 n = (State.regs[dstreg] & 0x80000000) != 0;
1755 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1756 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1759 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1760 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1768 dstreg = translate_rreg (SD_, RN0);
1770 State.regs[dstreg] ^= (IMM8 & 0xff);
1771 z = (State.regs[dstreg] == 0);
1772 n = (State.regs[dstreg] & 0x80000000) != 0;
1773 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1774 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1777 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1778 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1787 dstreg = translate_rreg (SD_, RN0);
1789 temp = State.regs[dstreg];
1791 temp >>= (IMM8 & 0xff);
1792 State.regs[dstreg] = temp;
1793 z = (State.regs[dstreg] == 0);
1794 n = (State.regs[dstreg] & 0x80000000) != 0;
1795 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1796 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1799 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1800 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1808 dstreg = translate_rreg (SD_, RN0);
1810 c = State.regs[dstreg] & 1;
1811 State.regs[dstreg] >>= (IMM8 & 0xff);
1812 z = (State.regs[dstreg] == 0);
1813 n = (State.regs[dstreg] & 0x80000000) != 0;
1814 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1815 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1818 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1819 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1827 dstreg = translate_rreg (SD_, RN0);
1829 State.regs[dstreg] <<= (IMM8 & 0xff);
1830 z = (State.regs[dstreg] == 0);
1831 n = (State.regs[dstreg] & 0x80000000) != 0;
1832 PSW &= ~(PSW_Z | PSW_N);
1833 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1836 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1837 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1842 unsigned long long temp;
1846 dstreg = translate_rreg (SD_, RN0);
1848 temp = ((signed64)(signed32)State.regs[dstreg]
1849 * (signed64)(signed32)EXTEND8 (IMM8));
1850 State.regs[dstreg] = temp & 0xffffffff;
1851 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1852 z = (State.regs[dstreg] == 0);
1853 n = (State.regs[dstreg] & 0x80000000) != 0;
1854 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1855 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1858 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1859 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1864 unsigned long long temp;
1868 dstreg = translate_rreg (SD_, RN0);
1870 temp = ((unsigned64)State.regs[dstreg]
1871 * (unsigned64)(IMM8 & 0xff));
1872 State.regs[dstreg] = temp & 0xffffffff;
1873 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1874 z = (State.regs[dstreg] == 0);
1875 n = (State.regs[dstreg] & 0x80000000) != 0;
1876 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1877 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1880 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1881 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1888 srcreg = translate_rreg (SD_, RM0);
1889 genericBtst(IMM8, State.regs[srcreg]);
1893 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1894 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1901 srcreg = translate_rreg (SD_, RM0);
1902 dstreg = translate_rreg (SD_, RN2);
1903 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1906 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1907 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1913 srcreg = translate_rreg (SD_, RM2);
1914 dstreg = translate_rreg (SD_, RN0);
1915 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1918 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1919 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1925 srcreg = translate_rreg (SD_, RM0);
1926 dstreg = translate_rreg (SD_, RN2);
1927 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1930 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1931 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1937 srcreg = translate_rreg (SD_, RM2);
1938 dstreg = translate_rreg (SD_, RN0);
1939 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1942 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1943 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1949 srcreg = translate_rreg (SD_, RM0);
1950 dstreg = translate_rreg (SD_, RN2);
1951 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1954 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1955 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1961 srcreg = translate_rreg (SD_, RM2);
1962 dstreg = translate_rreg (SD_, RN0);
1963 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1966 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1967 8.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
1974 srcreg = translate_rreg (SD_, RM0);
1975 dstreg = translate_rreg (SD_, RN2);
1976 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1977 State.regs[srcreg] += 4;
1980 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1981 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1987 srcreg = translate_rreg (SD_, RM2);
1988 dstreg = translate_rreg (SD_, RN0);
1989 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1990 State.regs[dstreg] += 4;
1994 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
1995 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2001 dstreg = translate_rreg (SD_, RN2);
2002 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2005 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2006 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2012 srcreg = translate_rreg (SD_, RM2);
2013 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2016 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2017 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2023 dstreg = translate_rreg (SD_, RN2);
2024 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2027 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2028 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2034 srcreg = translate_rreg (SD_, RM2);
2035 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2038 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2039 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2045 dstreg = translate_rreg (SD_, RN2);
2046 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2049 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2050 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2056 srcreg = translate_rreg (SD_, RM2);
2057 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2060 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2061 8.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
2068 srcreg = translate_rreg (SD_, RM0);
2069 dstreg = translate_rreg (SD_, RN2);
2070 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
2071 State.regs[srcreg] += 2;
2074 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2075 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2081 srcreg = translate_rreg (SD_, RM2);
2082 dstreg = translate_rreg (SD_, RN0);
2083 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2084 State.regs[dstreg] += 2;
2088 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2089 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2093 long long temp, sum;
2097 srcreg = translate_rreg (SD_, RN2);
2099 temp = ((signed64)EXTEND8 (IMM8)
2100 * (signed64)State.regs[srcreg]);
2101 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2102 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2103 State.regs[REG_MCRL] = sum;
2106 sum = State.regs[REG_MCRH] + temp + c;
2107 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2108 && (temp & 0x80000000) != (sum & 0x80000000));
2109 State.regs[REG_MCRH] = sum;
2111 State.regs[REG_MCVF] = 1;
2114 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2115 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2119 long long temp, sum;
2123 srcreg = translate_rreg (SD_, RN2);
2125 temp = ((unsigned64) (IMM8)
2126 * (unsigned64)State.regs[srcreg]);
2127 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2128 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2129 State.regs[REG_MCRL] = sum;
2132 sum = State.regs[REG_MCRH] + temp + c;
2133 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2134 && (temp & 0x80000000) != (sum & 0x80000000));
2135 State.regs[REG_MCRH] = sum;
2137 State.regs[REG_MCVF] = 1;
2140 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2141 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2145 long long temp, sum;
2149 srcreg = translate_rreg (SD_, RN2);
2151 temp = ((signed64)EXTEND8 (IMM8)
2152 * (signed64)State.regs[srcreg] & 0xff);
2153 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2154 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2155 State.regs[REG_MCRL] = sum;
2158 sum = State.regs[REG_MCRH] + temp + c;
2159 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2160 && (temp & 0x80000000) != (sum & 0x80000000));
2161 State.regs[REG_MCRH] = sum;
2163 State.regs[REG_MCVF] = 1;
2166 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2167 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2171 long long temp, sum;
2175 srcreg = translate_rreg (SD_, RN2);
2177 temp = ((unsigned64) (IMM8)
2178 * (unsigned64)State.regs[srcreg] & 0xff);
2179 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2180 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2181 State.regs[REG_MCRL] = sum;
2184 sum = State.regs[REG_MCRH] + temp + c;
2185 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2186 && (temp & 0x80000000) != (sum & 0x80000000));
2187 State.regs[REG_MCRH] = sum;
2189 State.regs[REG_MCVF] = 1;
2192 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2193 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2197 long long temp, sum;
2201 srcreg = translate_rreg (SD_, RN2);
2203 temp = ((signed64)EXTEND8 (IMM8)
2204 * (signed64)State.regs[srcreg] & 0xffff);
2205 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2206 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2207 State.regs[REG_MCRL] = sum;
2210 sum = State.regs[REG_MCRH] + temp + c;
2211 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2212 && (temp & 0x80000000) != (sum & 0x80000000));
2213 State.regs[REG_MCRH] = sum;
2215 State.regs[REG_MCVF] = 1;
2218 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2219 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2223 long long temp, sum;
2227 srcreg = translate_rreg (SD_, RN2);
2229 temp = ((unsigned64) (IMM8)
2230 * (unsigned64)State.regs[srcreg] & 0xffff);
2231 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2232 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2233 State.regs[REG_MCRL] = sum;
2236 sum = State.regs[REG_MCRH] + temp + c;
2237 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2238 && (temp & 0x80000000) != (sum & 0x80000000));
2239 State.regs[REG_MCRH] = sum;
2241 State.regs[REG_MCVF] = 1;
2244 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
2245 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2251 dstreg = translate_rreg (SD_, RN0);
2253 PSW &= ~(PSW_V | PSW_C);
2254 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2256 /* 32bit saturation. */
2261 tmp = State.regs[REG_MCRH];
2263 tmp += State.regs[REG_MCRL];
2265 if (tmp > 0x7fffffff)
2266 State.regs[dstreg] = 0x7fffffff;
2267 else if (tmp < 0xffffffff80000000LL)
2268 State.regs[dstreg] = 0x80000000;
2270 State.regs[dstreg] = tmp;
2272 /* 16bit saturation */
2273 else if (IMM8 == 0x10)
2277 tmp = State.regs[REG_MCRH];
2279 tmp += State.regs[REG_MCRL];
2282 State.regs[dstreg] = 0x7fff;
2283 else if (tmp < 0xffffffffffff8000LL)
2284 State.regs[dstreg] = 0x8000;
2286 State.regs[dstreg] = tmp;
2288 /* 8 bit saturation */
2289 else if (IMM8 == 0x8)
2293 tmp = State.regs[REG_MCRH];
2295 tmp += State.regs[REG_MCRL];
2298 State.regs[dstreg] = 0x7f;
2299 else if (tmp < 0xffffffffffffff80LL)
2300 State.regs[dstreg] = 0x80;
2302 State.regs[dstreg] = tmp;
2304 /* 9 bit saturation */
2305 else if (IMM8 == 0x9)
2309 tmp = State.regs[REG_MCRH];
2311 tmp += State.regs[REG_MCRL];
2314 State.regs[dstreg] = 0x80;
2315 else if (tmp < 0xffffffffffffff81LL)
2316 State.regs[dstreg] = 0x81;
2318 State.regs[dstreg] = tmp;
2320 /* 9 bit saturation */
2321 else if (IMM8 == 0x30)
2325 tmp = State.regs[REG_MCRH];
2327 tmp += State.regs[REG_MCRL];
2329 if (tmp > 0x7fffffffffffLL)
2330 tmp = 0x7fffffffffffLL;
2331 else if (tmp < 0xffff800000000000LL)
2332 tmp = 0xffff800000000000LL;
2335 State.regs[dstreg] = tmp;
2339 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2340 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2345 unsigned long sum, source1, source2;
2346 int srcreg1, srcreg2, dstreg;
2349 srcreg1 = translate_rreg (SD_, RM2);
2350 srcreg2 = translate_rreg (SD_, RN0);
2351 dstreg = translate_rreg (SD_, RD0);
2353 source1 = State.regs[srcreg1];
2354 source2 = State.regs[srcreg2];
2355 sum = source1 + source2;
2356 State.regs[dstreg] = sum;
2359 n = (sum & 0x80000000);
2360 c = (sum < source1) || (sum < source2);
2361 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2362 && (source1 & 0x80000000) != (sum & 0x80000000));
2364 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2365 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2366 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2369 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2370 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2375 unsigned long sum, source1, source2;
2376 int srcreg1, srcreg2, dstreg;
2379 srcreg1 = translate_rreg (SD_, RM2);
2380 srcreg2 = translate_rreg (SD_, RN0);
2381 dstreg = translate_rreg (SD_, RD0);
2383 source1 = State.regs[srcreg1];
2384 source2 = State.regs[srcreg2];
2385 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2386 State.regs[dstreg] = sum;
2389 n = (sum & 0x80000000);
2390 c = (sum < source1) || (sum < source2);
2391 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2392 && (source1 & 0x80000000) != (sum & 0x80000000));
2394 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2395 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2396 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2399 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2400 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2405 unsigned long difference, source1, source2;
2406 int srcreg1, srcreg2, dstreg;
2409 srcreg1 = translate_rreg (SD_, RM2);
2410 srcreg2 = translate_rreg (SD_, RN0);
2411 dstreg = translate_rreg (SD_, RD0);
2413 source1 = State.regs[srcreg1];
2414 source2 = State.regs[srcreg2];
2415 difference = source2 - source1;
2416 State.regs[dstreg] = difference;
2418 z = (difference == 0);
2419 n = (difference & 0x80000000);
2420 c = (source1 > source1);
2421 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2422 && (source1 & 0x80000000) != (difference & 0x80000000));
2424 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2425 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2426 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2429 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2430 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2435 unsigned long difference, source1, source2;
2436 int srcreg1, srcreg2, dstreg;
2439 srcreg1 = translate_rreg (SD_, RM2);
2440 srcreg2 = translate_rreg (SD_, RN0);
2441 dstreg = translate_rreg (SD_, RD0);
2443 source1 = State.regs[srcreg1];
2444 source2 = State.regs[srcreg2];
2445 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2446 State.regs[dstreg] = difference;
2448 z = (difference == 0);
2449 n = (difference & 0x80000000);
2450 c = (source1 > source2);
2451 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2452 && (source1 & 0x80000000) != (difference & 0x80000000));
2454 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2455 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2456 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2459 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2460 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2465 int srcreg1, srcreg2, dstreg;
2468 srcreg1 = translate_rreg (SD_, RM2);
2469 srcreg2 = translate_rreg (SD_, RN0);
2470 dstreg = translate_rreg (SD_, RD0);
2472 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2474 z = (State.regs[dstreg] == 0);
2475 n = (State.regs[dstreg] & 0x80000000);
2477 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2478 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2481 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2482 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2487 int srcreg1, srcreg2, dstreg;
2490 srcreg1 = translate_rreg (SD_, RM2);
2491 srcreg2 = translate_rreg (SD_, RN0);
2492 dstreg = translate_rreg (SD_, RD0);
2494 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2496 z = (State.regs[dstreg] == 0);
2497 n = (State.regs[dstreg] & 0x80000000);
2499 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2500 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2503 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2504 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2509 int srcreg1, srcreg2, dstreg;
2512 srcreg1 = translate_rreg (SD_, RM2);
2513 srcreg2 = translate_rreg (SD_, RN0);
2514 dstreg = translate_rreg (SD_, RD0);
2516 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2518 z = (State.regs[dstreg] == 0);
2519 n = (State.regs[dstreg] & 0x80000000);
2521 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2522 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2525 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2526 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2532 int srcreg1, srcreg2, dstreg;
2535 srcreg1 = translate_rreg (SD_, RM2);
2536 srcreg2 = translate_rreg (SD_, RN0);
2537 dstreg = translate_rreg (SD_, RD0);
2539 temp = State.regs[srcreg2];
2541 temp >>= State.regs[srcreg1];
2542 State.regs[dstreg] = temp;
2544 z = (State.regs[dstreg] == 0);
2545 n = (State.regs[dstreg] & 0x80000000);
2547 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2548 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2551 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2552 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2557 int srcreg1, srcreg2, dstreg;
2560 srcreg1 = translate_rreg (SD_, RM2);
2561 srcreg2 = translate_rreg (SD_, RN0);
2562 dstreg = translate_rreg (SD_, RD0);
2564 c = State.regs[srcreg2] & 1;
2565 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2567 z = (State.regs[dstreg] == 0);
2568 n = (State.regs[dstreg] & 0x80000000);
2570 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2571 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2574 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2575 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2580 int srcreg1, srcreg2, dstreg;
2583 srcreg1 = translate_rreg (SD_, RM2);
2584 srcreg2 = translate_rreg (SD_, RN0);
2585 dstreg = translate_rreg (SD_, RD0);
2587 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2589 z = (State.regs[dstreg] == 0);
2590 n = (State.regs[dstreg] & 0x80000000);
2592 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2593 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2596 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2597 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
2601 int srcreg1, srcreg2, dstreg1, dstreg2;
2602 signed long long temp;
2605 srcreg1 = translate_rreg (SD_, RM2);
2606 srcreg2 = translate_rreg (SD_, RN0);
2607 dstreg1 = translate_rreg (SD_, RD0);
2608 dstreg2 = translate_rreg (SD_, RD2);
2610 temp = ((signed64)(signed32)State.regs[srcreg1]
2611 * (signed64)(signed32)State.regs[srcreg2]);
2612 State.regs[dstreg1] = temp & 0xffffffff;
2613 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2616 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2617 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
2621 int srcreg1, srcreg2, dstreg1, dstreg2;
2622 signed long long temp;
2625 srcreg1 = translate_rreg (SD_, RM2);
2626 srcreg2 = translate_rreg (SD_, RN0);
2627 dstreg1 = translate_rreg (SD_, RD0);
2628 dstreg2 = translate_rreg (SD_, RD2);
2630 temp = ((unsigned64)(unsigned32)State.regs[srcreg1]
2631 * (unsigned64)(unsigned32)State.regs[srcreg2]);
2632 State.regs[dstreg1] = temp & 0xffffffff;
2633 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2636 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2637 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2644 dstreg = translate_rreg (SD_, RN2);
2645 State.regs[dstreg] = load_word (IMM8);
2648 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2649 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2656 srcreg = translate_rreg (SD_, RM2);
2657 store_word (IMM8, State.regs[srcreg]);
2660 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2661 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2668 dstreg = translate_rreg (SD_, RN2);
2669 State.regs[dstreg] = load_byte (IMM8);
2672 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2673 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2680 srcreg = translate_rreg (SD_, RM2);
2681 store_byte (IMM8, State.regs[srcreg]);
2684 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2685 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2692 dstreg = translate_rreg (SD_, RN2);
2693 State.regs[dstreg] = load_half (IMM8);
2696 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2697 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2704 srcreg = translate_rreg (SD_, RM2);
2705 store_half (IMM8, State.regs[srcreg]);
2708 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2709 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2713 int srcreg1, srcreg2, dstreg;
2716 srcreg1 = translate_rreg (SD_, RM0);
2717 srcreg1 = translate_rreg (SD_, RI0);
2718 dstreg = translate_rreg (SD_, RN0);
2719 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2722 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2723 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2727 int srcreg, dstreg1, dstreg2;
2730 srcreg = translate_rreg (SD_, RM0);
2731 dstreg1 = translate_rreg (SD_, RI0);
2732 dstreg2 = translate_rreg (SD_, RN0);
2733 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2736 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2737 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2741 int srcreg1, srcreg2, dstreg;
2744 srcreg1 = translate_rreg (SD_, RM0);
2745 srcreg1 = translate_rreg (SD_, RI0);
2746 dstreg = translate_rreg (SD_, RN0);
2747 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2750 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2751 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2755 int srcreg, dstreg1, dstreg2;
2758 srcreg = translate_rreg (SD_, RM0);
2759 dstreg1 = translate_rreg (SD_, RI0);
2760 dstreg2 = translate_rreg (SD_, RN0);
2761 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2764 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2765 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2769 int srcreg1, srcreg2, dstreg;
2772 srcreg1 = translate_rreg (SD_, RM0);
2773 srcreg1 = translate_rreg (SD_, RI0);
2774 dstreg = translate_rreg (SD_, RN0);
2775 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2778 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2779 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2783 int srcreg, dstreg1, dstreg2;
2786 srcreg = translate_rreg (SD_, RM0);
2787 dstreg1 = translate_rreg (SD_, RI0);
2788 dstreg2 = translate_rreg (SD_, RN0);
2789 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2792 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
2793 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mac
2797 int srcreg1, srcreg2, dstreg1, dstreg2;
2798 signed long long temp;
2803 srcreg1 = translate_rreg (SD_, RM2);
2804 srcreg2 = translate_rreg (SD_, RN0);
2805 dstreg1 = translate_rreg (SD_, RD0);
2806 dstreg2 = translate_rreg (SD_, RD2);
2808 temp = ((signed64)(signed32)State.regs[srcreg1]
2809 * (signed64)(signed32)State.regs[srcreg2]);
2811 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2812 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2813 State.regs[dstreg2] = sum;
2816 sum = State.regs[dstreg1] + temp + c;
2817 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2818 && (temp & 0x80000000) != (sum & 0x80000000));
2819 State.regs[dstreg1] = sum;
2821 State.regs[REG_MCVF] = 1;
2824 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
2825 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::macu
2829 int srcreg1, srcreg2, dstreg1, dstreg2;
2830 signed long long temp;
2835 srcreg1 = translate_rreg (SD_, RM2);
2836 srcreg2 = translate_rreg (SD_, RN0);
2837 dstreg1 = translate_rreg (SD_, RD0);
2838 dstreg2 = translate_rreg (SD_, RD2);
2840 temp = ((unsigned64)State.regs[srcreg1]
2841 * (unsigned64)State.regs[srcreg2]);
2843 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2844 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2845 State.regs[dstreg2] = sum;
2848 sum = State.regs[dstreg1] + temp + c;
2849 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2850 && (temp & 0x80000000) != (sum & 0x80000000));
2851 State.regs[dstreg1] = sum;
2853 State.regs[REG_MCVF] = 1;
2856 // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
2857 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2861 int srcreg1, srcreg2, dstreg;
2866 srcreg1 = translate_rreg (SD_, RM2);
2867 srcreg2 = translate_rreg (SD_, RN0);
2868 dstreg = translate_rreg (SD_, RD0);
2870 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2871 * (signed32)(State.regs[srcreg1] & 0xff));
2872 sum = State.regs[dstreg] + temp;
2873 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2874 && (temp & 0x80000000) != (sum & 0x80000000));
2875 State.regs[dstreg] = sum;
2877 State.regs[REG_MCVF] = 1;
2880 // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
2881 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2885 int srcreg1, srcreg2, dstreg;
2890 srcreg1 = translate_rreg (SD_, RM2);
2891 srcreg2 = translate_rreg (SD_, RN0);
2892 dstreg = translate_rreg (SD_, RD0);
2894 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2895 * (unsigned32)(State.regs[srcreg1] & 0xff));
2896 sum = State.regs[dstreg] + temp;
2897 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2898 && (temp & 0x80000000) != (sum & 0x80000000));
2899 State.regs[dstreg] = sum;
2901 State.regs[REG_MCVF] = 1;
2904 // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1
2905 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::mach
2909 int srcreg1, srcreg2, dstreg;
2914 srcreg1 = translate_rreg (SD_, RM2);
2915 srcreg2 = translate_rreg (SD_, RN0);
2916 dstreg = translate_rreg (SD_, RD0);
2918 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2919 * (signed32)(State.regs[srcreg1] & 0xffff));
2920 sum = State.regs[dstreg] + temp;
2921 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2922 && (temp & 0x80000000) != (sum & 0x80000000));
2923 State.regs[dstreg] = sum;
2925 State.regs[REG_MCVF] = 1;
2928 // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1
2929 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::machu
2933 int srcreg1, srcreg2, dstreg;
2938 srcreg1 = translate_rreg (SD_, RM2);
2939 srcreg2 = translate_rreg (SD_, RN0);
2940 dstreg = translate_rreg (SD_, RD0);
2942 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2943 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2944 sum = State.regs[dstreg] + temp;
2945 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2946 && (temp & 0x80000000) != (sum & 0x80000000));
2947 State.regs[dstreg] = sum;
2949 State.regs[REG_MCVF] = 1;
2952 // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
2953 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
2957 int srcreg1, srcreg2, dstreg;
2958 long temp, temp2, sum;
2962 srcreg1 = translate_rreg (SD_, RM2);
2963 srcreg2 = translate_rreg (SD_, RN0);
2964 dstreg = translate_rreg (SD_, RD0);
2966 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2967 * (signed32)(State.regs[srcreg1] & 0xffff));
2968 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
2969 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
2970 sum = temp + temp2 + State.regs[dstreg];
2971 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2972 && (temp & 0x80000000) != (sum & 0x80000000));
2973 State.regs[dstreg] = sum;
2975 State.regs[REG_MCVF] = 1;
2978 // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
2979 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
2983 int srcreg1, srcreg2, dstreg;
2984 long temp, temp2, sum;
2988 srcreg1 = translate_rreg (SD_, RM2);
2989 srcreg2 = translate_rreg (SD_, RN0);
2990 dstreg = translate_rreg (SD_, RD0);
2992 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2993 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2994 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
2995 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
2996 sum = temp + temp2 + State.regs[dstreg];
2997 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2998 && (temp & 0x80000000) != (sum & 0x80000000));
2999 State.regs[dstreg] = sum;
3001 State.regs[REG_MCVF] = 1;
3004 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3005 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulh
3009 int srcreg1, srcreg2, dstreg1, dstreg2;
3010 signed long long temp;
3013 srcreg1 = translate_rreg (SD_, RM2);
3014 srcreg2 = translate_rreg (SD_, RN0);
3015 dstreg1 = translate_rreg (SD_, RD0);
3016 dstreg2 = translate_rreg (SD_, RD2);
3018 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3019 * (signed32)(State.regs[srcreg1] & 0xffff));
3020 State.regs[dstreg2] = temp;
3021 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3022 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3023 State.regs[dstreg1] = temp;
3026 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3027 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulhu
3031 int srcreg1, srcreg2, dstreg1, dstreg2;
3032 signed long long temp;
3035 srcreg1 = translate_rreg (SD_, RM2);
3036 srcreg2 = translate_rreg (SD_, RN0);
3037 dstreg1 = translate_rreg (SD_, RD0);
3038 dstreg2 = translate_rreg (SD_, RD2);
3040 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3041 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3042 State.regs[dstreg2] = temp;
3043 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3044 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3045 State.regs[dstreg1] = temp;
3048 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3049 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3057 srcreg = translate_rreg (SD_, RM2);
3058 dstreg = translate_rreg (SD_, RN0);
3060 value = State.regs[srcreg];
3062 if (value >= 0x7fffff)
3063 State.regs[dstreg] = 0x7fffff;
3064 else if (value <= 0xff800000)
3065 State.regs[dstreg] = 0xff800000;
3067 State.regs[dstreg] = value;
3070 // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
3071 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3076 int srcreg1, srcreg2, dstreg;
3080 srcreg1 = translate_rreg (SD_, RM2);
3081 srcreg2 = translate_rreg (SD_, RN0);
3082 dstreg = translate_rreg (SD_, RD0);
3084 temp = State.regs[srcreg1];
3085 start = (State.regs[srcreg2] & 0x1f) - 1;
3089 for (i = start; i >= 0; i--)
3091 if (temp & (1 << i))
3094 State.regs[dstreg] = i;
3102 State.regs[dstreg] = 0;
3105 PSW |= (c ? PSW_C : 0);
3108 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3109 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3116 dstreg = translate_rreg (SD_, RN0);
3117 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3120 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
3121 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3128 dstreg = translate_rreg (SD_, RN0);
3129 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3132 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
3133 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3140 dstreg = translate_rreg (SD_, RN0);
3141 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3144 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
3145 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3149 int dstreg, z, n, c, v;
3150 unsigned long sum, imm, reg2;
3153 dstreg = translate_rreg (SD_, RN0);
3155 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3156 reg2 = State.regs[dstreg];
3157 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3158 State.regs[dstreg] = sum;
3161 n = (sum & 0x80000000);
3162 c = (sum < imm) || (sum < reg2);
3163 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3164 && (reg2 & 0x80000000) != (sum & 0x80000000));
3166 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3167 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3168 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3171 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
3172 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3179 dstreg = translate_rreg (SD_, RN0);
3180 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3183 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
3184 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3188 int dstreg, z, n, c, v;
3189 unsigned long difference, imm, reg2;
3192 dstreg = translate_rreg (SD_, RN0);
3194 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3195 reg2 = State.regs[dstreg];
3196 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3197 State.regs[dstreg] = difference;
3199 z = (difference == 0);
3200 n = (difference & 0x80000000);
3202 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3203 && (reg2 & 0x80000000) != (difference & 0x80000000));
3205 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3206 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3207 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3210 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
3211 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3218 srcreg = translate_rreg (SD_, RN0);
3219 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3222 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
3223 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3231 State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3237 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3238 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3246 dstreg = translate_rreg (SD_, RN0);
3248 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3249 z = (State.regs[dstreg] == 0);
3250 n = (State.regs[dstreg] & 0x80000000) != 0;
3251 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3252 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3255 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3256 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3264 dstreg = translate_rreg (SD_, RN0);
3266 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3267 z = (State.regs[dstreg] == 0);
3268 n = (State.regs[dstreg] & 0x80000000) != 0;
3269 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3270 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3273 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3274 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3282 dstreg = translate_rreg (SD_, RN0);
3284 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3285 z = (State.regs[dstreg] == 0);
3286 n = (State.regs[dstreg] & 0x80000000) != 0;
3287 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3288 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3291 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3292 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3301 dstreg = translate_rreg (SD_, RN0);
3303 temp = State.regs[dstreg];
3305 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3306 State.regs[dstreg] = temp;
3307 z = (State.regs[dstreg] == 0);
3308 n = (State.regs[dstreg] & 0x80000000) != 0;
3309 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3310 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3314 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3315 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3323 dstreg = translate_rreg (SD_, RN0);
3325 c = State.regs[dstreg] & 1;
3326 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3327 z = (State.regs[dstreg] == 0);
3328 n = (State.regs[dstreg] & 0x80000000) != 0;
3329 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3330 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3333 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3334 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3342 dstreg = translate_rreg (SD_, RN0);
3344 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3345 z = (State.regs[dstreg] == 0);
3346 n = (State.regs[dstreg] & 0x80000000) != 0;
3347 PSW &= ~(PSW_Z | PSW_N);
3348 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3351 // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3352 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3357 unsigned long long temp;
3361 dstreg = translate_rreg (SD_, RN0);
3363 temp = ((signed64)(signed32)State.regs[dstreg]
3364 * (signed64)(signed32)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3365 State.regs[dstreg] = temp & 0xffffffff;
3366 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3367 z = (State.regs[dstreg] == 0);
3368 n = (State.regs[dstreg] & 0x80000000) != 0;
3369 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3370 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3373 // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3374 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3379 unsigned long long temp;
3383 dstreg = translate_rreg (SD_, RN0);
3385 temp = ((unsigned64)State.regs[dstreg]
3386 * (unsigned64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3387 State.regs[dstreg] = temp & 0xffffffff;
3388 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3389 z = (State.regs[dstreg] == 0);
3390 n = (State.regs[dstreg] & 0x80000000) != 0;
3391 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3392 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3395 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3396 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3403 srcreg = translate_rreg (SD_, RN0);
3404 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3407 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3408 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3415 srcreg = translate_rreg (SD_, RM0);
3416 dstreg = translate_rreg (SD_, RN2);
3417 State.regs[dstreg] = load_word (State.regs[srcreg]
3418 + FETCH24 (IMM24A, IMM24B, IMM24C));
3421 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3422 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3429 srcreg = translate_rreg (SD_, RM2);
3430 dstreg = translate_rreg (SD_, RN0);
3431 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3432 State.regs[srcreg]);
3435 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3436 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3443 srcreg = translate_rreg (SD_, RM0);
3444 dstreg = translate_rreg (SD_, RN2);
3445 State.regs[dstreg] = load_byte (State.regs[srcreg]
3446 + FETCH24 (IMM24A, IMM24B, IMM24C));
3449 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3450 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3457 srcreg = translate_rreg (SD_, RM2);
3458 dstreg = translate_rreg (SD_, RN0);
3459 store_byte (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3460 State.regs[srcreg]);
3463 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3464 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3471 srcreg = translate_rreg (SD_, RM0);
3472 dstreg = translate_rreg (SD_, RN2);
3473 State.regs[dstreg] = load_half (State.regs[srcreg]
3474 + FETCH24 (IMM24A, IMM24B, IMM24C));
3477 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3478 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3485 srcreg = translate_rreg (SD_, RM2);
3486 dstreg = translate_rreg (SD_, RN0);
3487 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3488 State.regs[srcreg]);
3491 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3492 8.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3499 srcreg = translate_rreg (SD_, RM0);
3500 dstreg = translate_rreg (SD_, RN2);
3501 State.regs[dstreg] = load_word (State.regs[srcreg]
3502 + FETCH24 (IMM24A, IMM24B, IMM24C));
3503 State.regs[srcreg] += 4;
3506 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3507 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3514 srcreg = translate_rreg (SD_, RM2);
3515 dstreg = translate_rreg (SD_, RN0);
3516 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3517 State.regs[srcreg]);
3518 State.regs[dstreg] += 4;
3522 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3523 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3530 dstreg = translate_rreg (SD_, RN2);
3531 State.regs[dstreg] = load_word (State.regs[REG_SP]
3532 + FETCH24 (IMM24A, IMM24B, IMM24C));
3535 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3536 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3543 srcreg = translate_rreg (SD_, RM2);
3544 store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3545 State.regs[srcreg]);
3548 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
3549 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3556 dstreg = translate_rreg (SD_, RN2);
3557 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3558 + FETCH24 (IMM24A, IMM24B, IMM24C));
3561 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3562 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3569 srcreg = translate_rreg (SD_, RM2);
3570 store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3571 State.regs[srcreg]);
3574 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3575 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3582 dstreg = translate_rreg (SD_, RN2);
3583 State.regs[dstreg] = load_half (State.regs[REG_SP]
3584 + FETCH24 (IMM24A, IMM24B, IMM24C));
3587 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3588 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3595 srcreg = translate_rreg (SD_, RM2);
3596 store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3597 State.regs[srcreg]);
3600 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3601 8.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3608 srcreg = translate_rreg (SD_, RM0);
3609 dstreg = translate_rreg (SD_, RN2);
3610 State.regs[dstreg] = load_half (State.regs[srcreg]
3611 + FETCH24 (IMM24A, IMM24B, IMM24C));
3612 State.regs[dstreg] += 2;
3615 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3616 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3623 srcreg = translate_rreg (SD_, RM2);
3624 dstreg = translate_rreg (SD_, RN0);
3625 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3626 State.regs[srcreg]);
3627 State.regs[srcreg] += 2;
3630 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
3631 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3636 long long temp, sum;
3640 srcreg = translate_rreg (SD_, RN2);
3642 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3643 * (signed64)State.regs[srcreg]);
3644 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3645 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3646 State.regs[REG_MCRL] = sum;
3649 sum = State.regs[REG_MCRH] + temp + c;
3650 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3651 && (temp & 0x80000000) != (sum & 0x80000000));
3652 State.regs[REG_MCRH] = sum;
3654 State.regs[REG_MCVF] = 1;
3657 // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
3658 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3663 long long temp, sum;
3667 srcreg = translate_rreg (SD_, RN2);
3669 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3670 * (unsigned64)State.regs[srcreg]);
3671 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3672 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3673 State.regs[REG_MCRL] = sum;
3676 sum = State.regs[REG_MCRH] + temp + c;
3677 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3678 && (temp & 0x80000000) != (sum & 0x80000000));
3679 State.regs[REG_MCRH] = sum;
3681 State.regs[REG_MCVF] = 1;
3684 // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
3685 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3690 long long temp, sum;
3694 srcreg = translate_rreg (SD_, RN2);
3696 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3697 * (signed64)State.regs[srcreg] & 0xff);
3698 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3699 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3700 State.regs[REG_MCRL] = sum;
3703 sum = State.regs[REG_MCRH] + temp + c;
3704 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3705 && (temp & 0x80000000) != (sum & 0x80000000));
3706 State.regs[REG_MCRH] = sum;
3708 State.regs[REG_MCVF] = 1;
3711 // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
3712 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3717 long long temp, sum;
3721 srcreg = translate_rreg (SD_, RN2);
3723 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3724 * (unsigned64)State.regs[srcreg] & 0xff);
3725 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3726 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3727 State.regs[REG_MCRL] = sum;
3730 sum = State.regs[REG_MCRH] + temp + c;
3731 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3732 && (temp & 0x80000000) != (sum & 0x80000000));
3733 State.regs[REG_MCRH] = sum;
3735 State.regs[REG_MCVF] = 1;
3738 // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
3739 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3744 long long temp, sum;
3748 srcreg = translate_rreg (SD_, RN2);
3750 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3751 * (signed64)State.regs[srcreg] & 0xffff);
3752 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3753 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3754 State.regs[REG_MCRL] = sum;
3757 sum = State.regs[REG_MCRH] + temp + c;
3758 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3759 && (temp & 0x80000000) != (sum & 0x80000000));
3760 State.regs[REG_MCRH] = sum;
3762 State.regs[REG_MCVF] = 1;
3765 // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
3766 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3771 long long temp, sum;
3775 srcreg = translate_rreg (SD_, RN2);
3777 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3778 * (unsigned64)State.regs[srcreg] & 0xffff);
3779 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3780 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3781 State.regs[REG_MCRL] = sum;
3784 sum = State.regs[REG_MCRH] + temp + c;
3785 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3786 && (temp & 0x80000000) != (sum & 0x80000000));
3787 State.regs[REG_MCRH] = sum;
3789 State.regs[REG_MCVF] = 1;
3792 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3793 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3800 dstreg = translate_rreg (SD_, RN2);
3801 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3804 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3805 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3812 srcreg = translate_rreg (SD_, RM2);
3813 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3817 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3818 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3825 dstreg = translate_rreg (SD_, RN2);
3826 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3829 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3830 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3837 srcreg = translate_rreg (SD_, RM2);
3838 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3842 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3843 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3850 dstreg = translate_rreg (SD_, RN2);
3851 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3854 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3855 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3862 srcreg = translate_rreg (SD_, RM2);
3863 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3867 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3868 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3875 dstreg = translate_rreg (SD_, RN0);
3876 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3879 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3880 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3887 dstreg = translate_rreg (SD_, RN0);
3888 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3891 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3892 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3899 dstreg = translate_rreg (SD_, RN0);
3900 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3903 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3904 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3909 unsigned int imm, reg2, sum;
3913 dstreg = translate_rreg (SD_, RN0);
3915 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3916 reg2 = State.regs[dstreg];
3917 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3918 State.regs[dstreg] = sum;
3921 n = (sum & 0x80000000);
3922 c = (sum < imm) || (sum < reg2);
3923 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3924 && (reg2 & 0x80000000) != (sum & 0x80000000));
3926 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3927 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3928 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3931 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
3932 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3939 dstreg = translate_rreg (SD_, RN0);
3940 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3943 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
3944 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
3949 unsigned int imm, reg2, difference;
3953 dstreg = translate_rreg (SD_, RN0);
3955 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3956 reg2 = State.regs[dstreg];
3957 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3958 State.regs[dstreg] = difference;
3960 z = (difference == 0);
3961 n = (difference & 0x80000000);
3963 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3964 && (reg2 & 0x80000000) != (difference & 0x80000000));
3966 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3967 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3968 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3971 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
3972 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
3979 srcreg = translate_rreg (SD_, RN0);
3980 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3983 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
3984 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
3991 State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3996 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
3997 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4005 dstreg = translate_rreg (SD_, RN0);
4007 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4008 z = (State.regs[dstreg] == 0);
4009 n = (State.regs[dstreg] & 0x80000000) != 0;
4010 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4011 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4014 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
4015 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4023 dstreg = translate_rreg (SD_, RN0);
4025 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4026 z = (State.regs[dstreg] == 0);
4027 n = (State.regs[dstreg] & 0x80000000) != 0;
4028 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4029 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4032 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
4033 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4041 dstreg = translate_rreg (SD_, RN0);
4043 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4044 z = (State.regs[dstreg] == 0);
4045 n = (State.regs[dstreg] & 0x80000000) != 0;
4046 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4047 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4050 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
4051 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4060 dstreg = translate_rreg (SD_, RN0);
4062 temp = State.regs[dstreg];
4064 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4065 State.regs[dstreg] = temp;
4066 z = (State.regs[dstreg] == 0);
4067 n = (State.regs[dstreg] & 0x80000000) != 0;
4068 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4069 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4072 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
4073 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4081 dstreg = translate_rreg (SD_, RN0);
4083 c = State.regs[dstreg] & 1;
4084 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4085 z = (State.regs[dstreg] == 0);
4086 n = (State.regs[dstreg] & 0x80000000) != 0;
4087 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4088 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4091 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
4092 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4100 dstreg = translate_rreg (SD_, RN0);
4102 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4103 z = (State.regs[dstreg] == 0);
4104 n = (State.regs[dstreg] & 0x80000000) != 0;
4105 PSW &= ~(PSW_Z | PSW_N);
4106 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4112 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
4113 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4120 srcreg = translate_rreg (SD_, RN0);
4121 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4124 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
4125 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4132 srcreg = translate_rreg (SD_, RM0);
4133 dstreg = translate_rreg (SD_, RN2);
4134 State.regs[dstreg] = load_word (State.regs[srcreg]
4135 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4138 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
4139 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4146 srcreg = translate_rreg (SD_, RM2);
4147 dstreg = translate_rreg (SD_, RN0);
4148 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4149 State.regs[srcreg]);
4152 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
4153 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4160 srcreg = translate_rreg (SD_, RM0);
4161 dstreg = translate_rreg (SD_, RN2);
4162 State.regs[dstreg] = load_byte (State.regs[srcreg]
4163 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4166 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
4167 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4174 srcreg = translate_rreg (SD_, RM2);
4175 dstreg = translate_rreg (SD_, RN0);
4176 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4177 State.regs[srcreg]);
4180 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
4181 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4188 srcreg = translate_rreg (SD_, RM0);
4189 dstreg = translate_rreg (SD_, RN2);
4190 State.regs[dstreg] = load_half (State.regs[srcreg]
4191 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4194 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
4195 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4202 srcreg = translate_rreg (SD_, RM2);
4203 dstreg = translate_rreg (SD_, RN0);
4204 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4205 State.regs[srcreg]);
4208 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
4209 8.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4216 srcreg = translate_rreg (SD_, RM0);
4217 dstreg = translate_rreg (SD_, RN2);
4218 State.regs[dstreg] = load_word (State.regs[srcreg]
4219 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4220 State.regs[srcreg] += 4;
4223 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
4224 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4231 srcreg = translate_rreg (SD_, RM2);
4232 dstreg = translate_rreg (SD_, RN0);
4233 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4234 State.regs[srcreg]);
4235 State.regs[dstreg] += 4;
4239 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
4240 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4247 dstreg = translate_rreg (SD_, RN2);
4248 State.regs[dstreg] = load_word (State.regs[REG_SP]
4249 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4252 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
4253 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4260 srcreg = translate_rreg (SD_, RM2);
4261 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4262 State.regs[srcreg]);
4265 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
4266 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4273 dstreg = translate_rreg (SD_, RN2);
4274 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4275 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4278 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
4279 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4286 srcreg = translate_rreg (SD_, RM2);
4287 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4288 State.regs[srcreg]);
4291 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4292 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4299 dstreg = translate_rreg (SD_, RN2);
4300 State.regs[dstreg] = load_half (State.regs[REG_SP]
4301 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4304 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4305 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4312 srcreg = translate_rreg (SD_, RM2);
4313 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4314 State.regs[srcreg]);
4318 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
4319 8.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4326 srcreg = translate_rreg (SD_, RM0);
4327 dstreg = translate_rreg (SD_, RN2);
4328 State.regs[dstreg] = load_half (State.regs[srcreg]
4329 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4330 State.regs[srcreg] += 2;
4333 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
4334 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4341 srcreg = translate_rreg (SD_, RM2);
4342 dstreg = translate_rreg (SD_, RN0);
4343 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4344 State.regs[srcreg]);
4345 State.regs[dstreg] += 2;
4360 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4361 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4368 dstreg = translate_rreg (SD_, RN2);
4369 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4372 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4373 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4380 srcreg = translate_rreg (SD_, RM2);
4381 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4384 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4385 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4392 dstreg = translate_rreg (SD_, RN2);
4393 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4396 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4397 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4404 srcreg = translate_rreg (SD_, RM2);
4405 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4408 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4409 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4416 dstreg = translate_rreg (SD_, RN2);
4417 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4420 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4421 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4428 srcreg = translate_rreg (SD_, RM2);
4429 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);