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[deliverable/binutils-gdb.git] / sim / mn10300 / am33.igen
1 // Helper:
2 //
3 // Given an extended register number, translate it into an index into the
4 // register array. This is necessary as the upper 8 extended registers are
5 // actually synonyms for the d0-d3/a0-a3 registers.
6 //
7 //
8
9 :function:::int:translate_rreg:int rreg
10 {
11
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
18 else
19 return REG_E0 + rreg;
20 }
21
22 :function:::int:translate_xreg:int xreg
23 {
24 switch (xreg)
25 {
26 case 0:
27 return REG_SP;
28 case 1:
29 return REG_MDRQ;
30 case 2:
31 return REG_MCRH;
32 case 3:
33 return REG_MCRL;
34 case 4:
35 return REG_MCVF;
36 default:
37 abort ();
38 }
39 }
40
41 // 1111 0000 0010 00An; mov USP,An
42 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
43 "mov"
44 *am33
45 {
46 PC = cia;
47 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
48 }
49
50
51 // 1111 0000 0010 01An; mov SSP,An
52 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
53 "mov"
54 *am33
55 {
56 PC = cia;
57 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
58 }
59
60
61 // 1111 0000 0010 10An; mov MSP,An
62 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
63 "mov"
64 *am33
65 {
66 PC = cia;
67 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
68 }
69
70
71 // 1111 0000 0010 11An; mov PC,An
72 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
73 "mov"
74 *am33
75 {
76 PC = cia;
77 State.regs[REG_A0 + AN0] = PC;
78 }
79
80
81 // 1111 0000 0011 Am00; mov Am,USP
82 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
83 "mov"
84 *am33
85 {
86 PC = cia;
87 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
88 }
89
90 // 1111 0000 0011 Am01; mov Am,SSP
91 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
92 "mov"
93 *am33
94 {
95 PC = cia;
96 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
97 }
98
99 // 1111 0000 0011 Am10; mov Am,MSP
100 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
101 "mov"
102 *am33
103 {
104 PC = cia;
105 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
106 }
107
108
109 // 1111 0000 1110 imm4; syscall
110 8.0xf0+4.0xe,IMM4:D0t:::syscall
111 "syscall"
112 *am33
113 {
114 unsigned32 sp, next_pc;
115
116 PC = cia;
117 sp = State.regs[REG_SP];
118 next_pc = State.regs[REG_PC] + 2;
119 store_word (sp - 4, next_pc);
120 store_word (sp - 8, PSW);
121 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
122 nia = PC;
123 }
124
125
126 // 1111 0010 1110 11Dn; mov EPSW,Dn
127 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
128 "mov"
129 *am33
130 {
131 PC = cia;
132 State.regs[REG_D0 + DN0] = PSW;
133 }
134
135
136 // 1111 0010 1111 Dm01; mov Dm,EPSW
137 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
138 "mov"
139 *am33
140 {
141 PC = cia;
142 PSW = State.regs[REG_D0 + DM1];
143 }
144
145 // 1111 0101 00Am Rn; mov Am,Rn
146 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
147 "mov"
148 *am33
149 {
150 int destreg = translate_rreg (SD_, RN0);
151
152 PC = cia;
153 State.regs[destreg] = State.regs[REG_A0 + AM1];
154 }
155
156 // 1111 0101 01Dm Rn; mov Dm,Rn
157 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
158 "mov"
159 *am33
160 {
161 int destreg = translate_rreg (SD_, RN0);
162
163 PC = cia;
164 State.regs[destreg] = State.regs[REG_D0 + DM1];
165 }
166
167 // 1111 0101 10Rm An; mov Rm,An
168 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
169 "mov"
170 *am33
171 {
172 int destreg = translate_rreg (SD_, RM1);
173
174 PC = cia;
175 State.regs[REG_A0 + AN0] = State.regs[destreg];
176 }
177
178 // 1111 0101 11Rm Dn; mov Rm,Dn
179 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
180 "mov"
181 *am33
182 {
183 int destreg = translate_rreg (SD_, RM1);
184
185 PC = cia;
186 State.regs[REG_D0 + DN0] = State.regs[destreg];
187 }
188
189
190 // 1111 1000 1100 1110 regs....; movm (USP),regs
191 8.0xf8+8.0xce+8.REGS:D1a:::movm
192 "movm"
193 *am33
194 {
195 unsigned32 usp = State.regs[REG_USP];
196 unsigned32 mask;
197
198 PC = cia;
199 mask = REGS;
200
201 if (mask & 0x8)
202 {
203 usp += 4;
204 State.regs[REG_LAR] = load_word (usp);
205 usp += 4;
206 State.regs[REG_LIR] = load_word (usp);
207 usp += 4;
208 State.regs[REG_MDR] = load_word (usp);
209 usp += 4;
210 State.regs[REG_A0 + 1] = load_word (usp);
211 usp += 4;
212 State.regs[REG_A0] = load_word (usp);
213 usp += 4;
214 State.regs[REG_D0 + 1] = load_word (usp);
215 usp += 4;
216 State.regs[REG_D0] = load_word (usp);
217 usp += 4;
218 }
219
220 if (mask & 0x10)
221 {
222 State.regs[REG_A0 + 3] = load_word (usp);
223 usp += 4;
224 }
225
226 if (mask & 0x20)
227 {
228 State.regs[REG_A0 + 2] = load_word (usp);
229 usp += 4;
230 }
231
232 if (mask & 0x40)
233 {
234 State.regs[REG_D0 + 3] = load_word (usp);
235 usp += 4;
236 }
237
238 if (mask & 0x80)
239 {
240 State.regs[REG_D0 + 2] = load_word (usp);
241 usp += 4;
242 }
243
244 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
245 )
246 {
247 if (mask & 0x1)
248 {
249 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
250 usp += 16;
251 State.regs[REG_E0 + 1] = load_word (usp);
252 usp += 4;
253 State.regs[REG_E0 + 0] = load_word (usp);
254 usp += 4;
255 }
256
257 if (mask & 0x2)
258 {
259 State.regs[REG_E0 + 7] = load_word (usp);
260 usp += 4;
261 State.regs[REG_E0 + 6] = load_word (usp);
262 usp += 4;
263 State.regs[REG_E0 + 5] = load_word (usp);
264 usp += 4;
265 State.regs[REG_E0 + 4] = load_word (usp);
266 usp += 4;
267 }
268
269 if (mask & 0x4)
270 {
271 State.regs[REG_E0 + 3] = load_word (usp);
272 usp += 4;
273 State.regs[REG_E0 + 2] = load_word (usp);
274 usp += 4;
275 }
276 }
277
278 /* And make sure to update the stack pointer. */
279 State.regs[REG_USP] = usp;
280 }
281
282 // 1111 1000 1100 1111 regs....; movm (USP),regs
283 8.0xf8+8.0xcf+8.REGS:D1b:::movm
284 "movm"
285 *am33
286 {
287 unsigned32 usp = State.regs[REG_USP];
288 unsigned32 mask;
289
290 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
291 )
292 {
293 if (mask & 0x4)
294 {
295 usp -= 4;
296 store_word (usp, State.regs[REG_E0 + 2]);
297 usp -= 4;
298 store_word (usp, State.regs[REG_E0 + 3]);
299 }
300
301 if (mask & 0x2)
302 {
303 usp -= 4;
304 store_word (usp, State.regs[REG_E0 + 4]);
305 usp -= 4;
306 store_word (usp, State.regs[REG_E0 + 5]);
307 usp -= 4;
308 store_word (usp, State.regs[REG_E0 + 6]);
309 usp -= 4;
310 store_word (usp, State.regs[REG_E0 + 7]);
311 }
312
313 if (mask & 0x1)
314 {
315 usp -= 4;
316 store_word (usp, State.regs[REG_E0 + 0]);
317 usp -= 4;
318 store_word (usp, State.regs[REG_E0 + 1]);
319 usp -= 16;
320 /* Need to save MDQR, MCRH, MCRL, and MCVF */
321 }
322 }
323
324 if (mask & 0x80)
325 {
326 usp -= 4;
327 store_word (usp, State.regs[REG_D0 + 2]);
328 }
329
330 if (mask & 0x40)
331 {
332 usp -= 4;
333 store_word (usp, State.regs[REG_D0 + 3]);
334 }
335
336 if (mask & 0x20)
337 {
338 usp -= 4;
339 store_word (usp, State.regs[REG_A0 + 2]);
340 }
341
342 if (mask & 0x10)
343 {
344 usp -= 4;
345 store_word (usp, State.regs[REG_A0 + 3]);
346 }
347
348 if (mask & 0x8)
349 {
350 usp -= 4;
351 store_word (usp, State.regs[REG_D0]);
352 usp -= 4;
353 store_word (usp, State.regs[REG_D0 + 1]);
354 usp -= 4;
355 store_word (usp, State.regs[REG_A0]);
356 usp -= 4;
357 store_word (usp, State.regs[REG_A0 + 1]);
358 usp -= 4;
359 store_word (usp, State.regs[REG_MDR]);
360 usp -= 4;
361 store_word (usp, State.regs[REG_LIR]);
362 usp -= 4;
363 store_word (usp, State.regs[REG_LAR]);
364 usp -= 4;
365 }
366
367 /* And make sure to update the stack pointer. */
368 State.regs[REG_USP] = usp;
369 }
370
371 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
372 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
373 "and"
374 *am33
375 {
376 PC = cia;
377 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
378 }
379
380 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
381 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
382 "or"
383 *am33
384 {
385 PC = cia;
386 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
387 }
388
389 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
390 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
391 "mov"
392 *am33
393 {
394 int srcreg, dstreg;
395
396 PC = cia;
397
398 srcreg = translate_rreg (SD_, RM2);
399 dstreg = translate_rreg (SD_, RN0);
400 State.regs[dstreg] = State.regs[srcreg];
401 }
402
403 // 1111 1001 0001 1000 Rn Rn; ext Rn
404 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
405 "mov"
406 *am33
407 {
408 int srcreg;
409
410 PC = cia;
411 srcreg = translate_rreg (SD_, RN0);
412 if (State.regs[srcreg] & 0x80000000)
413 State.regs[REG_MDR] = -1;
414 else
415 State.regs[REG_MDR] = 0;
416 }
417
418 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
419 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
420 "extb"
421 *am33
422 {
423 int srcreg, dstreg;
424
425 PC = cia;
426 srcreg = translate_rreg (SD_, RM2);
427 dstreg = translate_rreg (SD_, RN0);
428 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
429 }
430
431 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
432 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
433 "extbu"
434 *am33
435 {
436 int srcreg, dstreg;
437
438 PC = cia;
439 srcreg = translate_rreg (SD_, RM2);
440 dstreg = translate_rreg (SD_, RN0);
441 State.regs[dstreg] = State.regs[srcreg] & 0xff;
442 }
443
444 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
445 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
446 "exth"
447 *am33
448 {
449 int srcreg, dstreg;
450
451 PC = cia;
452 srcreg = translate_rreg (SD_, RM2);
453 dstreg = translate_rreg (SD_, RN0);
454 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
455 }
456
457 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
458 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
459 "exthu"
460 *am33
461 {
462 int srcreg, dstreg;
463
464 PC = cia;
465 srcreg = translate_rreg (SD_, RM2);
466 dstreg = translate_rreg (SD_, RN0);
467 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
468 }
469
470 // 1111 1001 0110 1000 Rn Rn; clr Rn
471 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
472 "clr"
473 *am33
474 {
475 int dstreg;
476
477 PC = cia;
478 dstreg = translate_rreg (SD_, RN0);
479 State.regs[dstreg] = 0;
480 PSW |= PSW_Z;
481 PSW &= ~(PSW_V | PSW_C | PSW_N);
482 }
483
484 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
485 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
486 "add"
487 *am33
488 {
489 int srcreg, dstreg;
490
491 PC = cia;
492 srcreg = translate_rreg (SD_, RM2);
493 dstreg = translate_rreg (SD_, RN0);
494 genericAdd (State.regs[srcreg], dstreg);
495 }
496
497 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
498 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
499 "addc"
500 *am33
501 {
502 int srcreg, dstreg;
503 int z, c, n, v;
504 unsigned32 reg1, reg2, sum;
505
506 PC = cia;
507 srcreg = translate_rreg (SD_, RM2);
508 dstreg = translate_rreg (SD_, RN0);
509
510 reg1 = State.regs[srcreg];
511 reg2 = State.regs[dstreg];
512 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
513 State.regs[dstreg] = sum;
514
515 z = ((PSW & PSW_Z) != 0) && (sum == 0);
516 n = (sum & 0x80000000);
517 c = (sum < reg1) || (sum < reg2);
518 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
519 && (reg2 & 0x80000000) != (sum & 0x80000000));
520
521 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
522 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
523 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
524 }
525
526 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
527 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
528 "sub"
529 *am33
530 {
531 int srcreg, dstreg;
532
533 PC = cia;
534 srcreg = translate_rreg (SD_, RM2);
535 dstreg = translate_rreg (SD_, RN0);
536 genericSub (State.regs[srcreg], dstreg);
537 }
538
539 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
540 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
541 "subc"
542 *am33
543 {
544 int srcreg, dstreg;
545 int z, c, n, v;
546 unsigned32 reg1, reg2, difference;
547
548 PC = cia;
549 srcreg = translate_rreg (SD_, RM2);
550 dstreg = translate_rreg (SD_, RN0);
551
552 reg1 = State.regs[srcreg];
553 reg2 = State.regs[dstreg];
554 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
555 State.regs[dstreg] = difference;
556
557 z = ((PSW & PSW_Z) != 0) && (difference == 0);
558 n = (difference & 0x80000000);
559 c = (reg1 > reg2);
560 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
561 && (reg2 & 0x80000000) != (difference & 0x80000000));
562
563 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
564 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
565 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
566 }
567
568 // 1111 1001 1011 1000 Rn Rn; inc Rn
569 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
570 "inc"
571 *am33
572 {
573 int dstreg;
574
575 PC = cia;
576 dstreg = translate_rreg (SD_, RN0);
577 genericAdd (1, dstreg);
578 }
579
580 // 1111 1001 1101 1000 Rn Rn; inc Rn
581 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
582 "inc4"
583 *am33
584 {
585 int dstreg;
586
587 PC = cia;
588 dstreg = translate_rreg (SD_, RN0);
589 genericAdd (4, dstreg);
590 }
591
592 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
593 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
594 "cmp"
595 *am33
596 {
597 int srcreg1, srcreg2;
598
599 PC = cia;
600 srcreg1 = translate_rreg (SD_, RN0);
601 srcreg2 = translate_rreg (SD_, RM2);
602 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
603 }
604
605 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
606 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
607 "mov"
608 *am33
609 {
610 int dstreg, srcreg;
611
612 PC = cia;
613 dstreg = translate_rreg (SD_, RN0);
614 srcreg = translate_xreg (SD_, XRM2);
615
616 State.regs[dstreg] = State.regs[srcreg];
617 }
618
619 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
620 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
621 "mov"
622 *am33
623 {
624 int srcreg, dstreg;
625
626 PC = cia;
627 srcreg = translate_rreg (SD_, RM2);
628 dstreg = translate_xreg (SD_, XRN0);
629
630 State.regs[dstreg] = State.regs[srcreg];
631 }
632
633 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
634 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
635 "and"
636 *am33
637 {
638 int srcreg, dstreg;
639 int z, n;
640
641 PC = cia;
642
643 srcreg = translate_rreg (SD_, RM2);
644 dstreg = translate_rreg (SD_, RN0);
645
646 State.regs[dstreg] &= State.regs[srcreg];
647 z = (State.regs[dstreg] == 0);
648 n = (State.regs[dstreg] & 0x80000000) != 0;
649 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
650 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
651 }
652
653 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
654 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
655 "or"
656 *am33
657 {
658 int srcreg, dstreg;
659 int z, n;
660
661 PC = cia;
662 srcreg = translate_rreg (SD_, RM2);
663 dstreg = translate_rreg (SD_, RN0);
664
665 State.regs[dstreg] |= State.regs[srcreg];
666 z = (State.regs[dstreg] == 0);
667 n = (State.regs[dstreg] & 0x80000000) != 0;
668 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
669 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
670 }
671
672 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
673 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
674 "xor"
675 *am33
676 {
677 int srcreg, dstreg;
678 int z, n;
679
680 PC = cia;
681 srcreg = translate_rreg (SD_, RM2);
682 dstreg = translate_rreg (SD_, RN0);
683
684 State.regs[dstreg] ^= State.regs[srcreg];
685 z = (State.regs[dstreg] == 0);
686 n = (State.regs[dstreg] & 0x80000000) != 0;
687 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
688 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
689 }
690
691 // 1111 1001 0011 1001 Rn Rn; not Rn
692 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
693 "not"
694 *am33
695 {
696 int dstreg;
697 int z, n;
698
699 PC = cia;
700 dstreg = translate_rreg (SD_, RN0);
701
702 State.regs[dstreg] = ~State.regs[dstreg];
703 z = (State.regs[dstreg] == 0);
704 n = (State.regs[dstreg] & 0x80000000) != 0;
705 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
706 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
707 }
708
709 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
710 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
711 "asr"
712 *am33
713 {
714 int srcreg, dstreg;
715 signed32 temp;
716 int c, z, n;
717
718 PC = cia;
719 srcreg = translate_rreg (SD_, RM2);
720 dstreg = translate_rreg (SD_, RN0);
721
722 temp = State.regs[dstreg];
723 c = temp & 1;
724 temp >>= State.regs[srcreg];
725 State.regs[dstreg] = temp;
726 z = (State.regs[dstreg] == 0);
727 n = (State.regs[dstreg] & 0x80000000) != 0;
728 PSW &= ~(PSW_Z | PSW_N | PSW_C);
729 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
730 }
731
732 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
733 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
734 "lsr"
735 *am33
736 {
737 int srcreg, dstreg;
738 int z, n, c;
739
740 PC = cia;
741
742 srcreg = translate_rreg (SD_, RM2);
743 dstreg = translate_rreg (SD_, RN0);
744
745 c = State.regs[dstreg] & 1;
746 State.regs[dstreg] >>= State.regs[srcreg];
747 z = (State.regs[dstreg] == 0);
748 n = (State.regs[dstreg] & 0x80000000) != 0;
749 PSW &= ~(PSW_Z | PSW_N | PSW_C);
750 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
751 }
752
753 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
754 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
755 "asl"
756 *am33
757 {
758 int srcreg, dstreg;
759 int z, n;
760
761 PC = cia;
762 srcreg = translate_rreg (SD_, RM2);
763 dstreg = translate_rreg (SD_, RN0);
764
765 State.regs[dstreg] <<= State.regs[srcreg];
766 z = (State.regs[dstreg] == 0);
767 n = (State.regs[dstreg] & 0x80000000) != 0;
768 PSW &= ~(PSW_Z | PSW_N);
769 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
770 }
771
772 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
773 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
774 "asl2"
775 *am33
776 {
777 int dstreg;
778 int n, z;
779
780 PC = cia;
781 dstreg = translate_rreg (SD_, RN0);
782
783 State.regs[dstreg] <<= 2;
784 z = (State.regs[dstreg] == 0);
785 n = (State.regs[dstreg] & 0x80000000) != 0;
786 PSW &= ~(PSW_Z | PSW_N);
787 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
788 }
789
790 // 1111 1001 1000 1001 Rn Rn; ror Rn
791 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
792 "ror"
793 *am33
794 {
795 int dstreg;
796 int c, n, z;
797 unsigned32 value;
798
799 PC = cia;
800 dstreg = translate_rreg (SD_, RN0);
801
802 value = State.regs[dstreg];
803 c = (value & 0x1);
804
805 value >>= 1;
806 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
807 State.regs[dstreg] = value;
808 z = (value == 0);
809 n = (value & 0x80000000) != 0;
810 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
811 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
812 }
813
814 // 1111 1001 1001 1001 Rn Rn; rol Rn
815 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
816 "rol"
817 *am33
818 {
819 int dstreg;
820 int c, n, z;
821 unsigned32 value;
822
823 PC = cia;
824 dstreg = translate_rreg (SD_, RN0);
825
826 value = State.regs[dstreg];
827 c = (value & 0x80000000) ? 1 : 0;
828
829 value <<= 1;
830 value |= ((PSW & PSW_C) != 0);
831 State.regs[dstreg] = value;
832 z = (value == 0);
833 n = (value & 0x80000000) != 0;
834 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
835 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
836 }
837
838 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
839 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
840 "mul"
841 *am33
842 {
843 int srcreg, dstreg;
844 unsigned64 temp;
845 int n, z;
846
847 PC = cia;
848 srcreg = translate_rreg (SD_, RM2);
849 dstreg = translate_rreg (SD_, RN0);
850
851 temp = ((signed64)(signed32)State.regs[dstreg]
852 * (signed64)(signed32)State.regs[srcreg]);
853 State.regs[dstreg] = temp & 0xffffffff;
854 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
855 z = (State.regs[dstreg] == 0);
856 n = (State.regs[dstreg] & 0x80000000) != 0;
857 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
858 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
859 }
860
861 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
862 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
863 "mulu"
864 *am33
865 {
866 int srcreg, dstreg;
867 unsigned64 temp;
868 int n, z;
869
870 PC = cia;
871 srcreg = translate_rreg (SD_, RM2);
872 dstreg = translate_rreg (SD_, RN0);
873
874 temp = ((unsigned64)State.regs[dstreg]
875 * (unsigned64)State.regs[srcreg]);
876 State.regs[dstreg] = temp & 0xffffffff;
877 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
878 z = (State.regs[dstreg] == 0);
879 n = (State.regs[dstreg] & 0x80000000) != 0;
880 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
881 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
882 }
883
884 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
885 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
886 "div"
887 *am33
888 {
889 int srcreg, dstreg;
890 signed64 temp;
891 int n, z;
892
893 PC = cia;
894 srcreg = translate_rreg (SD_, RM2);
895 dstreg = translate_rreg (SD_, RN0);
896
897 temp = State.regs[REG_MDR];
898 temp <<= 32;
899 temp |= State.regs[dstreg];
900 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
901 temp /= (signed32)State.regs[srcreg];
902 State.regs[dstreg] = temp & 0xffffffff;
903 z = (State.regs[dstreg] == 0);
904 n = (State.regs[dstreg] & 0x80000000) != 0;
905 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
906 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
907 }
908
909 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
910 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
911 "divu"
912 *am33
913 {
914 int srcreg, dstreg;
915 unsigned64 temp;
916 int n, z;
917
918 PC = cia;
919 srcreg = translate_rreg (SD_, RM2);
920 dstreg = translate_rreg (SD_, RN0);
921
922 temp = State.regs[REG_MDR];
923 temp <<= 32;
924 temp |= State.regs[dstreg];
925 State.regs[REG_MDR] = temp % State.regs[srcreg];
926 temp /= State.regs[srcreg];
927 State.regs[dstreg] = temp & 0xffffffff;
928 z = (State.regs[dstreg] == 0);
929 n = (State.regs[dstreg] & 0x80000000) != 0;
930 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
931 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
932 }
933
934
935 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
936 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
937 "mov"
938 *am33
939 {
940 int srcreg, dstreg;
941
942 PC = cia;
943 srcreg = translate_rreg (SD_, RM0);
944 dstreg = translate_rreg (SD_, RN2);
945 State.regs[dstreg] = load_word (State.regs[srcreg]);
946 }
947
948 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
949 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
950 "mov"
951 *am33
952 {
953 int srcreg, dstreg;
954
955 PC = cia;
956 srcreg = translate_rreg (SD_, RM2);
957 dstreg = translate_rreg (SD_, RN0);
958 store_word (State.regs[dstreg], State.regs[srcreg]);
959 }
960
961 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
962 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
963 "movbu"
964 *am33
965 {
966 int srcreg, dstreg;
967
968 PC = cia;
969 srcreg = translate_rreg (SD_, RM0);
970 dstreg = translate_rreg (SD_, RN2);
971 State.regs[dstreg] = load_byte (State.regs[srcreg]);
972 }
973
974 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
975 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
976 "movbu"
977 *am33
978 {
979 int srcreg, dstreg;
980
981 PC = cia;
982 srcreg = translate_rreg (SD_, RM2);
983 dstreg = translate_rreg (SD_, RN0);
984 store_byte (State.regs[dstreg], State.regs[srcreg]);
985 }
986
987 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
988 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
989 "movhu"
990 *am33
991 {
992 int srcreg, dstreg;
993
994 PC = cia;
995 srcreg = translate_rreg (SD_, RM0);
996 dstreg = translate_rreg (SD_, RN2);
997 State.regs[dstreg] = load_half (State.regs[srcreg]);
998 }
999
1000 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
1001 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1002 "movhu"
1003 *am33
1004 {
1005 int srcreg, dstreg;
1006
1007 PC = cia;
1008 srcreg = translate_rreg (SD_, RM2);
1009 dstreg = translate_rreg (SD_, RN0);
1010 store_half (State.regs[dstreg], State.regs[srcreg]);
1011 }
1012
1013 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1014 8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
1015 "mov"
1016 *am33
1017 {
1018 int srcreg, dstreg;
1019
1020 PC = cia;
1021 srcreg = translate_rreg (SD_, RM0);
1022 dstreg = translate_rreg (SD_, RN2);
1023 State.regs[dstreg] = load_word (State.regs[srcreg]);
1024 State.regs[srcreg] += 4;
1025 }
1026
1027 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1028 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1029 "mov"
1030 *am33
1031 {
1032 int srcreg, dstreg;
1033
1034 PC = cia;
1035 srcreg = translate_rreg (SD_, RM2);
1036 dstreg = translate_rreg (SD_, RN0);
1037 store_word (State.regs[dstreg], State.regs[srcreg]);
1038 State.regs[dstreg] += 4;
1039 }
1040
1041 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1042 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1043 "mov"
1044 *am33
1045 {
1046 int dstreg;
1047
1048 PC = cia;
1049 dstreg = translate_rreg (SD_, RN2);
1050 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1051 }
1052
1053 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1054 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1055 "mov"
1056 *am33
1057 {
1058 int srcreg;
1059
1060 PC = cia;
1061 srcreg = translate_rreg (SD_, RM2);
1062 store_word (State.regs[REG_SP], State.regs[srcreg]);
1063 }
1064
1065 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1066 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1067 "movbu"
1068 *am33
1069 {
1070 int dstreg;
1071
1072 PC = cia;
1073 dstreg = translate_rreg (SD_, RN2);
1074 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1075 }
1076
1077 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1078 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1079 "movbu"
1080 *am33
1081 {
1082 int srcreg;
1083
1084 PC = cia;
1085 srcreg = translate_rreg (SD_, RM2);
1086 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1087 }
1088
1089 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1090 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1091 "movhu"
1092 *am33
1093 {
1094 int dstreg;
1095
1096 PC = cia;
1097 dstreg = translate_rreg (SD_, RN2);
1098 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1099 }
1100
1101 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1102 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1103 "movhu"
1104 *am33
1105 {
1106 int srcreg;
1107
1108 PC = cia;
1109 srcreg = translate_rreg (SD_, RM2);
1110 store_half (State.regs[REG_SP], State.regs[srcreg]);
1111 }
1112
1113 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1114 8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
1115 "movhu"
1116 *am33
1117 {
1118 int srcreg, dstreg;
1119
1120 PC = cia;
1121 srcreg = translate_rreg (SD_, RM0);
1122 dstreg = translate_rreg (SD_, RN2);
1123 State.regs[dstreg] = load_half (State.regs[srcreg]);
1124 State.regs[srcreg] += 2;
1125 }
1126
1127 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1128 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1129 "movhu"
1130 *am33
1131 {
1132 int srcreg, dstreg;
1133
1134 PC = cia;
1135 srcreg = translate_rreg (SD_, RM2);
1136 dstreg = translate_rreg (SD_, RN0);
1137 store_half (State.regs[dstreg], State.regs[srcreg]);
1138 State.regs[dstreg] += 2;
1139 }
1140
1141
1142 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1143 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1144 "mac"
1145 *am33
1146 {
1147 int srcreg1, srcreg2;
1148 signed64 temp, sum;
1149 int c, v;
1150
1151 PC = cia;
1152 srcreg1 = translate_rreg (SD_, RM2);
1153 srcreg2 = translate_rreg (SD_, RN0);
1154
1155 temp = ((signed64)(signed32)State.regs[srcreg2]
1156 * (signed64)(signed32)State.regs[srcreg1]);
1157 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1158 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1159 State.regs[REG_MCRL] = sum;
1160 temp >>= 32;
1161 temp &= 0xffffffff;
1162 sum = State.regs[REG_MCRH] + temp + c;
1163 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1164 && (temp & 0x80000000) != (sum & 0x80000000));
1165 State.regs[REG_MCRH] = sum;
1166 if (v)
1167 State.regs[REG_MCVF] = 1;
1168 }
1169
1170 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1171 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1172 "macu"
1173 *am33
1174 {
1175 int srcreg1, srcreg2;
1176 unsigned64 temp, sum;
1177 int c, v;
1178
1179 PC = cia;
1180 srcreg1 = translate_rreg (SD_, RM2);
1181 srcreg2 = translate_rreg (SD_, RN0);
1182
1183 temp = ((unsigned64)State.regs[srcreg2]
1184 * (unsigned64)State.regs[srcreg1]);
1185 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1186 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1187 State.regs[REG_MCRL] = sum;
1188 temp >>= 32;
1189 temp &= 0xffffffff;
1190 sum = State.regs[REG_MCRH] + temp + c;
1191 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1192 && (temp & 0x80000000) != (sum & 0x80000000));
1193 State.regs[REG_MCRH] = sum;
1194 if (v)
1195 State.regs[REG_MCVF] = 1;
1196 }
1197
1198 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1199 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1200 "macb"
1201 *am33
1202 {
1203 int srcreg1, srcreg2;
1204 signed32 temp, sum;
1205 int v;
1206
1207 PC = cia;
1208 srcreg1 = translate_rreg (SD_, RM2);
1209 srcreg2 = translate_rreg (SD_, RN0);
1210
1211 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1212 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
1213 sum = State.regs[REG_MCRL] + temp;
1214 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1215 && (temp & 0x80000000) != (sum & 0x80000000));
1216 State.regs[REG_MCRL] = sum;
1217 if (v)
1218 State.regs[REG_MCVF] = 1;
1219 }
1220
1221 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1222 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1223 "macbu"
1224 *am33
1225 {
1226 int srcreg1, srcreg2;
1227 signed64 temp, sum;
1228 int v;
1229
1230 PC = cia;
1231 srcreg1 = translate_rreg (SD_, RM2);
1232 srcreg2 = translate_rreg (SD_, RN0);
1233
1234 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1235 * (unsigned32)(State.regs[srcreg1] & 0xff));
1236 sum = State.regs[REG_MCRL] + temp;
1237 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1238 && (temp & 0x80000000) != (sum & 0x80000000));
1239 State.regs[REG_MCRL] = sum;
1240 if (v)
1241 State.regs[REG_MCVF] = 1;
1242 }
1243
1244 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1245 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1246 "mach"
1247 *am33
1248 {
1249 int srcreg1, srcreg2;
1250 signed64 temp, sum;
1251 int c, v;
1252
1253 PC = cia;
1254 srcreg1 = translate_rreg (SD_, RM2);
1255 srcreg2 = translate_rreg (SD_, RN0);
1256
1257 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1258 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
1259 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1260 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1261 State.regs[REG_MCRL] = sum;
1262 temp >>= 32;
1263 temp &= 0xffffffff;
1264 sum = State.regs[REG_MCRH] + temp + c;
1265 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1266 && (temp & 0x80000000) != (sum & 0x80000000));
1267 State.regs[REG_MCRH] = sum;
1268 if (v)
1269 State.regs[REG_MCVF] = 1;
1270 }
1271
1272 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1273 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1274 "machu"
1275 *am33
1276 {
1277 int srcreg1, srcreg2;
1278 signed64 temp, sum;
1279 int c, v;
1280
1281 PC = cia;
1282 srcreg1 = translate_rreg (SD_, RM2);
1283 srcreg2 = translate_rreg (SD_, RN0);
1284
1285 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1286 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1287 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1288 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1289 State.regs[REG_MCRL] = sum;
1290 temp >>= 32;
1291 temp &= 0xffffffff;
1292 sum = State.regs[REG_MCRH] + temp + c;
1293 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1294 && (temp & 0x80000000) != (sum & 0x80000000));
1295 State.regs[REG_MCRH] = sum;
1296 if (v)
1297 State.regs[REG_MCVF] = 1;
1298 }
1299
1300 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1301 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1302 "dmach"
1303 *am33
1304 {
1305 int srcreg1, srcreg2;
1306 signed32 temp, temp2, sum;
1307 int v;
1308
1309 PC = cia;
1310 srcreg1 = translate_rreg (SD_, RM2);
1311 srcreg2 = translate_rreg (SD_, RN0);
1312
1313 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1314 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1315 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1316 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
1317 sum = temp + temp2 + State.regs[REG_MCRL];
1318 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1319 && (temp & 0x80000000) != (sum & 0x80000000));
1320 State.regs[REG_MCRL] = sum;
1321 if (v)
1322 State.regs[REG_MCVF] = 1;
1323 }
1324
1325 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1326 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1327 "dmachu"
1328 *am33
1329 {
1330 int srcreg1, srcreg2;
1331 unsigned32 temp, temp2, sum;
1332 int v;
1333
1334 PC = cia;
1335 srcreg1 = translate_rreg (SD_, RM2);
1336 srcreg2 = translate_rreg (SD_, RN0);
1337
1338 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1339 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1340 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1341 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1342 sum = temp + temp2 + State.regs[REG_MCRL];
1343 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1344 && (temp & 0x80000000) != (sum & 0x80000000));
1345 State.regs[REG_MCRL] = sum;
1346 if (v)
1347 State.regs[REG_MCVF] = 1;
1348 }
1349
1350 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1351 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1352 "dmulh"
1353 *am33
1354 {
1355 int srcreg, dstreg;
1356 signed32 temp;
1357
1358 PC = cia;
1359 srcreg = translate_rreg (SD_, RM2);
1360 dstreg = translate_rreg (SD_, RN0);
1361
1362 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1363 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
1364 State.regs[REG_MDRQ] = temp;
1365 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1366 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
1367 State.regs[dstreg] = temp;
1368 }
1369
1370 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1371 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1372 "dmachu"
1373 *am33
1374 {
1375 int srcreg, dstreg;
1376 unsigned32 temp;
1377
1378 PC = cia;
1379 srcreg = translate_rreg (SD_, RM2);
1380 dstreg = translate_rreg (SD_, RN0);
1381
1382 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1383 * (unsigned32)(State.regs[srcreg] & 0xffff));
1384 State.regs[REG_MDRQ] = temp;
1385 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1386 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1387 State.regs[dstreg] = temp;
1388 }
1389
1390 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1391 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1392 "sat16"
1393 *am33
1394 {
1395 int srcreg, dstreg;
1396 int value, z, n;
1397
1398 PC = cia;
1399 srcreg = translate_rreg (SD_, RM2);
1400 dstreg = translate_rreg (SD_, RN0);
1401
1402 value = State.regs[srcreg];
1403
1404 if (value >= 0x7fff)
1405 State.regs[dstreg] = 0x7fff;
1406 else if (value <= 0xffff8000)
1407 State.regs[dstreg] = 0xffff8000;
1408 else
1409 State.regs[dstreg] = value;
1410
1411 n = (State.regs[dstreg] & 0x8000) != 0;
1412 z = (State.regs[dstreg] == 0);
1413 PSW &= ~(PSW_Z | PSW_N);
1414 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1415 }
1416
1417 // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
1418 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1419 "mcste"
1420 *am33
1421 {
1422 int srcreg, dstreg;
1423
1424 PC = cia;
1425 srcreg = translate_rreg (SD_, RM2);
1426 dstreg = translate_rreg (SD_, RN0);
1427
1428 PSW &= ~(PSW_V | PSW_C);
1429 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1430
1431 /* 32bit saturation. */
1432 if (State.regs[srcreg] == 0x20)
1433 {
1434 signed64 tmp;
1435
1436 tmp = State.regs[REG_MCRH];
1437 tmp <<= 32;
1438 tmp += State.regs[REG_MCRL];
1439
1440 if (tmp > 0x7fffffff)
1441 State.regs[dstreg] = 0x7fffffff;
1442 else if (tmp < 0xffffffff80000000LL)
1443 State.regs[dstreg] = 0x80000000;
1444 else
1445 State.regs[dstreg] = tmp;
1446 }
1447 /* 16bit saturation */
1448 else if (State.regs[srcreg] == 0x10)
1449 {
1450 signed64 tmp;
1451
1452 tmp = State.regs[REG_MCRH];
1453 tmp <<= 32;
1454 tmp += State.regs[REG_MCRL];
1455
1456 if (tmp > 0x7fff)
1457 State.regs[dstreg] = 0x7fff;
1458 else if (tmp < 0xffffffffffff8000LL)
1459 State.regs[dstreg] = 0x8000;
1460 else
1461 State.regs[dstreg] = tmp;
1462 }
1463 /* 8 bit saturation */
1464 else if (State.regs[srcreg] == 0x8)
1465 {
1466 signed64 tmp;
1467
1468 tmp = State.regs[REG_MCRH];
1469 tmp <<= 32;
1470 tmp += State.regs[REG_MCRL];
1471
1472 if (tmp > 0x7f)
1473 State.regs[dstreg] = 0x7f;
1474 else if (tmp < 0xffffffffffffff80LL)
1475 State.regs[dstreg] = 0x80;
1476 else
1477 State.regs[dstreg] = tmp;
1478 }
1479 /* 9 bit saturation */
1480 else if (State.regs[srcreg] == 0x9)
1481 {
1482 signed64 tmp;
1483
1484 tmp = State.regs[REG_MCRH];
1485 tmp <<= 32;
1486 tmp += State.regs[REG_MCRL];
1487
1488 if (tmp > 0x80)
1489 State.regs[dstreg] = 0x80;
1490 else if (tmp < 0xffffffffffffff81LL)
1491 State.regs[dstreg] = 0x81;
1492 else
1493 State.regs[dstreg] = tmp;
1494 }
1495 /* 9 bit saturation */
1496 else if (State.regs[srcreg] == 0x30)
1497 {
1498 signed64 tmp;
1499
1500 tmp = State.regs[REG_MCRH];
1501 tmp <<= 32;
1502 tmp += State.regs[REG_MCRL];
1503
1504 if (tmp > 0x7fffffffffffLL)
1505 tmp = 0x7fffffffffffLL;
1506 else if (tmp < 0xffff800000000000LL)
1507 tmp = 0xffff800000000000LL;
1508
1509 tmp >>= 16;
1510 State.regs[dstreg] = tmp;
1511 }
1512 }
1513
1514 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1515 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1516 "swap"
1517 *am33
1518 {
1519 int srcreg, dstreg;
1520
1521 PC = cia;
1522 srcreg = translate_rreg (SD_, RM2);
1523 dstreg = translate_rreg (SD_, RN0);
1524
1525 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1526 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1527 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1528 | ((State.regs[srcreg] >> 24) & 0xff));
1529 }
1530
1531 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1532 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1533 "swaph"
1534 *am33
1535 {
1536 int srcreg, dstreg;
1537
1538 PC = cia;
1539 srcreg = translate_rreg (SD_, RM2);
1540 dstreg = translate_rreg (SD_, RN0);
1541
1542 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1543 | ((State.regs[srcreg] >> 8) & 0xff)
1544 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1545 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1546 }
1547
1548 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1549 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1550 "swhw"
1551 *am33
1552 {
1553 int srcreg, dstreg;
1554
1555 PC = cia;
1556 srcreg = translate_rreg (SD_, RM2);
1557 dstreg = translate_rreg (SD_, RN0);
1558
1559 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1560 | ((State.regs[srcreg] >> 16) & 0xffff));
1561 }
1562
1563 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1564 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1565 "bsch"
1566 *am33
1567 {
1568 int temp, c, i;
1569 int srcreg, dstreg;
1570 int start;
1571
1572 PC = cia;
1573 srcreg = translate_rreg (SD_, RM2);
1574 dstreg = translate_rreg (SD_, RN0);
1575
1576 temp = State.regs[srcreg];
1577 start = (State.regs[dstreg] & 0x1f) - 1;
1578 if (start == -1)
1579 start = 31;
1580
1581 for (i = start; i >= 0; i--)
1582 {
1583 if (temp & (1 << i))
1584 {
1585 c = 1;
1586 State.regs[dstreg] = i;
1587 break;
1588 }
1589 }
1590
1591 if (i < 0)
1592 {
1593 c = 0;
1594 State.regs[dstreg] = 0;
1595 }
1596 PSW &= ~(PSW_C);
1597 PSW |= (c ? PSW_C : 0);
1598 }
1599
1600
1601 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1602 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1603 "mov"
1604 *am33
1605 {
1606 int dstreg;
1607
1608 PC = cia;
1609 dstreg = translate_rreg (SD_, RN0);
1610 State.regs[dstreg] = EXTEND8 (IMM8);
1611 }
1612
1613 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1614 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1615 "movu"
1616 *am33
1617 {
1618 int dstreg;
1619
1620 PC = cia;
1621 dstreg = translate_rreg (SD_, RN0);
1622 State.regs[dstreg] = IMM8 & 0xff;
1623 }
1624
1625 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1626 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1627 "add"
1628 *am33
1629 {
1630 int dstreg;
1631
1632 PC = cia;
1633 dstreg = translate_rreg (SD_, RN0);
1634 genericAdd (EXTEND8 (IMM8), dstreg);
1635 }
1636
1637 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1638 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1639 "addc"
1640 *am33
1641 {
1642 int dstreg, imm;
1643 int z, c, n, v;
1644 unsigned32 reg1, reg2, sum;
1645
1646 PC = cia;
1647 dstreg = translate_rreg (SD_, RN0);
1648
1649 imm = EXTEND8 (IMM8);
1650 reg2 = State.regs[dstreg];
1651 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1652 State.regs[dstreg] = sum;
1653
1654 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1655 n = (sum & 0x80000000);
1656 c = (sum < imm) || (sum < reg2);
1657 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1658 && (reg2 & 0x80000000) != (sum & 0x80000000));
1659
1660 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1661 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1662 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1663 }
1664
1665 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1666 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1667 "sub"
1668 *am33
1669 {
1670 int dstreg;
1671
1672 PC = cia;
1673 dstreg = translate_rreg (SD_, RN0);
1674
1675 genericSub (EXTEND8 (IMM8), dstreg);
1676 }
1677
1678 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1679 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1680 "subc"
1681 *am33
1682 {
1683 int imm, dstreg;
1684 int z, c, n, v;
1685 unsigned32 reg1, reg2, difference;
1686
1687 PC = cia;
1688 dstreg = translate_rreg (SD_, RN0);
1689
1690 imm = EXTEND8 (IMM8);
1691 reg2 = State.regs[dstreg];
1692 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1693 State.regs[dstreg] = difference;
1694
1695 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1696 n = (difference & 0x80000000);
1697 c = (imm > reg2);
1698 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1699 && (reg2 & 0x80000000) != (difference & 0x80000000));
1700
1701 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1702 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1703 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1704 }
1705
1706 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1707 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1708 "cmp"
1709 *am33
1710 {
1711 int srcreg;
1712
1713 PC = cia;
1714 srcreg = translate_rreg (SD_, RN0);
1715 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1716 }
1717
1718 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1719 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1720 "mov"
1721 *am33
1722 {
1723 int dstreg;
1724
1725 PC = cia;
1726 dstreg = translate_xreg (SD_, XRN0);
1727
1728 State.regs[dstreg] = IMM8;
1729 }
1730
1731 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1732 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1733 "and"
1734 *am33
1735 {
1736 int dstreg;
1737 int z, n;
1738
1739 PC = cia;
1740 dstreg = translate_rreg (SD_, RN0);
1741
1742 State.regs[dstreg] &= (IMM8 & 0xff);
1743 z = (State.regs[dstreg] == 0);
1744 n = (State.regs[dstreg] & 0x80000000) != 0;
1745 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1746 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1747 }
1748
1749 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1750 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1751 "or"
1752 *am33
1753 {
1754 int dstreg;
1755 int z, n;
1756
1757 PC = cia;
1758 dstreg = translate_rreg (SD_, RN0);
1759
1760 State.regs[dstreg] |= (IMM8 & 0xff);
1761 z = (State.regs[dstreg] == 0);
1762 n = (State.regs[dstreg] & 0x80000000) != 0;
1763 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1764 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1765 }
1766
1767 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1768 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1769 "xor"
1770 *am33
1771 {
1772 int dstreg;
1773 int z, n;
1774
1775 PC = cia;
1776 dstreg = translate_rreg (SD_, RN0);
1777
1778 State.regs[dstreg] ^= (IMM8 & 0xff);
1779 z = (State.regs[dstreg] == 0);
1780 n = (State.regs[dstreg] & 0x80000000) != 0;
1781 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1782 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1783 }
1784
1785 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1786 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1787 "asr"
1788 *am33
1789 {
1790 int dstreg;
1791 signed32 temp;
1792 int c, z, n;
1793
1794 PC = cia;
1795 dstreg = translate_rreg (SD_, RN0);
1796
1797 temp = State.regs[dstreg];
1798 c = temp & 1;
1799 temp >>= (IMM8 & 0xff);
1800 State.regs[dstreg] = temp;
1801 z = (State.regs[dstreg] == 0);
1802 n = (State.regs[dstreg] & 0x80000000) != 0;
1803 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1804 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1805 }
1806
1807 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1808 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1809 "lsr"
1810 *am33
1811 {
1812 int dstreg;
1813 int z, n, c;
1814
1815 PC = cia;
1816 dstreg = translate_rreg (SD_, RN0);
1817
1818 c = State.regs[dstreg] & 1;
1819 State.regs[dstreg] >>= (IMM8 & 0xff);
1820 z = (State.regs[dstreg] == 0);
1821 n = (State.regs[dstreg] & 0x80000000) != 0;
1822 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1823 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1824 }
1825
1826 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1827 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1828 "asl"
1829 *am33
1830 {
1831 int srcreg, dstreg;
1832 int z, n;
1833
1834 PC = cia;
1835 dstreg = translate_rreg (SD_, RN0);
1836
1837 State.regs[dstreg] <<= (IMM8 & 0xff);
1838 z = (State.regs[dstreg] == 0);
1839 n = (State.regs[dstreg] & 0x80000000) != 0;
1840 PSW &= ~(PSW_Z | PSW_N);
1841 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1842 }
1843
1844 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1845 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1846 "mul"
1847 *am33
1848 {
1849 int dstreg;
1850 unsigned64 temp;
1851 int z, n;
1852
1853 PC = cia;
1854 dstreg = translate_rreg (SD_, RN0);
1855
1856 temp = ((signed64)(signed32)State.regs[dstreg]
1857 * (signed64)(signed32)EXTEND8 (IMM8));
1858 State.regs[dstreg] = temp & 0xffffffff;
1859 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1860 z = (State.regs[dstreg] == 0);
1861 n = (State.regs[dstreg] & 0x80000000) != 0;
1862 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1863 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1864 }
1865
1866 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1867 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1868 "mulu"
1869 *am33
1870 {
1871 int dstreg;
1872 unsigned64 temp;
1873 int z, n;
1874
1875 PC = cia;
1876 dstreg = translate_rreg (SD_, RN0);
1877
1878 temp = ((unsigned64)State.regs[dstreg]
1879 * (unsigned64)(IMM8 & 0xff));
1880 State.regs[dstreg] = temp & 0xffffffff;
1881 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1882 z = (State.regs[dstreg] == 0);
1883 n = (State.regs[dstreg] & 0x80000000) != 0;
1884 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1885 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1886 }
1887
1888 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1889 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1890 "btst"
1891 *am33
1892 {
1893 int srcreg;
1894
1895 PC = cia;
1896 srcreg = translate_rreg (SD_, RM0);
1897 genericBtst(IMM8, State.regs[srcreg]);
1898 }
1899
1900 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1901 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1902 "mov"
1903 *am33
1904 {
1905 int srcreg, dstreg;
1906
1907 PC = cia;
1908 srcreg = translate_rreg (SD_, RM0);
1909 dstreg = translate_rreg (SD_, RN2);
1910 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1911 }
1912
1913 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1914 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1915 "mov"
1916 *am33
1917 {
1918 int srcreg, dstreg;
1919
1920 PC = cia;
1921 srcreg = translate_rreg (SD_, RM2);
1922 dstreg = translate_rreg (SD_, RN0);
1923 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1924 }
1925
1926 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1927 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1928 "movbu"
1929 *am33
1930 {
1931 int srcreg, dstreg;
1932
1933 PC = cia;
1934 srcreg = translate_rreg (SD_, RM0);
1935 dstreg = translate_rreg (SD_, RN2);
1936 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1937 }
1938
1939 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1940 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1941 "movbu"
1942 *am33
1943 {
1944 int srcreg, dstreg;
1945
1946 PC = cia;
1947 srcreg = translate_rreg (SD_, RM2);
1948 dstreg = translate_rreg (SD_, RN0);
1949 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1950 }
1951
1952 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1953 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1954 "movhu"
1955 *am33
1956 {
1957 int srcreg, dstreg;
1958
1959 PC = cia;
1960 srcreg = translate_rreg (SD_, RM0);
1961 dstreg = translate_rreg (SD_, RN2);
1962 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1963 }
1964
1965 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1966 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1967 "movhu"
1968 *am33
1969 {
1970 int srcreg, dstreg;
1971
1972 PC = cia;
1973 srcreg = translate_rreg (SD_, RM2);
1974 dstreg = translate_rreg (SD_, RN0);
1975 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1976 }
1977
1978 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1979 8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
1980 "mov"
1981 *am33
1982 {
1983 int srcreg, dstreg;
1984
1985 PC = cia;
1986 srcreg = translate_rreg (SD_, RM0);
1987 dstreg = translate_rreg (SD_, RN2);
1988 State.regs[dstreg] = load_word (State.regs[srcreg]);
1989 State.regs[srcreg] += EXTEND8 (IMM8);
1990 }
1991
1992 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1993 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1994 "mov"
1995 *am33
1996 {
1997 int srcreg, dstreg;
1998
1999 PC = cia;
2000 srcreg = translate_rreg (SD_, RM2);
2001 dstreg = translate_rreg (SD_, RN0);
2002 store_word (State.regs[dstreg], State.regs[srcreg]);
2003 State.regs[dstreg] += EXTEND8 (IMM8);
2004 }
2005
2006
2007 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
2008 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2009 "mov"
2010 *am33
2011 {
2012 int dstreg;
2013
2014 PC = cia;
2015 dstreg = translate_rreg (SD_, RN2);
2016 State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8);
2017 }
2018
2019 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,sp)
2020 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2021 "mov"
2022 *am33
2023 {
2024 int srcreg;
2025
2026 PC = cia;
2027 srcreg = translate_rreg (SD_, RM2);
2028 store_word (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
2029 }
2030
2031 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2032 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2033 "movbu"
2034 *am33
2035 {
2036 int dstreg;
2037
2038 PC = cia;
2039 dstreg = translate_rreg (SD_, RN2);
2040 State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8);
2041 }
2042
2043 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(d8,sp)
2044 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2045 "movbu"
2046 *am33
2047 {
2048 int srcreg;
2049
2050 PC = cia;
2051 srcreg = translate_rreg (SD_, RM2);
2052 store_byte (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
2053 }
2054
2055 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2056 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2057 "movhu"
2058 *am33
2059 {
2060 int dstreg;
2061
2062 PC = cia;
2063 dstreg = translate_rreg (SD_, RN2);
2064 State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8);
2065 }
2066
2067 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2068 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2069 "movhu"
2070 *am33
2071 {
2072 int srcreg;
2073
2074 PC = cia;
2075 srcreg = translate_rreg (SD_, RM2);
2076 store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
2077 }
2078
2079 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2080 8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
2081 "movhu"
2082 *am33
2083 {
2084 int srcreg, dstreg;
2085
2086 PC = cia;
2087 srcreg = translate_rreg (SD_, RM0);
2088 dstreg = translate_rreg (SD_, RN2);
2089 State.regs[dstreg] = load_half (State.regs[srcreg]);
2090 State.regs[srcreg] += EXTEND8 (IMM8);
2091 }
2092
2093 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2094 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2095 "movhu"
2096 *am33
2097 {
2098 int srcreg, dstreg;
2099
2100 PC = cia;
2101 srcreg = translate_rreg (SD_, RM2);
2102 dstreg = translate_rreg (SD_, RN0);
2103 store_half (State.regs[dstreg], State.regs[srcreg]);
2104 State.regs[dstreg] += EXTEND8 (IMM8);
2105 }
2106
2107
2108 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2109 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2110 "mac"
2111 *am33
2112 {
2113 int srcreg;
2114 signed64 temp, sum;
2115 int c, v;
2116
2117 PC = cia;
2118 srcreg = translate_rreg (SD_, RN2);
2119
2120 temp = ((signed64)(signed32)EXTEND8 (IMM8)
2121 * (signed64)(signed32)State.regs[srcreg]);
2122 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2123 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2124 State.regs[REG_MCRL] = sum;
2125 temp >>= 32;
2126 temp &= 0xffffffff;
2127 sum = State.regs[REG_MCRH] + temp + c;
2128 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2129 && (temp & 0x80000000) != (sum & 0x80000000));
2130 State.regs[REG_MCRH] = sum;
2131 if (v)
2132 State.regs[REG_MCVF] = 1;
2133 }
2134
2135 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2136 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2137 "macu"
2138 *am33
2139 {
2140 int srcreg;
2141 signed64 temp, sum;
2142 int c, v;
2143
2144 PC = cia;
2145 srcreg = translate_rreg (SD_, RN2);
2146
2147 temp = ((unsigned64) (IMM8)
2148 * (unsigned64)State.regs[srcreg]);
2149 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2150 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2151 State.regs[REG_MCRL] = sum;
2152 temp >>= 32;
2153 temp &= 0xffffffff;
2154 sum = State.regs[REG_MCRH] + temp + c;
2155 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2156 && (temp & 0x80000000) != (sum & 0x80000000));
2157 State.regs[REG_MCRH] = sum;
2158 if (v)
2159 State.regs[REG_MCVF] = 1;
2160 }
2161
2162 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2163 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2164 "macb"
2165 *am33
2166 {
2167 int srcreg;
2168 signed64 temp, sum;
2169 int c, v;
2170
2171 PC = cia;
2172 srcreg = translate_rreg (SD_, RN2);
2173
2174 temp = ((signed64)(signed8)EXTEND8 (IMM8)
2175 * (signed64)(signed8)State.regs[srcreg] & 0xff);
2176 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2177 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2178 State.regs[REG_MCRL] = sum;
2179 temp >>= 32;
2180 temp &= 0xffffffff;
2181 sum = State.regs[REG_MCRH] + temp + c;
2182 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2183 && (temp & 0x80000000) != (sum & 0x80000000));
2184 State.regs[REG_MCRH] = sum;
2185 if (v)
2186 State.regs[REG_MCVF] = 1;
2187 }
2188
2189 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2190 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2191 "macbu"
2192 *am33
2193 {
2194 int srcreg;
2195 signed64 temp, sum;
2196 int c, v;
2197
2198 PC = cia;
2199 srcreg = translate_rreg (SD_, RN2);
2200
2201 temp = ((unsigned64) (IMM8)
2202 * (unsigned64)State.regs[srcreg] & 0xff);
2203 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2204 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2205 State.regs[REG_MCRL] = sum;
2206 temp >>= 32;
2207 temp &= 0xffffffff;
2208 sum = State.regs[REG_MCRH] + temp + c;
2209 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2210 && (temp & 0x80000000) != (sum & 0x80000000));
2211 State.regs[REG_MCRH] = sum;
2212 if (v)
2213 State.regs[REG_MCVF] = 1;
2214 }
2215
2216 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2217 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2218 "mach"
2219 *am33
2220 {
2221 int srcreg;
2222 signed64 temp, sum;
2223 int c, v;
2224
2225 PC = cia;
2226 srcreg = translate_rreg (SD_, RN2);
2227
2228 temp = ((signed64)(signed16)EXTEND8 (IMM8)
2229 * (signed64)(signed16)State.regs[srcreg] & 0xffff);
2230 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2231 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2232 State.regs[REG_MCRL] = sum;
2233 temp >>= 32;
2234 temp &= 0xffffffff;
2235 sum = State.regs[REG_MCRH] + temp + c;
2236 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2237 && (temp & 0x80000000) != (sum & 0x80000000));
2238 State.regs[REG_MCRH] = sum;
2239 if (v)
2240 State.regs[REG_MCVF] = 1;
2241 }
2242
2243 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2244 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2245 "machu"
2246 *am33
2247 {
2248 int srcreg;
2249 signed64 temp, sum;
2250 int c, v;
2251
2252 PC = cia;
2253 srcreg = translate_rreg (SD_, RN2);
2254
2255 temp = ((unsigned64) (IMM8)
2256 * (unsigned64)State.regs[srcreg] & 0xffff);
2257 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2258 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2259 State.regs[REG_MCRL] = sum;
2260 temp >>= 32;
2261 temp &= 0xffffffff;
2262 sum = State.regs[REG_MCRH] + temp + c;
2263 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2264 && (temp & 0x80000000) != (sum & 0x80000000));
2265 State.regs[REG_MCRH] = sum;
2266 if (v)
2267 State.regs[REG_MCVF] = 1;
2268 }
2269
2270 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
2271 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2272 "mcste"
2273 *am33
2274 {
2275 int dstreg;
2276
2277 PC = cia;
2278 dstreg = translate_rreg (SD_, RN0);
2279
2280 PSW &= ~(PSW_V | PSW_C);
2281 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2282
2283 /* 32bit saturation. */
2284 if (IMM8 == 0x20)
2285 {
2286 signed64 tmp;
2287
2288 tmp = State.regs[REG_MCRH];
2289 tmp <<= 32;
2290 tmp += State.regs[REG_MCRL];
2291
2292 if (tmp > 0x7fffffff)
2293 State.regs[dstreg] = 0x7fffffff;
2294 else if (tmp < 0xffffffff80000000LL)
2295 State.regs[dstreg] = 0x80000000;
2296 else
2297 State.regs[dstreg] = tmp;
2298 }
2299 /* 16bit saturation */
2300 else if (IMM8 == 0x10)
2301 {
2302 signed64 tmp;
2303
2304 tmp = State.regs[REG_MCRH];
2305 tmp <<= 32;
2306 tmp += State.regs[REG_MCRL];
2307
2308 if (tmp > 0x7fff)
2309 State.regs[dstreg] = 0x7fff;
2310 else if (tmp < 0xffffffffffff8000LL)
2311 State.regs[dstreg] = 0x8000;
2312 else
2313 State.regs[dstreg] = tmp;
2314 }
2315 /* 8 bit saturation */
2316 else if (IMM8 == 0x8)
2317 {
2318 signed64 tmp;
2319
2320 tmp = State.regs[REG_MCRH];
2321 tmp <<= 32;
2322 tmp += State.regs[REG_MCRL];
2323
2324 if (tmp > 0x7f)
2325 State.regs[dstreg] = 0x7f;
2326 else if (tmp < 0xffffffffffffff80LL)
2327 State.regs[dstreg] = 0x80;
2328 else
2329 State.regs[dstreg] = tmp;
2330 }
2331 /* 9 bit saturation */
2332 else if (IMM8 == 0x9)
2333 {
2334 signed64 tmp;
2335
2336 tmp = State.regs[REG_MCRH];
2337 tmp <<= 32;
2338 tmp += State.regs[REG_MCRL];
2339
2340 if (tmp > 0x80)
2341 State.regs[dstreg] = 0x80;
2342 else if (tmp < 0xffffffffffffff81LL)
2343 State.regs[dstreg] = 0x81;
2344 else
2345 State.regs[dstreg] = tmp;
2346 }
2347 /* 9 bit saturation */
2348 else if (IMM8 == 0x30)
2349 {
2350 signed64 tmp;
2351
2352 tmp = State.regs[REG_MCRH];
2353 tmp <<= 32;
2354 tmp += State.regs[REG_MCRL];
2355
2356 if (tmp > 0x7fffffffffffLL)
2357 tmp = 0x7fffffffffffLL;
2358 else if (tmp < 0xffff800000000000LL)
2359 tmp = 0xffff800000000000LL;
2360
2361 tmp >>= 16;
2362 State.regs[dstreg] = tmp;
2363 }
2364 }
2365
2366 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2367 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2368 "add"
2369 *am33
2370 {
2371 int z, c, n, v;
2372 unsigned32 sum, source1, source2;
2373 int srcreg1, srcreg2, dstreg;
2374
2375 PC = cia;
2376 srcreg1 = translate_rreg (SD_, RM2);
2377 srcreg2 = translate_rreg (SD_, RN0);
2378 dstreg = translate_rreg (SD_, RD0);
2379
2380 source1 = State.regs[srcreg1];
2381 source2 = State.regs[srcreg2];
2382 sum = source1 + source2;
2383 State.regs[dstreg] = sum;
2384
2385 z = (sum == 0);
2386 n = (sum & 0x80000000);
2387 c = (sum < source1) || (sum < source2);
2388 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2389 && (source1 & 0x80000000) != (sum & 0x80000000));
2390
2391 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2392 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2393 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2394 }
2395
2396 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2397 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2398 "addc"
2399 *am33
2400 {
2401 int z, c, n, v;
2402 unsigned32 sum, source1, source2;
2403 int srcreg1, srcreg2, dstreg;
2404
2405 PC = cia;
2406 srcreg1 = translate_rreg (SD_, RM2);
2407 srcreg2 = translate_rreg (SD_, RN0);
2408 dstreg = translate_rreg (SD_, RD0);
2409
2410 source1 = State.regs[srcreg1];
2411 source2 = State.regs[srcreg2];
2412 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2413 State.regs[dstreg] = sum;
2414
2415 z = ((PSW & PSW_Z) != 0) && (sum == 0);
2416 n = (sum & 0x80000000);
2417 c = (sum < source1) || (sum < source2);
2418 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2419 && (source1 & 0x80000000) != (sum & 0x80000000));
2420
2421 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2422 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2423 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2424 }
2425
2426 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2427 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2428 "sub"
2429 *am33
2430 {
2431 int z, c, n, v;
2432 unsigned32 difference, source1, source2;
2433 int srcreg1, srcreg2, dstreg;
2434
2435 PC = cia;
2436 srcreg1 = translate_rreg (SD_, RM2);
2437 srcreg2 = translate_rreg (SD_, RN0);
2438 dstreg = translate_rreg (SD_, RD0);
2439
2440 source1 = State.regs[srcreg1];
2441 source2 = State.regs[srcreg2];
2442 difference = source2 - source1;
2443 State.regs[dstreg] = difference;
2444
2445 z = (difference == 0);
2446 n = (difference & 0x80000000);
2447 c = (source1 > source1);
2448 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2449 && (source1 & 0x80000000) != (difference & 0x80000000));
2450
2451 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2452 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2453 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2454 }
2455
2456 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2457 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2458 "subc"
2459 *am33
2460 {
2461 int z, c, n, v;
2462 unsigned32 difference, source1, source2;
2463 int srcreg1, srcreg2, dstreg;
2464
2465 PC = cia;
2466 srcreg1 = translate_rreg (SD_, RM2);
2467 srcreg2 = translate_rreg (SD_, RN0);
2468 dstreg = translate_rreg (SD_, RD0);
2469
2470 source1 = State.regs[srcreg1];
2471 source2 = State.regs[srcreg2];
2472 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2473 State.regs[dstreg] = difference;
2474
2475 z = ((PSW & PSW_Z) != 0) && (difference == 0);
2476 n = (difference & 0x80000000);
2477 c = (source1 > source2);
2478 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2479 && (source1 & 0x80000000) != (difference & 0x80000000));
2480
2481 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2482 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2483 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2484 }
2485
2486 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2487 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2488 "and"
2489 *am33
2490 {
2491 int z, n;
2492 int srcreg1, srcreg2, dstreg;
2493
2494 PC = cia;
2495 srcreg1 = translate_rreg (SD_, RM2);
2496 srcreg2 = translate_rreg (SD_, RN0);
2497 dstreg = translate_rreg (SD_, RD0);
2498
2499 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2500
2501 z = (State.regs[dstreg] == 0);
2502 n = (State.regs[dstreg] & 0x80000000);
2503
2504 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2505 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2506 }
2507
2508 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2509 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2510 "or"
2511 *am33
2512 {
2513 int z, n;
2514 int srcreg1, srcreg2, dstreg;
2515
2516 PC = cia;
2517 srcreg1 = translate_rreg (SD_, RM2);
2518 srcreg2 = translate_rreg (SD_, RN0);
2519 dstreg = translate_rreg (SD_, RD0);
2520
2521 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2522
2523 z = (State.regs[dstreg] == 0);
2524 n = (State.regs[dstreg] & 0x80000000);
2525
2526 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2527 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2528 }
2529
2530 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2531 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2532 "xor"
2533 *am33
2534 {
2535 int z, n;
2536 int srcreg1, srcreg2, dstreg;
2537
2538 PC = cia;
2539 srcreg1 = translate_rreg (SD_, RM2);
2540 srcreg2 = translate_rreg (SD_, RN0);
2541 dstreg = translate_rreg (SD_, RD0);
2542
2543 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2544
2545 z = (State.regs[dstreg] == 0);
2546 n = (State.regs[dstreg] & 0x80000000);
2547
2548 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2549 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2550 }
2551
2552 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2553 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2554 "asr"
2555 *am33
2556 {
2557 int z, c, n;
2558 signed32 temp;
2559 int srcreg1, srcreg2, dstreg;
2560
2561 PC = cia;
2562 srcreg1 = translate_rreg (SD_, RM2);
2563 srcreg2 = translate_rreg (SD_, RN0);
2564 dstreg = translate_rreg (SD_, RD0);
2565
2566 temp = State.regs[srcreg2];
2567 c = temp & 1;
2568 temp >>= State.regs[srcreg1];
2569 State.regs[dstreg] = temp;
2570
2571 z = (State.regs[dstreg] == 0);
2572 n = (State.regs[dstreg] & 0x80000000);
2573
2574 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2575 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2576 }
2577
2578 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2579 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2580 "lsr"
2581 *am33
2582 {
2583 int z, c, n;
2584 int srcreg1, srcreg2, dstreg;
2585
2586 PC = cia;
2587 srcreg1 = translate_rreg (SD_, RM2);
2588 srcreg2 = translate_rreg (SD_, RN0);
2589 dstreg = translate_rreg (SD_, RD0);
2590
2591 c = State.regs[srcreg2] & 1;
2592 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2593
2594 z = (State.regs[dstreg] == 0);
2595 n = (State.regs[dstreg] & 0x80000000);
2596
2597 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2598 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2599 }
2600
2601 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2602 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2603 "asl"
2604 *am33
2605 {
2606 int z, n;
2607 int srcreg1, srcreg2, dstreg;
2608
2609 PC = cia;
2610 srcreg1 = translate_rreg (SD_, RM2);
2611 srcreg2 = translate_rreg (SD_, RN0);
2612 dstreg = translate_rreg (SD_, RD0);
2613
2614 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
2615
2616 z = (State.regs[dstreg] == 0);
2617 n = (State.regs[dstreg] & 0x80000000);
2618
2619 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2620 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2621 }
2622
2623 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2624 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
2625 "mul"
2626 *am33
2627 {
2628 int srcreg1, srcreg2, dstreg1, dstreg2;
2629 signed64 temp;
2630 int n, z;
2631
2632 PC = cia;
2633 srcreg1 = translate_rreg (SD_, RM2);
2634 srcreg2 = translate_rreg (SD_, RN0);
2635 dstreg1 = translate_rreg (SD_, RD0);
2636 dstreg2 = translate_rreg (SD_, RD2);
2637
2638 temp = ((signed64)(signed32)State.regs[srcreg1]
2639 * (signed64)(signed32)State.regs[srcreg2]);
2640 State.regs[dstreg2] = temp & 0xffffffff;
2641 State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
2642
2643 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2644 n = (State.regs[dstreg1] & 0x80000000);
2645
2646 PSW &= ~(PSW_Z | PSW_N);
2647 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2648 }
2649
2650 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2651 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
2652 "mulu"
2653 *am33
2654 {
2655 int srcreg1, srcreg2, dstreg1, dstreg2;
2656 signed64 temp;
2657 int n, z;
2658
2659 PC = cia;
2660 srcreg1 = translate_rreg (SD_, RM2);
2661 srcreg2 = translate_rreg (SD_, RN0);
2662 dstreg1 = translate_rreg (SD_, RD0);
2663 dstreg2 = translate_rreg (SD_, RD2);
2664
2665 temp = ((unsigned64)State.regs[srcreg1]
2666 * (unsigned64)State.regs[srcreg2]);
2667 State.regs[dstreg2] = temp & 0xffffffff;
2668 State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
2669
2670 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2671 n = (State.regs[dstreg1] & 0x80000000);
2672
2673 PSW &= ~(PSW_Z | PSW_N);
2674 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2675 }
2676
2677 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2678 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2679 "mov"
2680 *am33
2681 {
2682 int dstreg;
2683
2684 PC = cia;
2685 dstreg = translate_rreg (SD_, RN2);
2686 State.regs[dstreg] = load_word (IMM8);
2687 }
2688
2689 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2690 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2691 "mov"
2692 *am33
2693 {
2694 int srcreg;
2695
2696 PC = cia;
2697 srcreg = translate_rreg (SD_, RM2);
2698 store_word (IMM8, State.regs[srcreg]);
2699 }
2700
2701 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2702 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2703 "movbu"
2704 *am33
2705 {
2706 int dstreg;
2707
2708 PC = cia;
2709 dstreg = translate_rreg (SD_, RN2);
2710 State.regs[dstreg] = load_byte (IMM8);
2711 }
2712
2713 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2714 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2715 "movbu"
2716 *am33
2717 {
2718 int srcreg;
2719
2720 PC = cia;
2721 srcreg = translate_rreg (SD_, RM2);
2722 store_byte (IMM8, State.regs[srcreg]);
2723 }
2724
2725 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2726 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2727 "movhu"
2728 *am33
2729 {
2730 int dstreg;
2731
2732 PC = cia;
2733 dstreg = translate_rreg (SD_, RN2);
2734 State.regs[dstreg] = load_half (IMM8);
2735 }
2736
2737 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2738 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2739 "movhu"
2740 *am33
2741 {
2742 int srcreg;
2743
2744 PC = cia;
2745 srcreg = translate_rreg (SD_, RM2);
2746 store_half (IMM8, State.regs[srcreg]);
2747 }
2748
2749 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2750 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2751 "mov"
2752 *am33
2753 {
2754 int srcreg1, srcreg2, dstreg;
2755
2756 PC = cia;
2757 srcreg1 = translate_rreg (SD_, RM0);
2758 srcreg1 = translate_rreg (SD_, RI0);
2759 dstreg = translate_rreg (SD_, RN0);
2760 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2761 }
2762
2763 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2764 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2765 "mov"
2766 *am33
2767 {
2768 int srcreg, dstreg1, dstreg2;
2769
2770 PC = cia;
2771 srcreg = translate_rreg (SD_, RM0);
2772 dstreg1 = translate_rreg (SD_, RI0);
2773 dstreg2 = translate_rreg (SD_, RN0);
2774 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2775 }
2776
2777 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2778 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2779 "movbu"
2780 *am33
2781 {
2782 int srcreg1, srcreg2, dstreg;
2783
2784 PC = cia;
2785 srcreg1 = translate_rreg (SD_, RM0);
2786 srcreg1 = translate_rreg (SD_, RI0);
2787 dstreg = translate_rreg (SD_, RN0);
2788 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2789 }
2790
2791 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2792 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2793 "movbu"
2794 *am33
2795 {
2796 int srcreg, dstreg1, dstreg2;
2797
2798 PC = cia;
2799 srcreg = translate_rreg (SD_, RM0);
2800 dstreg1 = translate_rreg (SD_, RI0);
2801 dstreg2 = translate_rreg (SD_, RN0);
2802 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2803 }
2804
2805 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2806 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2807 "movhu"
2808 *am33
2809 {
2810 int srcreg1, srcreg2, dstreg;
2811
2812 PC = cia;
2813 srcreg1 = translate_rreg (SD_, RM0);
2814 srcreg1 = translate_rreg (SD_, RI0);
2815 dstreg = translate_rreg (SD_, RN0);
2816 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2817 }
2818
2819 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2820 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2821 "movhu"
2822 *am33
2823 {
2824 int srcreg, dstreg1, dstreg2;
2825
2826 PC = cia;
2827 srcreg = translate_rreg (SD_, RM0);
2828 dstreg1 = translate_rreg (SD_, RI0);
2829 dstreg2 = translate_rreg (SD_, RN0);
2830 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2831 }
2832
2833 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
2834 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
2835 "mac"
2836 *am33
2837 {
2838 int srcreg1, srcreg2, dstreg1, dstreg2;
2839 signed64 temp;
2840 unsigned32 sum;
2841 int c, v;
2842
2843 PC = cia;
2844 srcreg1 = translate_rreg (SD_, RM2);
2845 srcreg2 = translate_rreg (SD_, RN0);
2846 dstreg1 = translate_rreg (SD_, RD0);
2847 dstreg2 = translate_rreg (SD_, RD2);
2848
2849 temp = ((signed64)(signed32)State.regs[srcreg1]
2850 * (signed64)(signed32)State.regs[srcreg2]);
2851
2852 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2853 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2854 State.regs[dstreg2] = sum;
2855 temp >>= 32;
2856 temp &= 0xffffffff;
2857 sum = State.regs[dstreg1] + temp + c;
2858 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2859 && (temp & 0x80000000) != (sum & 0x80000000));
2860 State.regs[dstreg1] = sum;
2861 if (v)
2862 {
2863 State.regs[REG_MCVF] = 1;
2864 PSW &= ~(PSW_V);
2865 PSW |= (( v ? PSW_V : 0));
2866 }
2867 }
2868
2869 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
2870 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
2871 "macu"
2872 *am33
2873 {
2874 int srcreg1, srcreg2, dstreg1, dstreg2;
2875 signed64 temp;
2876 unsigned32 sum;
2877 int c, v;
2878
2879 PC = cia;
2880 srcreg1 = translate_rreg (SD_, RM2);
2881 srcreg2 = translate_rreg (SD_, RN0);
2882 dstreg1 = translate_rreg (SD_, RD0);
2883 dstreg2 = translate_rreg (SD_, RD2);
2884
2885 temp = ((unsigned64)State.regs[srcreg1]
2886 * (unsigned64)State.regs[srcreg2]);
2887
2888 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2889 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2890 State.regs[dstreg2] = sum;
2891 temp >>= 32;
2892 temp &= 0xffffffff;
2893 sum = State.regs[dstreg1] + temp + c;
2894 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2895 && (temp & 0x80000000) != (sum & 0x80000000));
2896 State.regs[dstreg1] = sum;
2897 if (v)
2898 {
2899 State.regs[REG_MCVF] = 1;
2900 PSW &= ~(PSW_V);
2901 PSW |= (( v ? PSW_V : 0));
2902 }
2903 }
2904
2905 // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
2906 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2907 "macb"
2908 *am33
2909 {
2910 int srcreg1, srcreg2, dstreg;
2911 signed32 temp, sum;
2912 int v;
2913
2914 PC = cia;
2915 srcreg1 = translate_rreg (SD_, RM2);
2916 srcreg2 = translate_rreg (SD_, RN0);
2917 dstreg = translate_rreg (SD_, RD0);
2918
2919 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2920 * (signed32)(State.regs[srcreg1] & 0xff));
2921 sum = State.regs[dstreg] + temp;
2922 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2923 && (temp & 0x80000000) != (sum & 0x80000000));
2924 State.regs[dstreg] = sum;
2925 if (v)
2926 {
2927 State.regs[REG_MCVF] = 1;
2928 PSW &= ~(PSW_V);
2929 PSW |= ((v ? PSW_V : 0));
2930 }
2931 }
2932
2933 // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
2934 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2935 "macbu"
2936 *am33
2937 {
2938 int srcreg1, srcreg2, dstreg;
2939 signed32 temp, sum;
2940 int v;
2941
2942 PC = cia;
2943 srcreg1 = translate_rreg (SD_, RM2);
2944 srcreg2 = translate_rreg (SD_, RN0);
2945 dstreg = translate_rreg (SD_, RD0);
2946
2947 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2948 * (unsigned32)(State.regs[srcreg1] & 0xff));
2949 sum = State.regs[dstreg] + temp;
2950 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2951 && (temp & 0x80000000) != (sum & 0x80000000));
2952 State.regs[dstreg] = sum;
2953 if (v)
2954 {
2955 State.regs[REG_MCVF] = 1;
2956 PSW &= ~(PSW_V);
2957 PSW |= ((v ? PSW_V : 0));
2958 }
2959 }
2960
2961 // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
2962 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
2963 "mach"
2964 *am33
2965 {
2966 int srcreg1, srcreg2, dstreg1, dstreg2;
2967 signed64 temp, sum;
2968 int v;
2969
2970 PC = cia;
2971 srcreg1 = translate_rreg (SD_, RM2);
2972 srcreg2 = translate_rreg (SD_, RN0);
2973 dstreg1 = translate_rreg (SD_, RD0);
2974 dstreg2 = translate_rreg (SD_, RD0);
2975
2976 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2977 * (signed32)(State.regs[srcreg1] & 0xffff));
2978 State.regs[dstreg2] += (temp & 0xffffffff);
2979 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
2980 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2981 && (temp & 0x80000000) != (sum & 0x80000000));
2982 State.regs[dstreg1] = sum;
2983 if (v)
2984 {
2985 State.regs[REG_MCVF] = 1;
2986 PSW &= ~(PSW_V);
2987 PSW |= ((v ? PSW_V : 0));
2988 }
2989 }
2990
2991 // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
2992 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
2993 "machu"
2994 *am33
2995 {
2996 int srcreg1, srcreg2, dstreg1, dstreg2;
2997 signed64 temp, sum;
2998 int v;
2999
3000 PC = cia;
3001 srcreg1 = translate_rreg (SD_, RM2);
3002 srcreg2 = translate_rreg (SD_, RN0);
3003 dstreg1 = translate_rreg (SD_, RD0);
3004 dstreg2 = translate_rreg (SD_, RD0);
3005
3006 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3007 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3008 State.regs[dstreg2] += (temp & 0xffffffff);
3009 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
3010 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
3011 && (temp & 0x80000000) != (sum & 0x80000000));
3012 State.regs[dstreg1] = sum;
3013 if (v)
3014 {
3015 State.regs[REG_MCVF] = 1;
3016 PSW &= ~(PSW_V);
3017 PSW |= ((v ? PSW_V : 0));
3018 }
3019 }
3020
3021 // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
3022 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
3023 "dmach"
3024 *am33
3025 {
3026 int srcreg1, srcreg2, dstreg;
3027 signed32 temp, temp2, sum;
3028 int v;
3029
3030 PC = cia;
3031 srcreg1 = translate_rreg (SD_, RM2);
3032 srcreg2 = translate_rreg (SD_, RN0);
3033 dstreg = translate_rreg (SD_, RD0);
3034
3035 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
3036 * (signed32)(State.regs[srcreg1] & 0xffff));
3037 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3038 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
3039 sum = temp + temp2 + State.regs[dstreg];
3040 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3041 && (temp & 0x80000000) != (sum & 0x80000000));
3042 State.regs[dstreg] = sum;
3043 if (v)
3044 {
3045 State.regs[REG_MCVF] = 1;
3046 PSW &= ~(PSW_V);
3047 PSW |= ((v ? PSW_V : 0));
3048 }
3049 }
3050
3051 // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
3052 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
3053 "dmachu"
3054 *am33
3055 {
3056 int srcreg1, srcreg2, dstreg;
3057 signed32 temp, temp2, sum;
3058 int v;
3059
3060 PC = cia;
3061 srcreg1 = translate_rreg (SD_, RM2);
3062 srcreg2 = translate_rreg (SD_, RN0);
3063 dstreg = translate_rreg (SD_, RD0);
3064
3065 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3066 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3067 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3068 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
3069 sum = temp + temp2 + State.regs[dstreg];
3070 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3071 && (temp & 0x80000000) != (sum & 0x80000000));
3072 State.regs[dstreg] = sum;
3073 if (v)
3074 {
3075 State.regs[REG_MCVF] = 1;
3076 PSW &= ~(PSW_V);
3077 PSW |= ((v ? PSW_V : 0));
3078 }
3079 }
3080
3081 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3082 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
3083 "dmulh"
3084 *am33
3085 {
3086 int srcreg1, srcreg2, dstreg1, dstreg2;
3087 signed64 temp;
3088
3089 PC = cia;
3090 srcreg1 = translate_rreg (SD_, RM2);
3091 srcreg2 = translate_rreg (SD_, RN0);
3092 dstreg1 = translate_rreg (SD_, RD0);
3093 dstreg2 = translate_rreg (SD_, RD2);
3094
3095 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3096 * (signed32)(State.regs[srcreg1] & 0xffff));
3097 State.regs[dstreg2] = temp;
3098 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3099 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3100 State.regs[dstreg1] = temp;
3101 }
3102
3103 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3104 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
3105 "dmulhu"
3106 *am33
3107 {
3108 int srcreg1, srcreg2, dstreg1, dstreg2;
3109 signed64 temp;
3110
3111 PC = cia;
3112 srcreg1 = translate_rreg (SD_, RM2);
3113 srcreg2 = translate_rreg (SD_, RN0);
3114 dstreg1 = translate_rreg (SD_, RD0);
3115 dstreg2 = translate_rreg (SD_, RD2);
3116
3117 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3118 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3119 State.regs[dstreg2] = temp;
3120 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3121 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3122 State.regs[dstreg1] = temp;
3123 }
3124
3125 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3126 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3127 "sat24"
3128 *am33
3129 {
3130 int srcreg, dstreg;
3131 int value, n, z;
3132
3133 PC = cia;
3134 srcreg = translate_rreg (SD_, RM2);
3135 dstreg = translate_rreg (SD_, RN0);
3136
3137 value = State.regs[srcreg];
3138
3139 if (value >= 0x7fffff)
3140 State.regs[dstreg] = 0x7fffff;
3141 else if (value <= 0xff800000)
3142 State.regs[dstreg] = 0xff800000;
3143 else
3144 State.regs[dstreg] = value;
3145
3146 n = (State.regs[dstreg] & 0x800000) != 0;
3147 z = (State.regs[dstreg] == 0);
3148 PSW &= ~(PSW_Z | PSW_N);
3149 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3150 }
3151
3152 // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
3153 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3154 "bsch"
3155 *am33
3156 {
3157 int temp, c, i;
3158 int srcreg1, srcreg2, dstreg;
3159 int start;
3160
3161 PC = cia;
3162 srcreg1 = translate_rreg (SD_, RM2);
3163 srcreg2 = translate_rreg (SD_, RN0);
3164 dstreg = translate_rreg (SD_, RD0);
3165
3166 temp = State.regs[srcreg1];
3167 start = (State.regs[srcreg2] & 0x1f) - 1;
3168 if (start == -1)
3169 start = 31;
3170
3171 for (i = start; i >= 0; i--)
3172 {
3173 if (temp & (1 << i))
3174 {
3175 c = 1;
3176 State.regs[dstreg] = i;
3177 break;
3178 }
3179 }
3180
3181 if (i < 0)
3182 {
3183 c = 0;
3184 State.regs[dstreg] = 0;
3185 }
3186 PSW &= ~(PSW_C);
3187 PSW |= (c ? PSW_C : 0);
3188 }
3189
3190 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3191 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3192 "mov"
3193 *am33
3194 {
3195 int dstreg;
3196
3197 PC = cia;
3198 dstreg = translate_rreg (SD_, RN0);
3199 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3200 }
3201
3202 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
3203 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3204 "movu"
3205 *am33
3206 {
3207 int dstreg;
3208
3209 PC = cia;
3210 dstreg = translate_rreg (SD_, RN0);
3211 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3212 }
3213
3214 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
3215 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3216 "add"
3217 *am33
3218 {
3219 int dstreg;
3220
3221 PC = cia;
3222 dstreg = translate_rreg (SD_, RN0);
3223 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3224 }
3225
3226 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
3227 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3228 "addc"
3229 *am33
3230 {
3231 int dstreg, z, n, c, v;
3232 unsigned32 sum, imm, reg2;
3233
3234 PC = cia;
3235 dstreg = translate_rreg (SD_, RN0);
3236
3237 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3238 reg2 = State.regs[dstreg];
3239 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3240 State.regs[dstreg] = sum;
3241
3242 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3243 n = (sum & 0x80000000);
3244 c = (sum < imm) || (sum < reg2);
3245 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3246 && (reg2 & 0x80000000) != (sum & 0x80000000));
3247
3248 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3249 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3250 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3251 }
3252
3253 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
3254 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3255 "sub"
3256 *am33
3257 {
3258 int dstreg;
3259
3260 PC = cia;
3261 dstreg = translate_rreg (SD_, RN0);
3262 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3263 }
3264
3265 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
3266 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3267 "subc"
3268 *am33
3269 {
3270 int dstreg, z, n, c, v;
3271 unsigned32 difference, imm, reg2;
3272
3273 PC = cia;
3274 dstreg = translate_rreg (SD_, RN0);
3275
3276 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3277 reg2 = State.regs[dstreg];
3278 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3279 State.regs[dstreg] = difference;
3280
3281 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3282 n = (difference & 0x80000000);
3283 c = (imm > reg2);
3284 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3285 && (reg2 & 0x80000000) != (difference & 0x80000000));
3286
3287 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3288 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3289 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3290 }
3291
3292 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
3293 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3294 "cmp"
3295 *am33
3296 {
3297 int srcreg;
3298
3299 PC = cia;
3300 srcreg = translate_rreg (SD_, RN0);
3301 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3302 }
3303
3304 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
3305 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3306 "mov"
3307 *am33
3308 {
3309 int dstreg;
3310
3311 PC = cia;
3312 dstreg = translate_xreg (SD_, XRN0);
3313
3314 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3315 }
3316
3317 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3318 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3319 "and"
3320 *am33
3321 {
3322 int dstreg;
3323 int z,n;
3324
3325 PC = cia;
3326 dstreg = translate_rreg (SD_, RN0);
3327
3328 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3329 z = (State.regs[dstreg] == 0);
3330 n = (State.regs[dstreg] & 0x80000000) != 0;
3331 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3332 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3333 }
3334
3335 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3336 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3337 "or"
3338 *am33
3339 {
3340 int dstreg;
3341 int z,n;
3342
3343 PC = cia;
3344 dstreg = translate_rreg (SD_, RN0);
3345
3346 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3347 z = (State.regs[dstreg] == 0);
3348 n = (State.regs[dstreg] & 0x80000000) != 0;
3349 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3350 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3351 }
3352
3353 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3354 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3355 "xor"
3356 *am33
3357 {
3358 int dstreg;
3359 int z,n;
3360
3361 PC = cia;
3362 dstreg = translate_rreg (SD_, RN0);
3363
3364 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3365 z = (State.regs[dstreg] == 0);
3366 n = (State.regs[dstreg] & 0x80000000) != 0;
3367 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3368 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3369 }
3370
3371 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3372 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3373 "asr"
3374 *am33
3375 {
3376 int dstreg;
3377 signed32 temp;
3378 int c, z, n;
3379
3380 PC = cia;
3381 dstreg = translate_rreg (SD_, RN0);
3382
3383 temp = State.regs[dstreg];
3384 c = temp & 1;
3385 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3386 State.regs[dstreg] = temp;
3387 z = (State.regs[dstreg] == 0);
3388 n = (State.regs[dstreg] & 0x80000000) != 0;
3389 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3390 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3391 }
3392
3393
3394 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3395 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3396 "lsr"
3397 *am33
3398 {
3399 int dstreg;
3400 int z, n, c;
3401
3402 PC = cia;
3403 dstreg = translate_rreg (SD_, RN0);
3404
3405 c = State.regs[dstreg] & 1;
3406 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3407 z = (State.regs[dstreg] == 0);
3408 n = (State.regs[dstreg] & 0x80000000) != 0;
3409 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3410 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3411 }
3412
3413 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3414 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3415 "asl"
3416 *am33
3417 {
3418 int srcreg, dstreg;
3419 int z, n;
3420
3421 PC = cia;
3422 dstreg = translate_rreg (SD_, RN0);
3423
3424 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3425 z = (State.regs[dstreg] == 0);
3426 n = (State.regs[dstreg] & 0x80000000) != 0;
3427 PSW &= ~(PSW_Z | PSW_N);
3428 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3429 }
3430
3431 // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3432 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3433 "mul"
3434 *am33
3435 {
3436 int dstreg;
3437 unsigned64 temp;
3438 int z, n;
3439
3440 PC = cia;
3441 dstreg = translate_rreg (SD_, RN0);
3442
3443 temp = ((signed64)(signed32)State.regs[dstreg]
3444 * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3445 State.regs[dstreg] = temp & 0xffffffff;
3446 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
3447 z = (State.regs[dstreg] == 0);
3448 n = (State.regs[dstreg] & 0x80000000) != 0;
3449 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3450 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3451 }
3452
3453 // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3454 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3455 "mulu"
3456 *am33
3457 {
3458 int dstreg;
3459 unsigned64 temp;
3460 int z, n;
3461
3462 PC = cia;
3463 dstreg = translate_rreg (SD_, RN0);
3464
3465 temp = ((unsigned64)State.regs[dstreg]
3466 * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3467 State.regs[dstreg] = temp & 0xffffffff;
3468 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
3469 z = (State.regs[dstreg] == 0);
3470 n = (State.regs[dstreg] & 0x80000000) != 0;
3471 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3472 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3473 }
3474
3475 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3476 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3477 "btst"
3478 *am33
3479 {
3480 int srcreg;
3481
3482 PC = cia;
3483 srcreg = translate_rreg (SD_, RN0);
3484 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3485 }
3486
3487 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3488 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3489 "mov"
3490 *am33
3491 {
3492 int srcreg, dstreg;
3493
3494 PC = cia;
3495 srcreg = translate_rreg (SD_, RM0);
3496 dstreg = translate_rreg (SD_, RN2);
3497 State.regs[dstreg] = load_word (State.regs[srcreg]
3498 + EXTEND24 (FETCH24 (IMM24A,
3499 IMM24B, IMM24C)));
3500 }
3501
3502 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3503 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3504 "mov"
3505 *am33
3506 {
3507 int srcreg, dstreg;
3508
3509 PC = cia;
3510 srcreg = translate_rreg (SD_, RM2);
3511 dstreg = translate_rreg (SD_, RN0);
3512 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3513 State.regs[srcreg]);
3514 }
3515
3516 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3517 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3518 "movbu"
3519 *am33
3520 {
3521 int srcreg, dstreg;
3522
3523 PC = cia;
3524 srcreg = translate_rreg (SD_, RM0);
3525 dstreg = translate_rreg (SD_, RN2);
3526 State.regs[dstreg] = load_byte (State.regs[srcreg]
3527 + EXTEND24 (FETCH24 (IMM24A,
3528 IMM24B, IMM24C)));
3529 }
3530
3531 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3532 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3533 "movbu"
3534 *am33
3535 {
3536 int srcreg, dstreg;
3537
3538 PC = cia;
3539 srcreg = translate_rreg (SD_, RM2);
3540 dstreg = translate_rreg (SD_, RN0);
3541 store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3542 State.regs[srcreg]);
3543 }
3544
3545 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3546 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3547 "movhu"
3548 *am33
3549 {
3550 int srcreg, dstreg;
3551
3552 PC = cia;
3553 srcreg = translate_rreg (SD_, RM0);
3554 dstreg = translate_rreg (SD_, RN2);
3555 State.regs[dstreg] = load_half (State.regs[srcreg]
3556 + EXTEND24 (FETCH24 (IMM24A,
3557 IMM24B, IMM24C)));
3558 }
3559
3560 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3561 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3562 "movhu"
3563 *am33
3564 {
3565 int srcreg, dstreg;
3566
3567 PC = cia;
3568 srcreg = translate_rreg (SD_, RM2);
3569 dstreg = translate_rreg (SD_, RN0);
3570 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3571 State.regs[srcreg]);
3572 }
3573
3574 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3575 8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3576 "mov"
3577 *am33
3578 {
3579 int srcreg, dstreg;
3580
3581 PC = cia;
3582 srcreg = translate_rreg (SD_, RM0);
3583 dstreg = translate_rreg (SD_, RN2);
3584 State.regs[dstreg] = load_word (State.regs[srcreg]);
3585 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3586 }
3587
3588 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3589 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3590 "mov"
3591 *am33
3592 {
3593 int srcreg, dstreg;
3594
3595 PC = cia;
3596 srcreg = translate_rreg (SD_, RM2);
3597 dstreg = translate_rreg (SD_, RN0);
3598 store_word (State.regs[dstreg], State.regs[srcreg]);
3599 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3600 }
3601
3602
3603 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3604 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3605 "mov"
3606 *am33
3607 {
3608 int dstreg;
3609
3610 PC = cia;
3611 dstreg = translate_rreg (SD_, RN2);
3612 State.regs[dstreg] = load_word (State.regs[REG_SP]
3613 + FETCH24 (IMM24A, IMM24B, IMM24C));
3614 }
3615
3616 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3617 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3618 "mov"
3619 *am33
3620 {
3621 int srcreg;
3622
3623 PC = cia;
3624 srcreg = translate_rreg (SD_, RM2);
3625 store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3626 State.regs[srcreg]);
3627 }
3628
3629 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,sp),Rn
3630 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3631 "movbu"
3632 *am33
3633 {
3634 int dstreg;
3635
3636 PC = cia;
3637 dstreg = translate_rreg (SD_, RN2);
3638 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3639 + FETCH24 (IMM24A, IMM24B, IMM24C));
3640 }
3641
3642 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3643 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3644 "movbu"
3645 *am33
3646 {
3647 int srcreg;
3648
3649 PC = cia;
3650 srcreg = translate_rreg (SD_, RM2);
3651 store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3652 State.regs[srcreg]);
3653 }
3654
3655 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3656 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3657 "movhu"
3658 *am33
3659 {
3660 int dstreg;
3661
3662 PC = cia;
3663 dstreg = translate_rreg (SD_, RN2);
3664 State.regs[dstreg] = load_half (State.regs[REG_SP]
3665 + FETCH24 (IMM24A, IMM24B, IMM24C));
3666 }
3667
3668 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3669 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3670 "movhu"
3671 *am33
3672 {
3673 int srcreg;
3674
3675 PC = cia;
3676 srcreg = translate_rreg (SD_, RM2);
3677 store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3678 State.regs[srcreg]);
3679 }
3680
3681 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3682 8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3683 "movhu"
3684 *am33
3685 {
3686 int srcreg, dstreg;
3687
3688 PC = cia;
3689 srcreg = translate_rreg (SD_, RM0);
3690 dstreg = translate_rreg (SD_, RN2);
3691 State.regs[dstreg] = load_half (State.regs[srcreg]);
3692 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3693 }
3694
3695 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3696 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3697 "movhu"
3698 *am33
3699 {
3700 int srcreg, dstreg;
3701
3702 PC = cia;
3703 srcreg = translate_rreg (SD_, RM2);
3704 dstreg = translate_rreg (SD_, RN0);
3705 store_half (State.regs[dstreg], State.regs[srcreg]);
3706 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3707 }
3708
3709 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
3710 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3711 "mac"
3712 *am33
3713 {
3714 int srcreg;
3715 signed64 temp, sum;
3716 int c, v;
3717
3718 PC = cia;
3719 srcreg = translate_rreg (SD_, RN2);
3720
3721 temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
3722 * (signed64)State.regs[srcreg]);
3723 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3724 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3725 State.regs[REG_MCRL] = sum;
3726 temp >>= 32;
3727 temp &= 0xffffffff;
3728 sum = State.regs[REG_MCRH] + temp + c;
3729 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3730 && (temp & 0x80000000) != (sum & 0x80000000));
3731 State.regs[REG_MCRH] = sum;
3732 if (v)
3733 State.regs[REG_MCVF] = 1;
3734 }
3735
3736 // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
3737 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3738 "macu"
3739 *am33
3740 {
3741 int srcreg;
3742 signed64 temp, sum;
3743 int c, v;
3744
3745 PC = cia;
3746 srcreg = translate_rreg (SD_, RN2);
3747
3748 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3749 * (unsigned64)State.regs[srcreg]);
3750 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3751 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3752 State.regs[REG_MCRL] = sum;
3753 temp >>= 32;
3754 temp &= 0xffffffff;
3755 sum = State.regs[REG_MCRH] + temp + c;
3756 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3757 && (temp & 0x80000000) != (sum & 0x80000000));
3758 State.regs[REG_MCRH] = sum;
3759 if (v)
3760 State.regs[REG_MCVF] = 1;
3761 }
3762
3763 // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
3764 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3765 "macb"
3766 *am33
3767 {
3768 int srcreg;
3769 signed64 temp, sum;
3770 int c, v;
3771
3772 PC = cia;
3773 srcreg = translate_rreg (SD_, RN2);
3774
3775 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3776 * (signed64)State.regs[srcreg] & 0xff);
3777 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3778 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3779 State.regs[REG_MCRL] = sum;
3780 temp >>= 32;
3781 temp &= 0xffffffff;
3782 sum = State.regs[REG_MCRH] + temp + c;
3783 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3784 && (temp & 0x80000000) != (sum & 0x80000000));
3785 State.regs[REG_MCRH] = sum;
3786 if (v)
3787 State.regs[REG_MCVF] = 1;
3788 }
3789
3790 // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
3791 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3792 "macbu"
3793 *am33
3794 {
3795 int srcreg;
3796 signed64 temp, sum;
3797 int c, v;
3798
3799 PC = cia;
3800 srcreg = translate_rreg (SD_, RN2);
3801
3802 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3803 * (unsigned64)State.regs[srcreg] & 0xff);
3804 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3805 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3806 State.regs[REG_MCRL] = sum;
3807 temp >>= 32;
3808 temp &= 0xffffffff;
3809 sum = State.regs[REG_MCRH] + temp + c;
3810 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3811 && (temp & 0x80000000) != (sum & 0x80000000));
3812 State.regs[REG_MCRH] = sum;
3813 if (v)
3814 State.regs[REG_MCVF] = 1;
3815 }
3816
3817 // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
3818 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3819 "mach"
3820 *am33
3821 {
3822 int srcreg;
3823 signed64 temp, sum;
3824 int c, v;
3825
3826 PC = cia;
3827 srcreg = translate_rreg (SD_, RN2);
3828
3829 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3830 * (signed64)State.regs[srcreg] & 0xffff);
3831 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3832 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3833 State.regs[REG_MCRL] = sum;
3834 temp >>= 32;
3835 temp &= 0xffffffff;
3836 sum = State.regs[REG_MCRH] + temp + c;
3837 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3838 && (temp & 0x80000000) != (sum & 0x80000000));
3839 State.regs[REG_MCRH] = sum;
3840 if (v)
3841 State.regs[REG_MCVF] = 1;
3842 }
3843
3844 // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
3845 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3846 "machu"
3847 *am33
3848 {
3849 int srcreg;
3850 signed64 temp, sum;
3851 int c, v;
3852
3853 PC = cia;
3854 srcreg = translate_rreg (SD_, RN2);
3855
3856 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3857 * (unsigned64)State.regs[srcreg] & 0xffff);
3858 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3859 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3860 State.regs[REG_MCRL] = sum;
3861 temp >>= 32;
3862 temp &= 0xffffffff;
3863 sum = State.regs[REG_MCRH] + temp + c;
3864 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3865 && (temp & 0x80000000) != (sum & 0x80000000));
3866 State.regs[REG_MCRH] = sum;
3867 if (v)
3868 State.regs[REG_MCVF] = 1;
3869 }
3870
3871 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3872 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3873 "mov"
3874 *am33
3875 {
3876 int dstreg;
3877
3878 PC = cia;
3879 dstreg = translate_rreg (SD_, RN2);
3880 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3881 }
3882
3883 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3884 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3885 "mov"
3886 *am33
3887 {
3888 int srcreg;
3889
3890 PC = cia;
3891 srcreg = translate_rreg (SD_, RM2);
3892 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3893 }
3894
3895
3896 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3897 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3898 "movbu"
3899 *am33
3900 {
3901 int dstreg;
3902
3903 PC = cia;
3904 dstreg = translate_rreg (SD_, RN2);
3905 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3906 }
3907
3908 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3909 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3910 "movbu"
3911 *am33
3912 {
3913 int srcreg;
3914
3915 PC = cia;
3916 srcreg = translate_rreg (SD_, RM2);
3917 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3918 }
3919
3920
3921 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3922 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3923 "movhu"
3924 *am33
3925 {
3926 int dstreg;
3927
3928 PC = cia;
3929 dstreg = translate_rreg (SD_, RN2);
3930 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3931 }
3932
3933 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3934 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3935 "movhu"
3936 *am33
3937 {
3938 int srcreg;
3939
3940 PC = cia;
3941 srcreg = translate_rreg (SD_, RM2);
3942 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3943 }
3944
3945
3946 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3947 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3948 "mov"
3949 *am33
3950 {
3951 int dstreg;
3952
3953 PC = cia;
3954 dstreg = translate_rreg (SD_, RN0);
3955 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3956 }
3957
3958 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3959 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3960 "movu"
3961 *am33
3962 {
3963 int dstreg;
3964
3965 PC = cia;
3966 dstreg = translate_rreg (SD_, RN0);
3967 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3968 }
3969
3970 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3971 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3972 "add"
3973 *am33
3974 {
3975 int dstreg;
3976
3977 PC = cia;
3978 dstreg = translate_rreg (SD_, RN0);
3979 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3980 }
3981
3982 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3983 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3984 "addc"
3985 *am33
3986 {
3987 int dstreg;
3988 unsigned32 imm, reg2, sum;
3989 int z, n, c, v;
3990
3991 PC = cia;
3992 dstreg = translate_rreg (SD_, RN0);
3993
3994 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3995 reg2 = State.regs[dstreg];
3996 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3997 State.regs[dstreg] = sum;
3998
3999 z = ((PSW & PSW_Z) != 0) && (sum == 0);
4000 n = (sum & 0x80000000);
4001 c = (sum < imm) || (sum < reg2);
4002 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4003 && (reg2 & 0x80000000) != (sum & 0x80000000));
4004
4005 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4006 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4007 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4008 }
4009
4010 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
4011 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
4012 "sub"
4013 *am33
4014 {
4015 int dstreg;
4016
4017 PC = cia;
4018 dstreg = translate_rreg (SD_, RN0);
4019 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
4020 }
4021
4022 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
4023 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4024 "subc"
4025 *am33
4026 {
4027 int dstreg;
4028 unsigned32 imm, reg2, difference;
4029 int z, n, c, v;
4030
4031 PC = cia;
4032 dstreg = translate_rreg (SD_, RN0);
4033
4034 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4035 reg2 = State.regs[dstreg];
4036 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4037 State.regs[dstreg] = difference;
4038
4039 z = ((PSW & PSW_Z) != 0) && (difference == 0);
4040 n = (difference & 0x80000000);
4041 c = (imm > reg2);
4042 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4043 && (reg2 & 0x80000000) != (difference & 0x80000000));
4044
4045 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4046 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4047 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4048 }
4049
4050 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
4051 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4052 "cmp"
4053 *am33
4054 {
4055 int srcreg;
4056
4057 PC = cia;
4058 srcreg = translate_rreg (SD_, RN0);
4059 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4060 }
4061
4062 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
4063 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
4064 "mov"
4065 *am33
4066 {
4067 int dstreg;
4068
4069 PC = cia;
4070 dstreg = translate_xreg (SD_, XRN0);
4071
4072 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4073 }
4074
4075 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
4076 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4077 "and"
4078 *am33
4079 {
4080 int dstreg;
4081 int z,n;
4082
4083 PC = cia;
4084 dstreg = translate_rreg (SD_, RN0);
4085
4086 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4087 z = (State.regs[dstreg] == 0);
4088 n = (State.regs[dstreg] & 0x80000000) != 0;
4089 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4090 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4091 }
4092
4093 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
4094 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4095 "or"
4096 *am33
4097 {
4098 int dstreg;
4099 int z,n;
4100
4101 PC = cia;
4102 dstreg = translate_rreg (SD_, RN0);
4103
4104 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4105 z = (State.regs[dstreg] == 0);
4106 n = (State.regs[dstreg] & 0x80000000) != 0;
4107 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4108 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4109 }
4110
4111 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
4112 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4113 "xor"
4114 *am33
4115 {
4116 int dstreg;
4117 int z,n;
4118
4119 PC = cia;
4120 dstreg = translate_rreg (SD_, RN0);
4121
4122 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4123 z = (State.regs[dstreg] == 0);
4124 n = (State.regs[dstreg] & 0x80000000) != 0;
4125 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4126 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4127 }
4128
4129 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
4130 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4131 "asr"
4132 *am33
4133 {
4134 int dstreg;
4135 signed32 temp;
4136 int c, z, n;
4137
4138 PC = cia;
4139 dstreg = translate_rreg (SD_, RN0);
4140
4141 temp = State.regs[dstreg];
4142 c = temp & 1;
4143 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4144 State.regs[dstreg] = temp;
4145 z = (State.regs[dstreg] == 0);
4146 n = (State.regs[dstreg] & 0x80000000) != 0;
4147 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4148 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4149 }
4150
4151 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
4152 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4153 "lsr"
4154 *am33
4155 {
4156 int dstreg;
4157 int z, n, c;
4158
4159 PC = cia;
4160 dstreg = translate_rreg (SD_, RN0);
4161
4162 c = State.regs[dstreg] & 1;
4163 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4164 z = (State.regs[dstreg] == 0);
4165 n = (State.regs[dstreg] & 0x80000000) != 0;
4166 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4167 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4168 }
4169
4170 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
4171 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4172 "asl"
4173 *am33
4174 {
4175 int srcreg, dstreg;
4176 int z, n;
4177
4178 PC = cia;
4179 dstreg = translate_rreg (SD_, RN0);
4180
4181 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4182 z = (State.regs[dstreg] == 0);
4183 n = (State.regs[dstreg] & 0x80000000) != 0;
4184 PSW &= ~(PSW_Z | PSW_N);
4185 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4186 }
4187
4188 // 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
4189 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
4190 "mul"
4191 *am33
4192 {
4193 int dstreg;
4194 unsigned64 temp;
4195 int z, n;
4196
4197 PC = cia;
4198 dstreg = translate_rreg (SD_, RN0);
4199
4200 temp = ((signed64)(signed32)State.regs[dstreg]
4201 * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4202 State.regs[dstreg] = temp & 0xffffffff;
4203 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
4204 z = (State.regs[dstreg] == 0);
4205 n = (State.regs[dstreg] & 0x80000000) != 0;
4206 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4207 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4208 }
4209
4210 // 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
4211 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
4212 "mulu"
4213 *am33
4214 {
4215 int dstreg;
4216 unsigned64 temp;
4217 int z, n;
4218
4219 PC = cia;
4220 dstreg = translate_rreg (SD_, RN0);
4221
4222 temp = ((unsigned64)State.regs[dstreg]
4223 * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4224 State.regs[dstreg] = temp & 0xffffffff;
4225 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
4226 z = (State.regs[dstreg] == 0);
4227 n = (State.regs[dstreg] & 0x80000000) != 0;
4228 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4229 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4230 }
4231
4232 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
4233 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4234 "btst"
4235 *am33
4236 {
4237 int srcreg;
4238
4239 PC = cia;
4240 srcreg = translate_rreg (SD_, RN0);
4241 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4242 }
4243
4244 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
4245 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4246 "mov"
4247 *am33
4248 {
4249 int srcreg, dstreg;
4250
4251 PC = cia;
4252 srcreg = translate_rreg (SD_, RM0);
4253 dstreg = translate_rreg (SD_, RN2);
4254 State.regs[dstreg] = load_word (State.regs[srcreg]
4255 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4256 }
4257
4258 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
4259 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4260 "mov"
4261 *am33
4262 {
4263 int srcreg, dstreg;
4264
4265 PC = cia;
4266 srcreg = translate_rreg (SD_, RM2);
4267 dstreg = translate_rreg (SD_, RN0);
4268 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4269 State.regs[srcreg]);
4270 }
4271
4272 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
4273 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4274 "movbu"
4275 *am33
4276 {
4277 int srcreg, dstreg;
4278
4279 PC = cia;
4280 srcreg = translate_rreg (SD_, RM0);
4281 dstreg = translate_rreg (SD_, RN2);
4282 State.regs[dstreg] = load_byte (State.regs[srcreg]
4283 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4284 }
4285
4286 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
4287 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4288 "movbu"
4289 *am33
4290 {
4291 int srcreg, dstreg;
4292
4293 PC = cia;
4294 srcreg = translate_rreg (SD_, RM2);
4295 dstreg = translate_rreg (SD_, RN0);
4296 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4297 State.regs[srcreg]);
4298 }
4299
4300 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
4301 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4302 "movhu"
4303 *am33
4304 {
4305 int srcreg, dstreg;
4306
4307 PC = cia;
4308 srcreg = translate_rreg (SD_, RM0);
4309 dstreg = translate_rreg (SD_, RN2);
4310 State.regs[dstreg] = load_half (State.regs[srcreg]
4311 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4312 }
4313
4314 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
4315 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4316 "movhu"
4317 *am33
4318 {
4319 int srcreg, dstreg;
4320
4321 PC = cia;
4322 srcreg = translate_rreg (SD_, RM2);
4323 dstreg = translate_rreg (SD_, RN0);
4324 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4325 State.regs[srcreg]);
4326 }
4327
4328 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
4329 8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4330 "mov"
4331 *am33
4332 {
4333 int srcreg, dstreg;
4334
4335 PC = cia;
4336 srcreg = translate_rreg (SD_, RM0);
4337 dstreg = translate_rreg (SD_, RN2);
4338 State.regs[dstreg] = load_word (State.regs[srcreg]);
4339 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4340 }
4341
4342 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
4343 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4344 "mov"
4345 *am33
4346 {
4347 int srcreg, dstreg;
4348
4349 PC = cia;
4350 srcreg = translate_rreg (SD_, RM2);
4351 dstreg = translate_rreg (SD_, RN0);
4352 store_word (State.regs[dstreg], State.regs[srcreg]);
4353 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4354 }
4355
4356
4357 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
4358 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4359 "mov"
4360 *am33
4361 {
4362 int dstreg;
4363
4364 PC = cia;
4365 dstreg = translate_rreg (SD_, RN2);
4366 State.regs[dstreg] = load_word (State.regs[REG_SP]
4367 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4368 }
4369
4370 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
4371 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4372 "mov"
4373 *am33
4374 {
4375 int srcreg;
4376
4377 PC = cia;
4378 srcreg = translate_rreg (SD_, RM2);
4379 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4380 State.regs[srcreg]);
4381 }
4382
4383 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
4384 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4385 "movbu"
4386 *am33
4387 {
4388 int dstreg;
4389
4390 PC = cia;
4391 dstreg = translate_rreg (SD_, RN2);
4392 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4393 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4394 }
4395
4396 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
4397 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4398 "movbu"
4399 *am33
4400 {
4401 int srcreg;
4402
4403 PC = cia;
4404 srcreg = translate_rreg (SD_, RM2);
4405 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4406 State.regs[srcreg]);
4407 }
4408
4409 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4410 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4411 "movhu"
4412 *am33
4413 {
4414 int dstreg;
4415
4416 PC = cia;
4417 dstreg = translate_rreg (SD_, RN2);
4418 State.regs[dstreg] = load_half (State.regs[REG_SP]
4419 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4420 }
4421
4422 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4423 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4424 "movhu"
4425 *am33
4426 {
4427 int srcreg;
4428
4429 PC = cia;
4430 srcreg = translate_rreg (SD_, RM2);
4431 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4432 State.regs[srcreg]);
4433 }
4434
4435
4436 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
4437 8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4438 "movhu"
4439 *am33
4440 {
4441 int srcreg, dstreg;
4442
4443 PC = cia;
4444 srcreg = translate_rreg (SD_, RM0);
4445 dstreg = translate_rreg (SD_, RN2);
4446 State.regs[dstreg] = load_half (State.regs[srcreg]);
4447 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4448 }
4449
4450 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
4451 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4452 "movhu"
4453 *am33
4454 {
4455 int srcreg, dstreg;
4456
4457 PC = cia;
4458 srcreg = translate_rreg (SD_, RM2);
4459 dstreg = translate_rreg (SD_, RN0);
4460 store_half (State.regs[dstreg], State.regs[srcreg]);
4461 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4462 }
4463
4464
4465 // 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
4466 8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
4467 "mac"
4468 *am33
4469 {
4470 int srcreg, imm;
4471 signed64 temp, sum;
4472 int c, v;
4473
4474 PC = cia;
4475 srcreg = translate_rreg (SD_, RN0);
4476 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4477
4478 temp = ((signed64)(signed32)State.regs[srcreg]
4479 * (signed64)(signed32)imm);
4480 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4481 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4482 State.regs[REG_MCRL] = sum;
4483 temp >>= 32;
4484 temp &= 0xffffffff;
4485 sum = State.regs[REG_MCRH] + temp + c;
4486 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4487 && (temp & 0x80000000) != (sum & 0x80000000));
4488 State.regs[REG_MCRH] = sum;
4489 if (v)
4490 State.regs[REG_MCVF] = 1;
4491 }
4492
4493 // 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
4494 8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
4495 "macu"
4496 *am33
4497 {
4498 int srcreg, imm;
4499 signed64 temp, sum;
4500 int c, v;
4501
4502 PC = cia;
4503 srcreg = translate_rreg (SD_, RN0);
4504 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4505
4506 temp = ((unsigned64)State.regs[srcreg]
4507 * (unsigned64)imm);
4508 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4509 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4510 State.regs[REG_MCRL] = sum;
4511 temp >>= 32;
4512 temp &= 0xffffffff;
4513 sum = State.regs[REG_MCRH] + temp + c;
4514 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4515 && (temp & 0x80000000) != (sum & 0x80000000));
4516 State.regs[REG_MCRH] = sum;
4517 if (v)
4518 State.regs[REG_MCVF] = 1;
4519 }
4520
4521 // 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
4522 8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
4523 "macb"
4524 *am33
4525 {
4526 int srcreg, imm;
4527 signed32 temp, sum;
4528 int v;
4529
4530 PC = cia;
4531 srcreg = translate_rreg (SD_, RN0);
4532 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4533
4534 temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
4535 * (signed32)(signed8)(imm & 0xff));
4536 sum = State.regs[REG_MCRL] + temp;
4537 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4538 && (temp & 0x80000000) != (sum & 0x80000000));
4539 State.regs[REG_MCRL] = sum;
4540 if (v)
4541 State.regs[REG_MCVF] = 1;
4542 }
4543
4544 // 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
4545 8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
4546 "macbu"
4547 *am33
4548 {
4549 int srcreg, imm;
4550 signed32 temp, sum;
4551 int v;
4552
4553 PC = cia;
4554 srcreg = translate_rreg (SD_, RN0);
4555 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4556
4557 temp = ((unsigned32)(State.regs[srcreg] & 0xff)
4558 * (unsigned32)(imm & 0xff));
4559 sum = State.regs[REG_MCRL] + temp;
4560 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4561 && (temp & 0x80000000) != (sum & 0x80000000));
4562 State.regs[REG_MCRL] = sum;
4563 if (v)
4564 State.regs[REG_MCVF] = 1;
4565 }
4566
4567 // 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
4568 8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
4569 "mach"
4570 *am33
4571 {
4572 int srcreg, imm;
4573 signed32 temp, sum;
4574 int v;
4575
4576 PC = cia;
4577 srcreg = translate_rreg (SD_, RN0);
4578 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4579
4580 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4581 * (signed32)(signed16)(imm & 0xffff));
4582 sum = State.regs[REG_MCRL] + temp;
4583 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4584 && (temp & 0x80000000) != (sum & 0x80000000));
4585 State.regs[REG_MCRL] = sum;
4586 if (v)
4587 State.regs[REG_MCVF] = 1;
4588 }
4589
4590 // 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
4591 8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
4592 "machu"
4593 *am33
4594 {
4595 int srcreg, imm;
4596 signed32 temp, sum;
4597 int v;
4598
4599 PC = cia;
4600 srcreg = translate_rreg (SD_, RN0);
4601 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4602
4603 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4604 * (unsigned32)(imm & 0xffff));
4605 sum = State.regs[REG_MCRL] + temp;
4606 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4607 && (temp & 0x80000000) != (sum & 0x80000000));
4608 State.regs[REG_MCRL] = sum;
4609 if (v)
4610 State.regs[REG_MCVF] = 1;
4611 }
4612
4613 // 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
4614 8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
4615 "dmach"
4616 *am33
4617 {
4618 int srcreg, imm;
4619 signed32 temp, temp2, sum;
4620 int v;
4621
4622 PC = cia;
4623 srcreg = translate_rreg (SD_, RN0);
4624 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4625
4626 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4627 * (signed32)(signed16)(imm & 0xffff));
4628 temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
4629 * (signed32)(signed16)((imm >> 16) & 0xffff));
4630 sum = temp + temp2 + State.regs[REG_MCRL];
4631 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4632 && (temp & 0x80000000) != (sum & 0x80000000));
4633 State.regs[REG_MCRL] = sum;
4634 if (v)
4635 State.regs[REG_MCVF] = 1;
4636 }
4637
4638 // 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
4639 8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
4640 "dmachu"
4641 *am33
4642 {
4643 int srcreg, imm;
4644 signed32 temp, temp2, sum;
4645 int v;
4646
4647 PC = cia;
4648 srcreg = translate_rreg (SD_, RN0);
4649 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4650
4651 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4652 * (unsigned32)(imm & 0xffff));
4653 temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
4654 * (unsigned32)((imm >> 16) & 0xffff));
4655 sum = temp + temp2 + State.regs[REG_MCRL];
4656 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4657 && (temp & 0x80000000) != (sum & 0x80000000));
4658 State.regs[REG_MCRL] = sum;
4659 if (v)
4660 State.regs[REG_MCVF] = 1;
4661 }
4662
4663 // 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
4664 8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
4665 "dmulh"
4666 *am33
4667 {
4668 int imm, dstreg;
4669 signed32 temp;
4670
4671 PC = cia;
4672 dstreg = translate_rreg (SD_, RN0);
4673 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4674
4675 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
4676 * (signed32)(signed16)(imm & 0xffff));
4677 State.regs[REG_MDRQ] = temp;
4678 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
4679 * (signed32)(signed16)((imm>>16) & 0xffff));
4680 State.regs[dstreg] = temp;
4681 }
4682
4683 // 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
4684 8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
4685 "dmulhu"
4686 *am33
4687 {
4688 int imm, dstreg;
4689 signed32 temp;
4690
4691 PC = cia;
4692 dstreg = translate_rreg (SD_, RN0);
4693 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4694
4695 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
4696 * (unsigned32)(imm & 0xffff));
4697 State.regs[REG_MDRQ] = temp;
4698 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
4699 * (unsigned32)((imm >>16) & 0xffff));
4700 State.regs[dstreg] = temp;
4701 }
4702
4703 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4704 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4705 "mov"
4706 *am33
4707 {
4708 int dstreg;
4709
4710 PC = cia;
4711 dstreg = translate_rreg (SD_, RN2);
4712 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4713 }
4714
4715 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4716 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4717 "mov"
4718 *am33
4719 {
4720 int srcreg;
4721
4722 PC = cia;
4723 srcreg = translate_rreg (SD_, RM2);
4724 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4725 }
4726
4727 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4728 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4729 "movbu"
4730 *am33
4731 {
4732 int dstreg;
4733
4734 PC = cia;
4735 dstreg = translate_rreg (SD_, RN2);
4736 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4737 }
4738
4739 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4740 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4741 "movbu"
4742 *am33
4743 {
4744 int srcreg;
4745
4746 PC = cia;
4747 srcreg = translate_rreg (SD_, RM2);
4748 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4749 }
4750
4751 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4752 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4753 "movhu"
4754 *am33
4755 {
4756 int dstreg;
4757
4758 PC = cia;
4759 dstreg = translate_rreg (SD_, RN2);
4760 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4761 }
4762
4763 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4764 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4765 "movhu"
4766 *am33
4767 {
4768 int srcreg;
4769
4770 PC = cia;
4771 srcreg = translate_rreg (SD_, RM2);
4772 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4773 }
4774
4775 // 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
4776 8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
4777 "add_add"
4778 *am33
4779 {
4780 int srcreg1, srcreg2, dstreg1, dstreg2;
4781 int result1;
4782
4783 PC = cia;
4784 srcreg1 = translate_rreg (SD_, RM1);
4785 srcreg2 = translate_rreg (SD_, RM2);
4786 dstreg1 = translate_rreg (SD_, RN1);
4787 dstreg2 = translate_rreg (SD_, RN2);
4788
4789 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4790 State.regs[dstreg2] += State.regs[srcreg2];
4791 State.regs[dstreg1] = result1;
4792 }
4793
4794 // 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
4795 8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
4796 "add_add"
4797 *am33
4798 {
4799 int srcreg1, dstreg1, dstreg2;
4800 int result1;
4801
4802 PC = cia;
4803 srcreg1 = translate_rreg (SD_, RM1);
4804 dstreg1 = translate_rreg (SD_, RN1);
4805 dstreg2 = translate_rreg (SD_, RN2);
4806
4807 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4808 State.regs[dstreg2] += EXTEND4 (IMM4);
4809 State.regs[dstreg1] = result1;
4810 }
4811
4812 // 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
4813 8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
4814 "add_sub"
4815 *am33
4816 {
4817 int srcreg1, srcreg2, dstreg1, dstreg2;
4818 int result1;
4819
4820 PC = cia;
4821 srcreg1 = translate_rreg (SD_, RM1);
4822 srcreg2 = translate_rreg (SD_, RM2);
4823 dstreg1 = translate_rreg (SD_, RN1);
4824 dstreg2 = translate_rreg (SD_, RN2);
4825
4826 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4827 State.regs[dstreg2] -= State.regs[srcreg2];
4828 State.regs[dstreg1] = result1;
4829 }
4830
4831 // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
4832 8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
4833 "add_sub"
4834 *am33
4835 {
4836 int srcreg1, dstreg1, dstreg2;
4837 int result1;
4838
4839 PC = cia;
4840 srcreg1 = translate_rreg (SD_, RM1);
4841 dstreg1 = translate_rreg (SD_, RN1);
4842 dstreg2 = translate_rreg (SD_, RN2);
4843
4844 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4845 State.regs[dstreg2] -= EXTEND4 (IMM4);
4846 State.regs[dstreg1] = result1;
4847 }
4848
4849 // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
4850 8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
4851 "add_cmp"
4852 *am33
4853 {
4854 int srcreg1, srcreg2, dstreg1, dstreg2;
4855
4856 PC = cia;
4857 srcreg1 = translate_rreg (SD_, RM1);
4858 srcreg2 = translate_rreg (SD_, RM2);
4859 dstreg1 = translate_rreg (SD_, RN1);
4860 dstreg2 = translate_rreg (SD_, RN2);
4861
4862 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
4863 State.regs[dstreg1] += State.regs[srcreg1];
4864 }
4865
4866 // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
4867 8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
4868 "add_cmp"
4869 *am33
4870 {
4871 int srcreg1, dstreg1, dstreg2;
4872
4873 PC = cia;
4874 srcreg1 = translate_rreg (SD_, RM1);
4875 dstreg1 = translate_rreg (SD_, RN1);
4876 dstreg2 = translate_rreg (SD_, RN2);
4877
4878 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
4879 State.regs[dstreg1] += State.regs[srcreg1];
4880 }
4881
4882 // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
4883 8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
4884 "add_mov"
4885 *am33
4886 {
4887 int srcreg1, srcreg2, dstreg1, dstreg2;
4888 int result1;
4889
4890 PC = cia;
4891 srcreg1 = translate_rreg (SD_, RM1);
4892 srcreg2 = translate_rreg (SD_, RM2);
4893 dstreg1 = translate_rreg (SD_, RN1);
4894 dstreg2 = translate_rreg (SD_, RN2);
4895
4896 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4897 State.regs[dstreg2] = State.regs[srcreg2];
4898 State.regs[dstreg1] = result1;
4899 }
4900
4901 // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
4902 8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
4903 "add_mov"
4904 *am33
4905 {
4906 int srcreg1, dstreg1, dstreg2;
4907 int result1;
4908
4909 PC = cia;
4910 srcreg1 = translate_rreg (SD_, RM1);
4911 dstreg1 = translate_rreg (SD_, RN1);
4912 dstreg2 = translate_rreg (SD_, RN2);
4913
4914 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4915 State.regs[dstreg2] = EXTEND4 (IMM4);
4916 State.regs[dstreg1] = result1;
4917 }
4918
4919 // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
4920 8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
4921 "add_asr"
4922 *am33
4923 {
4924 int srcreg1, srcreg2, dstreg1, dstreg2;
4925 int result1;
4926 signed int temp;
4927
4928 PC = cia;
4929 srcreg1 = translate_rreg (SD_, RM1);
4930 srcreg2 = translate_rreg (SD_, RM2);
4931 dstreg1 = translate_rreg (SD_, RN1);
4932 dstreg2 = translate_rreg (SD_, RN2);
4933
4934 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4935 temp = State.regs[dstreg2];
4936 temp >>= State.regs[srcreg2];
4937 State.regs[dstreg2] = temp;
4938 State.regs[dstreg1] = result1;
4939 }
4940
4941 // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
4942 8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
4943 "add_asr"
4944 *am33
4945 {
4946 int srcreg1, dstreg1, dstreg2;
4947 int result1;
4948 signed int temp;
4949
4950 PC = cia;
4951 srcreg1 = translate_rreg (SD_, RM1);
4952 dstreg1 = translate_rreg (SD_, RN1);
4953 dstreg2 = translate_rreg (SD_, RN2);
4954
4955 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4956 temp = State.regs[dstreg2];
4957 temp >>= IMM4;
4958 State.regs[dstreg2] = temp;
4959 State.regs[dstreg1] = result1;
4960 }
4961
4962 // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
4963 8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
4964 "add_lsr"
4965 *am33
4966 {
4967 int srcreg1, srcreg2, dstreg1, dstreg2;
4968 int result1;
4969
4970 PC = cia;
4971 srcreg1 = translate_rreg (SD_, RM1);
4972 srcreg2 = translate_rreg (SD_, RM2);
4973 dstreg1 = translate_rreg (SD_, RN1);
4974 dstreg2 = translate_rreg (SD_, RN2);
4975
4976 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4977 State.regs[dstreg2] >>= State.regs[srcreg2];
4978 State.regs[dstreg1] = result1;
4979 }
4980
4981 // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
4982 8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
4983 "add_lsr"
4984 *am33
4985 {
4986 int srcreg1, dstreg1, dstreg2;
4987 int result1;
4988 signed int temp;
4989
4990 PC = cia;
4991 srcreg1 = translate_rreg (SD_, RM1);
4992 dstreg1 = translate_rreg (SD_, RN1);
4993 dstreg2 = translate_rreg (SD_, RN2);
4994
4995 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4996 State.regs[dstreg2] >>= IMM4;
4997 State.regs[dstreg1] = result1;
4998 }
4999
5000
5001 // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
5002 8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
5003 "add_asl"
5004 *am33
5005 {
5006 int srcreg1, srcreg2, dstreg1, dstreg2;
5007 int result1;
5008
5009 PC = cia;
5010 srcreg1 = translate_rreg (SD_, RM1);
5011 srcreg2 = translate_rreg (SD_, RM2);
5012 dstreg1 = translate_rreg (SD_, RN1);
5013 dstreg2 = translate_rreg (SD_, RN2);
5014
5015 result1 = State.regs[dstreg1] + State.regs[srcreg1];
5016 State.regs[dstreg2] <<= State.regs[srcreg2];
5017 State.regs[dstreg1] = result1;
5018 }
5019
5020 // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
5021 8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
5022 "add_asl"
5023 *am33
5024 {
5025 int srcreg1, dstreg1, dstreg2;
5026 int result1;
5027 signed int temp;
5028
5029 PC = cia;
5030 srcreg1 = translate_rreg (SD_, RM1);
5031 dstreg1 = translate_rreg (SD_, RN1);
5032 dstreg2 = translate_rreg (SD_, RN2);
5033
5034 result1 = State.regs[dstreg1] + State.regs[srcreg1];
5035 State.regs[dstreg2] <<= IMM4;
5036 State.regs[dstreg1] = result1;
5037 }
5038
5039 // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
5040 8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
5041 "cmp_add"
5042 *am33
5043 {
5044 int srcreg1, srcreg2, dstreg1, dstreg2;
5045
5046 PC = cia;
5047 srcreg1 = translate_rreg (SD_, RM1);
5048 srcreg2 = translate_rreg (SD_, RM2);
5049 dstreg1 = translate_rreg (SD_, RN1);
5050 dstreg2 = translate_rreg (SD_, RN2);
5051
5052 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5053 State.regs[dstreg2] += State.regs[srcreg2];
5054 }
5055
5056 // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
5057 8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
5058 "cmp_add"
5059 *am33
5060 {
5061 int srcreg1, dstreg1, dstreg2;
5062
5063 PC = cia;
5064 srcreg1 = translate_rreg (SD_, RM1);
5065 dstreg1 = translate_rreg (SD_, RN1);
5066 dstreg2 = translate_rreg (SD_, RN2);
5067
5068 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5069 State.regs[dstreg2] += EXTEND4 (IMM4);
5070 }
5071
5072 // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
5073 8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
5074 "cmp_sub"
5075 *am33
5076 {
5077 int srcreg1, srcreg2, dstreg1, dstreg2;
5078
5079 PC = cia;
5080 srcreg1 = translate_rreg (SD_, RM1);
5081 srcreg2 = translate_rreg (SD_, RM2);
5082 dstreg1 = translate_rreg (SD_, RN1);
5083 dstreg2 = translate_rreg (SD_, RN2);
5084
5085 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5086 State.regs[dstreg2] -= State.regs[srcreg2];
5087 }
5088
5089 // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
5090 8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
5091 "cmp_sub"
5092 *am33
5093 {
5094 int srcreg1, dstreg1, dstreg2;
5095
5096 PC = cia;
5097 srcreg1 = translate_rreg (SD_, RM1);
5098 dstreg1 = translate_rreg (SD_, RN1);
5099 dstreg2 = translate_rreg (SD_, RN2);
5100
5101 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5102 State.regs[dstreg2] -= EXTEND4 (IMM4);
5103 }
5104
5105 // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
5106 8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
5107 "cmp_mov"
5108 *am33
5109 {
5110 int srcreg1, srcreg2, dstreg1, dstreg2;
5111
5112 PC = cia;
5113 srcreg1 = translate_rreg (SD_, RM1);
5114 srcreg2 = translate_rreg (SD_, RM2);
5115 dstreg1 = translate_rreg (SD_, RN1);
5116 dstreg2 = translate_rreg (SD_, RN2);
5117
5118 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5119 State.regs[dstreg2] = State.regs[srcreg2];
5120 }
5121
5122 // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
5123 8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
5124 "cmp_mov"
5125 *am33
5126 {
5127 int srcreg1, dstreg1, dstreg2;
5128
5129 PC = cia;
5130 srcreg1 = translate_rreg (SD_, RM1);
5131 dstreg1 = translate_rreg (SD_, RN1);
5132 dstreg2 = translate_rreg (SD_, RN2);
5133
5134 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5135 State.regs[dstreg2] = EXTEND4 (IMM4);
5136 }
5137
5138 // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
5139 8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
5140 "cmp_asr"
5141 *am33
5142 {
5143 int srcreg1, srcreg2, dstreg1, dstreg2;
5144 signed int temp;
5145
5146 PC = cia;
5147 srcreg1 = translate_rreg (SD_, RM1);
5148 srcreg2 = translate_rreg (SD_, RM2);
5149 dstreg1 = translate_rreg (SD_, RN1);
5150 dstreg2 = translate_rreg (SD_, RN2);
5151
5152 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5153 temp = State.regs[dstreg2];
5154 temp >>= State.regs[srcreg2];
5155 State.regs[dstreg2] = temp;
5156 }
5157
5158 // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
5159 8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
5160 "cmp_asr"
5161 *am33
5162 {
5163 int srcreg1, dstreg1, dstreg2;
5164 signed int temp;
5165
5166 PC = cia;
5167 srcreg1 = translate_rreg (SD_, RM1);
5168 dstreg1 = translate_rreg (SD_, RN1);
5169 dstreg2 = translate_rreg (SD_, RN2);
5170
5171 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5172 temp = State.regs[dstreg2];
5173 temp >>= IMM4;
5174 State.regs[dstreg2] = temp;
5175 }
5176
5177 // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
5178 8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
5179 "cmp_lsr"
5180 *am33
5181 {
5182 int srcreg1, srcreg2, dstreg1, dstreg2;
5183
5184 PC = cia;
5185 srcreg1 = translate_rreg (SD_, RM1);
5186 srcreg2 = translate_rreg (SD_, RM2);
5187 dstreg1 = translate_rreg (SD_, RN1);
5188 dstreg2 = translate_rreg (SD_, RN2);
5189
5190 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5191 State.regs[dstreg2] >>= State.regs[srcreg2];
5192 }
5193
5194 // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
5195 8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
5196 "cmp_lsr"
5197 *am33
5198 {
5199 int srcreg1, dstreg1, dstreg2;
5200 signed int temp;
5201
5202 PC = cia;
5203 srcreg1 = translate_rreg (SD_, RM1);
5204 dstreg1 = translate_rreg (SD_, RN1);
5205 dstreg2 = translate_rreg (SD_, RN2);
5206
5207 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5208 State.regs[dstreg2] >>= IMM4;
5209 }
5210
5211
5212 // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
5213 8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
5214 "cmp_asl"
5215 *am33
5216 {
5217 int srcreg1, srcreg2, dstreg1, dstreg2;
5218
5219 PC = cia;
5220 srcreg1 = translate_rreg (SD_, RM1);
5221 srcreg2 = translate_rreg (SD_, RM2);
5222 dstreg1 = translate_rreg (SD_, RN1);
5223 dstreg2 = translate_rreg (SD_, RN2);
5224
5225 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5226 State.regs[dstreg2] <<= State.regs[srcreg2];
5227 }
5228
5229 // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
5230 8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
5231 "cmp_asl"
5232 *am33
5233 {
5234 int srcreg1, dstreg1, dstreg2;
5235 signed int temp;
5236
5237 PC = cia;
5238 srcreg1 = translate_rreg (SD_, RM1);
5239 dstreg1 = translate_rreg (SD_, RN1);
5240 dstreg2 = translate_rreg (SD_, RN2);
5241
5242 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5243 State.regs[dstreg2] <<= IMM4;
5244 }
5245
5246 // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
5247 8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
5248 "sub_add"
5249 *am33
5250 {
5251 int srcreg1, srcreg2, dstreg1, dstreg2;
5252 int result1;
5253
5254 PC = cia;
5255 srcreg1 = translate_rreg (SD_, RM1);
5256 srcreg2 = translate_rreg (SD_, RM2);
5257 dstreg1 = translate_rreg (SD_, RN1);
5258 dstreg2 = translate_rreg (SD_, RN2);
5259
5260 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5261 State.regs[dstreg2] += State.regs[srcreg2];
5262 State.regs[dstreg1] = result1;
5263 }
5264
5265 // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
5266 8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
5267 "sub_add"
5268 *am33
5269 {
5270 int srcreg1, dstreg1, dstreg2;
5271 int result1;
5272
5273 PC = cia;
5274 srcreg1 = translate_rreg (SD_, RM1);
5275 dstreg1 = translate_rreg (SD_, RN1);
5276 dstreg2 = translate_rreg (SD_, RN2);
5277
5278 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5279 State.regs[dstreg2] += EXTEND4 (IMM4);
5280 State.regs[dstreg1] = result1;
5281 }
5282
5283 // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
5284 8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
5285 "sub_sub"
5286 *am33
5287 {
5288 int srcreg1, srcreg2, dstreg1, dstreg2;
5289 int result1;
5290
5291 PC = cia;
5292 srcreg1 = translate_rreg (SD_, RM1);
5293 srcreg2 = translate_rreg (SD_, RM2);
5294 dstreg1 = translate_rreg (SD_, RN1);
5295 dstreg2 = translate_rreg (SD_, RN2);
5296
5297 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5298 State.regs[dstreg2] -= State.regs[srcreg2];
5299 State.regs[dstreg1] = result1;
5300 }
5301
5302 // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
5303 8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
5304 "sub_sub"
5305 *am33
5306 {
5307 int srcreg1, dstreg1, dstreg2;
5308 int result1;
5309
5310 PC = cia;
5311 srcreg1 = translate_rreg (SD_, RM1);
5312 dstreg1 = translate_rreg (SD_, RN1);
5313 dstreg2 = translate_rreg (SD_, RN2);
5314
5315 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5316 State.regs[dstreg2] -= EXTEND4 (IMM4);
5317 State.regs[dstreg1] = result1;
5318 }
5319
5320 // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
5321 8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
5322 "sub_cmp"
5323 *am33
5324 {
5325 int srcreg1, srcreg2, dstreg1, dstreg2;
5326
5327 PC = cia;
5328 srcreg1 = translate_rreg (SD_, RM1);
5329 srcreg2 = translate_rreg (SD_, RM2);
5330 dstreg1 = translate_rreg (SD_, RN1);
5331 dstreg2 = translate_rreg (SD_, RN2);
5332
5333 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5334 State.regs[dstreg1] -= State.regs[srcreg1];
5335 }
5336
5337 // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
5338 8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
5339 "sub_cmp"
5340 *am33
5341 {
5342 int srcreg1, dstreg1, dstreg2;
5343 int result1;
5344
5345 PC = cia;
5346 srcreg1 = translate_rreg (SD_, RM1);
5347 dstreg1 = translate_rreg (SD_, RN1);
5348 dstreg2 = translate_rreg (SD_, RN2);
5349
5350 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5351 State.regs[dstreg1] -= State.regs[srcreg1];
5352 }
5353
5354 // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
5355 8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
5356 "sub_mov"
5357 *am33
5358 {
5359 int srcreg1, srcreg2, dstreg1, dstreg2;
5360 int result1;
5361
5362 PC = cia;
5363 srcreg1 = translate_rreg (SD_, RM1);
5364 srcreg2 = translate_rreg (SD_, RM2);
5365 dstreg1 = translate_rreg (SD_, RN1);
5366 dstreg2 = translate_rreg (SD_, RN2);
5367
5368 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5369 State.regs[dstreg2] = State.regs[srcreg2];
5370 State.regs[dstreg1] = result1;
5371 }
5372
5373 // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
5374 8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
5375 "sub_mov"
5376 *am33
5377 {
5378 int srcreg1, dstreg1, dstreg2;
5379 int result1;
5380
5381 PC = cia;
5382 srcreg1 = translate_rreg (SD_, RM1);
5383 dstreg1 = translate_rreg (SD_, RN1);
5384 dstreg2 = translate_rreg (SD_, RN2);
5385
5386 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5387 State.regs[dstreg2] = EXTEND4 (IMM4);
5388 State.regs[dstreg1] = result1;
5389 }
5390
5391 // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
5392 8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
5393 "sub_asr"
5394 *am33
5395 {
5396 int srcreg1, srcreg2, dstreg1, dstreg2;
5397 int result1;
5398 signed int temp;
5399
5400 PC = cia;
5401 srcreg1 = translate_rreg (SD_, RM1);
5402 srcreg2 = translate_rreg (SD_, RM2);
5403 dstreg1 = translate_rreg (SD_, RN1);
5404 dstreg2 = translate_rreg (SD_, RN2);
5405
5406 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5407 temp = State.regs[dstreg2];
5408 temp >>= State.regs[srcreg2];
5409 State.regs[dstreg2] = temp;
5410 State.regs[dstreg1] = result1;
5411 }
5412
5413 // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
5414 8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
5415 "sub_asr"
5416 *am33
5417 {
5418 int srcreg1, dstreg1, dstreg2;
5419 int result1;
5420 signed int temp;
5421
5422 PC = cia;
5423 srcreg1 = translate_rreg (SD_, RM1);
5424 dstreg1 = translate_rreg (SD_, RN1);
5425 dstreg2 = translate_rreg (SD_, RN2);
5426
5427 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5428 temp = State.regs[dstreg2];
5429 temp >>= IMM4;
5430 State.regs[dstreg2] = temp;
5431 State.regs[dstreg1] = result1;
5432 }
5433
5434 // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
5435 8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
5436 "sub_lsr"
5437 *am33
5438 {
5439 int srcreg1, srcreg2, dstreg1, dstreg2;
5440 int result1;
5441
5442 PC = cia;
5443 srcreg1 = translate_rreg (SD_, RM1);
5444 srcreg2 = translate_rreg (SD_, RM2);
5445 dstreg1 = translate_rreg (SD_, RN1);
5446 dstreg2 = translate_rreg (SD_, RN2);
5447
5448 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5449 State.regs[dstreg2] >>= State.regs[srcreg2];
5450 State.regs[dstreg1] = result1;
5451 }
5452
5453 // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
5454 8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
5455 "sub_lsr"
5456 *am33
5457 {
5458 int srcreg1, dstreg1, dstreg2;
5459 int result1;
5460 signed int temp;
5461
5462 PC = cia;
5463 srcreg1 = translate_rreg (SD_, RM1);
5464 dstreg1 = translate_rreg (SD_, RN1);
5465 dstreg2 = translate_rreg (SD_, RN2);
5466
5467 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5468 State.regs[dstreg2] >>= IMM4;
5469 State.regs[dstreg1] = result1;
5470 }
5471
5472
5473 // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
5474 8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
5475 "sub_asl"
5476 *am33
5477 {
5478 int srcreg1, srcreg2, dstreg1, dstreg2;
5479 int result1;
5480
5481 PC = cia;
5482 srcreg1 = translate_rreg (SD_, RM1);
5483 srcreg2 = translate_rreg (SD_, RM2);
5484 dstreg1 = translate_rreg (SD_, RN1);
5485 dstreg2 = translate_rreg (SD_, RN2);
5486
5487 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5488 State.regs[dstreg2] <<= State.regs[srcreg2];
5489 State.regs[dstreg1] = result1;
5490 }
5491
5492 // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
5493 8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
5494 "sub_asl"
5495 *am33
5496 {
5497 int srcreg1, dstreg1, dstreg2;
5498 int result1;
5499 signed int temp;
5500
5501 PC = cia;
5502 srcreg1 = translate_rreg (SD_, RM1);
5503 dstreg1 = translate_rreg (SD_, RN1);
5504 dstreg2 = translate_rreg (SD_, RN2);
5505
5506 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5507 State.regs[dstreg2] <<= IMM4;
5508 State.regs[dstreg1] = result1;
5509 }
5510
5511 // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
5512 8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
5513 "mov_add"
5514 *am33
5515 {
5516 int srcreg1, srcreg2, dstreg1, dstreg2;
5517 int result1;
5518
5519 PC = cia;
5520 srcreg1 = translate_rreg (SD_, RM1);
5521 srcreg2 = translate_rreg (SD_, RM2);
5522 dstreg1 = translate_rreg (SD_, RN1);
5523 dstreg2 = translate_rreg (SD_, RN2);
5524
5525 result1 = State.regs[srcreg1];
5526 State.regs[dstreg2] += State.regs[srcreg2];
5527 State.regs[dstreg1] = result1;
5528 }
5529
5530 // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
5531 8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
5532 "mov_add"
5533 *am33
5534 {
5535 int srcreg1, dstreg1, dstreg2;
5536 int result1;
5537
5538 PC = cia;
5539 srcreg1 = translate_rreg (SD_, RM1);
5540 dstreg1 = translate_rreg (SD_, RN1);
5541 dstreg2 = translate_rreg (SD_, RN2);
5542
5543 result1 = State.regs[srcreg1];
5544 State.regs[dstreg2] += EXTEND4 (IMM4);
5545 State.regs[dstreg1] = result1;
5546 }
5547
5548 // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
5549 8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
5550 "mov_sub"
5551 *am33
5552 {
5553 int srcreg1, srcreg2, dstreg1, dstreg2;
5554 int result1;
5555
5556 PC = cia;
5557 srcreg1 = translate_rreg (SD_, RM1);
5558 srcreg2 = translate_rreg (SD_, RM2);
5559 dstreg1 = translate_rreg (SD_, RN1);
5560 dstreg2 = translate_rreg (SD_, RN2);
5561
5562 result1 = State.regs[srcreg1];
5563 State.regs[dstreg2] -= State.regs[srcreg2];
5564 State.regs[dstreg1] = result1;
5565 }
5566
5567 // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
5568 8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
5569 "mov_sub"
5570 *am33
5571 {
5572 int srcreg1, dstreg1, dstreg2;
5573 int result1;
5574
5575 PC = cia;
5576 srcreg1 = translate_rreg (SD_, RM1);
5577 dstreg1 = translate_rreg (SD_, RN1);
5578 dstreg2 = translate_rreg (SD_, RN2);
5579
5580 result1 = State.regs[srcreg1];
5581 State.regs[dstreg2] -= EXTEND4 (IMM4);
5582 State.regs[dstreg1] = result1;
5583 }
5584
5585 // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
5586 8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
5587 "mov_cmp"
5588 *am33
5589 {
5590 int srcreg1, srcreg2, dstreg1, dstreg2;
5591
5592 PC = cia;
5593 srcreg1 = translate_rreg (SD_, RM1);
5594 srcreg2 = translate_rreg (SD_, RM2);
5595 dstreg1 = translate_rreg (SD_, RN1);
5596 dstreg2 = translate_rreg (SD_, RN2);
5597
5598 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5599 State.regs[dstreg1] = State.regs[srcreg1];
5600 }
5601
5602 // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
5603 8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
5604 "mov_cmp"
5605 *am33
5606 {
5607 int srcreg1, dstreg1, dstreg2;
5608
5609 PC = cia;
5610 srcreg1 = translate_rreg (SD_, RM1);
5611 dstreg1 = translate_rreg (SD_, RN1);
5612 dstreg2 = translate_rreg (SD_, RN2);
5613
5614 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5615 State.regs[dstreg1] = State.regs[srcreg1];
5616 }
5617
5618 // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
5619 8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
5620 "mov_mov"
5621 *am33
5622 {
5623 int srcreg1, srcreg2, dstreg1, dstreg2;
5624 int result1;
5625
5626 PC = cia;
5627 srcreg1 = translate_rreg (SD_, RM1);
5628 srcreg2 = translate_rreg (SD_, RM2);
5629 dstreg1 = translate_rreg (SD_, RN1);
5630 dstreg2 = translate_rreg (SD_, RN2);
5631
5632 result1 = State.regs[srcreg1];
5633 State.regs[dstreg2] = State.regs[srcreg2];
5634 State.regs[dstreg1] = result1;
5635 }
5636
5637 // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
5638 8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
5639 "mov_mov"
5640 *am33
5641 {
5642 int srcreg1, dstreg1, dstreg2;
5643 int result1;
5644
5645 PC = cia;
5646 srcreg1 = translate_rreg (SD_, RM1);
5647 dstreg1 = translate_rreg (SD_, RN1);
5648 dstreg2 = translate_rreg (SD_, RN2);
5649
5650 result1 = State.regs[srcreg1];
5651 State.regs[dstreg2] = EXTEND4 (IMM4);
5652 State.regs[dstreg1] = result1;
5653 }
5654
5655 // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
5656 8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
5657 "mov_asr"
5658 *am33
5659 {
5660 int srcreg1, srcreg2, dstreg1, dstreg2;
5661 int result1;
5662 signed int temp;
5663
5664 PC = cia;
5665 srcreg1 = translate_rreg (SD_, RM1);
5666 srcreg2 = translate_rreg (SD_, RM2);
5667 dstreg1 = translate_rreg (SD_, RN1);
5668 dstreg2 = translate_rreg (SD_, RN2);
5669
5670 result1 = State.regs[srcreg1];
5671 temp = State.regs[dstreg2];
5672 temp >>= State.regs[srcreg2];
5673 State.regs[dstreg2] = temp;
5674 State.regs[dstreg1] = result1;
5675 }
5676
5677 // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
5678 8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
5679 "mov_asr"
5680 *am33
5681 {
5682 int srcreg1, dstreg1, dstreg2;
5683 int result1;
5684 signed int temp;
5685
5686 PC = cia;
5687 srcreg1 = translate_rreg (SD_, RM1);
5688 dstreg1 = translate_rreg (SD_, RN1);
5689 dstreg2 = translate_rreg (SD_, RN2);
5690
5691 result1 = State.regs[srcreg1];
5692 temp = State.regs[dstreg2];
5693 temp >>= IMM4;
5694 State.regs[dstreg2] = temp;
5695 State.regs[dstreg1] = result1;
5696 }
5697
5698 // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
5699 8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
5700 "mov_lsr"
5701 *am33
5702 {
5703 int srcreg1, srcreg2, dstreg1, dstreg2;
5704 int result1;
5705
5706 PC = cia;
5707 srcreg1 = translate_rreg (SD_, RM1);
5708 srcreg2 = translate_rreg (SD_, RM2);
5709 dstreg1 = translate_rreg (SD_, RN1);
5710 dstreg2 = translate_rreg (SD_, RN2);
5711
5712 result1 = State.regs[srcreg1];
5713 State.regs[dstreg2] >>= State.regs[srcreg2];
5714 State.regs[dstreg1] = result1;
5715 }
5716
5717 // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
5718 8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
5719 "mov_lsr"
5720 *am33
5721 {
5722 int srcreg1, dstreg1, dstreg2;
5723 int result1;
5724 signed int temp;
5725
5726 PC = cia;
5727 srcreg1 = translate_rreg (SD_, RM1);
5728 dstreg1 = translate_rreg (SD_, RN1);
5729 dstreg2 = translate_rreg (SD_, RN2);
5730
5731 result1 = State.regs[srcreg1];
5732 State.regs[dstreg2] >>= IMM4;
5733 State.regs[dstreg1] = result1;
5734 }
5735
5736
5737 // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
5738 8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
5739 "mov_asl"
5740 *am33
5741 {
5742 int srcreg1, srcreg2, dstreg1, dstreg2;
5743 int result1;
5744
5745 PC = cia;
5746 srcreg1 = translate_rreg (SD_, RM1);
5747 srcreg2 = translate_rreg (SD_, RM2);
5748 dstreg1 = translate_rreg (SD_, RN1);
5749 dstreg2 = translate_rreg (SD_, RN2);
5750
5751 result1 = State.regs[srcreg1];
5752 State.regs[dstreg2] <<= State.regs[srcreg2];
5753 State.regs[dstreg1] = result1;
5754 }
5755
5756 // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
5757 8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
5758 "mov_asl"
5759 *am33
5760 {
5761 int srcreg1, dstreg1, dstreg2;
5762 int result1;
5763 signed int temp;
5764
5765 PC = cia;
5766 srcreg1 = translate_rreg (SD_, RM1);
5767 dstreg1 = translate_rreg (SD_, RN1);
5768 dstreg2 = translate_rreg (SD_, RN2);
5769
5770 result1 = State.regs[srcreg1];
5771 State.regs[dstreg2] <<= IMM4;
5772 State.regs[dstreg1] = result1;
5773 }
5774
5775 // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
5776 8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
5777 "add_add"
5778 *am33
5779 {
5780 int srcreg2, dstreg1, dstreg2;
5781 int result1;
5782
5783 PC = cia;
5784 srcreg2 = translate_rreg (SD_, RM2);
5785 dstreg1 = translate_rreg (SD_, RN1);
5786 dstreg2 = translate_rreg (SD_, RN2);
5787
5788 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5789 State.regs[dstreg2] += State.regs[srcreg2];
5790 State.regs[dstreg1] = result1;
5791 }
5792
5793 // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
5794 8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
5795 "add_add"
5796 *am33
5797 {
5798 int dstreg1, dstreg2;
5799 int result1;
5800
5801 PC = cia;
5802 dstreg1 = translate_rreg (SD_, RN1);
5803 dstreg2 = translate_rreg (SD_, RN2);
5804
5805 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5806 State.regs[dstreg2] += EXTEND4 (IMM4);
5807 State.regs[dstreg1] = result1;
5808 }
5809
5810 // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
5811 8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
5812 "add_sub"
5813 *am33
5814 {
5815 int srcreg2, dstreg1, dstreg2;
5816 int result1;
5817
5818 PC = cia;
5819 srcreg2 = translate_rreg (SD_, RM2);
5820 dstreg1 = translate_rreg (SD_, RN1);
5821 dstreg2 = translate_rreg (SD_, RN2);
5822
5823 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5824 State.regs[dstreg2] -= State.regs[srcreg2];
5825 State.regs[dstreg1] = result1;
5826 }
5827
5828 // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
5829 8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
5830 "add_sub"
5831 *am33
5832 {
5833 int dstreg1, dstreg2;
5834 int result1;
5835
5836 PC = cia;
5837 dstreg1 = translate_rreg (SD_, RN1);
5838 dstreg2 = translate_rreg (SD_, RN2);
5839
5840 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5841 State.regs[dstreg2] -= EXTEND4 (IMM4);
5842 State.regs[dstreg1] = result1;
5843 }
5844
5845 // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
5846 8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
5847 "add_cmp"
5848 *am33
5849 {
5850 int srcreg2, dstreg1, dstreg2;
5851
5852 PC = cia;
5853 srcreg2 = translate_rreg (SD_, RM2);
5854 dstreg1 = translate_rreg (SD_, RN1);
5855 dstreg2 = translate_rreg (SD_, RN2);
5856
5857 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5858 State.regs[dstreg1] += EXTEND4 (IMM4A);
5859 }
5860
5861 // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
5862 8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
5863 "add_cmp"
5864 *am33
5865 {
5866 int dstreg1, dstreg2;
5867
5868 PC = cia;
5869 dstreg1 = translate_rreg (SD_, RN1);
5870 dstreg2 = translate_rreg (SD_, RN2);
5871
5872 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5873 State.regs[dstreg1] += EXTEND4 (IMM4A);
5874 }
5875
5876 // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
5877 8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
5878 "add_mov"
5879 *am33
5880 {
5881 int srcreg2, dstreg1, dstreg2;
5882 int result1;
5883
5884 PC = cia;
5885 srcreg2 = translate_rreg (SD_, RM2);
5886 dstreg1 = translate_rreg (SD_, RN1);
5887 dstreg2 = translate_rreg (SD_, RN2);
5888
5889 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5890 State.regs[dstreg2] = State.regs[srcreg2];
5891 State.regs[dstreg1] = result1;
5892 }
5893
5894 // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
5895 8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
5896 "add_mov"
5897 *am33
5898 {
5899 int dstreg1, dstreg2;
5900 int result1;
5901
5902 PC = cia;
5903 dstreg1 = translate_rreg (SD_, RN1);
5904 dstreg2 = translate_rreg (SD_, RN2);
5905
5906 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5907 State.regs[dstreg2] = EXTEND4 (IMM4);
5908 State.regs[dstreg1] = result1;
5909 }
5910
5911 // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
5912 8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
5913 "add_asr"
5914 *am33
5915 {
5916 int srcreg2, dstreg1, dstreg2;
5917 int result1;
5918 signed int temp;
5919
5920 PC = cia;
5921 srcreg2 = translate_rreg (SD_, RM2);
5922 dstreg1 = translate_rreg (SD_, RN1);
5923 dstreg2 = translate_rreg (SD_, RN2);
5924
5925 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5926 temp = State.regs[dstreg2];
5927 temp >>= State.regs[srcreg2];
5928 State.regs[dstreg2] = temp;
5929 State.regs[dstreg1] = result1;
5930 }
5931
5932 // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
5933 8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
5934 "add_asr"
5935 *am33
5936 {
5937 int dstreg1, dstreg2;
5938 int result1;
5939 signed int temp;
5940
5941 PC = cia;
5942 dstreg1 = translate_rreg (SD_, RN1);
5943 dstreg2 = translate_rreg (SD_, RN2);
5944
5945 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5946 temp = State.regs[dstreg2];
5947 temp >>= IMM4;
5948 State.regs[dstreg2] = temp;
5949 State.regs[dstreg1] = result1;
5950 }
5951
5952 // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
5953 8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
5954 "add_lsr"
5955 *am33
5956 {
5957 int srcreg2, dstreg1, dstreg2;
5958 int result1;
5959
5960 PC = cia;
5961 srcreg2 = translate_rreg (SD_, RM2);
5962 dstreg1 = translate_rreg (SD_, RN1);
5963 dstreg2 = translate_rreg (SD_, RN2);
5964
5965 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5966 State.regs[dstreg2] >>= State.regs[srcreg2];
5967 State.regs[dstreg1] = result1;
5968 }
5969
5970 // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
5971 8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
5972 "add_lsr"
5973 *am33
5974 {
5975 int dstreg1, dstreg2;
5976 int result1;
5977 signed int temp;
5978
5979 PC = cia;
5980 dstreg1 = translate_rreg (SD_, RN1);
5981 dstreg2 = translate_rreg (SD_, RN2);
5982
5983 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5984 State.regs[dstreg2] >>= IMM4;
5985 State.regs[dstreg1] = result1;
5986 }
5987
5988
5989 // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
5990 8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
5991 "add_asl"
5992 *am33
5993 {
5994 int srcreg2, dstreg1, dstreg2;
5995 int result1;
5996
5997 PC = cia;
5998 srcreg2 = translate_rreg (SD_, RM2);
5999 dstreg1 = translate_rreg (SD_, RN1);
6000 dstreg2 = translate_rreg (SD_, RN2);
6001
6002 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
6003 State.regs[dstreg2] <<= State.regs[srcreg2];
6004 State.regs[dstreg1] = result1;
6005 }
6006
6007 // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
6008 8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
6009 "add_asl"
6010 *am33
6011 {
6012 int dstreg1, dstreg2;
6013 int result1;
6014 signed int temp;
6015
6016 PC = cia;
6017 dstreg1 = translate_rreg (SD_, RN1);
6018 dstreg2 = translate_rreg (SD_, RN2);
6019
6020 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
6021 State.regs[dstreg2] <<= IMM4;
6022 State.regs[dstreg1] = result1;
6023 }
6024
6025 // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
6026 8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
6027 "cmp_add"
6028 *am33
6029 {
6030 int srcreg2, dstreg1, dstreg2;
6031
6032 PC = cia;
6033 srcreg2 = translate_rreg (SD_, RM2);
6034 dstreg1 = translate_rreg (SD_, RN1);
6035 dstreg2 = translate_rreg (SD_, RN2);
6036
6037 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6038 State.regs[dstreg2] += State.regs[srcreg2];
6039 }
6040
6041 // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
6042 8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
6043 "cmp_add"
6044 *am33
6045 {
6046 int dstreg1, dstreg2;
6047
6048 PC = cia;
6049 dstreg1 = translate_rreg (SD_, RN1);
6050 dstreg2 = translate_rreg (SD_, RN2);
6051
6052 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6053 State.regs[dstreg2] += EXTEND4 (IMM4);
6054 }
6055
6056 // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
6057 8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
6058 "cmp_sub"
6059 *am33
6060 {
6061 int srcreg2, dstreg1, dstreg2;
6062
6063 PC = cia;
6064 srcreg2 = translate_rreg (SD_, RM2);
6065 dstreg1 = translate_rreg (SD_, RN1);
6066 dstreg2 = translate_rreg (SD_, RN2);
6067
6068 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6069 State.regs[dstreg2] -= State.regs[srcreg2];
6070 }
6071
6072 // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
6073 8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
6074 "cmp_sub"
6075 *am33
6076 {
6077 int dstreg1, dstreg2;
6078
6079 PC = cia;
6080 dstreg1 = translate_rreg (SD_, RN1);
6081 dstreg2 = translate_rreg (SD_, RN2);
6082
6083 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6084 State.regs[dstreg2] -= EXTEND4 (IMM4);
6085 }
6086
6087 // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
6088 8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
6089 "cmp_mov"
6090 *am33
6091 {
6092 int srcreg2, dstreg1, dstreg2;
6093
6094 PC = cia;
6095 srcreg2 = translate_rreg (SD_, RM2);
6096 dstreg1 = translate_rreg (SD_, RN1);
6097 dstreg2 = translate_rreg (SD_, RN2);
6098
6099 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6100 State.regs[dstreg2] = State.regs[srcreg2];
6101 }
6102
6103 // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
6104 8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
6105 "cmp_mov"
6106 *am33
6107 {
6108 int dstreg1, dstreg2;
6109
6110 PC = cia;
6111 dstreg1 = translate_rreg (SD_, RN1);
6112 dstreg2 = translate_rreg (SD_, RN2);
6113
6114 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6115 State.regs[dstreg2] = EXTEND4 (IMM4);
6116 }
6117
6118 // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
6119 8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
6120 "cmp_asr"
6121 *am33
6122 {
6123 int srcreg2, dstreg1, dstreg2;
6124 signed int temp;
6125
6126 PC = cia;
6127 srcreg2 = translate_rreg (SD_, RM2);
6128 dstreg1 = translate_rreg (SD_, RN1);
6129 dstreg2 = translate_rreg (SD_, RN2);
6130
6131 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6132 temp = State.regs[dstreg2];
6133 temp >>= State.regs[srcreg2];
6134 State.regs[dstreg2] = temp;
6135 }
6136
6137 // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
6138 8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
6139 "cmp_asr"
6140 *am33
6141 {
6142 int dstreg1, dstreg2;
6143 signed int temp;
6144
6145 PC = cia;
6146 dstreg1 = translate_rreg (SD_, RN1);
6147 dstreg2 = translate_rreg (SD_, RN2);
6148
6149 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6150 temp = State.regs[dstreg2];
6151 temp >>= IMM4;
6152 State.regs[dstreg2] = temp;
6153 }
6154
6155 // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
6156 8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
6157 "cmp_lsr"
6158 *am33
6159 {
6160 int srcreg2, dstreg1, dstreg2;
6161
6162 PC = cia;
6163 srcreg2 = translate_rreg (SD_, RM2);
6164 dstreg1 = translate_rreg (SD_, RN1);
6165 dstreg2 = translate_rreg (SD_, RN2);
6166
6167 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6168 State.regs[dstreg2] >>= State.regs[srcreg2];
6169 }
6170
6171 // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
6172 8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
6173 "cmp_lsr"
6174 *am33
6175 {
6176 int dstreg1, dstreg2;
6177 signed int temp;
6178
6179 PC = cia;
6180 dstreg1 = translate_rreg (SD_, RN1);
6181 dstreg2 = translate_rreg (SD_, RN2);
6182
6183 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6184 State.regs[dstreg2] >>= IMM4;
6185 }
6186
6187
6188 // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
6189 8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
6190 "cmp_asl"
6191 *am33
6192 {
6193 int srcreg2, dstreg1, dstreg2;
6194
6195 PC = cia;
6196 srcreg2 = translate_rreg (SD_, RM2);
6197 dstreg1 = translate_rreg (SD_, RN1);
6198 dstreg2 = translate_rreg (SD_, RN2);
6199
6200 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6201 State.regs[dstreg2] <<= State.regs[srcreg2];
6202 }
6203
6204 // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
6205 8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
6206 "cmp_asl"
6207 *am33
6208 {
6209 int dstreg1, dstreg2;
6210 signed int temp;
6211
6212 PC = cia;
6213 dstreg1 = translate_rreg (SD_, RN1);
6214 dstreg2 = translate_rreg (SD_, RN2);
6215
6216 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6217 State.regs[dstreg2] <<= IMM4;
6218 }
6219
6220 // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
6221 8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
6222 "sub_add"
6223 *am33
6224 {
6225 int srcreg2, dstreg1, dstreg2;
6226 int result1;
6227
6228 PC = cia;
6229 srcreg2 = translate_rreg (SD_, RM2);
6230 dstreg1 = translate_rreg (SD_, RN1);
6231 dstreg2 = translate_rreg (SD_, RN2);
6232
6233 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6234 State.regs[dstreg2] += State.regs[srcreg2];
6235 State.regs[dstreg1] = result1;
6236 }
6237
6238 // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
6239 8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
6240 "sub_add"
6241 *am33
6242 {
6243 int dstreg1, dstreg2;
6244 int result1;
6245
6246 PC = cia;
6247 dstreg1 = translate_rreg (SD_, RN1);
6248 dstreg2 = translate_rreg (SD_, RN2);
6249
6250 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6251 State.regs[dstreg2] += EXTEND4 (IMM4);
6252 State.regs[dstreg1] = result1;
6253 }
6254
6255 // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
6256 8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
6257 "sub_sub"
6258 *am33
6259 {
6260 int srcreg2, dstreg1, dstreg2;
6261 int result1;
6262
6263 PC = cia;
6264 srcreg2 = translate_rreg (SD_, RM2);
6265 dstreg1 = translate_rreg (SD_, RN1);
6266 dstreg2 = translate_rreg (SD_, RN2);
6267
6268 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6269 State.regs[dstreg2] -= State.regs[srcreg2];
6270 State.regs[dstreg1] = result1;
6271 }
6272
6273 // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
6274 8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
6275 "sub_sub"
6276 *am33
6277 {
6278 int dstreg1, dstreg2;
6279 int result1;
6280
6281 PC = cia;
6282 dstreg1 = translate_rreg (SD_, RN1);
6283 dstreg2 = translate_rreg (SD_, RN2);
6284
6285 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6286 State.regs[dstreg2] -= EXTEND4 (IMM4);
6287 State.regs[dstreg1] = result1;
6288 }
6289
6290 // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
6291 8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
6292 "sub_cmp"
6293 *am33
6294 {
6295 int srcreg2, dstreg1, dstreg2;
6296 int result1;
6297
6298 PC = cia;
6299 srcreg2 = translate_rreg (SD_, RM2);
6300 dstreg1 = translate_rreg (SD_, RN1);
6301 dstreg2 = translate_rreg (SD_, RN2);
6302
6303 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6304 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6305 }
6306
6307 // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
6308 8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
6309 "sub_cmp"
6310 *am33
6311 {
6312 int dstreg1, dstreg2;
6313 int result1;
6314
6315 PC = cia;
6316 dstreg1 = translate_rreg (SD_, RN1);
6317 dstreg2 = translate_rreg (SD_, RN2);
6318
6319 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6320 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6321 }
6322
6323 // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
6324 8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
6325 "sub_mov"
6326 *am33
6327 {
6328 int srcreg2, dstreg1, dstreg2;
6329 int result1;
6330
6331 PC = cia;
6332 srcreg2 = translate_rreg (SD_, RM2);
6333 dstreg1 = translate_rreg (SD_, RN1);
6334 dstreg2 = translate_rreg (SD_, RN2);
6335
6336 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6337 State.regs[dstreg2] = State.regs[srcreg2];
6338 State.regs[dstreg1] = result1;
6339 }
6340
6341 // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
6342 8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
6343 "sub_mov"
6344 *am33
6345 {
6346 int dstreg1, dstreg2;
6347 int result1;
6348
6349 PC = cia;
6350 dstreg1 = translate_rreg (SD_, RN1);
6351 dstreg2 = translate_rreg (SD_, RN2);
6352
6353 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6354 State.regs[dstreg2] = EXTEND4 (IMM4);
6355 State.regs[dstreg1] = result1;
6356 }
6357
6358 // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
6359 8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
6360 "sub_asr"
6361 *am33
6362 {
6363 int srcreg2, dstreg1, dstreg2;
6364 int result1;
6365 signed int temp;
6366
6367 PC = cia;
6368 srcreg2 = translate_rreg (SD_, RM2);
6369 dstreg1 = translate_rreg (SD_, RN1);
6370 dstreg2 = translate_rreg (SD_, RN2);
6371
6372 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6373 temp = State.regs[dstreg2];
6374 temp >>= State.regs[srcreg2];
6375 State.regs[dstreg2] = temp;
6376 State.regs[dstreg1] = result1;
6377 }
6378
6379 // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
6380 8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
6381 "sub_asr"
6382 *am33
6383 {
6384 int dstreg1, dstreg2;
6385 int result1;
6386 signed int temp;
6387
6388 PC = cia;
6389 dstreg1 = translate_rreg (SD_, RN1);
6390 dstreg2 = translate_rreg (SD_, RN2);
6391
6392 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6393 temp = State.regs[dstreg2];
6394 temp >>= IMM4;
6395 State.regs[dstreg2] = temp;
6396 State.regs[dstreg1] = result1;
6397 }
6398
6399 // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
6400 8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
6401 "sub_lsr"
6402 *am33
6403 {
6404 int srcreg2, dstreg1, dstreg2;
6405 int result1;
6406
6407 PC = cia;
6408 srcreg2 = translate_rreg (SD_, RM2);
6409 dstreg1 = translate_rreg (SD_, RN1);
6410 dstreg2 = translate_rreg (SD_, RN2);
6411
6412 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6413 State.regs[dstreg2] >>= State.regs[srcreg2];
6414 State.regs[dstreg1] = result1;
6415 }
6416
6417 // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
6418 8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
6419 "sub_lsr"
6420 *am33
6421 {
6422 int dstreg1, dstreg2;
6423 int result1;
6424 signed int temp;
6425
6426 PC = cia;
6427 dstreg1 = translate_rreg (SD_, RN1);
6428 dstreg2 = translate_rreg (SD_, RN2);
6429
6430 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6431 State.regs[dstreg2] >>= IMM4;
6432 State.regs[dstreg1] = result1;
6433 }
6434
6435
6436 // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
6437 8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
6438 "sub_asl"
6439 *am33
6440 {
6441 int srcreg2, dstreg1, dstreg2;
6442 int result1;
6443
6444 PC = cia;
6445 srcreg2 = translate_rreg (SD_, RM2);
6446 dstreg1 = translate_rreg (SD_, RN1);
6447 dstreg2 = translate_rreg (SD_, RN2);
6448
6449 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6450 State.regs[dstreg2] <<= State.regs[srcreg2];
6451 State.regs[dstreg1] = result1;
6452 }
6453
6454 // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
6455 8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
6456 "sub_asl"
6457 *am33
6458 {
6459 int dstreg1, dstreg2;
6460 int result1;
6461 signed int temp;
6462
6463 PC = cia;
6464 dstreg1 = translate_rreg (SD_, RN1);
6465 dstreg2 = translate_rreg (SD_, RN2);
6466
6467 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6468 State.regs[dstreg2] <<= IMM4;
6469 State.regs[dstreg1] = result1;
6470 }
6471
6472 // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
6473 8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
6474 "mov_add"
6475 *am33
6476 {
6477 int srcreg2, dstreg1, dstreg2;
6478 int result1;
6479
6480 PC = cia;
6481 srcreg2 = translate_rreg (SD_, RM2);
6482 dstreg1 = translate_rreg (SD_, RN1);
6483 dstreg2 = translate_rreg (SD_, RN2);
6484
6485 result1 = EXTEND4 (IMM4A);
6486 State.regs[dstreg2] += State.regs[srcreg2];
6487 State.regs[dstreg1] = result1;
6488 }
6489
6490 // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
6491 8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
6492 "mov_add"
6493 *am33
6494 {
6495 int dstreg1, dstreg2;
6496 int result1;
6497
6498 PC = cia;
6499 dstreg1 = translate_rreg (SD_, RN1);
6500 dstreg2 = translate_rreg (SD_, RN2);
6501
6502 result1 = EXTEND4 (IMM4A);
6503 State.regs[dstreg2] += EXTEND4 (IMM4);
6504 State.regs[dstreg1] = result1;
6505 }
6506
6507 // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
6508 8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
6509 "mov_sub"
6510 *am33
6511 {
6512 int srcreg2, dstreg1, dstreg2;
6513 int result1;
6514
6515 PC = cia;
6516 srcreg2 = translate_rreg (SD_, RM2);
6517 dstreg1 = translate_rreg (SD_, RN1);
6518 dstreg2 = translate_rreg (SD_, RN2);
6519
6520 result1 = EXTEND4 (IMM4A);
6521 State.regs[dstreg2] -= State.regs[srcreg2];
6522 State.regs[dstreg1] = result1;
6523 }
6524
6525 // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
6526 8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
6527 "mov_sub"
6528 *am33
6529 {
6530 int dstreg1, dstreg2;
6531 int result1;
6532
6533 PC = cia;
6534 dstreg1 = translate_rreg (SD_, RN1);
6535 dstreg2 = translate_rreg (SD_, RN2);
6536
6537 result1 = EXTEND4 (IMM4A);
6538 State.regs[dstreg2] -= EXTEND4 (IMM4);
6539 State.regs[dstreg1] = result1;
6540 }
6541
6542 // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
6543 8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
6544 "mov_cmp"
6545 *am33
6546 {
6547 int srcreg2, dstreg1, dstreg2;
6548
6549 PC = cia;
6550 srcreg2 = translate_rreg (SD_, RM2);
6551 dstreg1 = translate_rreg (SD_, RN1);
6552 dstreg2 = translate_rreg (SD_, RN2);
6553
6554 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6555 State.regs[dstreg1] = EXTEND4 (IMM4A);
6556 }
6557
6558 // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
6559 8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
6560 "mov_cmp"
6561 *am33
6562 {
6563 int dstreg1, dstreg2;
6564
6565 PC = cia;
6566 dstreg1 = translate_rreg (SD_, RN1);
6567 dstreg2 = translate_rreg (SD_, RN2);
6568
6569 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6570 State.regs[dstreg1] = EXTEND4 (IMM4A);
6571 }
6572
6573 // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
6574 8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
6575 "mov_mov"
6576 *am33
6577 {
6578 int srcreg2, dstreg1, dstreg2;
6579 int result1;
6580
6581 PC = cia;
6582 srcreg2 = translate_rreg (SD_, RM2);
6583 dstreg1 = translate_rreg (SD_, RN1);
6584 dstreg2 = translate_rreg (SD_, RN2);
6585
6586 result1 = EXTEND4 (IMM4A);
6587 State.regs[dstreg2] = State.regs[srcreg2];
6588 State.regs[dstreg1] = result1;
6589 }
6590
6591 // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
6592 8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
6593 "mov_mov"
6594 *am33
6595 {
6596 int dstreg1, dstreg2;
6597 int result1;
6598
6599 PC = cia;
6600 dstreg1 = translate_rreg (SD_, RN1);
6601 dstreg2 = translate_rreg (SD_, RN2);
6602
6603 result1 = EXTEND4 (IMM4A);
6604 State.regs[dstreg2] = EXTEND4 (IMM4);
6605 State.regs[dstreg1] = result1;
6606 }
6607
6608 // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
6609 8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
6610 "mov_asr"
6611 *am33
6612 {
6613 int srcreg2, dstreg1, dstreg2;
6614 int result1;
6615 signed int temp;
6616
6617 PC = cia;
6618 srcreg2 = translate_rreg (SD_, RM2);
6619 dstreg1 = translate_rreg (SD_, RN1);
6620 dstreg2 = translate_rreg (SD_, RN2);
6621
6622 result1 = EXTEND4 (IMM4A);
6623 temp = State.regs[dstreg2];
6624 temp >>= State.regs[srcreg2];
6625 State.regs[dstreg2] = temp;
6626 State.regs[dstreg1] = result1;
6627 }
6628
6629 // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
6630 8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
6631 "mov_asr"
6632 *am33
6633 {
6634 int dstreg1, dstreg2;
6635 int result1;
6636 signed int temp;
6637
6638 PC = cia;
6639 dstreg1 = translate_rreg (SD_, RN1);
6640 dstreg2 = translate_rreg (SD_, RN2);
6641
6642 result1 = EXTEND4 (IMM4A);
6643 temp = State.regs[dstreg2];
6644 temp >>= IMM4;
6645 State.regs[dstreg2] = temp;
6646 State.regs[dstreg1] = result1;
6647 }
6648
6649 // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
6650 8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
6651 "mov_lsr"
6652 *am33
6653 {
6654 int srcreg2, dstreg1, dstreg2;
6655 int result1;
6656
6657 PC = cia;
6658 srcreg2 = translate_rreg (SD_, RM2);
6659 dstreg1 = translate_rreg (SD_, RN1);
6660 dstreg2 = translate_rreg (SD_, RN2);
6661
6662 result1 = EXTEND4 (IMM4A);
6663 State.regs[dstreg2] >>= State.regs[srcreg2];
6664 State.regs[dstreg1] = result1;
6665 }
6666
6667 // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
6668 8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
6669 "mov_lsr"
6670 *am33
6671 {
6672 int dstreg1, dstreg2;
6673 int result1;
6674 signed int temp;
6675
6676 PC = cia;
6677 dstreg1 = translate_rreg (SD_, RN1);
6678 dstreg2 = translate_rreg (SD_, RN2);
6679
6680 result1 = EXTEND4 (IMM4A);
6681 State.regs[dstreg2] >>= IMM4;
6682 State.regs[dstreg1] = result1;
6683 }
6684
6685
6686 // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
6687 8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
6688 "mov_asl"
6689 *am33
6690 {
6691 int srcreg2, dstreg1, dstreg2;
6692 int result1;
6693
6694 PC = cia;
6695 srcreg2 = translate_rreg (SD_, RM2);
6696 dstreg1 = translate_rreg (SD_, RN1);
6697 dstreg2 = translate_rreg (SD_, RN2);
6698
6699 result1 = EXTEND4 (IMM4A);
6700 State.regs[dstreg2] <<= State.regs[srcreg2];
6701 State.regs[dstreg1] = result1;
6702 }
6703
6704 // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
6705 8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
6706 "mov_asl"
6707 *am33
6708 {
6709 int dstreg1, dstreg2;
6710 int result1;
6711 signed int temp;
6712
6713 PC = cia;
6714 dstreg1 = translate_rreg (SD_, RN1);
6715 dstreg2 = translate_rreg (SD_, RN2);
6716
6717 result1 = EXTEND4 (IMM4A);
6718 State.regs[dstreg2] <<= IMM4;
6719 State.regs[dstreg1] = result1;
6720 }
6721
6722 // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
6723 8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
6724 "and_add"
6725 *am33
6726 {
6727 int srcreg1, srcreg2, dstreg1, dstreg2;
6728 int result1;
6729
6730 PC = cia;
6731 srcreg1 = translate_rreg (SD_, RM1);
6732 srcreg2 = translate_rreg (SD_, RM2);
6733 dstreg1 = translate_rreg (SD_, RN1);
6734 dstreg2 = translate_rreg (SD_, RN2);
6735
6736 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6737 State.regs[dstreg2] += State.regs[srcreg2];
6738 State.regs[dstreg1] = result1;
6739 }
6740
6741 // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
6742 8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
6743 "and_add"
6744 *am33
6745 {
6746 int srcreg1, dstreg1, dstreg2;
6747 int result1;
6748
6749 PC = cia;
6750 srcreg1 = translate_rreg (SD_, RM1);
6751 dstreg1 = translate_rreg (SD_, RN1);
6752 dstreg2 = translate_rreg (SD_, RN2);
6753
6754 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6755 State.regs[dstreg2] += EXTEND4 (IMM4);
6756 State.regs[dstreg1] = result1;
6757 }
6758
6759 // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
6760 8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
6761 "and_sub"
6762 *am33
6763 {
6764 int srcreg1, srcreg2, dstreg1, dstreg2;
6765 int result1;
6766
6767 PC = cia;
6768 srcreg1 = translate_rreg (SD_, RM1);
6769 srcreg2 = translate_rreg (SD_, RM2);
6770 dstreg1 = translate_rreg (SD_, RN1);
6771 dstreg2 = translate_rreg (SD_, RN2);
6772
6773 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6774 State.regs[dstreg2] -= State.regs[srcreg2];
6775 State.regs[dstreg1] = result1;
6776 }
6777
6778 // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
6779 8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
6780 "and_sub"
6781 *am33
6782 {
6783 int srcreg1, dstreg1, dstreg2;
6784 int result1;
6785
6786 PC = cia;
6787 srcreg1 = translate_rreg (SD_, RM1);
6788 dstreg1 = translate_rreg (SD_, RN1);
6789 dstreg2 = translate_rreg (SD_, RN2);
6790
6791 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6792 State.regs[dstreg2] -= EXTEND4 (IMM4);
6793 State.regs[dstreg1] = result1;
6794 }
6795
6796 // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
6797 8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
6798 "and_cmp"
6799 *am33
6800 {
6801 int srcreg1, srcreg2, dstreg1, dstreg2;
6802
6803 PC = cia;
6804 srcreg1 = translate_rreg (SD_, RM1);
6805 srcreg2 = translate_rreg (SD_, RM2);
6806 dstreg1 = translate_rreg (SD_, RN1);
6807 dstreg2 = translate_rreg (SD_, RN2);
6808
6809 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6810 State.regs[dstreg1] &= State.regs[srcreg1];
6811 }
6812
6813 // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
6814 8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
6815 "and_cmp"
6816 *am33
6817 {
6818 int srcreg1, dstreg1, dstreg2;
6819
6820 PC = cia;
6821 srcreg1 = translate_rreg (SD_, RM1);
6822 dstreg1 = translate_rreg (SD_, RN1);
6823 dstreg2 = translate_rreg (SD_, RN2);
6824
6825 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6826 State.regs[dstreg1] &= State.regs[srcreg1];
6827 }
6828
6829 // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
6830 8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
6831 "and_mov"
6832 *am33
6833 {
6834 int srcreg1, srcreg2, dstreg1, dstreg2;
6835 int result1;
6836
6837 PC = cia;
6838 srcreg1 = translate_rreg (SD_, RM1);
6839 srcreg2 = translate_rreg (SD_, RM2);
6840 dstreg1 = translate_rreg (SD_, RN1);
6841 dstreg2 = translate_rreg (SD_, RN2);
6842
6843 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6844 State.regs[dstreg2] = State.regs[srcreg2];
6845 State.regs[dstreg1] = result1;
6846 }
6847
6848 // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
6849 8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
6850 "and_mov"
6851 *am33
6852 {
6853 int srcreg1, dstreg1, dstreg2;
6854 int result1;
6855
6856 PC = cia;
6857 srcreg1 = translate_rreg (SD_, RM1);
6858 dstreg1 = translate_rreg (SD_, RN1);
6859 dstreg2 = translate_rreg (SD_, RN2);
6860
6861 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6862 State.regs[dstreg2] = EXTEND4 (IMM4);
6863 State.regs[dstreg1] = result1;
6864 }
6865
6866 // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
6867 8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
6868 "and_asr"
6869 *am33
6870 {
6871 int srcreg1, srcreg2, dstreg1, dstreg2;
6872 int result1;
6873 signed int temp;
6874
6875 PC = cia;
6876 srcreg1 = translate_rreg (SD_, RM1);
6877 srcreg2 = translate_rreg (SD_, RM2);
6878 dstreg1 = translate_rreg (SD_, RN1);
6879 dstreg2 = translate_rreg (SD_, RN2);
6880
6881 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6882 temp = State.regs[dstreg2];
6883 temp >>= State.regs[srcreg2];
6884 State.regs[dstreg2] = temp;
6885 State.regs[dstreg1] = result1;
6886 }
6887
6888 // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
6889 8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
6890 "and_asr"
6891 *am33
6892 {
6893 int srcreg1, dstreg1, dstreg2;
6894 int result1;
6895 signed int temp;
6896
6897 PC = cia;
6898 srcreg1 = translate_rreg (SD_, RM1);
6899 dstreg1 = translate_rreg (SD_, RN1);
6900 dstreg2 = translate_rreg (SD_, RN2);
6901
6902 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6903 temp = State.regs[dstreg2];
6904 temp >>= IMM4;
6905 State.regs[dstreg2] = temp;
6906 State.regs[dstreg1] = result1;
6907 }
6908
6909 // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
6910 8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
6911 "and_lsr"
6912 *am33
6913 {
6914 int srcreg1, srcreg2, dstreg1, dstreg2;
6915 int result1;
6916
6917 PC = cia;
6918 srcreg1 = translate_rreg (SD_, RM1);
6919 srcreg2 = translate_rreg (SD_, RM2);
6920 dstreg1 = translate_rreg (SD_, RN1);
6921 dstreg2 = translate_rreg (SD_, RN2);
6922
6923 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6924 State.regs[dstreg2] >>= State.regs[srcreg2];
6925 State.regs[dstreg1] = result1;
6926 }
6927
6928 // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
6929 8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
6930 "and_lsr"
6931 *am33
6932 {
6933 int srcreg1, dstreg1, dstreg2;
6934 int result1;
6935 signed int temp;
6936
6937 PC = cia;
6938 srcreg1 = translate_rreg (SD_, RM1);
6939 dstreg1 = translate_rreg (SD_, RN1);
6940 dstreg2 = translate_rreg (SD_, RN2);
6941
6942 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6943 State.regs[dstreg2] >>= IMM4;
6944 State.regs[dstreg1] = result1;
6945 }
6946
6947
6948 // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
6949 8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
6950 "and_asl"
6951 *am33
6952 {
6953 int srcreg1, srcreg2, dstreg1, dstreg2;
6954 int result1;
6955
6956 PC = cia;
6957 srcreg1 = translate_rreg (SD_, RM1);
6958 srcreg2 = translate_rreg (SD_, RM2);
6959 dstreg1 = translate_rreg (SD_, RN1);
6960 dstreg2 = translate_rreg (SD_, RN2);
6961
6962 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6963 State.regs[dstreg2] <<= State.regs[srcreg2];
6964 State.regs[dstreg1] = result1;
6965 }
6966
6967 // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
6968 8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
6969 "and_asl"
6970 *am33
6971 {
6972 int srcreg1, dstreg1, dstreg2;
6973 int result1;
6974 signed int temp;
6975
6976 PC = cia;
6977 srcreg1 = translate_rreg (SD_, RM1);
6978 dstreg1 = translate_rreg (SD_, RN1);
6979 dstreg2 = translate_rreg (SD_, RN2);
6980
6981 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6982 State.regs[dstreg2] <<= IMM4;
6983 State.regs[dstreg1] = result1;
6984 }
6985
6986 // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
6987 8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
6988 "dmach_add"
6989 *am33
6990 {
6991 int srcreg1, srcreg2, dstreg1, dstreg2;
6992 signed32 temp, temp2, sum;
6993
6994 PC = cia;
6995 srcreg1 = translate_rreg (SD_, RM1);
6996 srcreg2 = translate_rreg (SD_, RM2);
6997 dstreg1 = translate_rreg (SD_, RN1);
6998 dstreg2 = translate_rreg (SD_, RN2);
6999
7000 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7001 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7002 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7003 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7004 sum = temp + temp2 + State.regs[REG_MCRL];
7005
7006 State.regs[dstreg2] += State.regs[srcreg2];
7007 State.regs[dstreg1] = sum;
7008 }
7009
7010 // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
7011 8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
7012 "dmach_add"
7013 *am33
7014 {
7015 int srcreg1, dstreg1, dstreg2;
7016 signed32 temp, temp2, sum;
7017
7018 PC = cia;
7019 srcreg1 = translate_rreg (SD_, RM1);
7020 dstreg1 = translate_rreg (SD_, RN1);
7021 dstreg2 = translate_rreg (SD_, RN2);
7022
7023 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7024 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7025 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7026 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7027 sum = temp + temp2 + State.regs[REG_MCRL];
7028
7029 State.regs[dstreg2] += EXTEND4 (IMM4);
7030 State.regs[dstreg1] = sum;
7031 }
7032
7033 // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
7034 8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
7035 "dmach_sub"
7036 *am33
7037 {
7038 int srcreg1, srcreg2, dstreg1, dstreg2;
7039 signed32 temp, temp2, sum;
7040
7041 PC = cia;
7042 srcreg1 = translate_rreg (SD_, RM1);
7043 srcreg2 = translate_rreg (SD_, RM2);
7044 dstreg1 = translate_rreg (SD_, RN1);
7045 dstreg2 = translate_rreg (SD_, RN2);
7046
7047 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7048 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7049 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7050 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7051 sum = temp + temp2 + State.regs[REG_MCRL];
7052
7053 State.regs[dstreg2] -= State.regs[srcreg2];
7054 State.regs[dstreg1] = sum;
7055 }
7056
7057 // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
7058 8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
7059 "dmach_sub"
7060 *am33
7061 {
7062 int srcreg1, dstreg1, dstreg2;
7063 signed32 temp, temp2, sum;
7064
7065 PC = cia;
7066 srcreg1 = translate_rreg (SD_, RM1);
7067 dstreg1 = translate_rreg (SD_, RN1);
7068 dstreg2 = translate_rreg (SD_, RN2);
7069
7070 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7071 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7072 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7073 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7074 sum = temp + temp2 + State.regs[REG_MCRL];
7075
7076 State.regs[dstreg2] -= EXTEND4 (IMM4);
7077 State.regs[dstreg1] = sum;
7078 }
7079
7080 // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
7081 8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
7082 "dmach_cmp"
7083 *am33
7084 {
7085 int srcreg1, srcreg2, dstreg1, dstreg2;
7086 signed32 temp, temp2, sum;
7087
7088 PC = cia;
7089 srcreg1 = translate_rreg (SD_, RM1);
7090 srcreg2 = translate_rreg (SD_, RM2);
7091 dstreg1 = translate_rreg (SD_, RN1);
7092 dstreg2 = translate_rreg (SD_, RN2);
7093
7094 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7095 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7096 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7097 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7098 sum = temp + temp2 + State.regs[REG_MCRL];
7099
7100 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7101 State.regs[dstreg1] = sum;
7102 }
7103
7104 // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
7105 8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
7106 "dmach_cmp"
7107 *am33
7108 {
7109 int srcreg1, dstreg1, dstreg2;
7110 signed32 temp, temp2, sum;
7111
7112 PC = cia;
7113 srcreg1 = translate_rreg (SD_, RM1);
7114 dstreg1 = translate_rreg (SD_, RN1);
7115 dstreg2 = translate_rreg (SD_, RN2);
7116
7117 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7118 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7119 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7120 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7121 sum = temp + temp2 + State.regs[REG_MCRL];
7122
7123 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7124 State.regs[dstreg1] = sum;
7125 }
7126
7127 // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
7128 8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
7129 "dmach_mov"
7130 *am33
7131 {
7132 int srcreg1, srcreg2, dstreg1, dstreg2;
7133 signed32 temp, temp2, sum;
7134
7135 PC = cia;
7136 srcreg1 = translate_rreg (SD_, RM1);
7137 srcreg2 = translate_rreg (SD_, RM2);
7138 dstreg1 = translate_rreg (SD_, RN1);
7139 dstreg2 = translate_rreg (SD_, RN2);
7140
7141 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7142 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7143 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7144 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7145 sum = temp + temp2 + State.regs[REG_MCRL];
7146
7147 State.regs[dstreg2] = State.regs[srcreg2];
7148 State.regs[dstreg1] = sum;
7149 }
7150
7151 // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
7152 8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
7153 "dmach_mov"
7154 *am33
7155 {
7156 int srcreg1, dstreg1, dstreg2;
7157 signed32 temp, temp2, sum;
7158
7159 PC = cia;
7160 srcreg1 = translate_rreg (SD_, RM1);
7161 dstreg1 = translate_rreg (SD_, RN1);
7162 dstreg2 = translate_rreg (SD_, RN2);
7163
7164 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7165 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7166 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7167 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7168 sum = temp + temp2 + State.regs[REG_MCRL];
7169
7170 State.regs[dstreg2] = EXTEND4 (IMM4);
7171 State.regs[dstreg1] = sum;
7172 }
7173
7174 // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
7175 8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
7176 "dmach_asr"
7177 *am33
7178 {
7179 int srcreg1, srcreg2, dstreg1, dstreg2;
7180 signed32 temp, temp2, sum;
7181
7182 PC = cia;
7183 srcreg1 = translate_rreg (SD_, RM1);
7184 srcreg2 = translate_rreg (SD_, RM2);
7185 dstreg1 = translate_rreg (SD_, RN1);
7186 dstreg2 = translate_rreg (SD_, RN2);
7187
7188 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7189 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7190 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7191 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7192 sum = temp + temp2 + State.regs[REG_MCRL];
7193
7194 temp = State.regs[dstreg2];
7195 temp >>= State.regs[srcreg2];
7196 State.regs[dstreg2] = temp;
7197 State.regs[dstreg1] = sum;
7198 }
7199
7200 // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
7201 8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
7202 "dmach_asr"
7203 *am33
7204 {
7205 int srcreg1, dstreg1, dstreg2;
7206 signed32 temp, temp2, sum;
7207
7208 PC = cia;
7209 srcreg1 = translate_rreg (SD_, RM1);
7210 dstreg1 = translate_rreg (SD_, RN1);
7211 dstreg2 = translate_rreg (SD_, RN2);
7212
7213 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7214 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7215 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7216 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7217 sum = temp + temp2 + State.regs[REG_MCRL];
7218
7219 temp = State.regs[dstreg2];
7220 temp >>= IMM4;
7221 State.regs[dstreg2] = temp;
7222 State.regs[dstreg1] = sum;
7223 }
7224
7225 // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
7226 8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
7227 "dmach_lsr"
7228 *am33
7229 {
7230 int srcreg1, srcreg2, dstreg1, dstreg2;
7231 signed32 temp, temp2, sum;
7232
7233 PC = cia;
7234 srcreg1 = translate_rreg (SD_, RM1);
7235 srcreg2 = translate_rreg (SD_, RM2);
7236 dstreg1 = translate_rreg (SD_, RN1);
7237 dstreg2 = translate_rreg (SD_, RN2);
7238
7239 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7240 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7241 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7242 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7243 sum = temp + temp2 + State.regs[REG_MCRL];
7244
7245 State.regs[dstreg2] >>= State.regs[srcreg2];
7246 State.regs[dstreg1] = sum;
7247 }
7248
7249 // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
7250 8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
7251 "dmach_lsr"
7252 *am33
7253 {
7254 int srcreg1, dstreg1, dstreg2;
7255 signed32 temp, temp2, sum;
7256
7257 PC = cia;
7258 srcreg1 = translate_rreg (SD_, RM1);
7259 dstreg1 = translate_rreg (SD_, RN1);
7260 dstreg2 = translate_rreg (SD_, RN2);
7261
7262 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7263 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7264 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7265 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7266 sum = temp + temp2 + State.regs[REG_MCRL];
7267
7268 State.regs[dstreg2] >>= IMM4;
7269 State.regs[dstreg1] = sum;
7270 }
7271
7272
7273 // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
7274 8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
7275 "dmach_asl"
7276 *am33
7277 {
7278 int srcreg1, srcreg2, dstreg1, dstreg2;
7279 signed32 temp, temp2, sum;
7280
7281 PC = cia;
7282 srcreg1 = translate_rreg (SD_, RM1);
7283 srcreg2 = translate_rreg (SD_, RM2);
7284 dstreg1 = translate_rreg (SD_, RN1);
7285 dstreg2 = translate_rreg (SD_, RN2);
7286
7287 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7288 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7289 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7290 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7291 sum = temp + temp2 + State.regs[REG_MCRL];
7292
7293 State.regs[dstreg2] <<= State.regs[srcreg2];
7294 State.regs[dstreg1] = sum;
7295 }
7296
7297 // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
7298 8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
7299 "dmach_asl"
7300 *am33
7301 {
7302 int srcreg1, dstreg1, dstreg2;
7303 signed32 temp, temp2, sum;
7304
7305 PC = cia;
7306 srcreg1 = translate_rreg (SD_, RM1);
7307 dstreg1 = translate_rreg (SD_, RN1);
7308 dstreg2 = translate_rreg (SD_, RN2);
7309
7310 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7311 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7312 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7313 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7314 sum = temp + temp2 + State.regs[REG_MCRL];
7315
7316 State.regs[dstreg2] <<= IMM4;
7317 State.regs[dstreg1] = sum;
7318 }
7319
7320 // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
7321 8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
7322 "xor_add"
7323 *am33
7324 {
7325 int srcreg1, srcreg2, dstreg1, dstreg2;
7326 int result1;
7327
7328 PC = cia;
7329 srcreg1 = translate_rreg (SD_, RM1);
7330 srcreg2 = translate_rreg (SD_, RM2);
7331 dstreg1 = translate_rreg (SD_, RN1);
7332 dstreg2 = translate_rreg (SD_, RN2);
7333
7334 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7335 State.regs[dstreg2] += State.regs[srcreg2];
7336 State.regs[dstreg1] = result1;
7337 }
7338
7339 // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
7340 8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
7341 "xor_add"
7342 *am33
7343 {
7344 int srcreg1, dstreg1, dstreg2;
7345 int result1;
7346
7347 PC = cia;
7348 srcreg1 = translate_rreg (SD_, RM1);
7349 dstreg1 = translate_rreg (SD_, RN1);
7350 dstreg2 = translate_rreg (SD_, RN2);
7351
7352 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7353 State.regs[dstreg2] += EXTEND4 (IMM4);
7354 State.regs[dstreg1] = result1;
7355 }
7356
7357 // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
7358 8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
7359 "xor_sub"
7360 *am33
7361 {
7362 int srcreg1, srcreg2, dstreg1, dstreg2;
7363 int result1;
7364
7365 PC = cia;
7366 srcreg1 = translate_rreg (SD_, RM1);
7367 srcreg2 = translate_rreg (SD_, RM2);
7368 dstreg1 = translate_rreg (SD_, RN1);
7369 dstreg2 = translate_rreg (SD_, RN2);
7370
7371 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7372 State.regs[dstreg2] -= State.regs[srcreg2];
7373 State.regs[dstreg1] = result1;
7374 }
7375
7376 // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
7377 8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
7378 "xor_sub"
7379 *am33
7380 {
7381 int srcreg1, dstreg1, dstreg2;
7382 int result1;
7383
7384 PC = cia;
7385 srcreg1 = translate_rreg (SD_, RM1);
7386 dstreg1 = translate_rreg (SD_, RN1);
7387 dstreg2 = translate_rreg (SD_, RN2);
7388
7389 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7390 State.regs[dstreg2] -= EXTEND4 (IMM4);
7391 State.regs[dstreg1] = result1;
7392 }
7393
7394 // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
7395 8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
7396 "xor_cmp"
7397 *am33
7398 {
7399 int srcreg1, srcreg2, dstreg1, dstreg2;
7400
7401 PC = cia;
7402 srcreg1 = translate_rreg (SD_, RM1);
7403 srcreg2 = translate_rreg (SD_, RM2);
7404 dstreg1 = translate_rreg (SD_, RN1);
7405 dstreg2 = translate_rreg (SD_, RN2);
7406
7407 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7408 State.regs[dstreg1] ^= State.regs[srcreg1];
7409 }
7410
7411 // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
7412 8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
7413 "xor_cmp"
7414 *am33
7415 {
7416 int srcreg1, dstreg1, dstreg2;
7417
7418 PC = cia;
7419 srcreg1 = translate_rreg (SD_, RM1);
7420 dstreg1 = translate_rreg (SD_, RN1);
7421 dstreg2 = translate_rreg (SD_, RN2);
7422
7423 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7424 State.regs[dstreg1] ^= State.regs[srcreg1];
7425 }
7426
7427 // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
7428 8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
7429 "xor_mov"
7430 *am33
7431 {
7432 int srcreg1, srcreg2, dstreg1, dstreg2;
7433 int result1;
7434
7435 PC = cia;
7436 srcreg1 = translate_rreg (SD_, RM1);
7437 srcreg2 = translate_rreg (SD_, RM2);
7438 dstreg1 = translate_rreg (SD_, RN1);
7439 dstreg2 = translate_rreg (SD_, RN2);
7440
7441 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7442 State.regs[dstreg2] = State.regs[srcreg2];
7443 State.regs[dstreg1] = result1;
7444 }
7445
7446 // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
7447 8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
7448 "xor_mov"
7449 *am33
7450 {
7451 int srcreg1, dstreg1, dstreg2;
7452 int result1;
7453
7454 PC = cia;
7455 srcreg1 = translate_rreg (SD_, RM1);
7456 dstreg1 = translate_rreg (SD_, RN1);
7457 dstreg2 = translate_rreg (SD_, RN2);
7458
7459 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7460 State.regs[dstreg2] = EXTEND4 (IMM4);
7461 State.regs[dstreg1] = result1;
7462 }
7463
7464 // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
7465 8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
7466 "xor_asr"
7467 *am33
7468 {
7469 int srcreg1, srcreg2, dstreg1, dstreg2;
7470 int result1;
7471 signed int temp;
7472
7473 PC = cia;
7474 srcreg1 = translate_rreg (SD_, RM1);
7475 srcreg2 = translate_rreg (SD_, RM2);
7476 dstreg1 = translate_rreg (SD_, RN1);
7477 dstreg2 = translate_rreg (SD_, RN2);
7478
7479 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7480 temp = State.regs[dstreg2];
7481 temp >>= State.regs[srcreg2];
7482 State.regs[dstreg2] = temp;
7483 State.regs[dstreg1] = result1;
7484 }
7485
7486 // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
7487 8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
7488 "xor_asr"
7489 *am33
7490 {
7491 int srcreg1, dstreg1, dstreg2;
7492 int result1;
7493 signed int temp;
7494
7495 PC = cia;
7496 srcreg1 = translate_rreg (SD_, RM1);
7497 dstreg1 = translate_rreg (SD_, RN1);
7498 dstreg2 = translate_rreg (SD_, RN2);
7499
7500 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7501 temp = State.regs[dstreg2];
7502 temp >>= IMM4;
7503 State.regs[dstreg2] = temp;
7504 State.regs[dstreg1] = result1;
7505 }
7506
7507 // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
7508 8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
7509 "xor_lsr"
7510 *am33
7511 {
7512 int srcreg1, srcreg2, dstreg1, dstreg2;
7513 int result1;
7514
7515 PC = cia;
7516 srcreg1 = translate_rreg (SD_, RM1);
7517 srcreg2 = translate_rreg (SD_, RM2);
7518 dstreg1 = translate_rreg (SD_, RN1);
7519 dstreg2 = translate_rreg (SD_, RN2);
7520
7521 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7522 State.regs[dstreg2] >>= State.regs[srcreg2];
7523 State.regs[dstreg1] = result1;
7524 }
7525
7526 // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
7527 8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
7528 "xor_lsr"
7529 *am33
7530 {
7531 int srcreg1, dstreg1, dstreg2;
7532 int result1;
7533 signed int temp;
7534
7535 PC = cia;
7536 srcreg1 = translate_rreg (SD_, RM1);
7537 dstreg1 = translate_rreg (SD_, RN1);
7538 dstreg2 = translate_rreg (SD_, RN2);
7539
7540 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7541 State.regs[dstreg2] >>= IMM4;
7542 State.regs[dstreg1] = result1;
7543 }
7544
7545
7546 // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
7547 8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
7548 "xor_asl"
7549 *am33
7550 {
7551 int srcreg1, srcreg2, dstreg1, dstreg2;
7552 int result1;
7553
7554 PC = cia;
7555 srcreg1 = translate_rreg (SD_, RM1);
7556 srcreg2 = translate_rreg (SD_, RM2);
7557 dstreg1 = translate_rreg (SD_, RN1);
7558 dstreg2 = translate_rreg (SD_, RN2);
7559
7560 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7561 State.regs[dstreg2] <<= State.regs[srcreg2];
7562 State.regs[dstreg1] = result1;
7563 }
7564
7565 // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
7566 8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
7567 "xor_asl"
7568 *am33
7569 {
7570 int srcreg1, dstreg1, dstreg2;
7571 int result1;
7572 signed int temp;
7573
7574 PC = cia;
7575 srcreg1 = translate_rreg (SD_, RM1);
7576 dstreg1 = translate_rreg (SD_, RN1);
7577 dstreg2 = translate_rreg (SD_, RN2);
7578
7579 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7580 State.regs[dstreg2] <<= IMM4;
7581 State.regs[dstreg1] = result1;
7582 }
7583
7584 // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
7585 8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
7586 "swhw_add"
7587 *am33
7588 {
7589 int srcreg1, srcreg2, dstreg1, dstreg2;
7590 int result1;
7591
7592 PC = cia;
7593 srcreg1 = translate_rreg (SD_, RM1);
7594 srcreg2 = translate_rreg (SD_, RM2);
7595 dstreg1 = translate_rreg (SD_, RN1);
7596 dstreg2 = translate_rreg (SD_, RN2);
7597
7598 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7599 State.regs[dstreg2] += State.regs[srcreg2];
7600 State.regs[dstreg1] = result1;
7601 }
7602
7603 // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
7604 8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
7605 "swhw_add"
7606 *am33
7607 {
7608 int srcreg1, dstreg1, dstreg2;
7609 int result1;
7610
7611 PC = cia;
7612 srcreg1 = translate_rreg (SD_, RM1);
7613 dstreg1 = translate_rreg (SD_, RN1);
7614 dstreg2 = translate_rreg (SD_, RN2);
7615
7616 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7617 | ((State.regs[srcreg1] >> 16) & 0xffff));
7618 State.regs[dstreg2] += EXTEND4 (IMM4);
7619 State.regs[dstreg1] = result1;
7620 }
7621
7622 // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
7623 8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
7624 "swhw_sub"
7625 *am33
7626 {
7627 int srcreg1, srcreg2, dstreg1, dstreg2;
7628 int result1;
7629
7630 PC = cia;
7631 srcreg1 = translate_rreg (SD_, RM1);
7632 srcreg2 = translate_rreg (SD_, RM2);
7633 dstreg1 = translate_rreg (SD_, RN1);
7634 dstreg2 = translate_rreg (SD_, RN2);
7635
7636 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7637 | ((State.regs[srcreg1] >> 16) & 0xffff));
7638 State.regs[dstreg2] -= State.regs[srcreg2];
7639 State.regs[dstreg1] = result1;
7640 }
7641
7642 // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
7643 8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
7644 "swhw_sub"
7645 *am33
7646 {
7647 int srcreg1, dstreg1, dstreg2;
7648 int result1;
7649
7650 PC = cia;
7651 srcreg1 = translate_rreg (SD_, RM1);
7652 dstreg1 = translate_rreg (SD_, RN1);
7653 dstreg2 = translate_rreg (SD_, RN2);
7654
7655 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7656 | ((State.regs[srcreg1] >> 16) & 0xffff));
7657 State.regs[dstreg2] -= EXTEND4 (IMM4);
7658 State.regs[dstreg1] = result1;
7659 }
7660
7661 // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
7662 8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
7663 "swhw_cmp"
7664 *am33
7665 {
7666 int srcreg1, srcreg2, dstreg1, dstreg2;
7667
7668 PC = cia;
7669 srcreg1 = translate_rreg (SD_, RM1);
7670 srcreg2 = translate_rreg (SD_, RM2);
7671 dstreg1 = translate_rreg (SD_, RN1);
7672 dstreg2 = translate_rreg (SD_, RN2);
7673
7674 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7675 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7676 | ((State.regs[srcreg1] >> 16) & 0xffff));
7677 }
7678
7679 // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
7680 8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
7681 "swhw_cmp"
7682 *am33
7683 {
7684 int srcreg1, dstreg1, dstreg2;
7685
7686 PC = cia;
7687 srcreg1 = translate_rreg (SD_, RM1);
7688 dstreg1 = translate_rreg (SD_, RN1);
7689 dstreg2 = translate_rreg (SD_, RN2);
7690
7691 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7692 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7693 | ((State.regs[srcreg1] >> 16) & 0xffff));
7694 }
7695
7696 // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
7697 8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
7698 "swhw_mov"
7699 *am33
7700 {
7701 int srcreg1, srcreg2, dstreg1, dstreg2;
7702 int result1;
7703
7704 PC = cia;
7705 srcreg1 = translate_rreg (SD_, RM1);
7706 srcreg2 = translate_rreg (SD_, RM2);
7707 dstreg1 = translate_rreg (SD_, RN1);
7708 dstreg2 = translate_rreg (SD_, RN2);
7709
7710 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7711 | ((State.regs[srcreg1] >> 16) & 0xffff));
7712 State.regs[dstreg2] = State.regs[srcreg2];
7713 State.regs[dstreg1] = result1;
7714 }
7715
7716 // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
7717 8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
7718 "swhw_mov"
7719 *am33
7720 {
7721 int srcreg1, dstreg1, dstreg2;
7722 int result1;
7723
7724 PC = cia;
7725 srcreg1 = translate_rreg (SD_, RM1);
7726 dstreg1 = translate_rreg (SD_, RN1);
7727 dstreg2 = translate_rreg (SD_, RN2);
7728
7729 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7730 | ((State.regs[srcreg1] >> 16) & 0xffff));
7731 State.regs[dstreg2] = EXTEND4 (IMM4);
7732 State.regs[dstreg1] = result1;
7733 }
7734
7735 // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
7736 8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
7737 "swhw_asr"
7738 *am33
7739 {
7740 int srcreg1, srcreg2, dstreg1, dstreg2;
7741 int result1;
7742 signed int temp;
7743
7744 PC = cia;
7745 srcreg1 = translate_rreg (SD_, RM1);
7746 srcreg2 = translate_rreg (SD_, RM2);
7747 dstreg1 = translate_rreg (SD_, RN1);
7748 dstreg2 = translate_rreg (SD_, RN2);
7749
7750 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7751 | ((State.regs[srcreg1] >> 16) & 0xffff));
7752 temp = State.regs[dstreg2];
7753 temp >>= State.regs[srcreg2];
7754 State.regs[dstreg2] = temp;
7755 State.regs[dstreg1] = result1;
7756 }
7757
7758 // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
7759 8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
7760 "swhw_asr"
7761 *am33
7762 {
7763 int srcreg1, dstreg1, dstreg2;
7764 int result1;
7765 signed int temp;
7766
7767 PC = cia;
7768 srcreg1 = translate_rreg (SD_, RM1);
7769 dstreg1 = translate_rreg (SD_, RN1);
7770 dstreg2 = translate_rreg (SD_, RN2);
7771
7772 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7773 | ((State.regs[srcreg1] >> 16) & 0xffff));
7774 temp = State.regs[dstreg2];
7775 temp >>= IMM4;
7776 State.regs[dstreg2] = temp;
7777 State.regs[dstreg1] = result1;
7778 }
7779
7780 // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
7781 8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
7782 "swhw_lsr"
7783 *am33
7784 {
7785 int srcreg1, srcreg2, dstreg1, dstreg2;
7786 int result1;
7787
7788 PC = cia;
7789 srcreg1 = translate_rreg (SD_, RM1);
7790 srcreg2 = translate_rreg (SD_, RM2);
7791 dstreg1 = translate_rreg (SD_, RN1);
7792 dstreg2 = translate_rreg (SD_, RN2);
7793
7794 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7795 | ((State.regs[srcreg1] >> 16) & 0xffff));
7796 State.regs[dstreg2] >>= State.regs[srcreg2];
7797 State.regs[dstreg1] = result1;
7798 }
7799
7800 // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
7801 8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
7802 "swhw_lsr"
7803 *am33
7804 {
7805 int srcreg1, dstreg1, dstreg2;
7806 int result1;
7807 signed int temp;
7808
7809 PC = cia;
7810 srcreg1 = translate_rreg (SD_, RM1);
7811 dstreg1 = translate_rreg (SD_, RN1);
7812 dstreg2 = translate_rreg (SD_, RN2);
7813
7814 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7815 | ((State.regs[srcreg1] >> 16) & 0xffff));
7816 State.regs[dstreg2] >>= IMM4;
7817 State.regs[dstreg1] = result1;
7818 }
7819
7820
7821 // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
7822 8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
7823 "swhw_asl"
7824 *am33
7825 {
7826 int srcreg1, srcreg2, dstreg1, dstreg2;
7827 int result1;
7828
7829 PC = cia;
7830 srcreg1 = translate_rreg (SD_, RM1);
7831 srcreg2 = translate_rreg (SD_, RM2);
7832 dstreg1 = translate_rreg (SD_, RN1);
7833 dstreg2 = translate_rreg (SD_, RN2);
7834
7835 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7836 | ((State.regs[srcreg1] >> 16) & 0xffff));
7837 State.regs[dstreg2] <<= State.regs[srcreg2];
7838 State.regs[dstreg1] = result1;
7839 }
7840
7841 // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
7842 8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
7843 "swhw_asl"
7844 *am33
7845 {
7846 int srcreg1, dstreg1, dstreg2;
7847 int result1;
7848 signed int temp;
7849
7850 PC = cia;
7851 srcreg1 = translate_rreg (SD_, RM1);
7852 dstreg1 = translate_rreg (SD_, RN1);
7853 dstreg2 = translate_rreg (SD_, RN2);
7854
7855 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7856 | ((State.regs[srcreg1] >> 16) & 0xffff));
7857 State.regs[dstreg2] <<= IMM4;
7858 State.regs[dstreg1] = result1;
7859 }
7860
7861 // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
7862 8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
7863 "or_add"
7864 *am33
7865 {
7866 int srcreg1, srcreg2, dstreg1, dstreg2;
7867 int result1;
7868
7869 PC = cia;
7870 srcreg1 = translate_rreg (SD_, RM1);
7871 srcreg2 = translate_rreg (SD_, RM2);
7872 dstreg1 = translate_rreg (SD_, RN1);
7873 dstreg2 = translate_rreg (SD_, RN2);
7874
7875 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7876 State.regs[dstreg2] += State.regs[srcreg2];
7877 State.regs[dstreg1] = result1;
7878 }
7879
7880 // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
7881 8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
7882 "or_add"
7883 *am33
7884 {
7885 int srcreg1, dstreg1, dstreg2;
7886 int result1;
7887
7888 PC = cia;
7889 srcreg1 = translate_rreg (SD_, RM1);
7890 dstreg1 = translate_rreg (SD_, RN1);
7891 dstreg2 = translate_rreg (SD_, RN2);
7892
7893 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7894 State.regs[dstreg2] += EXTEND4 (IMM4);
7895 State.regs[dstreg1] = result1;
7896 }
7897
7898 // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
7899 8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
7900 "or_sub"
7901 *am33
7902 {
7903 int srcreg1, srcreg2, dstreg1, dstreg2;
7904 int result1;
7905
7906 PC = cia;
7907 srcreg1 = translate_rreg (SD_, RM1);
7908 srcreg2 = translate_rreg (SD_, RM2);
7909 dstreg1 = translate_rreg (SD_, RN1);
7910 dstreg2 = translate_rreg (SD_, RN2);
7911
7912 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7913 State.regs[dstreg2] -= State.regs[srcreg2];
7914 State.regs[dstreg1] = result1;
7915 }
7916
7917 // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
7918 8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
7919 "or_sub"
7920 *am33
7921 {
7922 int srcreg1, dstreg1, dstreg2;
7923 int result1;
7924
7925 PC = cia;
7926 srcreg1 = translate_rreg (SD_, RM1);
7927 dstreg1 = translate_rreg (SD_, RN1);
7928 dstreg2 = translate_rreg (SD_, RN2);
7929
7930 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7931 State.regs[dstreg2] -= EXTEND4 (IMM4);
7932 State.regs[dstreg1] = result1;
7933 }
7934
7935 // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
7936 8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
7937 "or_cmp"
7938 *am33
7939 {
7940 int srcreg1, srcreg2, dstreg1, dstreg2;
7941
7942 PC = cia;
7943 srcreg1 = translate_rreg (SD_, RM1);
7944 srcreg2 = translate_rreg (SD_, RM2);
7945 dstreg1 = translate_rreg (SD_, RN1);
7946 dstreg2 = translate_rreg (SD_, RN2);
7947
7948 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7949 State.regs[dstreg1] |= State.regs[srcreg1];
7950 }
7951
7952 // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
7953 8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
7954 "or_cmp"
7955 *am33
7956 {
7957 int srcreg1, dstreg1, dstreg2;
7958
7959 PC = cia;
7960 srcreg1 = translate_rreg (SD_, RM1);
7961 dstreg1 = translate_rreg (SD_, RN1);
7962 dstreg2 = translate_rreg (SD_, RN2);
7963
7964 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7965 State.regs[dstreg1] |= State.regs[srcreg1];
7966 }
7967
7968 // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
7969 8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
7970 "or_mov"
7971 *am33
7972 {
7973 int srcreg1, srcreg2, dstreg1, dstreg2;
7974 int result1;
7975
7976 PC = cia;
7977 srcreg1 = translate_rreg (SD_, RM1);
7978 srcreg2 = translate_rreg (SD_, RM2);
7979 dstreg1 = translate_rreg (SD_, RN1);
7980 dstreg2 = translate_rreg (SD_, RN2);
7981
7982 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7983 State.regs[dstreg2] = State.regs[srcreg2];
7984 State.regs[dstreg1] = result1;
7985 }
7986
7987 // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
7988 8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
7989 "or_mov"
7990 *am33
7991 {
7992 int srcreg1, dstreg1, dstreg2;
7993 int result1;
7994
7995 PC = cia;
7996 srcreg1 = translate_rreg (SD_, RM1);
7997 dstreg1 = translate_rreg (SD_, RN1);
7998 dstreg2 = translate_rreg (SD_, RN2);
7999
8000 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8001 State.regs[dstreg2] = EXTEND4 (IMM4);
8002 State.regs[dstreg1] = result1;
8003 }
8004
8005 // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
8006 8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
8007 "or_asr"
8008 *am33
8009 {
8010 int srcreg1, srcreg2, dstreg1, dstreg2;
8011 int result1;
8012 signed int temp;
8013
8014 PC = cia;
8015 srcreg1 = translate_rreg (SD_, RM1);
8016 srcreg2 = translate_rreg (SD_, RM2);
8017 dstreg1 = translate_rreg (SD_, RN1);
8018 dstreg2 = translate_rreg (SD_, RN2);
8019
8020 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8021 temp = State.regs[dstreg2];
8022 temp >>= State.regs[srcreg2];
8023 State.regs[dstreg2] = temp;
8024 State.regs[dstreg1] = result1;
8025 }
8026
8027 // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
8028 8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
8029 "or_asr"
8030 *am33
8031 {
8032 int srcreg1, dstreg1, dstreg2;
8033 int result1;
8034 signed int temp;
8035
8036 PC = cia;
8037 srcreg1 = translate_rreg (SD_, RM1);
8038 dstreg1 = translate_rreg (SD_, RN1);
8039 dstreg2 = translate_rreg (SD_, RN2);
8040
8041 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8042 temp = State.regs[dstreg2];
8043 temp >>= IMM4;
8044 State.regs[dstreg2] = temp;
8045 State.regs[dstreg1] = result1;
8046 }
8047
8048 // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
8049 8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
8050 "or_lsr"
8051 *am33
8052 {
8053 int srcreg1, srcreg2, dstreg1, dstreg2;
8054 int result1;
8055
8056 PC = cia;
8057 srcreg1 = translate_rreg (SD_, RM1);
8058 srcreg2 = translate_rreg (SD_, RM2);
8059 dstreg1 = translate_rreg (SD_, RN1);
8060 dstreg2 = translate_rreg (SD_, RN2);
8061
8062 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8063 State.regs[dstreg2] >>= State.regs[srcreg2];
8064 State.regs[dstreg1] = result1;
8065 }
8066
8067 // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
8068 8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
8069 "or_lsr"
8070 *am33
8071 {
8072 int srcreg1, dstreg1, dstreg2;
8073 int result1;
8074 signed int temp;
8075
8076 PC = cia;
8077 srcreg1 = translate_rreg (SD_, RM1);
8078 dstreg1 = translate_rreg (SD_, RN1);
8079 dstreg2 = translate_rreg (SD_, RN2);
8080
8081 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8082 State.regs[dstreg2] >>= IMM4;
8083 State.regs[dstreg1] = result1;
8084 }
8085
8086
8087 // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
8088 8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
8089 "or_asl"
8090 *am33
8091 {
8092 int srcreg1, srcreg2, dstreg1, dstreg2;
8093 int result1;
8094
8095 PC = cia;
8096 srcreg1 = translate_rreg (SD_, RM1);
8097 srcreg2 = translate_rreg (SD_, RM2);
8098 dstreg1 = translate_rreg (SD_, RN1);
8099 dstreg2 = translate_rreg (SD_, RN2);
8100
8101 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8102 State.regs[dstreg2] <<= State.regs[srcreg2];
8103 State.regs[dstreg1] = result1;
8104 }
8105
8106 // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
8107 8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
8108 "or_asl"
8109 *am33
8110 {
8111 int srcreg1, dstreg1, dstreg2;
8112 int result1;
8113 signed int temp;
8114
8115 PC = cia;
8116 srcreg1 = translate_rreg (SD_, RM1);
8117 dstreg1 = translate_rreg (SD_, RN1);
8118 dstreg2 = translate_rreg (SD_, RN2);
8119
8120 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8121 State.regs[dstreg2] <<= IMM4;
8122 State.regs[dstreg1] = result1;
8123 }
8124
8125 // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
8126 8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
8127 "sat16_add"
8128 *am33
8129 {
8130 int srcreg1, srcreg2, dstreg1, dstreg2;
8131 int result1;
8132
8133 PC = cia;
8134 srcreg1 = translate_rreg (SD_, RM1);
8135 srcreg2 = translate_rreg (SD_, RM2);
8136 dstreg1 = translate_rreg (SD_, RN1);
8137 dstreg2 = translate_rreg (SD_, RN2);
8138
8139 if (State.regs[srcreg1] >= 0x7fff)
8140 result1 = 0x7fff;
8141 else if (State.regs[srcreg1] <= 0xffff8000)
8142 result1 = 0xffff8000;
8143 else
8144 result1 = State.regs[srcreg1];
8145
8146 State.regs[dstreg2] += State.regs[srcreg2];
8147 State.regs[dstreg1] = result1;
8148 }
8149
8150 // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
8151 8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
8152 "sat16_add"
8153 *am33
8154 {
8155 int srcreg1, dstreg1, dstreg2;
8156 int result1;
8157
8158 PC = cia;
8159 srcreg1 = translate_rreg (SD_, RM1);
8160 dstreg1 = translate_rreg (SD_, RN1);
8161 dstreg2 = translate_rreg (SD_, RN2);
8162
8163 if (State.regs[srcreg1] >= 0x7fff)
8164 result1 = 0x7fff;
8165 else if (State.regs[srcreg1] <= 0xffff8000)
8166 result1 = 0xffff8000;
8167 else
8168 result1 = State.regs[srcreg1];
8169
8170 State.regs[dstreg2] += EXTEND4 (IMM4);
8171 State.regs[dstreg1] = result1;
8172 }
8173
8174 // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
8175 8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
8176 "sat16_sub"
8177 *am33
8178 {
8179 int srcreg1, srcreg2, dstreg1, dstreg2;
8180 int result1;
8181
8182 PC = cia;
8183 srcreg1 = translate_rreg (SD_, RM1);
8184 srcreg2 = translate_rreg (SD_, RM2);
8185 dstreg1 = translate_rreg (SD_, RN1);
8186 dstreg2 = translate_rreg (SD_, RN2);
8187
8188 if (State.regs[srcreg1] >= 0x7fff)
8189 result1 = 0x7fff;
8190 else if (State.regs[srcreg1] <= 0xffff8000)
8191 result1 = 0xffff8000;
8192 else
8193 result1 = State.regs[srcreg1];
8194
8195 State.regs[dstreg2] -= State.regs[srcreg2];
8196 State.regs[dstreg1] = result1;
8197 }
8198
8199 // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
8200 8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
8201 "sat16_sub"
8202 *am33
8203 {
8204 int srcreg1, dstreg1, dstreg2;
8205 int result1;
8206
8207 PC = cia;
8208 srcreg1 = translate_rreg (SD_, RM1);
8209 dstreg1 = translate_rreg (SD_, RN1);
8210 dstreg2 = translate_rreg (SD_, RN2);
8211
8212 if (State.regs[srcreg1] >= 0x7fff)
8213 result1 = 0x7fff;
8214 else if (State.regs[srcreg1] <= 0xffff8000)
8215 result1 = 0xffff8000;
8216 else
8217 result1 = State.regs[srcreg1];
8218
8219 State.regs[dstreg2] -= EXTEND4 (IMM4);
8220 State.regs[dstreg1] = result1;
8221 }
8222
8223 // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
8224 8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
8225 "sat16_cmp"
8226 *am33
8227 {
8228 int srcreg1, srcreg2, dstreg1, dstreg2;
8229 int result1;
8230
8231 PC = cia;
8232 srcreg1 = translate_rreg (SD_, RM1);
8233 srcreg2 = translate_rreg (SD_, RM2);
8234 dstreg1 = translate_rreg (SD_, RN1);
8235 dstreg2 = translate_rreg (SD_, RN2);
8236
8237 State.regs[dstreg1] = result1;
8238 if (State.regs[srcreg1] >= 0x7fff)
8239 State.regs[dstreg1] = 0x7fff;
8240 else if (State.regs[srcreg1] <= 0xffff8000)
8241 State.regs[dstreg1] = 0xffff8000;
8242 else
8243 State.regs[dstreg1] = State.regs[srcreg1];
8244 }
8245
8246 // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
8247 8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
8248 "sat16_cmp"
8249 *am33
8250 {
8251 int srcreg1, dstreg1, dstreg2;
8252
8253 PC = cia;
8254 srcreg1 = translate_rreg (SD_, RM1);
8255 dstreg1 = translate_rreg (SD_, RN1);
8256 dstreg2 = translate_rreg (SD_, RN2);
8257
8258 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
8259 if (State.regs[srcreg1] >= 0x7fff)
8260 State.regs[dstreg1] = 0x7fff;
8261 else if (State.regs[srcreg1] <= 0xffff8000)
8262 State.regs[dstreg1] = 0xffff8000;
8263 else
8264 State.regs[dstreg1] = State.regs[srcreg1];
8265 }
8266
8267 // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
8268 8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
8269 "sat16_mov"
8270 *am33
8271 {
8272 int srcreg1, srcreg2, dstreg1, dstreg2;
8273 int result1;
8274
8275 PC = cia;
8276 srcreg1 = translate_rreg (SD_, RM1);
8277 srcreg2 = translate_rreg (SD_, RM2);
8278 dstreg1 = translate_rreg (SD_, RN1);
8279 dstreg2 = translate_rreg (SD_, RN2);
8280
8281 if (State.regs[srcreg1] >= 0x7fff)
8282 result1 = 0x7fff;
8283 else if (State.regs[srcreg1] <= 0xffff8000)
8284 result1 = 0xffff8000;
8285 else
8286 result1 = State.regs[srcreg1];
8287
8288 State.regs[dstreg2] = State.regs[srcreg2];
8289 State.regs[dstreg1] = result1;
8290 }
8291
8292 // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
8293 8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
8294 "sat16_mov"
8295 *am33
8296 {
8297 int srcreg1, dstreg1, dstreg2;
8298 int result1;
8299
8300 PC = cia;
8301 srcreg1 = translate_rreg (SD_, RM1);
8302 dstreg1 = translate_rreg (SD_, RN1);
8303 dstreg2 = translate_rreg (SD_, RN2);
8304
8305 if (State.regs[srcreg1] >= 0x7fff)
8306 result1 = 0x7fff;
8307 else if (State.regs[srcreg1] <= 0xffff8000)
8308 result1 = 0xffff8000;
8309 else
8310 result1 = State.regs[srcreg1];
8311
8312 State.regs[dstreg2] = EXTEND4 (IMM4);
8313 State.regs[dstreg1] = result1;
8314 }
8315
8316 // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
8317 8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
8318 "sat16_asr"
8319 *am33
8320 {
8321 int srcreg1, srcreg2, dstreg1, dstreg2;
8322 int result1;
8323 signed int temp;
8324
8325 PC = cia;
8326 srcreg1 = translate_rreg (SD_, RM1);
8327 srcreg2 = translate_rreg (SD_, RM2);
8328 dstreg1 = translate_rreg (SD_, RN1);
8329 dstreg2 = translate_rreg (SD_, RN2);
8330
8331 if (State.regs[srcreg1] >= 0x7fff)
8332 result1 = 0x7fff;
8333 else if (State.regs[srcreg1] <= 0xffff8000)
8334 result1 = 0xffff8000;
8335 else
8336 result1 = State.regs[srcreg1];
8337
8338 temp = State.regs[dstreg2];
8339 temp >>= State.regs[srcreg2];
8340 State.regs[dstreg2] = temp;
8341 State.regs[dstreg1] = result1;
8342 }
8343
8344 // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
8345 8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
8346 "sat16_asr"
8347 *am33
8348 {
8349 int srcreg1, dstreg1, dstreg2;
8350 int result1;
8351 signed int temp;
8352
8353 PC = cia;
8354 srcreg1 = translate_rreg (SD_, RM1);
8355 dstreg1 = translate_rreg (SD_, RN1);
8356 dstreg2 = translate_rreg (SD_, RN2);
8357
8358 if (State.regs[srcreg1] >= 0x7fff)
8359 result1 = 0x7fff;
8360 else if (State.regs[srcreg1] <= 0xffff8000)
8361 result1 = 0xffff8000;
8362 else
8363 result1 = State.regs[srcreg1];
8364
8365 temp = State.regs[dstreg2];
8366 temp >>= IMM4;
8367 State.regs[dstreg2] = temp;
8368 State.regs[dstreg1] = result1;
8369 }
8370
8371 // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
8372 8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
8373 "sat16_lsr"
8374 *am33
8375 {
8376 int srcreg1, srcreg2, dstreg1, dstreg2;
8377 int result1;
8378
8379 PC = cia;
8380 srcreg1 = translate_rreg (SD_, RM1);
8381 srcreg2 = translate_rreg (SD_, RM2);
8382 dstreg1 = translate_rreg (SD_, RN1);
8383 dstreg2 = translate_rreg (SD_, RN2);
8384
8385 if (State.regs[srcreg1] >= 0x7fff)
8386 result1 = 0x7fff;
8387 else if (State.regs[srcreg1] <= 0xffff8000)
8388 result1 = 0xffff8000;
8389 else
8390 result1 = State.regs[srcreg1];
8391
8392 State.regs[dstreg2] >>= State.regs[srcreg2];
8393 State.regs[dstreg1] = result1;
8394 }
8395
8396 // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
8397 8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
8398 "sat16_lsr"
8399 *am33
8400 {
8401 int srcreg1, dstreg1, dstreg2;
8402 int result1;
8403 signed int temp;
8404
8405 PC = cia;
8406 srcreg1 = translate_rreg (SD_, RM1);
8407 dstreg1 = translate_rreg (SD_, RN1);
8408 dstreg2 = translate_rreg (SD_, RN2);
8409
8410 if (State.regs[srcreg1] >= 0x7fff)
8411 result1 = 0x7fff;
8412 else if (State.regs[srcreg1] <= 0xffff8000)
8413 result1 = 0xffff8000;
8414 else
8415 result1 = State.regs[srcreg1];
8416
8417 State.regs[dstreg2] >>= IMM4;
8418 State.regs[dstreg1] = result1;
8419 }
8420
8421
8422 // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
8423 8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
8424 "sat16_asl"
8425 *am33
8426 {
8427 int srcreg1, srcreg2, dstreg1, dstreg2;
8428 int result1;
8429
8430 PC = cia;
8431 srcreg1 = translate_rreg (SD_, RM1);
8432 srcreg2 = translate_rreg (SD_, RM2);
8433 dstreg1 = translate_rreg (SD_, RN1);
8434 dstreg2 = translate_rreg (SD_, RN2);
8435
8436 if (State.regs[srcreg1] >= 0x7fff)
8437 result1 = 0x7fff;
8438 else if (State.regs[srcreg1] <= 0xffff8000)
8439 result1 = 0xffff8000;
8440 else
8441 result1 = State.regs[srcreg1];
8442
8443 State.regs[dstreg2] <<= State.regs[srcreg2];
8444 State.regs[dstreg1] = result1;
8445 }
8446
8447 // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
8448 8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
8449 "sat16_asl"
8450 *am33
8451 {
8452 int srcreg1, dstreg1, dstreg2;
8453 int result1;
8454 signed int temp;
8455
8456 PC = cia;
8457 srcreg1 = translate_rreg (SD_, RM1);
8458 dstreg1 = translate_rreg (SD_, RN1);
8459 dstreg2 = translate_rreg (SD_, RN2);
8460
8461 if (State.regs[srcreg1] >= 0x7fff)
8462 result1 = 0x7fff;
8463 else if (State.regs[srcreg1] <= 0xffff8000)
8464 result1 = 0xffff8000;
8465 else
8466 result1 = State.regs[srcreg1];
8467
8468 State.regs[dstreg2] <<= IMM4;
8469 State.regs[dstreg1] = result1;
8470 }
8471
8472 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
8473 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
8474 "mov_llt"
8475 *am33
8476 {
8477 int srcreg, dstreg;
8478 int result1;
8479
8480 PC = cia;
8481 srcreg = translate_rreg (SD_, RM);
8482 dstreg = translate_rreg (SD_, RN);
8483
8484 State.regs[dstreg] = load_word (State.regs[srcreg]);
8485 State.regs[srcreg] += EXTEND4 (IMM4);
8486
8487 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
8488 {
8489 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8490 nia = PC;
8491 }
8492 State.regs[dstreg] = result1;
8493 }
8494
8495 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
8496 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
8497 "mov_lgt"
8498 *am33
8499 {
8500 int srcreg, dstreg;
8501
8502 PC = cia;
8503 srcreg = translate_rreg (SD_, RM);
8504 dstreg = translate_rreg (SD_, RN);
8505
8506 State.regs[dstreg] = load_word (State.regs[srcreg]);
8507 State.regs[srcreg] += EXTEND4 (IMM4);
8508
8509 if (!((PSW & PSW_Z)
8510 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
8511 {
8512 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8513 nia = PC;
8514 }
8515 }
8516
8517 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
8518 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
8519 "mov_lge"
8520 *am33
8521 {
8522 int srcreg, dstreg;
8523
8524 PC = cia;
8525 srcreg = translate_rreg (SD_, RM);
8526 dstreg = translate_rreg (SD_, RN);
8527
8528 State.regs[dstreg] = load_word (State.regs[srcreg]);
8529 State.regs[srcreg] += EXTEND4 (IMM4);
8530
8531 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8532 {
8533 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8534 nia = PC;
8535 }
8536 }
8537
8538 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
8539 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
8540 "mov_lle"
8541 *am33
8542 {
8543 int srcreg, dstreg;
8544
8545 PC = cia;
8546 srcreg = translate_rreg (SD_, RM);
8547 dstreg = translate_rreg (SD_, RN);
8548
8549 State.regs[dstreg] = load_word (State.regs[srcreg]);
8550 State.regs[srcreg] += EXTEND4 (IMM4);
8551
8552 if ((PSW & PSW_Z)
8553 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8554 {
8555 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8556 nia = PC;
8557 }
8558 }
8559
8560 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
8561 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
8562 "mov_lcs"
8563 *am33
8564 {
8565 int srcreg, dstreg;
8566
8567 PC = cia;
8568 srcreg = translate_rreg (SD_, RM);
8569 dstreg = translate_rreg (SD_, RN);
8570
8571 State.regs[dstreg] = load_word (State.regs[srcreg]);
8572 State.regs[srcreg] += EXTEND4 (IMM4);
8573
8574 if (PSW & PSW_C)
8575 {
8576 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8577 nia = PC;
8578 }
8579 }
8580
8581 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
8582 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
8583 "mov_lhi"
8584 *am33
8585 {
8586 int srcreg, dstreg;
8587
8588 PC = cia;
8589 srcreg = translate_rreg (SD_, RM);
8590 dstreg = translate_rreg (SD_, RN);
8591
8592 State.regs[dstreg] = load_word (State.regs[srcreg]);
8593 State.regs[srcreg] += EXTEND4 (IMM4);
8594
8595 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
8596 {
8597 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8598 nia = PC;
8599 }
8600 }
8601
8602 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
8603 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
8604 "mov_lcc"
8605 *am33
8606 {
8607 int srcreg, dstreg;
8608
8609 PC = cia;
8610 srcreg = translate_rreg (SD_, RM);
8611 dstreg = translate_rreg (SD_, RN);
8612
8613 State.regs[dstreg] = load_word (State.regs[srcreg]);
8614 State.regs[srcreg] += EXTEND4 (IMM4);
8615
8616 if (!(PSW & PSW_C))
8617 {
8618 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8619 nia = PC;
8620 }
8621 }
8622
8623 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
8624 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
8625 "mov_lls"
8626 *am33
8627 {
8628 int srcreg, dstreg;
8629
8630 PC = cia;
8631 srcreg = translate_rreg (SD_, RM);
8632 dstreg = translate_rreg (SD_, RN);
8633
8634 State.regs[dstreg] = load_word (State.regs[srcreg]);
8635 State.regs[srcreg] += EXTEND4 (IMM4);
8636
8637 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
8638 {
8639 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8640 nia = PC;
8641 }
8642 }
8643
8644 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
8645 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
8646 "mov_leq"
8647 *am33
8648 {
8649 int srcreg, dstreg;
8650
8651 PC = cia;
8652 srcreg = translate_rreg (SD_, RM);
8653 dstreg = translate_rreg (SD_, RN);
8654
8655 State.regs[dstreg] = load_word (State.regs[srcreg]);
8656 State.regs[srcreg] += EXTEND4 (IMM4);
8657
8658 if (PSW & PSW_Z)
8659 {
8660 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8661 nia = PC;
8662 }
8663 }
8664
8665 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
8666 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
8667 "mov_lne"
8668 *am33
8669 {
8670 int srcreg, dstreg;
8671
8672 PC = cia;
8673 srcreg = translate_rreg (SD_, RM);
8674 dstreg = translate_rreg (SD_, RN);
8675
8676 State.regs[dstreg] = load_word (State.regs[srcreg]);
8677 State.regs[srcreg] += EXTEND4 (IMM4);
8678
8679 if (!(PSW & PSW_Z))
8680 {
8681 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8682 nia = PC;
8683 }
8684 }
8685
8686 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
8687 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
8688 "mov_lra"
8689 *am33
8690 {
8691 int srcreg, dstreg;
8692
8693 PC = cia;
8694 srcreg = translate_rreg (SD_, RM);
8695 dstreg = translate_rreg (SD_, RN);
8696
8697 State.regs[dstreg] = load_word (State.regs[srcreg]);
8698 State.regs[srcreg] += EXTEND4 (IMM4);
8699
8700 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8701 nia = PC;
8702 }
8703
GDB Binutils - Deliverables
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