sim/mn10300/interp.c

   1 #include <signal.h>
   2
   3 #if WITH_COMMON
   4 #include "sim-main.h"
   5 #include "sim-options.h"
   6 #include "sim-hw.h"
   7 #else
   8 #include "mn10300_sim.h"
   9 #endif
  10
  11 #include "sysdep.h"
  12 #include "bfd.h"
  13 #include "sim-assert.h"
  14
  15
  16 #ifdef HAVE_STDLIB_H
  17 #include <stdlib.h>
  18 #endif
  19
  20 #ifdef HAVE_STRING_H
  21 #include <string.h>
  22 #else
  23 #ifdef HAVE_STRINGS_H
  24 #include <strings.h>
  25 #endif
  26 #endif
  27
  28 #include "bfd.h"
  29
  30 #ifndef INLINE
  31 #ifdef __GNUC__
  32 #define INLINE inline
  33 #else
  34 #define INLINE
  35 #endif
  36 #endif
  37
  38
  39 host_callback *mn10300_callback;
  40 int mn10300_debug;
  41
  42 #if WITH_COMMON
  43 #else
  44 static void dispatch PARAMS ((uint32, uint32, int));
  45 static long hash PARAMS ((long));
  46 static void init_system PARAMS ((void));
  47
  48 static SIM_OPEN_KIND sim_kind;
  49 static char *myname;
  50 #define MAX_HASH  127
  51
  52 struct hash_entry
  53 {
  54   struct hash_entry *next;
  55   long opcode;
  56   long mask;
  57   struct simops *ops;
  58 #ifdef HASH_STAT
  59   unsigned long count;
  60 #endif
  61 };
  62
  63 static int max_mem = 0;
  64 struct hash_entry hash_table[MAX_HASH+1];
  65
  66
  67 /* This probably doesn't do a very good job at bucket filling, but
  68    it's simple... */
  69 static INLINE long
  70 hash(insn)
  71      long insn;
  72 {
  73   /* These are one byte insns, we special case these since, in theory,
  74      they should be the most heavily used.  */
  75   if ((insn & 0xffffff00) == 0)
  76     {
  77       switch (insn & 0xf0)
  78         {
  79           case 0x00:
  80             return 0x70;
  81
  82           case 0x40:
  83             return 0x71;
  84
  85           case 0x10:
  86             return 0x72;
  87
  88           case 0x30:
  89             return 0x73;
  90
  91           case 0x50:
  92             return 0x74;
  93
  94           case 0x60:
  95             return 0x75;
  96
  97           case 0x70:
  98             return 0x76;
  99
 100           case 0x80:
 101             return 0x77;
 102
 103           case 0x90:
 104             return 0x78;
 105
 106           case 0xa0:
 107             return 0x79;
 108
 109           case 0xb0:
 110             return 0x7a;
 111
 112           case 0xe0:
 113             return 0x7b;
 114
 115           default:
 116             return 0x7c;
 117         }
 118     }
 119
 120   /* These are two byte insns */
 121   if ((insn & 0xffff0000) == 0)
 122     {
 123       if ((insn & 0xf000) == 0x2000
 124           || (insn & 0xf000) == 0x5000)
 125         return ((insn & 0xfc00) >> 8) & 0x7f;
 126
 127       if ((insn & 0xf000) == 0x4000)
 128         return ((insn & 0xf300) >> 8) & 0x7f;
 129
 130       if ((insn & 0xf000) == 0x8000
 131           || (insn & 0xf000) == 0x9000
 132           || (insn & 0xf000) == 0xa000
 133           || (insn & 0xf000) == 0xb000)
 134         return ((insn & 0xf000) >> 8) & 0x7f;
 135
 136       if ((insn & 0xff00) == 0xf000
 137           || (insn & 0xff00) == 0xf100
 138           || (insn & 0xff00) == 0xf200
 139           || (insn & 0xff00) == 0xf500
 140           || (insn & 0xff00) == 0xf600)
 141         return ((insn & 0xfff0) >> 4) & 0x7f;
 142
 143       if ((insn & 0xf000) == 0xc000)
 144         return ((insn & 0xff00) >> 8) & 0x7f;
 145
 146       return ((insn & 0xffc0) >> 6) & 0x7f;
 147     }
 148
 149   /* These are three byte insns.  */
 150   if ((insn & 0xff000000) == 0)
 151     {
 152       if ((insn & 0xf00000) == 0x000000)
 153         return ((insn & 0xf30000) >> 16) & 0x7f;
 154
 155       if ((insn & 0xf00000) == 0x200000
 156           || (insn & 0xf00000) == 0x300000)
 157         return ((insn & 0xfc0000) >> 16) & 0x7f;
 158
 159       if ((insn & 0xff0000) == 0xf80000)
 160         return ((insn & 0xfff000) >> 12) & 0x7f;
 161
 162       if ((insn & 0xff0000) == 0xf90000)
 163         return ((insn & 0xfffc00) >> 10) & 0x7f;
 164
 165       return ((insn & 0xff0000) >> 16) & 0x7f;
 166     }
 167
 168   /* These are four byte or larger insns.  */
 169   if ((insn & 0xf0000000) == 0xf0000000)
 170     return ((insn & 0xfff00000) >> 20) & 0x7f;
 171
 172   return ((insn & 0xff000000) >> 24) & 0x7f;
 173 }
 174
 175 static INLINE void
 176 dispatch (insn, extension, length)
 177      uint32 insn;
 178      uint32 extension;
 179      int length;
 180 {
 181   struct hash_entry *h;
 182
 183   h = &hash_table[hash(insn)];
 184
 185   while ((insn & h->mask) != h->opcode
 186           || (length != h->ops->length))
 187     {
 188       if (!h->next)
 189         {
 190           (*mn10300_callback->printf_filtered) (mn10300_callback,
 191             "ERROR looking up hash for 0x%x, PC=0x%x\n", insn, PC);
 192           exit(1);
 193         }
 194       h = h->next;
 195     }
 196
 197
 198 #ifdef HASH_STAT
 199   h->count++;
 200 #endif
 201
 202   /* Now call the right function.  */
 203   (h->ops->func)(insn, extension);
 204   PC += length;
 205 }
 206
 207 void
 208 sim_size (power)
 209      int power;
 210
 211 {
 212   if (State.mem)
 213     free (State.mem);
 214
 215   max_mem = 1 << power;
 216   State.mem = (uint8 *) calloc (1,  1 << power);
 217   if (!State.mem)
 218     {
 219       (*mn10300_callback->printf_filtered) (mn10300_callback, "Allocation of main memory failed.\n");
 220       exit (1);
 221     }
 222 }
 223
 224 static void
 225 init_system ()
 226 {
 227   if (!State.mem)
 228     sim_size(19);
 229 }
 230
 231 int
 232 sim_write (sd, addr, buffer, size)
 233      SIM_DESC sd;
 234      SIM_ADDR addr;
 235      unsigned char *buffer;
 236      int size;
 237 {
 238   int i;
 239
 240   init_system ();
 241
 242   for (i = 0; i < size; i++)
 243     store_byte (addr + i, buffer[i]);
 244
 245   return size;
 246 }
 247
 248 /* Compare two opcode table entries for qsort.  */
 249 static int
 250 compare_simops (arg1, arg2)
 251      const PTR arg1;
 252      const PTR arg2;
 253 {
 254   unsigned long code1 = ((struct simops *)arg1)->opcode;
 255   unsigned long code2 = ((struct simops *)arg2)->opcode;
 256
 257   if (code1 < code2)
 258     return -1;
 259   if (code2 < code1)
 260     return 1;
 261   return 0;
 262 }
 263
 264
 265 SIM_DESC
 266 sim_open (kind, cb, abfd, argv)
 267      SIM_OPEN_KIND kind;
 268      host_callback *cb;
 269      struct _bfd *abfd;
 270      char **argv;
 271 {
 272   struct simops *s;
 273   struct hash_entry *h;
 274   char **p;
 275   int i;
 276
 277   mn10300_callback = cb;
 278
 279   /* Sort the opcode array from smallest opcode to largest.
 280      This will generally improve simulator performance as the smaller
 281      opcodes are generally preferred to the larger opcodes.  */
 282   for (i = 0, s = Simops; s->func; s++, i++)
 283     ;
 284   qsort (Simops, i, sizeof (Simops[0]), compare_simops);
 285
 286   sim_kind = kind;
 287   myname = argv[0];
 288
 289   for (p = argv + 1; *p; ++p)
 290     {
 291       if (strcmp (*p, "-E") == 0)
 292         ++p; /* ignore endian spec */
 293       else
 294 #ifdef DEBUG
 295       if (strcmp (*p, "-t") == 0)
 296         mn10300_debug = DEBUG;
 297       else
 298 #endif
 299         (*mn10300_callback->printf_filtered) (mn10300_callback, "ERROR: unsupported option(s): %s\n",*p);
 300     }
 301
 302  /* put all the opcodes in the hash table */
 303   for (s = Simops; s->func; s++)
 304     {
 305       h = &hash_table[hash(s->opcode)];
 306
 307       /* go to the last entry in the chain */
 308       while (h->next)
 309         {
 310           /* Don't insert the same opcode more than once.  */
 311           if (h->opcode == s->opcode
 312               && h->mask == s->mask
 313               && h->ops == s)
 314             break;
 315           else
 316             h = h->next;
 317         }
 318
 319       /* Don't insert the same opcode more than once.  */
 320       if (h->opcode == s->opcode
 321           && h->mask == s->mask
 322           && h->ops == s)
 323         continue;
 324
 325       if (h->ops)
 326         {
 327           h->next = calloc(1,sizeof(struct hash_entry));
 328           h = h->next;
 329         }
 330       h->ops = s;
 331       h->mask = s->mask;
 332       h->opcode = s->opcode;
 333 #if HASH_STAT
 334       h->count = 0;
 335 #endif
 336     }
 337
 338
 339   /* fudge our descriptor for now */
 340   return (SIM_DESC) 1;
 341 }
 342
 343
 344 void
 345 sim_close (sd, quitting)
 346      SIM_DESC sd;
 347      int quitting;
 348 {
 349   /* nothing to do */
 350 }
 351
 352 void
 353 sim_set_profile (n)
 354      int n;
 355 {
 356   (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile %d\n", n);
 357 }
 358
 359 void
 360 sim_set_profile_size (n)
 361      int n;
 362 {
 363   (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile_size %d\n", n);
 364 }
 365
 366 int
 367 sim_stop (sd)
 368      SIM_DESC sd;
 369 {
 370   return 0;
 371 }
 372
 373 void
 374 sim_resume (sd, step, siggnal)
 375      SIM_DESC sd;
 376      int step, siggnal;
 377 {
 378   uint32 inst;
 379   reg_t oldpc;
 380   struct hash_entry *h;
 381
 382   if (step)
 383     State.exception = SIGTRAP;
 384   else
 385     State.exception = 0;
 386
 387   State.exited = 0;
 388
 389   do
 390     {
 391       unsigned long insn, extension;
 392
 393       /* Fetch the current instruction.  */
 394       inst = load_mem_big (PC, 2);
 395       oldpc = PC;
 396
 397       /* Using a giant case statement may seem like a waste because of the
 398         code/rodata size the table itself will consume.  However, using
 399         a giant case statement speeds up the simulator by 10-15% by avoiding
 400         cascading if/else statements or cascading case statements.  */
 401
 402       switch ((inst >> 8) & 0xff)
 403         {
 404           /* All the single byte insns except 0x80, 0x90, 0xa0, 0xb0
 405              which must be handled specially.  */
 406           case 0x00:
 407           case 0x04:
 408           case 0x08:
 409           case 0x0c:
 410           case 0x10:
 411           case 0x11:
 412           case 0x12:
 413           case 0x13:
 414           case 0x14:
 415           case 0x15:
 416           case 0x16:
 417           case 0x17:
 418           case 0x18:
 419           case 0x19:
 420           case 0x1a:
 421           case 0x1b:
 422           case 0x1c:
 423           case 0x1d:
 424           case 0x1e:
 425           case 0x1f:
 426           case 0x3c:
 427           case 0x3d:
 428           case 0x3e:
 429           case 0x3f:
 430           case 0x40:
 431           case 0x41:
 432           case 0x44:
 433           case 0x45:
 434           case 0x48:
 435           case 0x49:
 436           case 0x4c:
 437           case 0x4d:
 438           case 0x50:
 439           case 0x51:
 440           case 0x52:
 441           case 0x53:
 442           case 0x54:
 443           case 0x55:
 444           case 0x56:
 445           case 0x57:
 446           case 0x60:
 447           case 0x61:
 448           case 0x62:
 449           case 0x63:
 450           case 0x64:
 451           case 0x65:
 452           case 0x66:
 453           case 0x67:
 454           case 0x68:
 455           case 0x69:
 456           case 0x6a:
 457           case 0x6b:
 458           case 0x6c:
 459           case 0x6d:
 460           case 0x6e:
 461           case 0x6f:
 462           case 0x70:
 463           case 0x71:
 464           case 0x72:
 465           case 0x73:
 466           case 0x74:
 467           case 0x75:
 468           case 0x76:
 469           case 0x77:
 470           case 0x78:
 471           case 0x79:
 472           case 0x7a:
 473           case 0x7b:
 474           case 0x7c:
 475           case 0x7d:
 476           case 0x7e:
 477           case 0x7f:
 478           case 0xcb:
 479           case 0xd0:
 480           case 0xd1:
 481           case 0xd2:
 482           case 0xd3:
 483           case 0xd4:
 484           case 0xd5:
 485           case 0xd6:
 486           case 0xd7:
 487           case 0xd8:
 488           case 0xd9:
 489           case 0xda:
 490           case 0xdb:
 491           case 0xe0:
 492           case 0xe1:
 493           case 0xe2:
 494           case 0xe3:
 495           case 0xe4:
 496           case 0xe5:
 497           case 0xe6:
 498           case 0xe7:
 499           case 0xe8:
 500           case 0xe9:
 501           case 0xea:
 502           case 0xeb:
 503           case 0xec:
 504           case 0xed:
 505           case 0xee:
 506           case 0xef:
 507           case 0xff:
 508             insn = (inst >> 8) & 0xff;
 509             extension = 0;
 510             dispatch (insn, extension, 1);
 511             break;
 512
 513           /* Special cases where dm == dn is used to encode a different
 514              instruction.  */
 515           case 0x80:
 516           case 0x85:
 517           case 0x8a:
 518           case 0x8f:
 519           case 0x90:
 520           case 0x95:
 521           case 0x9a:
 522           case 0x9f:
 523           case 0xa0:
 524           case 0xa5:
 525           case 0xaa:
 526           case 0xaf:
 527           case 0xb0:
 528           case 0xb5:
 529           case 0xba:
 530           case 0xbf:
 531             insn = inst;
 532             extension = 0;
 533             dispatch (insn, extension, 2);
 534             break;
 535
 536           case 0x81:
 537           case 0x82:
 538           case 0x83:
 539           case 0x84:
 540           case 0x86:
 541           case 0x87:
 542           case 0x88:
 543           case 0x89:
 544           case 0x8b:
 545           case 0x8c:
 546           case 0x8d:
 547           case 0x8e:
 548           case 0x91:
 549           case 0x92:
 550           case 0x93:
 551           case 0x94:
 552           case 0x96:
 553           case 0x97:
 554           case 0x98:
 555           case 0x99:
 556           case 0x9b:
 557           case 0x9c:
 558           case 0x9d:
 559           case 0x9e:
 560           case 0xa1:
 561           case 0xa2:
 562           case 0xa3:
 563           case 0xa4:
 564           case 0xa6:
 565           case 0xa7:
 566           case 0xa8:
 567           case 0xa9:
 568           case 0xab:
 569           case 0xac:
 570           case 0xad:
 571           case 0xae:
 572           case 0xb1:
 573           case 0xb2:
 574           case 0xb3:
 575           case 0xb4:
 576           case 0xb6:
 577           case 0xb7:
 578           case 0xb8:
 579           case 0xb9:
 580           case 0xbb:
 581           case 0xbc:
 582           case 0xbd:
 583           case 0xbe:
 584             insn = (inst >> 8) & 0xff;
 585             extension = 0;
 586           dispatch (insn, extension, 1);
 587           break;
 588
 589           /* The two byte instructions.  */
 590           case 0x20:
 591           case 0x21:
 592           case 0x22:
 593           case 0x23:
 594           case 0x28:
 595           case 0x29:
 596           case 0x2a:
 597           case 0x2b:
 598           case 0x42:
 599           case 0x43:
 600           case 0x46:
 601           case 0x47:
 602           case 0x4a:
 603           case 0x4b:
 604           case 0x4e:
 605           case 0x4f:
 606           case 0x58:
 607           case 0x59:
 608           case 0x5a:
 609           case 0x5b:
 610           case 0x5c:
 611           case 0x5d:
 612           case 0x5e:
 613           case 0x5f:
 614           case 0xc0:
 615           case 0xc1:
 616           case 0xc2:
 617           case 0xc3:
 618           case 0xc4:
 619           case 0xc5:
 620           case 0xc6:
 621           case 0xc7:
 622           case 0xc8:
 623           case 0xc9:
 624           case 0xca:
 625           case 0xce:
 626           case 0xcf:
 627           case 0xf0:
 628           case 0xf1:
 629           case 0xf2:
 630           case 0xf3:
 631           case 0xf4:
 632           case 0xf5:
 633           case 0xf6:
 634             insn = inst;
 635             extension = 0;
 636             dispatch (insn, extension, 2);
 637             break;
 638
 639           /* The three byte insns with a 16bit operand in little endian
 640              format.  */
 641           case 0x01:
 642           case 0x02:
 643           case 0x03:
 644           case 0x05:
 645           case 0x06:
 646           case 0x07:
 647           case 0x09:
 648           case 0x0a:
 649           case 0x0b:
 650           case 0x0d:
 651           case 0x0e:
 652           case 0x0f:
 653           case 0x24:
 654           case 0x25:
 655           case 0x26:
 656           case 0x27:
 657           case 0x2c:
 658           case 0x2d:
 659           case 0x2e:
 660           case 0x2f:
 661           case 0x30:
 662           case 0x31:
 663           case 0x32:
 664           case 0x33:
 665           case 0x34:
 666           case 0x35:
 667           case 0x36:
 668           case 0x37:
 669           case 0x38:
 670           case 0x39:
 671           case 0x3a:
 672           case 0x3b:
 673           case 0xcc:
 674             insn = load_byte (PC);
 675             insn <<= 16;
 676             insn |= load_half (PC + 1);
 677             extension = 0;
 678             dispatch (insn, extension, 3);
 679             break;
 680
 681           /* The three byte insns without 16bit operand.  */
 682           case 0xde:
 683           case 0xdf:
 684           case 0xf8:
 685           case 0xf9:
 686             insn = load_mem_big (PC, 3);
 687             extension = 0;
 688             dispatch (insn, extension, 3);
 689             break;
 690
 691           /* Four byte insns.  */
 692           case 0xfa:
 693           case 0xfb:
 694             if ((inst & 0xfffc) == 0xfaf0
 695                 || (inst & 0xfffc) == 0xfaf4
 696                 || (inst & 0xfffc) == 0xfaf8)
 697               insn = load_mem_big (PC, 4);
 698             else
 699               {
 700                 insn = inst;
 701                 insn <<= 16;
 702                 insn |= load_half (PC + 2);
 703                 extension = 0;
 704               }
 705             dispatch (insn, extension, 4);
 706             break;
 707
 708           /* Five byte insns.  */
 709           case 0xcd:
 710             insn = load_byte (PC);
 711             insn <<= 24;
 712             insn |= (load_half (PC + 1) << 8);
 713             insn |= load_byte (PC + 3);
 714             extension = load_byte (PC + 4);
 715             dispatch (insn, extension, 5);
 716             break;
 717
 718           case 0xdc:
 719             insn = load_byte (PC);
 720             insn <<= 24;
 721             extension = load_word (PC + 1);
 722             insn |= (extension & 0xffffff00) >> 8;
 723             extension &= 0xff;
 724             dispatch (insn, extension, 5);
 725             break;
 726
 727           /* Six byte insns.  */
 728           case 0xfc:
 729           case 0xfd:
 730             insn = (inst << 16);
 731             extension = load_word (PC + 2);
 732             insn |= ((extension & 0xffff0000) >> 16);
 733             extension &= 0xffff;
 734             dispatch (insn, extension, 6);
 735             break;
 736
 737           case 0xdd:
 738             insn = load_byte (PC) << 24;
 739             extension = load_word (PC + 1);
 740             insn |= ((extension >> 8) & 0xffffff);
 741             extension = (extension & 0xff) << 16;
 742             extension |= load_byte (PC + 5) << 8;
 743             extension |= load_byte (PC + 6);
 744             dispatch (insn, extension, 7);
 745             break;
 746
 747           case 0xfe:
 748             insn = inst << 16;
 749             extension = load_word (PC + 2);
 750             insn |= ((extension >> 16) & 0xffff);
 751             extension <<= 8;
 752             extension &= 0xffff00;
 753             extension |= load_byte (PC + 6);
 754             dispatch (insn, extension, 7);
 755             break;
 756
 757           default:
 758             abort ();
 759         }
 760     }
 761   while (!State.exception);
 762
 763 #ifdef HASH_STAT
 764   {
 765     int i;
 766     for (i = 0; i < MAX_HASH; i++)
 767       {
 768          struct hash_entry *h;
 769          h = &hash_table[i];
 770
 771          printf("hash 0x%x:\n", i);
 772
 773          while (h)
 774            {
 775              printf("h->opcode = 0x%x, count = 0x%x\n", h->opcode, h->count);
 776              h = h->next;
 777            }
 778
 779          printf("\n\n");
 780       }
 781     fflush (stdout);
 782   }
 783 #endif
 784
 785 }
 786
 787 int
 788 sim_trace (sd)
 789      SIM_DESC sd;
 790 {
 791 #ifdef DEBUG
 792   mn10300_debug = DEBUG;
 793 #endif
 794   sim_resume (sd, 0, 0);
 795   return 1;
 796 }
 797
 798 void
 799 sim_info (sd, verbose)
 800      SIM_DESC sd;
 801      int verbose;
 802 {
 803   (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_info\n");
 804 }
 805
 806 SIM_RC
 807 sim_create_inferior (sd, abfd, argv, env)
 808      SIM_DESC sd;
 809      struct _bfd *abfd;
 810      char **argv;
 811      char **env;
 812 {
 813   if (abfd != NULL)
 814     PC = bfd_get_start_address (abfd);
 815   else
 816     PC = 0;
 817   return SIM_RC_OK;
 818 }
 819
 820 void
 821 sim_set_callbacks (p)
 822      host_callback *p;
 823 {
 824   mn10300_callback = p;
 825 }
 826
 827 /* All the code for exiting, signals, etc needs to be revamped.
 828
 829    This is enough to get c-torture limping though.  */
 830
 831 void
 832 sim_stop_reason (sd, reason, sigrc)
 833      SIM_DESC sd;
 834      enum sim_stop *reason;
 835      int *sigrc;
 836 {
 837   if (State.exited)
 838     *reason = sim_exited;
 839   else
 840     *reason = sim_stopped;
 841   if (State.exception == SIGQUIT)
 842     *sigrc = 0;
 843   else
 844     *sigrc = State.exception;
 845 }
 846
 847 int
 848 sim_read (sd, addr, buffer, size)
 849      SIM_DESC sd;
 850      SIM_ADDR addr;
 851      unsigned char *buffer;
 852      int size;
 853 {
 854   int i;
 855   for (i = 0; i < size; i++)
 856     buffer[i] = load_byte (addr + i);
 857
 858   return size;
 859 }
 860
 861 void
 862 sim_do_command (sd, cmd)
 863      SIM_DESC sd;
 864      char *cmd;
 865 {
 866   (*mn10300_callback->printf_filtered) (mn10300_callback, "\"%s\" is not a valid mn10300 simulator command.\n", cmd);
 867 }
 868
 869 SIM_RC
 870 sim_load (sd, prog, abfd, from_tty)
 871      SIM_DESC sd;
 872      char *prog;
 873      bfd *abfd;
 874      int from_tty;
 875 {
 876   extern bfd *sim_load_file (); /* ??? Don't know where this should live.  */
 877   bfd *prog_bfd;
 878
 879   prog_bfd = sim_load_file (sd, myname, mn10300_callback, prog, abfd,
 880                             sim_kind == SIM_OPEN_DEBUG,
 881                             0, sim_write);
 882   if (prog_bfd == NULL)
 883     return SIM_RC_FAIL;
 884   if (abfd == NULL)
 885     bfd_close (prog_bfd);
 886   return SIM_RC_OK;
 887 }
 888 #endif  /* not WITH_COMMON */
 889
 890
 891 #if WITH_COMMON
 892
 893 /* For compatibility */
 894 SIM_DESC simulator;
 895
 896 /* These default values correspond to expected usage for the chip.  */
 897
 898 SIM_DESC
 899 sim_open (kind, cb, abfd, argv)
 900      SIM_OPEN_KIND kind;
 901      host_callback *cb;
 902      struct _bfd *abfd;
 903      char **argv;
 904 {
 905   SIM_DESC sd = sim_state_alloc (kind, cb);
 906   struct hw *hw;
 907   mn10300_callback = cb;
 908
 909   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 910
 911   /* for compatibility */
 912   simulator = sd;
 913
 914   /* FIXME: should be better way of setting up interrupts.  For
 915      moment, only support watchpoints causing a breakpoint (gdb
 916      halt). */
 917   STATE_WATCHPOINTS (sd)->pc = &(PC);
 918   STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
 919   STATE_WATCHPOINTS (sd)->interrupt_handler = NULL;
 920   STATE_WATCHPOINTS (sd)->interrupt_names = NULL;
 921
 922   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
 923     return 0;
 924
 925   /* Allocate core managed memory */
 926   sim_do_command (sd, "memory region 0,0x100000");
 927   sim_do_command (sd, "memory region 0x40000000,0x100000");
 928
 929   /* getopt will print the error message so we just have to exit if this fails.
 930      FIXME: Hmmm...  in the case of gdb we need getopt to call
 931      print_filtered.  */
 932   if (sim_parse_args (sd, argv) != SIM_RC_OK)
 933     {
 934       /* Uninstall the modules to avoid memory leaks,
 935          file descriptor leaks, etc.  */
 936       sim_module_uninstall (sd);
 937       return 0;
 938     }
 939
 940   hw = hw_tree_create (sd, "core");
 941   hw_tree_parse (hw, "/");
 942   if (STATE_VERBOSE_P (sd))
 943     hw_tree_parse (hw, "/trace? true");
 944
 945
 946   /* interrupt controller */
 947
 948   hw_tree_parse (hw, "/mn103int@0x34000100");
 949   if (STATE_VERBOSE_P (sd))
 950     hw_tree_parse (hw, "/mn103int/trace? true");
 951   hw_tree_parse (hw, "/mn103int/reg 0x34000100 0x68 0x34000200 0x8 0x3400280 0x8");
 952
 953   /* NMI input's */
 954   hw_tree_parse (hw, "/glue@0x30000000");
 955   if (STATE_VERBOSE_P (sd))
 956     hw_tree_parse (hw, "/glue@0x30000000/trace? true");
 957   hw_tree_parse (hw, "/glue@0x30000000/reg 0x30000000 16");
 958   hw_tree_parse (hw, "/glue@0x30000000 > int1 nmirq /mn103int");
 959   hw_tree_parse (hw, "/glue@0x30000000 > int2 watchdog /mn103int");
 960   hw_tree_parse (hw, "/glue@0x30000000 > int3 syserr /mn103int");
 961
 962   /* NMI output */
 963   hw_tree_parse (hw, "/mn103int > nmi int0 /glue@0x30000000");
 964
 965   /* ACK input */
 966   hw_tree_parse (hw, "/glue@0x30002000");
 967   if (STATE_VERBOSE_P (sd))
 968     hw_tree_parse (hw, "/glue@0x30002000/trace? true");
 969   hw_tree_parse (hw, "/glue@0x30002000/reg 0x30002000 4");
 970   hw_tree_parse (hw, "/glue@0x30002000 > int ack /mn103int");
 971
 972   /* LEVEL output */
 973   hw_tree_parse (hw, "/glue@0x30004000");
 974   if (STATE_VERBOSE_P (sd))
 975     hw_tree_parse (hw, "/glue@0x30004000/trace? true");
 976   hw_tree_parse (hw, "/glue@0x30004000/reg 0x30004000 4");
 977   hw_tree_parse (hw, "/mn103int > level int /glue@0x30004000");
 978
 979   /* A bunch of interrupt inputs */
 980   hw_tree_parse (hw, "/glue@0x30006000");
 981   if (STATE_VERBOSE_P (sd))
 982     hw_tree_parse (hw, "/glue@0x30006000/trace? true");
 983   hw_tree_parse (hw, "/glue@0x30006000/reg 0x30006000 16");
 984   hw_tree_parse (hw, "/glue@0x30006000 > int0 irq-0 /mn103int");
 985   hw_tree_parse (hw, "/glue@0x30006000 > int1 irq-1 /mn103int");
 986   hw_tree_parse (hw, "/glue@0x30006000 > int2 irq-2 /mn103int");
 987   hw_tree_parse (hw, "/glue@0x30006000 > int3 irq-3 /mn103int");
 988
 989
 990   /* processor interrupt device */
 991
 992   /* the device */
 993   hw_tree_parse (hw, "/mn103cpu@0x20000000");
 994   if (STATE_VERBOSE_P (sd))
 995     hw_tree_parse (hw, "/mn103cpu@0x20000000/trace? true");
 996   hw_tree_parse (hw, "/mn103cpu@0x20000000/reg 0x20000000 0x42");
 997
 998   /* DEBUG: ACK output wired upto a glue device */
 999   hw_tree_parse (hw, "/glue@0x20002000");
1000   if (STATE_VERBOSE_P (sd))
1001     hw_tree_parse (hw, "/glue@0x20002000/trace? true");
1002   hw_tree_parse (hw, "/glue@0x20002000/reg 0x20002000 4");
1003   hw_tree_parse (hw, "/mn103cpu > ack int0 /glue@0x20002000");
1004
1005   /* DEBUG: RESET/NMI/LEVEL wired up to a glue device */
1006   hw_tree_parse (hw, "/glue@0x20004000");
1007   if (STATE_VERBOSE_P (sd))
1008     hw_tree_parse (hw, "/glue@0x20004000/trace? true");
1009   hw_tree_parse (hw, "/glue@0x20004000/reg 0x20004000 12");
1010   hw_tree_parse (hw, "/glue@0x20004000 > int0 reset /mn103cpu");
1011   hw_tree_parse (hw, "/glue@0x20004000 > int1 nmi /mn103cpu");
1012   hw_tree_parse (hw, "/glue@0x20004000 > int2 level /mn103cpu");
1013
1014   /* The processor wired up to the real interrupt controller */
1015   hw_tree_parse (hw, "/mn103cpu > ack ack /mn103int");
1016   hw_tree_parse (hw, "/mn103int > level level /mn103cpu");
1017   hw_tree_parse (hw, "/mn103int > nmi nmi /mn103cpu");
1018
1019
1020   /* PAL */
1021
1022   /* the device */
1023   hw_tree_parse (hw, "/pal@0x31000000");
1024   if (STATE_VERBOSE_P (sd))
1025     hw_tree_parse (hw, "/pal@0x31000000/trace? true");
1026   hw_tree_parse (hw, "/pal@0x31000000/reg 0x31000000 64");
1027
1028   /* DEBUG: PAL wired up to a glue device */
1029   hw_tree_parse (hw, "/glue@0x31002000");
1030   if (STATE_VERBOSE_P (sd))
1031     hw_tree_parse (hw, "/glue@0x31002000/trace? true");
1032   hw_tree_parse (hw, "/glue@0x31002000/reg 0x31002000 16");
1033   hw_tree_parse (hw, "/pal@0x31000000 > countdown int0 /glue@0x31002000");
1034   hw_tree_parse (hw, "/pal@0x31000000 > timer int1 /glue@0x31002000");
1035   hw_tree_parse (hw, "/pal@0x31000000 > int int2 /glue@0x31002000");
1036   hw_tree_parse (hw, "/glue@0x31002000 > int0 int3 /glue@0x31002000");
1037   hw_tree_parse (hw, "/glue@0x31002000 > int1 int3 /glue@0x31002000");
1038   hw_tree_parse (hw, "/glue@0x31002000 > int2 int3 /glue@0x31002000");
1039
1040   /* The PAL wired up to the real interrupt controller */
1041   hw_tree_parse (hw, "/pal@0x31000000 > countdown irq-0 /mn103int");
1042   hw_tree_parse (hw, "/pal@0x31000000 > timer irq-1 /mn103int");
1043   hw_tree_parse (hw, "/pal@0x31000000 > int irq-2 /mn103int");
1044
1045
1046
1047   hw_tree_finish (hw);
1048   if (STATE_VERBOSE_P (sd))
1049     hw_tree_print (hw);
1050
1051   /* check for/establish the a reference program image */
1052   if (sim_analyze_program (sd,
1053                            (STATE_PROG_ARGV (sd) != NULL
1054                             ? *STATE_PROG_ARGV (sd)
1055                             : NULL),
1056                            abfd) != SIM_RC_OK)
1057     {
1058       sim_module_uninstall (sd);
1059       return 0;
1060     }
1061
1062   /* establish any remaining configuration options */
1063   if (sim_config (sd) != SIM_RC_OK)
1064     {
1065       sim_module_uninstall (sd);
1066       return 0;
1067     }
1068
1069   if (sim_post_argv_init (sd) != SIM_RC_OK)
1070     {
1071       /* Uninstall the modules to avoid memory leaks,
1072          file descriptor leaks, etc.  */
1073       sim_module_uninstall (sd);
1074       return 0;
1075     }
1076
1077
1078   /* set machine specific configuration */
1079 /*   STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */
1080 /*                           | PSW_CY | PSW_OV | PSW_S | PSW_Z); */
1081
1082   return sd;
1083 }
1084
1085
1086 void
1087 sim_close (sd, quitting)
1088      SIM_DESC sd;
1089      int quitting;
1090 {
1091   sim_module_uninstall (sd);
1092 }
1093
1094
1095 SIM_RC
1096 sim_create_inferior (sd, prog_bfd, argv, env)
1097      SIM_DESC sd;
1098      struct _bfd *prog_bfd;
1099      char **argv;
1100      char **env;
1101 {
1102   memset (&State, 0, sizeof (State));
1103   if (prog_bfd != NULL) {
1104     PC = bfd_get_start_address (prog_bfd);
1105   } else {
1106     PC = 0;
1107   }
1108   CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC);
1109
1110   return SIM_RC_OK;
1111 }
1112
1113 void
1114 sim_do_command (sd, cmd)
1115      SIM_DESC sd;
1116      char *cmd;
1117 {
1118   char *mm_cmd = "memory-map";
1119   char *int_cmd = "interrupt";
1120
1121   if (sim_args_command (sd, cmd) != SIM_RC_OK)
1122     {
1123       if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0))
1124         sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n");
1125       else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0)
1126         sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n");
1127       else
1128         sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
1129     }
1130 }
1131 #endif  /* WITH_COMMON */
1132
1133 /* FIXME These would more efficient to use than load_mem/store_mem,
1134    but need to be changed to use the memory map.  */
1135
1136 uint8
1137 get_byte (x)
1138      uint8 *x;
1139 {
1140   return *x;
1141 }
1142
1143 uint16
1144 get_half (x)
1145      uint8 *x;
1146 {
1147   uint8 *a = x;
1148   return (a[1] << 8) + (a[0]);
1149 }
1150
1151 uint32
1152 get_word (x)
1153       uint8 *x;
1154 {
1155   uint8 *a = x;
1156   return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]);
1157 }
1158
1159 void
1160 put_byte (addr, data)
1161      uint8 *addr;
1162      uint8 data;
1163 {
1164   uint8 *a = addr;
1165   a[0] = data;
1166 }
1167
1168 void
1169 put_half (addr, data)
1170      uint8 *addr;
1171      uint16 data;
1172 {
1173   uint8 *a = addr;
1174   a[0] = data & 0xff;
1175   a[1] = (data >> 8) & 0xff;
1176 }
1177
1178 void
1179 put_word (addr, data)
1180      uint8 *addr;
1181      uint32 data;
1182 {
1183   uint8 *a = addr;
1184   a[0] = data & 0xff;
1185   a[1] = (data >> 8) & 0xff;
1186   a[2] = (data >> 16) & 0xff;
1187   a[3] = (data >> 24) & 0xff;
1188 }
1189
1190 int
1191 sim_fetch_register (sd, rn, memory, length)
1192      SIM_DESC sd;
1193      int rn;
1194      unsigned char *memory;
1195      int length;
1196 {
1197   put_word (memory, State.regs[rn]);
1198   return -1;
1199 }
1200
1201 int
1202 sim_store_register (sd, rn, memory, length)
1203      SIM_DESC sd;
1204      int rn;
1205      unsigned char *memory;
1206      int length;
1207 {
1208   State.regs[rn] = get_word (memory);
1209   return -1;
1210 }