2 :option:::insn-bit-size:8
3 :option:::insn-specifying-widths:true
5 :model:::mn10300:mn10300:
8 // What do we do with an illegal instruction?
11 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
13 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
16 // 1000 DnDn imm8....; mov imm8,Dn (imm8 is sign extended)
17 4.0x8,2.DM1,2.DN0=DM1+IMM8:S0i:::mov
20 // start-sanitize-am33
25 signed32 immed = EXTEND8 (IMM8);
26 State.regs[REG_D0+DN0] = immed;
30 // 1000 DmDn; mov Dm,Dn (Dm != Dn, see above when Dm == Dn)
31 4.0x8,2.DM1,2.DN0!DM1:S0:::mov
34 // start-sanitize-am33
40 State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1];
44 // 1111 0001 1110 DmAn; mov Dm,An
45 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
48 // start-sanitize-am33
54 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1];
58 // 1111 0001 1101 AmDn; mov Am,Dn
59 8.0xf1+1101,2.AM1,2.DN0:D0a:::mov
62 // start-sanitize-am33
68 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1];
72 // 1001 AnAn imm8....; mov imm8,An (imm8 is zero-extended)
73 4.0x9,2.AM1,2.AN0=AM1+IMM8:S0ai:::mov
76 // start-sanitize-am33
82 State.regs[REG_A0+AN0] = IMM8;
86 // 1001 AmAn; mov Am,An (Am != An, save above when Am == An)
87 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
90 // start-sanitize-am33
96 State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1];
100 // 0011 11An; mov SP,An
101 4.0x3,11,2.AN0:S0b:::mov
104 // start-sanitize-am33
110 State.regs[REG_A0 + AN0] = State.regs[REG_SP];
114 // 1111 0010 1111 Am00; mov Am,SP
115 8.0xf2+4.0xf,2.AM1,00:D0b:::mov
118 // start-sanitize-am33
124 State.regs[REG_SP] = State.regs[REG_A0 + AM1];
128 // 1111 0010 1110 01Dn; mov PSW,Dn
129 8.0xf2+4.0xe,01,2.DN0:D0c:::mov
132 // start-sanitize-am33
138 State.regs[REG_D0 + DN0] = PSW;
142 // 1111 0010 1111 Dm11; mov Dm,PSW
143 8.0xf2+4.0xf,2.DM1,11:D0d:::mov
146 // start-sanitize-am33
152 PSW = State.regs[REG_D0 + DM1];
156 // 1111 0010 1110 00Dn; mov MDR,Dn
157 8.0xf2+4.0xe,00,2.DN0:D0e:::mov
160 // start-sanitize-am33
166 State.regs[REG_D0 + DN0] = State.regs[REG_MDR];
170 // 1111 0010 1111 Dm10; mov Dm,MDR
171 8.0xf2+4.0xf,2.DM1,10:D0f:::mov
174 // start-sanitize-am33
180 State.regs[REG_MDR] = State.regs[REG_D0 + DM1];
184 // 0111 DnAm; mov (Am),Dn
185 4.0x7,2.DN1,2.AM0:S0c:::mov
188 // start-sanitize-am33
194 State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]);
198 // 1111 1000 0000 DnAm d8......; mov (d8,Am),Dn (d8 is sign-extended)
199 8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
202 // start-sanitize-am33
208 State.regs[REG_D0 + DN1]
209 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
213 // 1111 1010 0000 DnAm d16.....; mov (d16,Am),Dn (d16 is sign-extended.)
214 8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
217 // start-sanitize-am33
223 State.regs[REG_D0 + DN1]
224 = load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B))));
228 // 1111 1100 0000 DnAm d32.....; mov (d32,Am),Dn
229 8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
232 // start-sanitize-am33
238 State.regs[REG_D0 + DN1]
239 = load_word ((State.regs[REG_A0 + AM0]
240 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
244 // 0101 10Dn d8......; mov (d8,SP),Dn (d8 is zero-extended)
245 4.0x5,10,2.DN0+8.D8:S1:::mov
248 // start-sanitize-am33
254 State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8);
258 // 1111 1010 1011 01Dn d16.....; mov (d16,SP),Dn (d16 is zero-extended.)
259 8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
262 // start-sanitize-am33
268 State.regs[REG_D0 + DN0]
269 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
273 // 1111 1010 1011 01Dn d32.....; mov (d32,SP),Dn
274 8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
277 // start-sanitize-am33
283 State.regs[REG_D0 + DN0]
284 = load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
288 // 1111 0011 00Dn DiAm; mov (Di,Am),Dn
289 8.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov
292 // start-sanitize-am33
298 State.regs[REG_D0 + DN2]
299 = load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
303 // 0011 00Dn abs16...; mov (abs16),Dn (abs16 is zero-extended)
304 4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
307 // start-sanitize-am33
313 State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B));
316 // 1111 1100 1010 01Dn abs32...; mov (abs32),Dn
317 8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
320 // start-sanitize-am33
326 State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
330 // 1111 0000 0000 AnAm; mov (Am),An
331 8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
334 // start-sanitize-am33
340 State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]);
344 // 1111 1000 0010 AnAm d8......; mov (d8,Am),An (d8 is sign-extended)
345 8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
348 // start-sanitize-am33
354 State.regs[REG_A0 + AN1]
355 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
359 // 1111 1010 0010 AnAm d16.....; mov (d16,Am),An (d16 is sign-extended.)
360 8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
363 // start-sanitize-am33
369 State.regs[REG_A0 + AN1]
370 = load_word ((State.regs[REG_A0 + AM0]
371 + EXTEND16 (FETCH16(D16A, D16B))));
375 // 1111 1100 0010 AnAm d32.....; mov (d32,Am),An
376 8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
379 // start-sanitize-am33
385 State.regs[REG_A0 + AN1]
386 = load_word ((State.regs[REG_A0 + AM0]
387 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
391 // 0101 11An d8......; mov (d8,SP),An (d8 is zero-extended)
392 4.0x5,11,2.AN0+8.D8:S1a:::mov
395 // start-sanitize-am33
401 State.regs[REG_A0 + AN0]
402 = load_word (State.regs[REG_SP] + D8);
406 // 1111 1010 1011 00An d16.....; mov (d16,SP),An (d16 is zero-extended.)
407 8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
410 // start-sanitize-am33
416 State.regs[REG_A0 + AN0]
417 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
421 // 1111 1100 1011 00An d32.....; mov (d32,SP),An
422 8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
425 // start-sanitize-am33
431 State.regs[REG_A0 + AN0]
432 = load_word (State.regs[REG_SP]
433 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
437 // 1111 0011 10An DiAm; mov (Di,Am),An
438 8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
441 // start-sanitize-am33
447 State.regs[REG_A0 + AN2]
448 = load_word ((State.regs[REG_A0 + AM0]
449 + State.regs[REG_D0 + DI]));
453 // 1111 1010 1010 00An abs16...; mov (abs16),An (abs16 is zero-extended)
454 8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
457 // start-sanitize-am33
463 State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B));
467 // 1111 1100 1010 00An abs32...; mov (abs32),An
468 8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
471 // start-sanitize-am33
477 State.regs[REG_A0 + AN0]
478 = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
482 // 1111 1000 1111 00Am d8......; mov (d8,Am),SP (d8 is sign-extended)
483 8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
486 // start-sanitize-am33
493 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
497 // 0110 DmAn; mov Dm,(An)
498 4.0x6,2.DM1,2.AN0:S0d:::mov
501 // start-sanitize-am33
507 store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
511 // 1111 1000 0001 DmAn d8......; mov Dm,(d8,An) (d8 is sign-extended)
512 8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
515 // start-sanitize-am33
521 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
522 State.regs[REG_D0 + DM1]);
526 // 1111 1010 0001 DmAn d16.....; mov Dm,(d16,An) (d16 is sign-extended.)
527 8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
530 // start-sanitize-am33
536 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
537 State.regs[REG_D0 + DM1]);
541 // 1111 1100 0001 DmAn d32.....; mov Dm,(d32,An)
542 8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
545 // start-sanitize-am33
551 store_word ((State.regs[REG_A0 + AN0]
552 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
553 State.regs[REG_D0 + DM1]);
557 // 0100 Dm10 d8......; mov Dm,(d8,SP) (d8 is zero-extended)
558 4.0x4,2.DM1,10+8.D8:S1b:::mov
561 // start-sanitize-am33
567 store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]);
571 // 1111 1010 1001 Dm01 d16.....; mov Dm,(d16,SP) (d16 is zero-extended.)
572 8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
575 // start-sanitize-am33
581 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
582 State.regs[REG_D0 + DM1]);
586 // 1111 1100 1001 Dm01 d32.....; mov Dm,(d32,SP)
587 8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
590 // start-sanitize-am33
596 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
597 State.regs[REG_D0 + DM1]);
601 // 1111 0011 01Dm DiAn; mov Dm,(Di,An)
602 8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
605 // start-sanitize-am33
611 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
612 State.regs[REG_D0 + DM2]);
616 // 0000 Dm01 abs16..., mov Dm,(abs16) (abs16 is zero-extended).
617 4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
620 // start-sanitize-am33
626 store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
630 // 1111 1100 1000 Dm01 abs32...; mov Dm,(abs32)
631 8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
634 // start-sanitize-am33
640 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
641 State.regs[REG_D0 + DM1]);
645 // 1111 0000 0001 AmAn; mov Am,(An)
646 8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
649 // start-sanitize-am33
655 store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]);
659 // 1111 1000 0011 AmAn d8......; mov Am,(d8,An) (d8 is sign-extended)
660 8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
663 // start-sanitize-am33
669 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
670 State.regs[REG_A0 + AM1]);
674 // 1111 1010 0011 AmAn d16.....; mov Am,(d16,An) (d16 is sign-extended.)
675 8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
678 // start-sanitize-am33
684 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
685 State.regs[REG_A0 + AM1]);
689 // 1111 1100 0011 AmAn d32.....; mov Am,(d32,An)
690 8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
693 // start-sanitize-am33
699 store_word ((State.regs[REG_A0 + AN0]
700 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
701 State.regs[REG_A0 + AM1]);
705 // 0100 Am11 d8......; mov Am,(d8,SP) (d8 is zero-extended)
706 4.0x4,2.AM1,11+8.D8:S1c:::mov
709 // start-sanitize-am33
715 store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]);
719 // 1111 1010 1001 Am00 d16.....; mov Am,(d16,SP) (d16 is zero-extended.)
720 8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
723 // start-sanitize-am33
729 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
730 State.regs[REG_A0 + AM1]);
734 // 1111 1100 1001 Am00 d32.....; mov Am,(d32,SP)
735 8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
738 // start-sanitize-am33
744 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
745 State.regs[REG_A0 + AM1]);
749 // 1111 0011 11Am DiAn; mov Am,(Di,An)
750 8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
753 // start-sanitize-am33
759 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
760 State.regs[REG_A0 + AM2]);
764 // 1111 1010 1000 Am00 abs16...; mov Am,(abs16) (abs16 is zero-extended)
765 8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
768 // start-sanitize-am33
774 store_word (FETCH16(IMM16A, IMM16B),
775 State.regs[REG_A0 + AM1]);
779 // 1111 1100 1000 Am00 abs32...; mov Am,(abs32)
780 8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
783 // start-sanitize-am33
789 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
790 State.regs[REG_A0 + AM1]);
794 // 1111 1000 1111 01An d8......; mov SP,(d8,An) (d8 is sign-extended)
795 8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
798 // start-sanitize-am33
804 store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8),
809 // 0010 11Dn imm16...; mov imm16,Dn (imm16 is sign-extended)
810 4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
813 // start-sanitize-am33
821 value = EXTEND16 (FETCH16(IMM16A, IMM16B));
822 State.regs[REG_D0 + DN0] = value;
826 // 1111 1100 1100 11Dn imm32...; mov imm32,Dn
827 8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
830 // start-sanitize-am33
838 value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
839 State.regs[REG_D0 + DN0] = value;
843 // 0010 01An imm16...; mov imm16,An (imm16 is zero-extended)
844 4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
847 // start-sanitize-am33
855 value = FETCH16(IMM16A, IMM16B);
856 State.regs[REG_A0 + AN0] = value;
860 // 1111 1100 1101 11An imm32...; mov imm32,An
861 8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
864 // start-sanitize-am33
870 State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
874 // 1111 0000 0100 DnAm; movbu (Am),Dn
875 8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
878 // start-sanitize-am33
884 State.regs[REG_D0 + DN1]
885 = load_byte (State.regs[REG_A0 + AM0]);
889 // 1111 1000 0100 DnAm d8......; movbu (d8,Am),Dn (d8 is sign-extended)
890 8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
893 // start-sanitize-am33
899 State.regs[REG_D0 + DN1]
900 = load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
904 // 1111 1010 0100 DnAm d16.....; movbu (d16,Am),Dn (d16 is sign-extended.)
905 8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
908 // start-sanitize-am33
914 State.regs[REG_D0 + DN1]
915 = load_byte ((State.regs[REG_A0 + AM0]
916 + EXTEND16 (FETCH16(D16A, D16B))));
920 // 1111 1100 0100 DnAm d32.....; movbu (d32,Am),Dn
921 8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
924 // start-sanitize-am33
930 State.regs[REG_D0 + DN1]
931 = load_byte ((State.regs[REG_A0 + AM0]
932 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
936 // 1111 1000 1011 10Dn d8......; movbu (d8,SP),Dn (d8 is zero-extended)
937 8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
940 // start-sanitize-am33
946 State.regs[REG_D0 + DN0]
947 = load_byte ((State.regs[REG_SP] + (D8)));
951 // 1111 1010 1011 10Dn d16.....; movbu (d16,SP),Dn (d16 is zero-extended.)
952 8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
955 // start-sanitize-am33
961 State.regs[REG_D0 + DN0]
962 = load_byte ((State.regs[REG_SP]
963 + FETCH16(IMM16A, IMM16B)));
967 // 1111 1100 1011 10Dn d32.....; movbu (d32,SP),Dn
968 8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
971 // start-sanitize-am33
977 State.regs[REG_D0 + DN0]
978 = load_byte (State.regs[REG_SP]
979 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
983 // 1111 0100 00Dn DiAm; movbu (Di,Am),Dn
984 8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
987 // start-sanitize-am33
993 State.regs[REG_D0 + DN2]
994 = load_byte ((State.regs[REG_A0 + AM0]
995 + State.regs[REG_D0 + DI]));
999 // 0011 01Dn abs16...; movbu (abs16),Dn (abs16 is zero-extended)
1000 4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
1003 // start-sanitize-am33
1005 // end-sanitize-am33
1009 State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B));
1013 // 1111 1100 1010 10Dn abs32...; movbu (abs32),Dn
1014 8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
1017 // start-sanitize-am33
1019 // end-sanitize-am33
1023 State.regs[REG_D0 + DN0]
1024 = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1028 // 1111 0000 0101 DmAn; movbu Dm,(An)
1029 8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
1032 // start-sanitize-am33
1034 // end-sanitize-am33
1038 store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
1042 // 1111 1000 0101 DmAn d8......; movbu Dm,(d8,An) (d8 is sign-extended)
1043 8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
1046 // start-sanitize-am33
1048 // end-sanitize-am33
1052 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1053 State.regs[REG_D0 + DM1]);
1057 // 1111 1010 0101 DmAn d16.....; movbu Dm,(d16,An) (d16 is sign-extended.)
1058 8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
1061 // start-sanitize-am33
1063 // end-sanitize-am33
1067 store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1068 State.regs[REG_D0 + DM1]);
1072 // 1111 1100 0101 DmAn d32.....; movbu Dm,(d32,An)
1073 8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
1076 // start-sanitize-am33
1078 // end-sanitize-am33
1082 store_byte ((State.regs[REG_A0 + AN0]
1083 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1084 State.regs[REG_D0 + DM1]);
1088 // 1111 1000 1001 Dm10 d8......; movbu Dm,(d8,SP) (d8 is zero-extended)
1089 8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
1092 // start-sanitize-am33
1094 // end-sanitize-am33
1098 store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]);
1102 // 1111 1010 1001 Dm10 d16.....; movbu Dm,(d16,SP) (d16 is zero-extended.)
1103 8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
1106 // start-sanitize-am33
1108 // end-sanitize-am33
1112 store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1113 State.regs[REG_D0 + DM1]);
1117 // 1111 1100 1001 Dm10 d32.....; movbu Dm,(d32,SP)
1118 8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
1121 // start-sanitize-am33
1123 // end-sanitize-am33
1127 store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1128 State.regs[REG_D0 + DM1]);
1132 // 1111 0100 01Dm DiAn; movbu Dm,(Di,An)
1133 8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
1136 // start-sanitize-am33
1138 // end-sanitize-am33
1142 store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1143 State.regs[REG_D0 + DM2]);
1147 // 0000 Dm10 abs16...; movbu Dm,(abs16) (abs16 is zero-extended)
1148 4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
1151 // start-sanitize-am33
1153 // end-sanitize-am33
1157 store_byte (FETCH16(IMM16A, IMM16B),
1158 State.regs[REG_D0 + DM1]);
1162 // 1111 1100 1000 Dm10 abs32...; movbu Dm,(abs32)
1163 8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
1166 // start-sanitize-am33
1168 // end-sanitize-am33
1172 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1173 State.regs[REG_D0 + DM1]);
1177 // 1111 0000 0110 DnAm; movhu (Am),Dn
1178 8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
1181 // start-sanitize-am33
1183 // end-sanitize-am33
1187 State.regs[REG_D0 + DN1]
1188 = load_half (State.regs[REG_A0 + AM0]);
1192 // 1111 1000 0110 DnAm d8......; movhu (d8,Am),Dn (d8 is sign-extended)
1193 8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
1196 // start-sanitize-am33
1198 // end-sanitize-am33
1202 State.regs[REG_D0 + DN1]
1203 = load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
1207 // 1111 1010 0110 DnAm d16.....; movhu (d16,Am),Dn (d16 is sign-extended.)
1208 8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
1211 // start-sanitize-am33
1213 // end-sanitize-am33
1217 State.regs[REG_D0 + DN1]
1218 = load_half ((State.regs[REG_A0 + AM0]
1219 + EXTEND16 (FETCH16(D16A, D16B))));
1223 // 1111 1100 0110 DnAm d32.....; movhu (d32,Am),Dn
1224 8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
1227 // start-sanitize-am33
1229 // end-sanitize-am33
1233 State.regs[REG_D0 + DN1]
1234 = load_half ((State.regs[REG_A0 + AM0]
1235 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
1239 // 1111 1000 1011 11Dn d8.....; movhu (d8,SP),Dn (d8 is zero-extended)
1240 8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
1243 // start-sanitize-am33
1245 // end-sanitize-am33
1249 State.regs[REG_D0 + DN0]
1250 = load_half ((State.regs[REG_SP] + (D8)));
1254 // 1111 1010 1011 11Dn d16.....; movhu (d16,SP),Dn (d16 is zero-extended.)
1255 8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
1258 // start-sanitize-am33
1260 // end-sanitize-am33
1264 State.regs[REG_D0 + DN0]
1265 = load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)));
1269 // 1111 1100 1011 11Dn d32.....; movhu (d32,SP),Dn
1270 8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
1273 // start-sanitize-am33
1275 // end-sanitize-am33
1279 State.regs[REG_D0 + DN0]
1280 = load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1284 // 1111 0100 10Dn DiAm; movhu (Di,Am),Dn
1285 8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
1288 // start-sanitize-am33
1290 // end-sanitize-am33
1294 State.regs[REG_D0 + DN2]
1295 = load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
1299 // 0011 10Dn abs16...; movhu (abs16),Dn (abs16 is zero-extended)
1300 4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
1303 // start-sanitize-am33
1305 // end-sanitize-am33
1309 State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B));
1313 // 1111 1100 1010 11Dn abs32...; movhu (abs32),Dn
1314 8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
1317 // start-sanitize-am33
1319 // end-sanitize-am33
1323 State.regs[REG_D0 + DN0]
1324 = load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1328 // 1111 0000 0111 DmAn; movhu Dm,(An)
1329 8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
1332 // start-sanitize-am33
1334 // end-sanitize-am33
1338 store_half (State.regs[REG_A0 + AN0],
1339 State.regs[REG_D0 + DM1]);
1343 // 1111 1000 0111 DmAn d8......; movhu Dm,(d8,An) (d8 is sign-extended)
1344 8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
1347 // start-sanitize-am33
1349 // end-sanitize-am33
1353 store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1354 State.regs[REG_D0 + DM1]);
1358 // 1111 1010 0111 DnAm d16.....; movhu Dm,(d16,An) (d16 is sign-extended.)
1359 8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
1362 // start-sanitize-am33
1364 // end-sanitize-am33
1368 store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1369 State.regs[REG_D0 + DM1]);
1373 // 1111 1100 0111 DmAn d32.....; movhu Dm,(d32,An)
1374 8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
1377 // start-sanitize-am33
1379 // end-sanitize-am33
1383 store_half ((State.regs[REG_A0 + AN0]
1384 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1385 State.regs[REG_D0 + DM1]);
1389 // 1111 1000 1001 Dm11 d8....; movhu Dm,(d8,SP) (d8 is zero-extended)
1390 8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
1393 // start-sanitize-am33
1395 // end-sanitize-am33
1399 store_half (State.regs[REG_SP] + (D8),
1400 State.regs[REG_D0 + DM1]);
1404 // 1111 1010 1001 Dm11 d16.....; movhu Dm,(d16,SP) (d16 is zero-extended.)
1405 8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
1408 // start-sanitize-am33
1410 // end-sanitize-am33
1414 store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1415 State.regs[REG_D0 + DM1]);
1419 // 1111 1100 1001 Dm11 d32.....; movhu Dm,(d32,SP)
1420 8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
1423 // start-sanitize-am33
1425 // end-sanitize-am33
1429 store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1430 State.regs[REG_D0 + DM1]);
1434 // 1111 0100 11Dm DiAn; movhu Dm,(Di,An)
1435 8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
1438 // start-sanitize-am33
1440 // end-sanitize-am33
1444 store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1445 State.regs[REG_D0 + DM2]);
1449 // 0000 Dm11 abs16...; movhu Dm,(abs16) (abs16 is zero-extended)
1450 4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
1453 // start-sanitize-am33
1455 // end-sanitize-am33
1459 store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
1463 // 1111 1100 1000 Dm11 abs32...; movhu Dm,(abs32)
1464 8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
1467 // start-sanitize-am33
1469 // end-sanitize-am33
1473 store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1474 State.regs[REG_D0 + DM1]);
1478 // 1111 0010 1101 00Dn; ext Dn
1479 8.0xf2+4.0xd,00,2.DN0:D0:::ext
1482 // start-sanitize-am33
1484 // end-sanitize-am33
1488 if (State.regs[REG_D0 + DN0] & 0x80000000)
1489 State.regs[REG_MDR] = -1;
1491 State.regs[REG_MDR] = 0;
1495 // 0001 00Dn; extb Dn
1496 4.0x1,00,2.DN0:S0:::extb
1499 // start-sanitize-am33
1501 // end-sanitize-am33
1505 State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]);
1509 // 0001 01Dn; extbu Dn
1510 4.0x1,01,2.DN0:S0:::extbu
1513 // start-sanitize-am33
1515 // end-sanitize-am33
1519 State.regs[REG_D0 + DN0] &= 0xff;
1523 // 0001 10Dn; exth Dn
1524 4.0x1,10,2.DN0:S0:::exth
1527 // start-sanitize-am33
1529 // end-sanitize-am33
1533 State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]);
1537 // 0001 11Dn; exthu Dn
1538 4.0x1,11,2.DN0:S0:::exthu
1541 // start-sanitize-am33
1543 // end-sanitize-am33
1547 State.regs[REG_D0 + DN0] &= 0xffff;
1551 // 0000 Dn00; clr Dn
1552 4.0x0,2.DN1,00:S0:::clr
1555 // start-sanitize-am33
1557 // end-sanitize-am33
1561 State.regs[REG_D0 + DN1] = 0;
1564 PSW &= ~(PSW_V | PSW_C | PSW_N);
1568 // 1110 DmDn; add Dm,Dn
1569 4.0xe,2.DM1,2.DN0:S0:::add
1572 // start-sanitize-am33
1574 // end-sanitize-am33
1578 genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1581 // 1111 0001 0110 DmAn; add Dm,An
1582 8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
1585 // start-sanitize-am33
1587 // end-sanitize-am33
1591 genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1595 // 1111 0001 0101 AmDn; add Am,Dn
1596 8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
1599 // start-sanitize-am33
1601 // end-sanitize-am33
1605 genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1609 // 1111 0001 0111 AmAn; add Am,An
1610 8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
1613 // start-sanitize-am33
1615 // end-sanitize-am33
1619 genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1623 // 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended)
1624 4.0x2,10,2.DN0+8.IMM8:S1:::add
1627 // start-sanitize-am33
1629 // end-sanitize-am33
1633 genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
1637 // 1111 1010 1100 00Dn imm16...; add imm16,Dn
1638 8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
1641 // start-sanitize-am33
1643 // end-sanitize-am33
1647 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
1651 // 1111 1100 1100 00Dn imm32...; add imm32,Dn
1652 8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
1655 // start-sanitize-am33
1657 // end-sanitize-am33
1661 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1665 // 0010 00An imm8....; add imm8,An (imm8 is sign-extended)
1666 4.0x2,00,2.AN0+8.IMM8:S1a:::add
1669 // start-sanitize-am33
1671 // end-sanitize-am33
1675 genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
1679 // 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.)
1680 8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
1683 // start-sanitize-am33
1685 // end-sanitize-am33
1689 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
1693 // 1111 1100 1101 00An imm32...; add imm32,An
1694 8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
1697 // start-sanitize-am33
1699 // end-sanitize-am33
1703 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1707 // 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.)
1708 8.0xf8+8.0xfe+8.IMM8:D1:::add
1711 // start-sanitize-am33
1713 // end-sanitize-am33
1718 // Note: no PSW changes.
1720 imm = EXTEND8 (IMM8);
1721 State.regs[REG_SP] += imm;
1725 // 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.)
1726 8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
1729 // start-sanitize-am33
1731 // end-sanitize-am33
1736 // Note: no PSW changes.
1738 imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
1739 State.regs[REG_SP] += imm;
1743 // 1111 1100 1111 1110 imm32...; add imm32,SP
1744 8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
1747 // start-sanitize-am33
1749 // end-sanitize-am33
1754 // Note: no PSW changes.
1756 imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1757 State.regs[REG_SP] += imm;
1761 // 1111 0001 0100 DmDn; addc Dm,Dn
1762 8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
1765 // start-sanitize-am33
1767 // end-sanitize-am33
1771 unsigned long reg1, reg2, sum;
1774 reg1 = State.regs[REG_D0 + DM1];
1775 reg2 = State.regs[REG_D0 + DN0];
1776 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
1777 State.regs[REG_D0 + DN0] = sum;
1780 n = (sum & 0x80000000);
1781 c = (sum < reg1) || (sum < reg2);
1782 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1783 && (reg2 & 0x80000000) != (sum & 0x80000000));
1785 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1786 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1787 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1791 // 1111 0001 0000 DmDn; sub Dm,Dn
1792 8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
1795 // start-sanitize-am33
1797 // end-sanitize-am33
1801 genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1804 // 1111 0001 0010 DmAn; sub DmAn
1805 8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
1808 // start-sanitize-am33
1810 // end-sanitize-am33
1814 genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1818 // 1111 0001 0001 AmDn; sub AmDn
1819 8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
1822 // start-sanitize-am33
1824 // end-sanitize-am33
1828 genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1832 // 1111 0001 0011 AmAn; sub Am,An
1833 8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
1836 // start-sanitize-am33
1838 // end-sanitize-am33
1842 genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1846 // 1111 1100 1100 01Dn imm32...; sub imm32,Dn
1847 8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
1850 // start-sanitize-am33
1852 // end-sanitize-am33
1856 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1860 // 1111 1100 1101 01An imm32...; sub imm32,An
1861 8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
1864 // start-sanitize-am33
1866 // end-sanitize-am33
1870 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1874 // 1111 0001 1000 DmDn; subc Dm,Dn
1875 8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
1878 // start-sanitize-am33
1880 // end-sanitize-am33
1884 unsigned long reg1, reg2, difference;
1887 reg1 = State.regs[REG_D0 + DM1];
1888 reg2 = State.regs[REG_D0 + DN0];
1889 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
1890 State.regs[REG_D0 + DN0] = difference;
1892 z = (difference == 0);
1893 n = (difference & 0x80000000);
1895 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1896 && (reg2 & 0x80000000) != (difference & 0x80000000));
1898 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1899 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1900 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1904 // 1111 0010 0100 DmDn; mul Dm,Dn
1905 8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
1908 // start-sanitize-am33
1910 // end-sanitize-am33
1913 unsigned long long temp;
1917 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
1918 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
1919 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1920 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1921 z = (State.regs[REG_D0 + DN0] == 0);
1922 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1923 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1924 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1928 // 1111 0010 0101 DmDn; mulu Dm,Dn
1929 8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
1932 // start-sanitize-am33
1934 // end-sanitize-am33
1937 unsigned long long temp;
1941 temp = ((unsigned64)State.regs[REG_D0 + DN0]
1942 * (unsigned64)State.regs[REG_D0 + DM1]);
1943 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1944 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1945 z = (State.regs[REG_D0 + DN0] == 0);
1946 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1947 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1948 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1952 // 1111 0010 0110 DmDn; div Dm,Dn
1953 8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
1956 // start-sanitize-am33
1958 // end-sanitize-am33
1965 temp = State.regs[REG_MDR];
1967 temp |= State.regs[REG_D0 + DN0];
1968 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + DM1];
1969 temp /= (long)State.regs[REG_D0 + DM1];
1970 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1971 z = (State.regs[REG_D0 + DN0] == 0);
1972 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1973 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1974 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1978 // 1111 0010 0111 DmDn; divu Dm,Dn
1979 8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
1982 // start-sanitize-am33
1984 // end-sanitize-am33
1987 unsigned long long temp;
1991 temp = State.regs[REG_MDR];
1993 temp |= State.regs[REG_D0 + DN0];
1994 State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
1995 temp /= State.regs[REG_D0 + DM1];
1996 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1997 z = (State.regs[REG_D0 + DN0] == 0);
1998 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1999 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2000 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2004 // 0100 Dn00; inc Dn
2005 4.0x4,2.DN1,00:S0:::inc
2008 // start-sanitize-am33
2010 // end-sanitize-am33
2017 genericAdd(imm, REG_D0 + DN1);
2022 4.0x4,2.AN1,01:S0a:::inc
2025 // start-sanitize-am33
2027 // end-sanitize-am33
2031 State.regs[REG_A0 + AN1] += 1;
2035 // 0101 00An; inc4 An
2036 4.0x5,00,2.AN0:S0:::inc4
2039 // start-sanitize-am33
2041 // end-sanitize-am33
2045 State.regs[REG_A0 + AN0] += 4;
2049 // 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.)
2050 4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
2053 // start-sanitize-am33
2055 // end-sanitize-am33
2059 genericCmp(EXTEND8 (IMM8), State.regs[REG_D0 + DN0]);
2063 // 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn)
2064 4.0xa,2.DM1,2.DN0!DM1:S0:::cmp
2067 // start-sanitize-am33
2069 // end-sanitize-am33
2073 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
2077 // 1111 0001 1010 DmAn; cmp Dm,An
2078 8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
2081 // start-sanitize-am33
2083 // end-sanitize-am33
2087 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
2091 // 1111 0001 1001 AmDn; cmp Am,Dn
2092 8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
2095 // start-sanitize-am33
2097 // end-sanitize-am33
2101 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
2105 // 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.)
2106 4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
2109 // start-sanitize-am33
2111 // end-sanitize-am33
2116 State.regs[REG_A0 + AN0]);
2120 // 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn)
2121 4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
2124 // start-sanitize-am33
2126 // end-sanitize-am33
2130 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
2134 // 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.)
2135 8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
2138 // start-sanitize-am33
2140 // end-sanitize-am33
2144 genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
2145 State.regs[REG_D0 + DN0]);
2149 // 1111 1100 1100 10Dn imm32...; cmp imm32,Dn
2150 8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
2153 // start-sanitize-am33
2155 // end-sanitize-am33
2159 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2160 State.regs[REG_D0 + DN0]);
2164 // 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.)
2165 8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
2168 // start-sanitize-am33
2170 // end-sanitize-am33
2174 genericCmp(FETCH16(IMM16A, IMM16B),
2175 State.regs[REG_A0 + AN0]);
2179 // 1111 1100 1101 10An imm32...; cmp imm32,An
2180 8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
2183 // start-sanitize-am33
2185 // end-sanitize-am33
2189 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2190 State.regs[REG_A0 + AN0]);
2194 // 1111 0010 0000 DmDn; and Dm,Dn
2195 8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
2198 // start-sanitize-am33
2200 // end-sanitize-am33
2206 State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
2207 z = (State.regs[REG_D0 + DN0] == 0);
2208 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2209 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2210 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2214 // 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.)
2215 8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
2218 // start-sanitize-am33
2220 // end-sanitize-am33
2226 State.regs[REG_D0 + DN0] &= IMM8;
2227 z = (State.regs[REG_D0 + DN0] == 0);
2228 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2229 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2230 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2234 // 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.)
2235 8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
2238 // start-sanitize-am33
2240 // end-sanitize-am33
2246 State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
2247 z = (State.regs[REG_D0 + DN0] == 0);
2248 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2249 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2250 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2254 // 1111 1100 1110 00Dn imm32...; and imm32,Dn
2255 8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
2258 // start-sanitize-am33
2260 // end-sanitize-am33
2266 State.regs[REG_D0 + DN0]
2267 &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
2268 z = (State.regs[REG_D0 + DN0] == 0);
2269 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2270 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2271 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2275 // 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.)
2276 8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
2279 // start-sanitize-am33
2281 // end-sanitize-am33
2285 PSW &= FETCH16(IMM16A, IMM16B);
2290 // 1111 0010 0001 DmDn; or DmDn
2291 8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
2294 // start-sanitize-am33
2296 // end-sanitize-am33
2300 genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2304 // 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n
2305 8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
2308 // start-sanitize-am33
2310 // end-sanitize-am33
2314 genericOr(IMM8, REG_D0 + DN0);
2318 // 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.)
2319 8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
2322 // start-sanitize-am33
2324 // end-sanitize-am33
2328 genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2332 // 1111 1100 1110 01Dn imm32...; or imm32,Dn
2333 8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
2336 // start-sanitize-am33
2338 // end-sanitize-am33
2342 genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2346 // 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.)
2347 8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
2350 // start-sanitize-am33
2352 // end-sanitize-am33
2356 PSW |= FETCH16(IMM16A, IMM16B);
2360 // 1111 0010 0010 DmDn; xor Dm,Dn
2361 8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
2364 // start-sanitize-am33
2366 // end-sanitize-am33
2370 genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2374 // 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.)
2375 8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
2378 // start-sanitize-am33
2380 // end-sanitize-am33
2384 genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2388 // 1111 1100 1110 10Dn imm32...; xor imm32,Dn
2389 8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
2392 // start-sanitize-am33
2394 // end-sanitize-am33
2398 genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2402 // 1111 0010 0011 00Dn; not Dn
2403 8.0xf2+4.0x3,00,2.DN0:D0:::not
2406 // start-sanitize-am33
2408 // end-sanitize-am33
2414 State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
2415 z = (State.regs[REG_D0 + DN0] == 0);
2416 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2417 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2418 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2422 // 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.)
2423 8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
2426 // start-sanitize-am33
2428 // end-sanitize-am33
2432 genericBtst(IMM8, State.regs[REG_D0 + DN0]);
2436 // 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.)
2437 8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
2440 // start-sanitize-am33
2442 // end-sanitize-am33
2446 genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
2450 // 1111 1100 1110 11Dn imm32...; btst imm32,Dn
2451 8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
2454 // start-sanitize-am33
2456 // end-sanitize-am33
2460 genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2461 State.regs[REG_D0 + DN0]);
2465 // 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2466 8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
2469 // start-sanitize-am33
2471 // end-sanitize-am33
2476 load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
2480 // 1111 1010 1111 10An d8...... imm8....;
2481 // btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte)
2482 8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
2485 // start-sanitize-am33
2487 // end-sanitize-am33
2492 load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
2496 // 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte)
2497 8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
2500 // start-sanitize-am33
2502 // end-sanitize-am33
2509 temp = load_byte (State.regs[REG_A0 + AN0]);
2510 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2511 temp |= State.regs[REG_D0 + DM1];
2512 store_byte (State.regs[REG_A0 + AN0], temp);
2513 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2514 PSW |= (z ? PSW_Z : 0);
2518 // 1111 1110 0000 0000 abs32... imm8....;
2519 // bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2520 8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
2523 // start-sanitize-am33
2525 // end-sanitize-am33
2532 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2533 z = (temp & IMM8) == 0;
2535 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2536 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2537 PSW |= (z ? PSW_Z : 0);
2541 // 1111 1010 1111 00AnAn d8...... imm8....;
2542 // bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2543 8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
2546 // start-sanitize-am33
2548 // end-sanitize-am33
2555 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2556 z = (temp & (IMM8)) == 0;
2558 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2559 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2560 PSW |= (z ? PSW_Z : 0);
2564 // 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte)
2565 8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
2568 // start-sanitize-am33
2570 // end-sanitize-am33
2577 temp = load_byte (State.regs[REG_A0 + AN0]);
2578 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2579 temp = temp & ~State.regs[REG_D0 + DM1];
2580 store_byte (State.regs[REG_A0 + AN0], temp);
2581 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2582 PSW |= (z ? PSW_Z : 0);
2586 // 1111 1110 0000 0001 abs32... imm8....;
2587 // bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2588 8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
2591 // start-sanitize-am33
2593 // end-sanitize-am33
2600 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2601 z = (temp & IMM8) == 0;
2602 temp = temp & ~(IMM8);
2603 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2604 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2605 PSW |= (z ? PSW_Z : 0);
2609 // 1111 1010 1111 01An d8...... imm8....;
2610 // bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2611 8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
2614 // start-sanitize-am33
2616 // end-sanitize-am33
2623 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2624 z = (temp & (IMM8)) == 0;
2625 temp = temp & ~(IMM8);
2626 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2627 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2628 PSW |= (z ? PSW_Z : 0);
2632 // 1111 0010 1011 DmDn; asr Dm,Dn
2633 8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
2636 // start-sanitize-am33
2638 // end-sanitize-am33
2645 temp = State.regs[REG_D0 + DN0];
2647 temp >>= State.regs[REG_D0 + DM1];
2648 State.regs[REG_D0 + DN0] = temp;
2649 z = (State.regs[REG_D0 + DN0] == 0);
2650 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2651 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2652 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2656 // 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.)
2657 8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
2660 // start-sanitize-am33
2662 // end-sanitize-am33
2669 temp = State.regs[REG_D0 + DN0];
2672 State.regs[REG_D0 + DN0] = temp;
2673 z = (State.regs[REG_D0 + DN0] == 0);
2674 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2675 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2676 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2680 // 1111 0010 1010 DmDn; lsr Dm,Dn
2681 8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
2684 // start-sanitize-am33
2686 // end-sanitize-am33
2692 c = State.regs[REG_D0 + DN0] & 1;
2693 State.regs[REG_D0 + DN0]
2694 >>= State.regs[REG_D0 + DM1];
2695 z = (State.regs[REG_D0 + DN0] == 0);
2696 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2697 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2698 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2702 // 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.)
2703 8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
2706 // start-sanitize-am33
2708 // end-sanitize-am33
2714 c = State.regs[REG_D0 + DN0] & 1;
2715 State.regs[REG_D0 + DN0] >>= IMM8;
2716 z = (State.regs[REG_D0 + DN0] == 0);
2717 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2718 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2719 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2723 // 1111 0010 1001 DmDn; asl Dm,Dn
2724 8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
2727 // start-sanitize-am33
2729 // end-sanitize-am33
2735 State.regs[REG_D0 + DN0]
2736 <<= State.regs[REG_D0 + DM1];
2737 z = (State.regs[REG_D0 + DN0] == 0);
2738 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2739 PSW &= ~(PSW_Z | PSW_N);
2740 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2744 // 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.)
2745 8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
2748 // start-sanitize-am33
2750 // end-sanitize-am33
2756 State.regs[REG_D0 + DN0] <<= IMM8;
2757 z = (State.regs[REG_D0 + DN0] == 0);
2758 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2759 PSW &= ~(PSW_Z | PSW_N);
2760 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2764 // 0101 01Dn; als2 Dn
2765 4.0x5,01,2.DN0:S0:::asl2
2768 // start-sanitize-am33
2770 // end-sanitize-am33
2776 State.regs[REG_D0 + DN0] <<= 2;
2777 z = (State.regs[REG_D0 + DN0] == 0);
2778 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2779 PSW &= ~(PSW_Z | PSW_N);
2780 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2784 // 1111 0010 1000 01Dn; ror Dn
2785 8.0xf2+4.0x8,01,2.DN0:D0:::ror
2788 // start-sanitize-am33
2790 // end-sanitize-am33
2793 unsigned long value;
2797 value = State.regs[REG_D0 + DN0];
2801 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2802 State.regs[REG_D0 + DN0] = value;
2804 n = (value & 0x80000000) != 0;
2805 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2806 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2810 // 1111 0010 1000 00Dn; rol Dn
2811 8.0xf2+4.0x8,00,2.DN0:D0:::rol
2814 // start-sanitize-am33
2816 // end-sanitize-am33
2818 // handle ror above, too.
2820 unsigned long value;
2824 value = State.regs[REG_D0 + DN0];
2825 c = (value & 0x80000000) ? 1 : 0;
2828 value |= ((PSW & PSW_C) != 0);
2829 State.regs[REG_D0 + DN0] = value;
2831 n = (value & 0x80000000) != 0;
2832 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2833 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2837 // 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended)
2838 8.0xc8+8.D8:S1:::beq
2841 // start-sanitize-am33
2843 // end-sanitize-am33
2849 State.regs[REG_PC] += EXTEND8 (D8);
2855 // 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended)
2856 8.0xc9+8.D8:S1:::bne
2859 // start-sanitize-am33
2861 // end-sanitize-am33
2867 State.regs[REG_PC] += EXTEND8 (D8);
2873 // 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended)
2874 8.0xc1+8.D8:S1:::bgt
2877 // start-sanitize-am33
2879 // end-sanitize-am33
2884 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2886 State.regs[REG_PC] += EXTEND8 (D8);
2892 // 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended)
2893 8.0xc2+8.D8:S1:::bge
2896 // start-sanitize-am33
2898 // end-sanitize-am33
2902 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2904 State.regs[REG_PC] += EXTEND8 (D8);
2910 // 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended)
2911 8.0xc3+8.D8:S1:::ble
2914 // start-sanitize-am33
2916 // end-sanitize-am33
2921 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2923 State.regs[REG_PC] += EXTEND8 (D8);
2929 // 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended)
2930 8.0xc0+8.D8:S1:::blt
2933 // start-sanitize-am33
2935 // end-sanitize-am33
2939 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2941 State.regs[REG_PC] += EXTEND8 (D8);
2947 // 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended)
2948 8.0xc5+8.D8:S1:::bhi
2951 // start-sanitize-am33
2953 // end-sanitize-am33
2957 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2959 State.regs[REG_PC] += EXTEND8 (D8);
2965 // 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended)
2966 8.0xc6+8.D8:S1:::bcc
2969 // start-sanitize-am33
2971 // end-sanitize-am33
2977 State.regs[REG_PC] += EXTEND8 (D8);
2983 // 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended)
2984 8.0xc7+8.D8:S1:::bls
2987 // start-sanitize-am33
2989 // end-sanitize-am33
2993 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2995 State.regs[REG_PC] += EXTEND8 (D8);
3001 // 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended)
3002 8.0xc4+8.D8:S1:::bcs
3005 // start-sanitize-am33
3007 // end-sanitize-am33
3013 State.regs[REG_PC] += EXTEND8 (D8);
3019 // 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended)
3020 8.0xf8+8.0xe8+8.D8:D1:::bvc
3023 // start-sanitize-am33
3025 // end-sanitize-am33
3031 State.regs[REG_PC] += EXTEND8 (D8);
3037 // 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended)
3038 8.0xf8+8.0xe9+8.D8:D1:::bvs
3041 // start-sanitize-am33
3043 // end-sanitize-am33
3049 State.regs[REG_PC] += EXTEND8 (D8);
3055 // 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended)
3056 8.0xf8+8.0xea+8.D8:D1:::bnc
3059 // start-sanitize-am33
3061 // end-sanitize-am33
3067 State.regs[REG_PC] += EXTEND8 (D8);
3073 // 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended)
3074 8.0xf8+8.0xeb+8.D8:D1:::bns
3077 // start-sanitize-am33
3079 // end-sanitize-am33
3085 State.regs[REG_PC] += EXTEND8 (D8);
3091 // 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended)
3092 8.0xca+8.D8:S1:::bra
3095 // start-sanitize-am33
3097 // end-sanitize-am33
3101 State.regs[REG_PC] += EXTEND8 (D8);
3110 // start-sanitize-am33
3112 // end-sanitize-am33
3118 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3128 // start-sanitize-am33
3130 // end-sanitize-am33
3136 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3146 // start-sanitize-am33
3148 // end-sanitize-am33
3153 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
3155 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3165 // start-sanitize-am33
3167 // end-sanitize-am33
3171 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3173 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3183 // start-sanitize-am33
3185 // end-sanitize-am33
3190 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3192 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3202 // start-sanitize-am33
3204 // end-sanitize-am33
3208 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
3210 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3220 // start-sanitize-am33
3222 // end-sanitize-am33
3226 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
3228 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3238 // start-sanitize-am33
3240 // end-sanitize-am33
3246 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3256 // start-sanitize-am33
3258 // end-sanitize-am33
3262 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
3264 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3274 // start-sanitize-am33
3276 // end-sanitize-am33
3282 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3292 // start-sanitize-am33
3294 // end-sanitize-am33
3298 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3307 // start-sanitize-am33
3309 // end-sanitize-am33
3313 State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
3314 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
3318 // 1111 0000 1111 01An; jmp (An)
3319 8.0xf0+4.0xf,01,2.AN0:D0:::jmp
3322 // start-sanitize-am33
3324 // end-sanitize-am33
3327 PC = State.regs[REG_A0 + AN0];
3332 // 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.)
3333 8.0xcc+8.D16A+8.D16B:S2:::jmp
3336 // start-sanitize-am33
3338 // end-sanitize-am33
3341 PC = cia + EXTEND16(FETCH16(D16A, D16B));
3346 // 1101 1100 d32........; jmp (d32, PC)
3347 8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
3350 // start-sanitize-am33
3352 // end-sanitize-am33
3355 PC = cia + FETCH32(D32A, D32B, D32C, D32D);
3360 // 1111 0000 1111 00An; calls (An)
3361 8.0xf0+4.0xf,00,2.AN0:D0:::calls
3364 // start-sanitize-am33
3366 // end-sanitize-am33
3369 unsigned int next_pc, sp;
3372 sp = State.regs[REG_SP];
3373 next_pc = State.regs[REG_PC] + 2;
3374 store_word(sp, next_pc);
3375 State.regs[REG_MDR] = next_pc;
3376 State.regs[REG_PC] = State.regs[REG_A0 + AN0];
3381 // 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.)
3382 8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
3385 // start-sanitize-am33
3387 // end-sanitize-am33
3390 unsigned int next_pc, sp;
3393 sp = State.regs[REG_SP];
3394 next_pc = State.regs[REG_PC] + 4;
3395 store_word(sp, next_pc);
3396 State.regs[REG_MDR] = next_pc;
3397 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
3402 // 1111 1100 1111 1111 d32.....; calls (d32,PC)
3403 8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
3406 // start-sanitize-am33
3408 // end-sanitize-am33
3411 unsigned int next_pc, sp;
3414 sp = State.regs[REG_SP];
3415 next_pc = State.regs[REG_PC] + 6;
3416 store_word(sp, next_pc);
3417 State.regs[REG_MDR] = next_pc;
3418 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
3423 // 1111 0000 1111 1100; rets
3424 8.0xf0+8.0xfc:D0:::rets
3427 // start-sanitize-am33
3429 // end-sanitize-am33
3434 sp = State.regs[REG_SP];
3435 State.regs[REG_PC] = load_word(sp);
3440 // 1111 0000 1111 1101; rti
3441 8.0xf0+8.0xfd:D0:::rti
3444 // start-sanitize-am33
3446 // end-sanitize-am33
3451 sp = State.regs[REG_SP];
3452 PSW = load_half(sp);
3453 State.regs[REG_PC] = load_word(sp+4);
3454 State.regs[REG_SP] +=8;
3459 // 1111 0000 1111 1110; trap
3460 8.0xf0+8.0xfe:D0:::trap
3463 // start-sanitize-am33
3465 // end-sanitize-am33
3468 unsigned int sp, next_pc;
3471 sp = State.regs[REG_SP];
3472 next_pc = State.regs[REG_PC] + 2;
3473 store_word(sp, next_pc);
3478 // 1111 0000 1111 1111; rtm
3479 8.0xf0+8.0xff:D0:::rtm
3482 // start-sanitize-am33
3484 // end-sanitize-am33
3496 // start-sanitize-am33
3498 // end-sanitize-am33
3505 // 1111 0101 0000 DmDn; udf20 Dm,Dn
3506 8.0xf5+4.0x0,2.DN1,2.DN0:D0:::putx
3512 State.regs[REG_MDRQ] = State.regs[REG_D0 + DN0];
3516 // 1111 0110 1111 DmDn; udf15 Dm,Dn
3517 8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
3520 // start-sanitize-am33
3522 // end-sanitize-am33
3528 z = (State.regs[REG_MDRQ] == 0);
3529 n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
3530 State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];
3532 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3533 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
3537 // 1111 0110 0000 DmDn; udf00 Dm,Dn
3538 8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
3541 // start-sanitize-am33
3543 // end-sanitize-am33
3546 unsigned long long temp;
3550 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3551 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
3552 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3553 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3554 z = (State.regs[REG_D0 + DN0] == 0);
3555 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3556 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3557 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3561 // 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.)
3562 8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
3565 // start-sanitize-am33
3567 // end-sanitize-am33
3570 unsigned long long temp;
3574 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3575 * (signed64)(signed32)EXTEND8 (IMM8));
3576 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3577 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3578 z = (State.regs[REG_D0 + DN0] == 0);
3579 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3580 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3581 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3585 // 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.)
3586 8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
3589 // start-sanitize-am33
3591 // end-sanitize-am33
3594 unsigned long long temp;
3598 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3599 * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
3600 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3601 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3602 z = (State.regs[REG_D0 + DN0] == 0);
3603 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3604 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3605 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3609 // 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn
3610 8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
3613 // start-sanitize-am33
3615 // end-sanitize-am33
3618 unsigned long long temp;
3622 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3623 * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3624 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3625 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3626 z = (State.regs[REG_D0 + DN0] == 0);
3627 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3628 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3629 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3633 // 1111 0110 0001 DmDn; udf01 Dm,Dn
3634 8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
3637 // start-sanitize-am33
3639 // end-sanitize-am33
3642 unsigned long long temp;
3646 temp = ((unsigned64) State.regs[REG_D0 + DN0]
3647 * (unsigned64) State.regs[REG_D0 + DM1]);
3648 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3649 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3650 z = (State.regs[REG_D0 + DN0] == 0);
3651 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3652 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3653 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3657 // 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.)
3658 8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
3661 // start-sanitize-am33
3663 // end-sanitize-am33
3666 unsigned long long temp;
3670 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3671 * (unsigned64)EXTEND8 (IMM8));
3672 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3673 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3674 z = (State.regs[REG_D0 + DN0] == 0);
3675 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3676 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3677 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3681 // 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.)
3682 8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
3685 // start-sanitize-am33
3687 // end-sanitize-am33
3690 unsigned long long temp;
3694 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3695 * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
3696 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3697 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3698 z = (State.regs[REG_D0 + DN0] == 0);
3699 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3700 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3701 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3705 // 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn
3706 8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
3709 // start-sanitize-am33
3711 // end-sanitize-am33
3714 unsigned long long temp;
3718 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3719 * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3720 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3721 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3722 z = (State.regs[REG_D0 + DN0] == 0);
3723 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3724 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3725 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3729 // 1111 0110 0100 DmDn; udf04 Dm,Dn
3730 8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
3733 // start-sanitize-am33
3735 // end-sanitize-am33
3741 temp = State.regs[REG_D0 + DM1];
3742 temp = (temp > 0x7fff ? 0x7fff : temp);
3743 temp = (temp < -0x8000 ? -0x8000 : temp);
3744 State.regs[REG_D0 + DN0] = temp;
3748 // 1111 0110 0101 DmDn; udf05 Dm,Dn
3749 8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
3752 // start-sanitize-am33
3754 // end-sanitize-am33
3760 temp = State.regs[REG_D0 + DM1];
3761 temp = (temp > 0x7fffff ? 0x7fffff : temp);
3762 temp = (temp < -0x800000 ? -0x800000 : temp);
3763 State.regs[REG_D0 + DN0] = temp;
3767 // 1111 0110 0111 DmDn; udf07 Dm,Dn
3768 8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
3771 // start-sanitize-am33
3773 // end-sanitize-am33
3779 temp = State.regs[REG_D0 + DM1];
3780 temp <<= (State.regs[REG_D0 + DN0] & 0x1f);
3781 c = (temp != 0 ? 1 : 0);
3783 PSW |= (c ? PSW_C : 0);
3787 // 1111 0000 1100 0000; syscall
3788 8.0xf0+8.0xc0:D0:::syscall
3791 // start-sanitize-am33
3793 // end-sanitize-am33
3805 // start-sanitize-am33
3807 // end-sanitize-am33
3811 // State.exception = SIGTRAP;
3812 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
3816 // 1100 1110 regs....; movm (SP),regs
3817 8.0xce+8.REGS:S1:::movm
3820 // start-sanitize-am33
3822 // end-sanitize-am33
3825 unsigned long sp = State.regs[REG_SP];
3834 State.regs[REG_LAR] = load_word (sp);
3836 State.regs[REG_LIR] = load_word (sp);
3838 State.regs[REG_MDR] = load_word (sp);
3840 State.regs[REG_A0 + 1] = load_word (sp);
3842 State.regs[REG_A0] = load_word (sp);
3844 State.regs[REG_D0 + 1] = load_word (sp);
3846 State.regs[REG_D0] = load_word (sp);
3852 State.regs[REG_A0 + 3] = load_word (sp);
3858 State.regs[REG_A0 + 2] = load_word (sp);
3864 State.regs[REG_D0 + 3] = load_word (sp);
3870 State.regs[REG_D0 + 2] = load_word (sp);
3874 /* start-sanitize-am33 */
3875 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
3879 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
3881 State.regs[REG_E0 + 1] = load_word (sp);
3883 State.regs[REG_E0 + 0] = load_word (sp);
3889 State.regs[REG_E0 + 7] = load_word (sp);
3891 State.regs[REG_E0 + 6] = load_word (sp);
3893 State.regs[REG_E0 + 5] = load_word (sp);
3895 State.regs[REG_E0 + 4] = load_word (sp);
3901 State.regs[REG_E0 + 3] = load_word (sp);
3903 State.regs[REG_E0 + 2] = load_word (sp);
3907 /* end-sanitize-am33 */
3909 /* And make sure to update the stack pointer. */
3910 State.regs[REG_SP] = sp;
3914 // 1100 1111 regs....; movm regs,(SP)
3915 8.0xcf+8.REGS:S1a:::movm
3918 // start-sanitize-am33
3920 // end-sanitize-am33
3923 unsigned long sp = State.regs[REG_SP];
3929 /* start-sanitize-am33 */
3930 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
3935 store_word (sp, State.regs[REG_E0 + 2]);
3937 store_word (sp, State.regs[REG_E0 + 3]);
3943 store_word (sp, State.regs[REG_E0 + 4]);
3945 store_word (sp, State.regs[REG_E0 + 5]);
3947 store_word (sp, State.regs[REG_E0 + 6]);
3949 store_word (sp, State.regs[REG_E0 + 7]);
3955 store_word (sp, State.regs[REG_E0 + 0]);
3957 store_word (sp, State.regs[REG_E0 + 1]);
3959 /* Need to save MDQR, MCRH, MCRL, and MCVF */
3962 /* end-sanitize-am33 */
3967 store_word (sp, State.regs[REG_D0 + 2]);
3973 store_word (sp, State.regs[REG_D0 + 3]);
3979 store_word (sp, State.regs[REG_A0 + 2]);
3985 store_word (sp, State.regs[REG_A0 + 3]);
3991 store_word (sp, State.regs[REG_D0]);
3993 store_word (sp, State.regs[REG_D0 + 1]);
3995 store_word (sp, State.regs[REG_A0]);
3997 store_word (sp, State.regs[REG_A0 + 1]);
3999 store_word (sp, State.regs[REG_MDR]);
4001 store_word (sp, State.regs[REG_LIR]);
4003 store_word (sp, State.regs[REG_LAR]);
4007 /* And make sure to update the stack pointer. */
4008 State.regs[REG_SP] = sp;
4011 // 1100 1101 d16..... regs.... imm8....;
4012 // call (d16,PC),regs,imm8 (d16 is sign-extended., imm8 is zero-extended.)
4013 8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
4016 // start-sanitize-am33
4018 // end-sanitize-am33
4021 unsigned int next_pc, sp;
4025 sp = State.regs[REG_SP];
4027 store_word(sp, next_pc);
4031 /* start-sanitize-am33 */
4032 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4037 store_word (sp, State.regs[REG_E0 + 2]);
4039 store_word (sp, State.regs[REG_E0 + 3]);
4045 store_word (sp, State.regs[REG_E0 + 4]);
4047 store_word (sp, State.regs[REG_E0 + 5]);
4049 store_word (sp, State.regs[REG_E0 + 6]);
4051 store_word (sp, State.regs[REG_E0 + 7]);
4057 store_word (sp, State.regs[REG_E0 + 0]);
4059 store_word (sp, State.regs[REG_E0 + 1]);
4061 /* Need to save MDQR, MCRH, MCRL, and MCVF */
4064 /* end-sanitize-am33 */
4069 store_word (sp, State.regs[REG_D0 + 2]);
4075 store_word (sp, State.regs[REG_D0 + 3]);
4081 store_word (sp, State.regs[REG_A0 + 2]);
4087 store_word (sp, State.regs[REG_A0 + 3]);
4093 store_word (sp, State.regs[REG_D0]);
4095 store_word (sp, State.regs[REG_D0 + 1]);
4097 store_word (sp, State.regs[REG_A0]);
4099 store_word (sp, State.regs[REG_A0 + 1]);
4101 store_word (sp, State.regs[REG_MDR]);
4103 store_word (sp, State.regs[REG_LIR]);
4105 store_word (sp, State.regs[REG_LAR]);
4109 /* Update the stack pointer, note that the register saves to do not
4110 modify SP. The SP adjustment is derived totally from the imm8
4112 State.regs[REG_SP] -= IMM8;
4113 State.regs[REG_MDR] = next_pc;
4114 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
4119 // 1101 1101 d32..... regs.... imm8....;
4120 // call (d32,PC),regs,imm8 (imm8 is zero-extended.)
4121 8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
4124 // start-sanitize-am33
4126 // end-sanitize-am33
4129 unsigned int next_pc, sp;
4133 sp = State.regs[REG_SP];
4134 next_pc = State.regs[REG_PC] + 7;
4135 /* could assert that nia == next_pc here */
4136 store_word(sp, next_pc);
4137 // store_byte(sp, next_pc & 0xff);
4138 // store_byte(sp+1, (next_pc & 0xff00) >> 8 );
4139 // store_byte(sp+2, (next_pc & 0xff0000) >> 16 );
4140 // store_byte(sp+3, (next_pc & 0xff000000) >> 24);
4144 /* start-sanitize-am33 */
4145 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4150 store_word (sp, State.regs[REG_E0 + 2]);
4152 store_word (sp, State.regs[REG_E0 + 3]);
4158 store_word (sp, State.regs[REG_E0 + 4]);
4160 store_word (sp, State.regs[REG_E0 + 5]);
4162 store_word (sp, State.regs[REG_E0 + 6]);
4164 store_word (sp, State.regs[REG_E0 + 7]);
4170 store_word (sp, State.regs[REG_E0 + 0]);
4172 store_word (sp, State.regs[REG_E0 + 1]);
4174 /* Need to save MDQR, MCRH, MCRL, and MCVF */
4177 /* end-sanitize-am33 */
4182 store_word (sp, State.regs[REG_D0 + 2]);
4188 store_word (sp, State.regs[REG_D0 + 3]);
4194 store_word (sp, State.regs[REG_A0 + 2]);
4200 store_word (sp, State.regs[REG_A0 + 3]);
4206 store_word (sp, State.regs[REG_D0]);
4208 store_word (sp, State.regs[REG_D0 + 1]);
4210 store_word (sp, State.regs[REG_A0]);
4212 store_word (sp, State.regs[REG_A0 + 1]);
4214 store_word (sp, State.regs[REG_MDR]);
4216 store_word (sp, State.regs[REG_LIR]);
4218 store_word (sp, State.regs[REG_LAR]);
4222 /* Update the stack pointer, note that the register saves to do not
4223 modify SP. The SP adjustment is derived totally from the imm8
4225 State.regs[REG_SP] -= IMM8;
4226 State.regs[REG_MDR] = next_pc;
4227 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
4232 // 1101 1111 regs.... imm8....; ret regs,imm8 (imm8 is zero-extended.)
4233 8.0xdf+8.REGS+8.IMM8:S2:::ret
4236 // start-sanitize-am33
4238 // end-sanitize-am33
4241 unsigned int sp, offset;
4245 State.regs[REG_SP] += IMM8;
4246 sp = State.regs[REG_SP];
4251 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4256 State.regs[REG_E0 + 2] = load_word (sp + offset);
4258 State.regs[REG_E0 + 3] = load_word (sp + offset);
4264 State.regs[REG_E0 + 4] = load_word (sp + offset);
4266 State.regs[REG_E0 + 5] = load_word (sp + offset);
4268 State.regs[REG_E0 + 6] = load_word (sp + offset);
4270 State.regs[REG_E0 + 7] = load_word (sp + offset);
4276 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
4278 State.regs[REG_E0 + 0] = load_word (sp + offset);
4280 State.regs[REG_E0 + 1] = load_word (sp + offset);
4288 State.regs[REG_D0 + 2] = load_word (sp + offset);
4294 State.regs[REG_D0 + 3] = load_word (sp + offset);
4300 State.regs[REG_A0 + 2] = load_word (sp + offset);
4306 State.regs[REG_A0 + 3] = load_word (sp + offset);
4312 State.regs[REG_D0] = load_word (sp + offset);
4314 State.regs[REG_D0 + 1] = load_word (sp + offset);
4316 State.regs[REG_A0] = load_word (sp + offset);
4318 State.regs[REG_A0 + 1] = load_word (sp + offset);
4320 State.regs[REG_MDR] = load_word (sp + offset);
4322 State.regs[REG_LIR] = load_word (sp + offset);
4324 State.regs[REG_LAR] = load_word (sp + offset);
4328 /* Restore the PC value. */
4329 State.regs[REG_PC] = load_word(sp);
4334 // 1101 1110 regs.... imm8....; retf regs,imm8 (imm8 is zero-extended.)
4335 8.0xde+8.REGS+8.IMM8:S2:::retf
4338 // start-sanitize-am33
4340 // end-sanitize-am33
4343 unsigned int sp, offset;
4347 State.regs[REG_SP] += IMM8;
4348 sp = State.regs[REG_SP];
4349 State.regs[REG_PC] = State.regs[REG_MDR] - 3;
4354 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4359 State.regs[REG_E0 + 2] = load_word (sp + offset);
4361 State.regs[REG_E0 + 3] = load_word (sp + offset);
4367 State.regs[REG_E0 + 4] = load_word (sp + offset);
4369 State.regs[REG_E0 + 5] = load_word (sp + offset);
4371 State.regs[REG_E0 + 6] = load_word (sp + offset);
4373 State.regs[REG_E0 + 7] = load_word (sp + offset);
4379 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
4381 State.regs[REG_E0 + 0] = load_word (sp + offset);
4383 State.regs[REG_E0 + 1] = load_word (sp + offset);
4391 State.regs[REG_D0 + 2] = load_word (sp + offset);
4397 State.regs[REG_D0 + 3] = load_word (sp + offset);
4403 State.regs[REG_A0 + 2] = load_word (sp + offset);
4409 State.regs[REG_A0 + 3] = load_word (sp + offset);
4415 State.regs[REG_D0] = load_word (sp + offset);
4417 State.regs[REG_D0 + 1] = load_word (sp + offset);
4419 State.regs[REG_A0] = load_word (sp + offset);
4421 State.regs[REG_A0 + 1] = load_word (sp + offset);
4423 State.regs[REG_MDR] = load_word (sp + offset);
4425 State.regs[REG_LIR] = load_word (sp + offset);
4427 State.regs[REG_LAR] = load_word (sp + offset);
4432 // start-sanitize-am33
4433 :include::am33:am33.igen
4434 // end-sanitize-am33