2 :option:::insn-bit-size:8
3 :option:::insn-specifying-widths:true
5 :model:::mn10300:mn10300:
7 // What do we do with an illegal instruction?
11 program_interrupt(SD, CPU, cia, SIM_SIGILL);
14 // 1000 DnDn imm8....; mov imm8,Dn (imm8 is sign extended)
15 4.0x8,2.DM1,2.DN0=DM1+8.IMM8:S0i:::mov
20 signed32 immed = EXTEND8 (IMM8);
21 State.regs[REG_D0+DN0] = immed;
25 // 1000 DmDn; mov Dm,Dn (Dm != Dn, see above when Dm == Dn)
26 4.0x8,2.DM1,2.DN0!DM1:S0:::mov
32 State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1];
36 // 1111 0001 1110 DmAn; mov Dm,An
37 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
43 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1];
47 // 1111 0001 1101 AmDn; mov Am,Dn
48 8.0xf1+1101,2.AM1,2.DN0:D0a:::mov
54 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1];
58 // 1001 AnAn imm8....; mov imm8,An (imm8 is zero-extended)
59 4.0x9,2.AM1,2.AN0=AM1+8.IMM8:S0ai:::mov
65 State.regs[REG_A0+AN0] = IMM8;
69 // 1001 AmAn; mov Am,An (Am != An, save above when Am == An)
70 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
76 State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1];
80 // 0011 11An; mov SP,An
81 4.0x3,11,2.AN0:S0b:::mov
87 State.regs[REG_A0 + AN0] = State.regs[REG_SP];
91 // 1111 0010 1111 Am00; mov Am,SP
92 8.0xf2+4.0xf,2.AM1,00:D0b:::mov
98 State.regs[REG_SP] = State.regs[REG_A0 + AM1];
102 // 1111 0010 1110 01Dn; mov PSW,Dn
103 8.0xf2+4.0xe,01,2.DN0:D0c:::mov
109 State.regs[REG_D0 + DN0] = PSW;
113 // 1111 0010 1111 Dm11; mov Dm,PSW
114 8.0xf2+4.0xf,2.DM1,11:D0d:::mov
120 PSW = State.regs[REG_D0 + DM1];
124 // 1111 0010 1110 00Dn; mov MDR,Dn
125 8.0xf2+4.0xe,00,2.DN0:D0e:::mov
131 State.regs[REG_D0 + DN0] = State.regs[REG_MDR];
135 // 1111 0010 1111 Dm10; mov Dm,MDR
136 8.0xf2+4.0xf,2.DM1,10:D0f:::mov
142 State.regs[REG_MDR] = State.regs[REG_D0 + DM1];
146 // 0111 DnAm; mov (Am),Dn
147 4.0x7,2.DN1,2.AM0:S0c:::mov
153 State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]);
157 // 1111 1000 0000 DnAm d8......; mov (d8,Am),Dn (d8 is sign-extended)
158 8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
164 State.regs[REG_D0 + DN1]
165 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
169 // 1111 1010 0000 DnAm d16.....; mov (d16,Am),Dn (d16 is sign-extended.)
170 8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
174 /* OP_FA000000 (); */
176 State.regs[REG_D0 + DN1]
177 = load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B))));
181 // 1111 1100 0000 DnAm d32.....; mov (d32,Am),Dn
182 8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
186 /* OP_FC000000 (); */
188 State.regs[REG_D0 + DN1]
189 = load_word ((State.regs[REG_A0 + AM0]
190 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
194 // 0101 10Dn d8......; mov (d8,SP),Dn (d8 is zero-extended)
195 4.0x5,10,2.DN0+8.D8:S1:::mov
201 State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8);
205 // 1111 1010 1011 01Dn d16.....; mov (d16,SP),Dn (d16 is zero-extended.)
206 8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
210 /* OP_FAB40000 (); */
212 State.regs[REG_D0 + DN0]
213 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
217 // 1111 1010 1011 01Dn d32.....; mov (d32,SP),Dn
218 8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
222 /* OP_FCB40000 (); */
224 State.regs[REG_D0 + DN0]
225 = load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
229 // 1111 0011 00Dn DiAm; mov (Di,Am),Dn
230 8.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov
236 State.regs[REG_D0 + DN2]
237 = load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
241 // 0011 00Dn abs16...; mov (abs16),Dn (abs16 is zero-extended)
242 4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
248 State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B));
251 // 1111 1100 1010 01Dn abs32...; mov (abs32),Dn
252 8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
256 /* OP_FCA40000 (); */
258 State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
262 // 1111 0000 0000 AnAm; mov (Am),An
263 8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
269 State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]);
273 // 1111 1000 0010 AnAm d8......; mov (d8,Am),An (d8 is sign-extended)
274 8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
280 State.regs[REG_A0 + AN1]
281 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
285 // 1111 1010 0010 AnAm d16.....; mov (d16,Am),An (d16 is sign-extended.)
286 8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
290 /* OP_FA200000 (); */
292 State.regs[REG_A0 + AN1]
293 = load_word ((State.regs[REG_A0 + AM0]
294 + EXTEND16 (FETCH16(D16A, D16B))));
298 // 1111 1100 0010 AnAm d32.....; mov (d32,Am),An
299 8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
303 /* OP_FC200000 (); */
305 State.regs[REG_A0 + AN1]
306 = load_word ((State.regs[REG_A0 + AM0]
307 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
311 // 0101 11An d8......; mov (d8,SP),An (d8 is zero-extended)
312 4.0x5,11,2.AN0+8.D8:S1a:::mov
318 State.regs[REG_A0 + AN0]
319 = load_word (State.regs[REG_SP] + D8);
323 // 1111 1010 1011 00An d16.....; mov (d16,SP),An (d16 is zero-extended.)
324 8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
328 /* OP_FAB00000 (); */
330 State.regs[REG_A0 + AN0]
331 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
335 // 1111 1100 1011 00An d32.....; mov (d32,SP),An
336 8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
340 /* OP_FCB00000 (); */
342 State.regs[REG_A0 + AN0]
343 = load_word (State.regs[REG_SP]
344 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
348 // 1111 0011 10An DiAm; mov (Di,Am),An
349 8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
355 State.regs[REG_A0 + AN2]
356 = load_word ((State.regs[REG_A0 + AM0]
357 + State.regs[REG_D0 + DI]));
361 // 1111 1010 1010 00An abs16...; mov (abs16),An (abs16 is zero-extended)
362 8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
366 /* OP_FAA00000 (); */
368 State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B));
372 // 1111 1100 1010 00An abs32...; mov (abs32),An
373 8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
377 /* OP_FCA00000 (); */
379 State.regs[REG_A0 + AN0]
380 = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
384 // 1111 1000 1111 00Am d8......; mov (d8,Am),SP (d8 is sign-extended)
385 8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
392 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
396 // 0110 DmAn; mov Dm,(An)
397 4.0x6,2.DM1,2.AN0:S0d:::mov
403 store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
407 // 1111 1000 0001 DmAn d8......; mov Dm,(d8,An) (d8 is sign-extended)
408 8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
414 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
415 State.regs[REG_D0 + DM1]);
419 // 1111 1010 0001 DmAn d16.....; mov Dm,(d16,An) (d16 is sign-extended.)
420 8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
424 /* OP_FA100000 (); */
426 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
427 State.regs[REG_D0 + DM1]);
431 // 1111 1100 0001 DmAn d32.....; mov Dm,(d32,An)
432 8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
436 /* OP_FC100000 (); */
438 store_word ((State.regs[REG_A0 + AN0]
439 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
440 State.regs[REG_D0 + DM1]);
444 // 0100 Dm10 d8......; mov Dm,(d8,SP) (d8 is zero-extended)
445 4.0x4,2.DM1,10+8.D8:S1b:::mov
451 store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]);
455 // 1111 1010 1001 Dm01 d16.....; mov Dm,(d16,SP) (d16 is zero-extended.)
456 8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
460 /* OP_FA910000 (); */
462 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
463 State.regs[REG_D0 + DM1]);
467 // 1111 1100 1001 Dm01 d32.....; mov Dm,(d32,SP)
468 8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
472 /* OP_FC910000 (); */
474 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
475 State.regs[REG_D0 + DM1]);
479 // 1111 0011 01Dm DiAn; mov Dm,(Di,An)
480 8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
486 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
487 State.regs[REG_D0 + DM2]);
491 // 0000 Dm01 abs16..., mov Dm,(abs16) (abs16 is zero-extended).
492 4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
498 store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
502 // 1111 1100 1000 Dm01 abs32...; mov Dm,(abs32)
503 8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
507 /* OP_FC810000 (); */
509 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
510 State.regs[REG_D0 + DM1]);
514 // 1111 0000 0001 AmAn; mov Am,(An)
515 8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
521 store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]);
525 // 1111 1000 0011 AmAn d8......; mov Am,(d8,An) (d8 is sign-extended)
526 8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
532 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
533 State.regs[REG_A0 + AM1]);
537 // 1111 1010 0011 AmAn d16.....; mov Am,(d16,An) (d16 is sign-extended.)
538 8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
542 /* OP_FA300000 (); */
544 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
545 State.regs[REG_A0 + AM1]);
549 // 1111 1100 0011 AmAn d32.....; mov Am,(d32,An)
550 8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
554 /* OP_FC300000 (); */
556 store_word ((State.regs[REG_A0 + AN0]
557 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
558 State.regs[REG_A0 + AM1]);
562 // 0100 Am11 d8......; mov Am,(d8,SP) (d8 is zero-extended)
563 4.0x4,2.AM1,11+8.D8:S1c:::mov
569 store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]);
573 // 1111 1010 1001 Am00 d16.....; mov Am,(d16,SP) (d16 is zero-extended.)
574 8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
578 /* OP_FA900000 (); */
580 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
581 State.regs[REG_A0 + AM1]);
585 // 1111 1100 1001 Am00 d32.....; mov Am,(d32,SP)
586 8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
590 /* OP_FC900000 (); */
592 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
593 State.regs[REG_A0 + AM1]);
597 // 1111 0011 11Am DiAn; mov Am,(Di,An)
598 8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
604 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
605 State.regs[REG_A0 + AM2]);
609 // 1111 1010 1000 Am00 abs16...; mov Am,(abs16) (abs16 is zero-extended)
610 8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
614 /* OP_FA800000 (); */
616 store_word (FETCH16(IMM16A, IMM16B),
617 State.regs[REG_A0 + AM1]);
621 // 1111 1100 1000 Am00 abs32...; mov Am,(abs32)
622 8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
626 /* OP_FC800000 (); */
628 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
629 State.regs[REG_A0 + AM1]);
633 // 1111 1000 1111 01An d8......; mov SP,(d8,An) (d8 is sign-extended)
634 8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
640 store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8),
645 // 0010 11Dn imm16...; mov imm16,Dn (imm16 is sign-extended)
646 4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
654 value = EXTEND16 (FETCH16(IMM16A, IMM16B));
655 State.regs[REG_D0 + DN0] = value;
659 // 1111 1100 1100 11Dn imm32...; mov imm32,Dn
660 8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
664 /* OP_FCCC0000 (); */
668 value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
669 State.regs[REG_D0 + DN0] = value;
673 // 0010 01An imm16...; mov imm16,An (imm16 is zero-extended)
674 4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
682 value = FETCH16(IMM16A, IMM16B);
683 State.regs[REG_A0 + AN0] = value;
687 // 1111 1100 1101 11An imm32...; mov imm32,An
688 8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
692 /* OP_FCDC0000 (); */
694 State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
698 // 1111 0000 0100 DnAm; movbu (Am),Dn
699 8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
705 State.regs[REG_D0 + DN1]
706 = load_byte (State.regs[REG_A0 + AM0]);
710 // 1111 1000 0100 DnAm d8......; movbu (d8,Am),Dn (d8 is sign-extended)
711 8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
717 State.regs[REG_D0 + DN1]
718 = load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
722 // 1111 1010 0100 DnAm d16.....; movbu (d16,Am),Dn (d16 is sign-extended.)
723 8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
727 /* OP_FA400000 (); */
729 State.regs[REG_D0 + DN1]
730 = load_byte ((State.regs[REG_A0 + AM0]
731 + EXTEND16 (FETCH16(D16A, D16B))));
735 // 1111 1100 0100 DnAm d32.....; movbu (d32,Am),Dn
736 8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
740 /* OP_FC400000 (); */
742 State.regs[REG_D0 + DN1]
743 = load_byte ((State.regs[REG_A0 + AM0]
744 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
748 // 1111 1000 1011 10Dn d8......; movbu (d8,SP),Dn (d8 is zero-extended)
749 8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
755 State.regs[REG_D0 + DN0]
756 = load_byte ((State.regs[REG_SP] + (D8)));
760 // 1111 1010 1011 10Dn d16.....; movbu (d16,SP),Dn (d16 is zero-extended.)
761 8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
765 /* OP_FAB80000 (); */
767 State.regs[REG_D0 + DN0]
768 = load_byte ((State.regs[REG_SP]
769 + FETCH16(IMM16A, IMM16B)));
773 // 1111 1100 1011 10Dn d32.....; movbu (d32,SP),Dn
774 8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
778 /* OP_FCB80000 (); */
780 State.regs[REG_D0 + DN0]
781 = load_byte (State.regs[REG_SP]
782 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
786 // 1111 0100 00Dn DiAm; movbu (Di,Am),Dn
787 8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
793 State.regs[REG_D0 + DN2]
794 = load_byte ((State.regs[REG_A0 + AM0]
795 + State.regs[REG_D0 + DI]));
799 // 0011 01Dn abs16...; movbu (abs16),Dn (abs16 is zero-extended)
800 4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
806 State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B));
810 // 1111 1100 1010 10Dn abs32...; movbu (abs32),Dn
811 8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
815 /* OP_FCA80000 (); */
817 State.regs[REG_D0 + DN0]
818 = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
822 // 1111 0000 0101 DmAn; movbu Dm,(An)
823 8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
829 store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
833 // 1111 1000 0101 DmAn d8......; movbu Dm,(d8,An) (d8 is sign-extended)
834 8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
840 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
841 State.regs[REG_D0 + DM1]);
845 // 1111 1010 0101 DmAn d16.....; movbu Dm,(d16,An) (d16 is sign-extended.)
846 8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
850 /* OP_FA500000 (); */
852 store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
853 State.regs[REG_D0 + DM1]);
857 // 1111 1100 0101 DmAn d32.....; movbu Dm,(d32,An)
858 8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
862 /* OP_FC500000 (); */
864 store_byte ((State.regs[REG_A0 + AN0]
865 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
866 State.regs[REG_D0 + DM1]);
870 // 1111 1000 1001 Dm10 d8......; movbu Dm,(d8,SP) (d8 is zero-extended)
871 8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
877 store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]);
881 // 1111 1010 1001 Dm10 d16.....; movbu Dm,(d16,SP) (d16 is zero-extended.)
882 8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
886 /* OP_FA920000 (); */
888 store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
889 State.regs[REG_D0 + DM1]);
893 // 1111 1100 1001 Dm10 d32.....; movbu Dm,(d32,SP)
894 8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
898 /* OP_FC920000 (); */
900 store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
901 State.regs[REG_D0 + DM1]);
905 // 1111 0100 01Dm DiAn; movbu Dm,(Di,An)
906 8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
912 store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
913 State.regs[REG_D0 + DM2]);
917 // 0000 Dm10 abs16...; movbu Dm,(abs16) (abs16 is zero-extended)
918 4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
924 store_byte (FETCH16(IMM16A, IMM16B),
925 State.regs[REG_D0 + DM1]);
929 // 1111 1100 1000 Dm10 abs32...; movbu Dm,(abs32)
930 8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
934 /* OP_FC820000 (); */
936 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
937 State.regs[REG_D0 + DM1]);
941 // 1111 0000 0110 DnAm; movhu (Am),Dn
942 8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
948 State.regs[REG_D0 + DN1]
949 = load_half (State.regs[REG_A0 + AM0]);
953 // 1111 1000 0110 DnAm d8......; movhu (d8,Am),Dn (d8 is sign-extended)
954 8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
960 State.regs[REG_D0 + DN1]
961 = load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
965 // 1111 1010 0110 DnAm d16.....; movhu (d16,Am),Dn (d16 is sign-extended.)
966 8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
970 /* OP_FA600000 (); */
972 State.regs[REG_D0 + DN1]
973 = load_half ((State.regs[REG_A0 + AM0]
974 + EXTEND16 (FETCH16(D16A, D16B))));
978 // 1111 1100 0110 DnAm d32.....; movhu (d32,Am),Dn
979 8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
983 /* OP_FC600000 (); */
985 State.regs[REG_D0 + DN1]
986 = load_half ((State.regs[REG_A0 + AM0]
987 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
991 // 1111 1000 1011 11Dn d8.....; movhu (d8,SP),Dn (d8 is zero-extended)
992 8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
998 State.regs[REG_D0 + DN0]
999 = load_half ((State.regs[REG_SP] + (D8)));
1003 // 1111 1010 1011 11Dn d16.....; movhu (d16,SP),Dn (d16 is zero-extended.)
1004 8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
1008 /* OP_FABC0000 (); */
1010 State.regs[REG_D0 + DN0]
1011 = load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)));
1015 // 1111 1100 1011 11Dn d32.....; movhu (d32,SP),Dn
1016 8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
1020 /* OP_FCBC0000 (); */
1022 State.regs[REG_D0 + DN0]
1023 = load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1027 // 1111 0100 10Dn DiAm; movhu (Di,Am),Dn
1028 8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
1034 State.regs[REG_D0 + DN2]
1035 = load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
1039 // 0011 10Dn abs16...; movhu (abs16),Dn (abs16 is zero-extended)
1040 4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
1046 State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B));
1050 // 1111 1100 1010 11Dn abs32...; movhu (abs32),Dn
1051 8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
1055 /* OP_FCAC0000 (); */
1057 State.regs[REG_D0 + DN0]
1058 = load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1062 // 1111 0000 0111 DmAn; movhu Dm,(An)
1063 8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
1069 store_half (State.regs[REG_A0 + AN0],
1070 State.regs[REG_D0 + DM1]);
1074 // 1111 1000 0111 DmAn d8......; movhu Dm,(d8,An) (d8 is sign-extended)
1075 8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
1081 store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1082 State.regs[REG_D0 + DM1]);
1086 // 1111 1010 0111 DnAm d16.....; movhu Dm,(d16,An) (d16 is sign-extended.)
1087 8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
1091 /* OP_FA700000 (); */
1093 store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1094 State.regs[REG_D0 + DM1]);
1098 // 1111 1100 0111 DmAn d32.....; movhu Dm,(d32,An)
1099 8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
1103 /* OP_FC700000 (); */
1105 store_half ((State.regs[REG_A0 + AN0]
1106 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1107 State.regs[REG_D0 + DM1]);
1111 // 1111 1000 1001 Dm11 d8....; movhu Dm,(d8,SP) (d8 is zero-extended)
1112 8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
1118 store_half (State.regs[REG_SP] + (D8),
1119 State.regs[REG_D0 + DM1]);
1123 // 1111 1010 1001 Dm11 d16.....; movhu Dm,(d16,SP) (d16 is zero-extended.)
1124 8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
1128 /* OP_FA930000 (); */
1130 store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1131 State.regs[REG_D0 + DM1]);
1135 // 1111 1100 1001 Dm11 d32.....; movhu Dm,(d32,SP)
1136 8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
1140 /* OP_FC930000 (); */
1142 store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1143 State.regs[REG_D0 + DM1]);
1147 // 1111 0100 11Dm DiAn; movhu Dm,(Di,An)
1148 8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
1154 store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1155 State.regs[REG_D0 + DM2]);
1159 // 0000 Dm11 abs16...; movhu Dm,(abs16) (abs16 is zero-extended)
1160 4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
1166 store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
1170 // 1111 1100 1000 Dm11 abs32...; movhu Dm,(abs32)
1171 8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
1175 /* OP_FC830000 (); */
1177 store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1178 State.regs[REG_D0 + DM1]);
1182 // 1111 0010 1101 00Dn; ext Dn
1183 8.0xf2+4.0xd,00,2.DN0:D0:::ext
1189 if (State.regs[REG_D0 + DN0] & 0x80000000)
1190 State.regs[REG_MDR] = -1;
1192 State.regs[REG_MDR] = 0;
1196 // 0001 00Dn; extb Dn
1197 4.0x1,00,2.DN0:S0:::extb
1203 State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]);
1207 // 0001 01Dn; extbu Dn
1208 4.0x1,01,2.DN0:S0:::extbu
1214 State.regs[REG_D0 + DN0] &= 0xff;
1218 // 0001 10Dn; exth Dn
1219 4.0x1,10,2.DN0:S0:::exth
1225 State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]);
1229 // 0001 11Dn; exthu Dn
1230 4.0x1,11,2.DN0:S0:::exthu
1236 State.regs[REG_D0 + DN0] &= 0xffff;
1240 // 0000 Dn00; clr Dn
1241 4.0x0,2.DN1,00:S0:::clr
1247 State.regs[REG_D0 + DN1] = 0;
1250 PSW &= ~(PSW_V | PSW_C | PSW_N);
1254 // 1110 DmDn; add Dm,Dn
1255 4.0xe,2.DM1,2.DN0:S0:::add
1261 genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1264 // 1111 0001 0110 DmAn; add Dm,An
1265 8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
1271 genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1275 // 1111 0001 0101 AmDn; add Am,Dn
1276 8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
1282 genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1286 // 1111 0001 0111 AmAn; add Am,An
1287 8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
1293 genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1297 // 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended)
1298 4.0x2,10,2.DN0+8.IMM8:S1:::add
1304 genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
1308 // 1111 1010 1100 00Dn imm16...; add imm16,Dn
1309 8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
1313 /* OP_FAC00000 (); */
1315 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
1319 // 1111 1100 1100 00Dn imm32...; add imm32,Dn
1320 8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
1324 /* OP_FCC00000 (); */
1326 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1330 // 0010 00An imm8....; add imm8,An (imm8 is sign-extended)
1331 4.0x2,00,2.AN0+8.IMM8:S1a:::add
1337 genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
1341 // 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.)
1342 8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
1346 /* OP_FAD00000 (); */
1348 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
1352 // 1111 1100 1101 00An imm32...; add imm32,An
1353 8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
1357 /* OP_FCD00000 (); */
1359 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1363 // 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.)
1364 8.0xf8+8.0xfe+8.IMM8:D1:::add
1371 /* Note: no PSW changes. */
1373 imm = EXTEND8 (IMM8);
1374 State.regs[REG_SP] += imm;
1378 // 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.)
1379 8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
1383 /* OP_FAFE0000 (); */
1386 /* Note: no PSW changes. */
1388 imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
1389 State.regs[REG_SP] += imm;
1393 // 1111 1100 1111 1110 imm32...; add imm32,SP
1394 8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
1398 /* OP_FCFE0000 (); */
1401 /* Note: no PSW changes. */
1403 imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1404 State.regs[REG_SP] += imm;
1408 // 1111 0001 0100 DmDn; addc Dm,Dn
1409 8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
1415 unsigned long reg1, reg2, sum;
1418 reg1 = State.regs[REG_D0 + DM1];
1419 reg2 = State.regs[REG_D0 + DN0];
1420 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
1421 State.regs[REG_D0 + DN0] = sum;
1423 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1424 n = (sum & 0x80000000);
1425 c = (sum < reg1) || (sum < reg2);
1426 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1427 && (reg2 & 0x80000000) != (sum & 0x80000000));
1429 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1430 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1431 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1435 // 1111 0001 0000 DmDn; sub Dm,Dn
1436 8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
1442 genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1445 // 1111 0001 0010 DmAn; sub DmAn
1446 8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
1452 genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1456 // 1111 0001 0001 AmDn; sub AmDn
1457 8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
1463 genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1467 // 1111 0001 0011 AmAn; sub Am,An
1468 8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
1474 genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1478 // 1111 1100 1100 01Dn imm32...; sub imm32,Dn
1479 8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
1483 /* OP_FCC40000 (); */
1485 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1489 // 1111 1100 1101 01An imm32...; sub imm32,An
1490 8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
1494 /* OP_FCD40000 (); */
1496 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1500 // 1111 0001 1000 DmDn; subc Dm,Dn
1501 8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
1507 unsigned long reg1, reg2, difference;
1510 reg1 = State.regs[REG_D0 + DM1];
1511 reg2 = State.regs[REG_D0 + DN0];
1512 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
1513 State.regs[REG_D0 + DN0] = difference;
1515 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1516 n = (difference & 0x80000000);
1518 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1519 && (reg2 & 0x80000000) != (difference & 0x80000000));
1521 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1522 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1523 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1527 // 1111 0010 0100 DmDn; mul Dm,Dn
1528 8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
1533 unsigned long long temp;
1537 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
1538 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
1539 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1540 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1541 z = (State.regs[REG_D0 + DN0] == 0);
1542 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1543 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1544 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1548 // 1111 0010 0101 DmDn; mulu Dm,Dn
1549 8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
1554 unsigned long long temp;
1558 temp = ((unsigned64)State.regs[REG_D0 + DN0]
1559 * (unsigned64)State.regs[REG_D0 + DM1]);
1560 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1561 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1562 z = (State.regs[REG_D0 + DN0] == 0);
1563 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1564 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1565 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1569 // 1111 0010 0110 DmDn; div Dm,Dn
1570 8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
1580 denom = (signed32)State.regs[REG_D0 + DM1];
1582 temp = State.regs[REG_MDR];
1584 temp |= State.regs[REG_D0 + DN0];
1585 if ( !(v = (0 == denom)) )
1587 State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1];
1588 temp /= (signed32)State.regs[REG_D0 + DM1];
1589 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1593 State.regs[REG_MDR] = temp;
1594 State.regs[REG_D0 + DN0] = 0xff;
1596 z = (State.regs[REG_D0 + DN0] == 0);
1597 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1598 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1599 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
1603 // 1111 0010 0111 DmDn; divu Dm,Dn
1604 8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
1614 denom = (unsigned32)State.regs[REG_D0 + DM1];
1615 temp = State.regs[REG_MDR];
1617 temp |= State.regs[REG_D0 + DN0];
1618 if ( !(v = (0 == denom)) )
1620 State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
1621 temp /= State.regs[REG_D0 + DM1];
1622 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1626 State.regs[REG_MDR] = temp;
1627 State.regs[REG_D0 + DN0] = 0xff;
1629 z = (State.regs[REG_D0 + DN0] == 0);
1630 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1631 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1632 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
1636 // 0100 Dn00; inc Dn
1637 4.0x4,2.DN1,00:S0:::inc
1646 genericAdd(imm, REG_D0 + DN1);
1651 4.0x4,2.AN1,01:S0a:::inc
1657 State.regs[REG_A0 + AN1] += 1;
1661 // 0101 00An; inc4 An
1662 4.0x5,00,2.AN0:S0:::inc4
1668 State.regs[REG_A0 + AN0] += 4;
1672 // 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.)
1673 4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
1679 genericCmp(EXTEND8 (IMM8), State.regs[REG_D0 + DN0]);
1683 // 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn)
1684 4.0xa,2.DM1,2.DN0!DM1:S0:::cmp
1690 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
1694 // 1111 0001 1010 DmAn; cmp Dm,An
1695 8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
1701 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
1705 // 1111 0001 1001 AmDn; cmp Am,Dn
1706 8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
1712 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
1716 // 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.)
1717 4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
1724 State.regs[REG_A0 + AN0]);
1728 // 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn)
1729 4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
1735 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
1739 // 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.)
1740 8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
1744 /* OP_FAC80000 (); */
1746 genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
1747 State.regs[REG_D0 + DN0]);
1751 // 1111 1100 1100 10Dn imm32...; cmp imm32,Dn
1752 8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
1756 /* OP_FCC80000 (); */
1758 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1759 State.regs[REG_D0 + DN0]);
1763 // 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.)
1764 8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
1768 /* OP_FAD80000 (); */
1770 genericCmp(FETCH16(IMM16A, IMM16B),
1771 State.regs[REG_A0 + AN0]);
1775 // 1111 1100 1101 10An imm32...; cmp imm32,An
1776 8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
1780 /* OP_FCD80000 (); */
1782 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1783 State.regs[REG_A0 + AN0]);
1787 // 1111 0010 0000 DmDn; and Dm,Dn
1788 8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
1796 State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
1797 z = (State.regs[REG_D0 + DN0] == 0);
1798 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1799 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1800 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1804 // 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.)
1805 8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
1813 State.regs[REG_D0 + DN0] &= IMM8;
1814 z = (State.regs[REG_D0 + DN0] == 0);
1815 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1816 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1817 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1821 // 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.)
1822 8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
1826 /* OP_FAE00000 (); */
1830 State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
1831 z = (State.regs[REG_D0 + DN0] == 0);
1832 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1833 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1834 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1838 // 1111 1100 1110 00Dn imm32...; and imm32,Dn
1839 8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
1843 /* OP_FCE00000 (); */
1847 State.regs[REG_D0 + DN0]
1848 &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1849 z = (State.regs[REG_D0 + DN0] == 0);
1850 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1851 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1852 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1856 // 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.)
1857 8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
1861 /* OP_FAFC0000 (); */
1863 PSW &= FETCH16(IMM16A, IMM16B);
1868 // 1111 0010 0001 DmDn; or DmDn
1869 8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
1875 genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1879 // 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n
1880 8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
1886 genericOr(IMM8, REG_D0 + DN0);
1890 // 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.)
1891 8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
1895 /* OP_FAE40000 (); */
1897 genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
1901 // 1111 1100 1110 01Dn imm32...; or imm32,Dn
1902 8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
1906 /* OP_FCE40000 (); */
1908 genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1912 // 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.)
1913 8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
1917 /* OP_FAFD0000 (); */
1919 PSW |= FETCH16(IMM16A, IMM16B);
1923 // 1111 0010 0010 DmDn; xor Dm,Dn
1924 8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
1930 genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1934 // 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.)
1935 8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
1939 /* OP_FAE80000 (); */
1941 genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
1945 // 1111 1100 1110 10Dn imm32...; xor imm32,Dn
1946 8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
1950 /* OP_FCE80000 (); */
1952 genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1956 // 1111 0010 0011 00Dn; not Dn
1957 8.0xf2+4.0x3,00,2.DN0:D0:::not
1965 State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
1966 z = (State.regs[REG_D0 + DN0] == 0);
1967 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1968 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1969 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1973 // 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.)
1974 8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
1980 genericBtst(IMM8, State.regs[REG_D0 + DN0]);
1984 // 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.)
1985 8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
1989 /* OP_FAEC0000 (); */
1991 genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
1995 // 1111 1100 1110 11Dn imm32...; btst imm32,Dn
1996 8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
2000 /* OP_FCEC0000 (); */
2002 genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2003 State.regs[REG_D0 + DN0]);
2007 // 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2008 8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
2012 /* OP_FE020000 (); */
2015 load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
2019 // 1111 1010 1111 10An d8...... imm8....;
2020 // btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte)
2021 8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
2025 /* OP_FAF80000 (); */
2028 load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
2032 // 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte)
2033 8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
2042 temp = load_byte (State.regs[REG_A0 + AN0]);
2043 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2044 temp |= State.regs[REG_D0 + DM1];
2045 store_byte (State.regs[REG_A0 + AN0], temp);
2046 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2047 PSW |= (z ? PSW_Z : 0);
2051 // 1111 1110 0000 0000 abs32... imm8....;
2052 // bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2053 8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
2057 /* OP_FE000000 (); */
2062 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2063 z = (temp & IMM8) == 0;
2065 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2066 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2067 PSW |= (z ? PSW_Z : 0);
2071 // 1111 1010 1111 00AnAn d8...... imm8....;
2072 // bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2073 8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
2077 /* OP_FAF00000 (); */
2082 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2083 z = (temp & (IMM8)) == 0;
2085 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2086 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2087 PSW |= (z ? PSW_Z : 0);
2091 // 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte)
2092 8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
2101 temp = load_byte (State.regs[REG_A0 + AN0]);
2102 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2103 temp = temp & ~State.regs[REG_D0 + DM1];
2104 store_byte (State.regs[REG_A0 + AN0], temp);
2105 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2106 PSW |= (z ? PSW_Z : 0);
2110 // 1111 1110 0000 0001 abs32... imm8....;
2111 // bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2112 8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
2116 /* OP_FE010000 (); */
2121 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2122 z = (temp & IMM8) == 0;
2123 temp = temp & ~(IMM8);
2124 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2125 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2126 PSW |= (z ? PSW_Z : 0);
2130 // 1111 1010 1111 01An d8...... imm8....;
2131 // bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2132 8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
2136 /* OP_FAF40000 (); */
2141 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2142 z = (temp & (IMM8)) == 0;
2143 temp = temp & ~(IMM8);
2144 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2145 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2146 PSW |= (z ? PSW_Z : 0);
2150 // 1111 0010 1011 DmDn; asr Dm,Dn
2151 8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
2160 temp = State.regs[REG_D0 + DN0];
2162 temp >>= State.regs[REG_D0 + DM1];
2163 State.regs[REG_D0 + DN0] = temp;
2164 z = (State.regs[REG_D0 + DN0] == 0);
2165 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2166 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2167 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2171 // 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.)
2172 8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
2181 temp = State.regs[REG_D0 + DN0];
2184 State.regs[REG_D0 + DN0] = temp;
2185 z = (State.regs[REG_D0 + DN0] == 0);
2186 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2187 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2188 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2192 // 1111 0010 1010 DmDn; lsr Dm,Dn
2193 8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
2201 c = State.regs[REG_D0 + DN0] & 1;
2202 State.regs[REG_D0 + DN0]
2203 >>= State.regs[REG_D0 + DM1];
2204 z = (State.regs[REG_D0 + DN0] == 0);
2205 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2206 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2207 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2211 // 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.)
2212 8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
2220 c = State.regs[REG_D0 + DN0] & 1;
2221 State.regs[REG_D0 + DN0] >>= IMM8;
2222 z = (State.regs[REG_D0 + DN0] == 0);
2223 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2224 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2225 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2229 // 1111 0010 1001 DmDn; asl Dm,Dn
2230 8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
2238 State.regs[REG_D0 + DN0]
2239 <<= State.regs[REG_D0 + DM1];
2240 z = (State.regs[REG_D0 + DN0] == 0);
2241 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2242 PSW &= ~(PSW_Z | PSW_N);
2243 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2247 // 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.)
2248 8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
2256 State.regs[REG_D0 + DN0] <<= IMM8;
2257 z = (State.regs[REG_D0 + DN0] == 0);
2258 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2259 PSW &= ~(PSW_Z | PSW_N);
2260 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2264 // 0101 01Dn; als2 Dn
2265 4.0x5,01,2.DN0:S0:::asl2
2273 State.regs[REG_D0 + DN0] <<= 2;
2274 z = (State.regs[REG_D0 + DN0] == 0);
2275 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2276 PSW &= ~(PSW_Z | PSW_N);
2277 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2281 // 1111 0010 1000 01Dn; ror Dn
2282 8.0xf2+4.0x8,01,2.DN0:D0:::ror
2287 unsigned long value;
2291 value = State.regs[REG_D0 + DN0];
2295 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2296 State.regs[REG_D0 + DN0] = value;
2298 n = (value & 0x80000000) != 0;
2299 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2300 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2304 // 1111 0010 1000 00Dn; rol Dn
2305 8.0xf2+4.0x8,00,2.DN0:D0:::rol
2310 unsigned long value;
2314 value = State.regs[REG_D0 + DN0];
2315 c = (value & 0x80000000) ? 1 : 0;
2318 value |= ((PSW & PSW_C) != 0);
2319 State.regs[REG_D0 + DN0] = value;
2321 n = (value & 0x80000000) != 0;
2322 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2323 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2327 // 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended)
2328 8.0xc8+8.D8:S1:::beq
2336 State.regs[REG_PC] += EXTEND8 (D8);
2342 // 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended)
2343 8.0xc9+8.D8:S1:::bne
2351 State.regs[REG_PC] += EXTEND8 (D8);
2357 // 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended)
2358 8.0xc1+8.D8:S1:::bgt
2365 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2367 State.regs[REG_PC] += EXTEND8 (D8);
2373 // 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended)
2374 8.0xc2+8.D8:S1:::bge
2380 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2382 State.regs[REG_PC] += EXTEND8 (D8);
2388 // 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended)
2389 8.0xc3+8.D8:S1:::ble
2396 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2398 State.regs[REG_PC] += EXTEND8 (D8);
2404 // 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended)
2405 8.0xc0+8.D8:S1:::blt
2411 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2413 State.regs[REG_PC] += EXTEND8 (D8);
2419 // 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended)
2420 8.0xc5+8.D8:S1:::bhi
2426 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2428 State.regs[REG_PC] += EXTEND8 (D8);
2434 // 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended)
2435 8.0xc6+8.D8:S1:::bcc
2443 State.regs[REG_PC] += EXTEND8 (D8);
2449 // 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended)
2450 8.0xc7+8.D8:S1:::bls
2456 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2458 State.regs[REG_PC] += EXTEND8 (D8);
2464 // 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended)
2465 8.0xc4+8.D8:S1:::bcs
2473 State.regs[REG_PC] += EXTEND8 (D8);
2479 // 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended)
2480 8.0xf8+8.0xe8+8.D8:D1:::bvc
2488 State.regs[REG_PC] += EXTEND8 (D8);
2494 // 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended)
2495 8.0xf8+8.0xe9+8.D8:D1:::bvs
2503 State.regs[REG_PC] += EXTEND8 (D8);
2509 // 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended)
2510 8.0xf8+8.0xea+8.D8:D1:::bnc
2518 State.regs[REG_PC] += EXTEND8 (D8);
2524 // 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended)
2525 8.0xf8+8.0xeb+8.D8:D1:::bns
2533 State.regs[REG_PC] += EXTEND8 (D8);
2539 // 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended)
2540 8.0xca+8.D8:S1:::bra
2546 State.regs[REG_PC] += EXTEND8 (D8);
2560 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2575 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2589 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2591 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2604 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2606 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2620 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2622 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2635 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2637 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2650 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2652 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2667 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2680 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2682 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2697 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2710 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2722 State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
2723 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
2727 // 1111 0000 1111 01An; jmp (An)
2728 8.0xf0+4.0xf,01,2.AN0:D0:::jmp
2733 PC = State.regs[REG_A0 + AN0];
2738 // 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.)
2739 8.0xcc+8.D16A+8.D16B:S2:::jmp
2744 PC = cia + EXTEND16(FETCH16(D16A, D16B));
2749 // 1101 1100 d32........; jmp (d32, PC)
2750 8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
2754 /* OP_DC000000 (); */
2755 PC = cia + FETCH32(D32A, D32B, D32C, D32D);
2760 // 1111 0000 1111 00An; calls (An)
2761 8.0xf0+4.0xf,00,2.AN0:D0:::calls
2766 unsigned int next_pc, sp;
2769 sp = State.regs[REG_SP];
2770 next_pc = State.regs[REG_PC] + 2;
2771 store_word(sp, next_pc);
2772 State.regs[REG_MDR] = next_pc;
2773 State.regs[REG_PC] = State.regs[REG_A0 + AN0];
2778 // 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.)
2779 8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
2783 /* OP_FAFF0000 (); */
2784 unsigned int next_pc, sp;
2787 sp = State.regs[REG_SP];
2788 next_pc = State.regs[REG_PC] + 4;
2789 store_word(sp, next_pc);
2790 State.regs[REG_MDR] = next_pc;
2791 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
2796 // 1111 1100 1111 1111 d32.....; calls (d32,PC)
2797 8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
2801 /* OP_FCFF0000 (); */
2802 unsigned int next_pc, sp;
2805 sp = State.regs[REG_SP];
2806 next_pc = State.regs[REG_PC] + 6;
2807 store_word(sp, next_pc);
2808 State.regs[REG_MDR] = next_pc;
2809 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
2814 // 1111 0000 1111 1100; rets
2815 8.0xf0+8.0xfc:D0:::rets
2822 sp = State.regs[REG_SP];
2823 State.regs[REG_PC] = load_word(sp);
2828 // 1111 0000 1111 1101; rti
2829 8.0xf0+8.0xfd:D0:::rti
2836 sp = State.regs[REG_SP];
2837 PSW = load_half(sp);
2838 State.regs[REG_PC] = load_word(sp+4);
2839 State.regs[REG_SP] +=8;
2844 // 1111 0000 1111 1110; trap
2845 8.0xf0+8.0xfe:D0:::trap
2850 unsigned int sp, next_pc;
2853 sp = State.regs[REG_SP];
2854 next_pc = State.regs[REG_PC] + 2;
2855 store_word(sp, next_pc);
2860 // 1111 0000 1111 1111; rtm
2861 8.0xf0+8.0xff:D0:::rtm
2881 // 1111 0101 0000 DmDn; udf20 Dm,Dn
2882 8.0xf5+4.0x0,2.DM1,2.DN0:D0:::putx
2888 State.regs[REG_MDRQ] = State.regs[REG_D0 + DN0];
2892 // 1111 0110 1111 DmDn; udf15 Dm,Dn
2893 8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
2901 z = (State.regs[REG_MDRQ] == 0);
2902 n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
2903 State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];
2905 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2906 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2910 // 1111 0110 0000 DmDn; udf00 Dm,Dn
2911 8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
2916 unsigned long long temp;
2920 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
2921 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
2922 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2923 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
2924 z = (State.regs[REG_D0 + DN0] == 0);
2925 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2926 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2927 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2931 // 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.)
2932 8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
2937 unsigned long long temp;
2941 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
2942 * (signed64)(signed32)EXTEND8 (IMM8));
2943 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2944 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
2945 z = (State.regs[REG_D0 + DN0] == 0);
2946 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2947 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2948 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2952 // 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.)
2953 8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
2957 /* OP_FB000000 (); */
2958 unsigned long long temp;
2962 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
2963 * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
2964 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2965 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
2966 z = (State.regs[REG_D0 + DN0] == 0);
2967 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2968 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2969 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2973 // 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn
2974 8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
2978 /* OP_FD000000 (); */
2979 unsigned long long temp;
2983 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
2984 * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
2985 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2986 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
2987 z = (State.regs[REG_D0 + DN0] == 0);
2988 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2989 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2990 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2994 // 1111 0110 0001 DmDn; udf01 Dm,Dn
2995 8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
3000 unsigned long long temp;
3004 temp = ((unsigned64) State.regs[REG_D0 + DN0]
3005 * (unsigned64) State.regs[REG_D0 + DM1]);
3006 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3007 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3008 z = (State.regs[REG_D0 + DN0] == 0);
3009 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3010 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3011 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3015 // 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.)
3016 8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
3021 unsigned long long temp;
3025 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3026 * (unsigned64)EXTEND8 (IMM8));
3027 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3028 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3029 z = (State.regs[REG_D0 + DN0] == 0);
3030 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3031 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3032 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3036 // 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.)
3037 8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
3041 /* OP_FB140000 (); */
3042 unsigned long long temp;
3046 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3047 * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
3048 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3049 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3050 z = (State.regs[REG_D0 + DN0] == 0);
3051 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3052 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3053 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3057 // 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn
3058 8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
3062 /* OP_FD140000 (); */
3063 unsigned long long temp;
3067 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3068 * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3069 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3070 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3071 z = (State.regs[REG_D0 + DN0] == 0);
3072 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3073 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3074 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3078 // 1111 0110 0100 DmDn; udf04 Dm,Dn
3079 8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
3087 temp = State.regs[REG_D0 + DM1];
3088 temp = (temp > 0x7fff ? 0x7fff : temp);
3089 temp = (temp < -0x8000 ? -0x8000 : temp);
3090 State.regs[REG_D0 + DN0] = temp;
3094 // 1111 0110 0101 DmDn; udf05 Dm,Dn
3095 8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
3103 temp = State.regs[REG_D0 + DM1];
3104 temp = (temp > 0x7fffff ? 0x7fffff : temp);
3105 temp = (temp < -0x800000 ? -0x800000 : temp);
3106 State.regs[REG_D0 + DN0] = temp;
3110 // 1111 0110 0111 DmDn; udf07 Dm,Dn
3111 8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
3119 temp = State.regs[REG_D0 + DM1];
3120 temp <<= (State.regs[REG_D0 + DN0] & 0x1f);
3121 c = (temp != 0 ? 1 : 0);
3123 PSW |= (c ? PSW_C : 0);
3127 // 1111 0000 1100 0000; syscall
3128 8.0xf0+8.0xc0:D0:::syscall
3145 program_interrupt(SD, CPU, cia, SIM_SIGTRAP);
3148 // 1100 1110 regs....; movm (SP),regs
3149 8.0xce+8.REGS:S1:::movm
3154 unsigned long sp = State.regs[REG_SP];
3163 State.regs[REG_LAR] = load_word (sp);
3165 State.regs[REG_LIR] = load_word (sp);
3167 State.regs[REG_MDR] = load_word (sp);
3169 State.regs[REG_A0 + 1] = load_word (sp);
3171 State.regs[REG_A0] = load_word (sp);
3173 State.regs[REG_D0 + 1] = load_word (sp);
3175 State.regs[REG_D0] = load_word (sp);
3181 State.regs[REG_A0 + 3] = load_word (sp);
3187 State.regs[REG_A0 + 2] = load_word (sp);
3193 State.regs[REG_D0 + 3] = load_word (sp);
3199 State.regs[REG_D0 + 2] = load_word (sp);
3204 /* And make sure to update the stack pointer. */
3205 State.regs[REG_SP] = sp;
3209 // 1100 1111 regs....; movm regs,(SP)
3210 8.0xcf+8.REGS:S1a:::movm
3215 unsigned long sp = State.regs[REG_SP];
3225 store_word (sp, State.regs[REG_D0 + 2]);
3231 store_word (sp, State.regs[REG_D0 + 3]);
3237 store_word (sp, State.regs[REG_A0 + 2]);
3243 store_word (sp, State.regs[REG_A0 + 3]);
3249 store_word (sp, State.regs[REG_D0]);
3251 store_word (sp, State.regs[REG_D0 + 1]);
3253 store_word (sp, State.regs[REG_A0]);
3255 store_word (sp, State.regs[REG_A0 + 1]);
3257 store_word (sp, State.regs[REG_MDR]);
3259 store_word (sp, State.regs[REG_LIR]);
3261 store_word (sp, State.regs[REG_LAR]);
3265 /* And make sure to update the stack pointer. */
3266 State.regs[REG_SP] = sp;
3269 // 1100 1101 d16..... regs.... imm8....;
3270 // call (d16,PC),regs,imm8 (d16 is sign-extended., imm8 is zero-extended.)
3271 8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
3275 /* OP_CD000000 (); */
3276 unsigned int next_pc, sp;
3280 sp = State.regs[REG_SP];
3282 store_word(sp, next_pc);
3290 store_word (sp, State.regs[REG_D0 + 2]);
3296 store_word (sp, State.regs[REG_D0 + 3]);
3302 store_word (sp, State.regs[REG_A0 + 2]);
3308 store_word (sp, State.regs[REG_A0 + 3]);
3314 store_word (sp, State.regs[REG_D0]);
3316 store_word (sp, State.regs[REG_D0 + 1]);
3318 store_word (sp, State.regs[REG_A0]);
3320 store_word (sp, State.regs[REG_A0 + 1]);
3322 store_word (sp, State.regs[REG_MDR]);
3324 store_word (sp, State.regs[REG_LIR]);
3326 store_word (sp, State.regs[REG_LAR]);
3330 /* Update the stack pointer, note that the register saves to do not
3331 modify SP. The SP adjustment is derived totally from the imm8
3333 State.regs[REG_SP] -= IMM8;
3334 State.regs[REG_MDR] = next_pc;
3335 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
3340 // 1101 1101 d32..... regs.... imm8....;
3341 // call (d32,PC),regs,imm8 (imm8 is zero-extended.)
3342 8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
3346 /* OP_DD000000 (); */
3347 unsigned int next_pc, sp;
3351 sp = State.regs[REG_SP];
3352 next_pc = State.regs[REG_PC] + 7;
3353 /* could assert that nia == next_pc here */
3354 store_word(sp, next_pc);
3362 store_word (sp, State.regs[REG_D0 + 2]);
3368 store_word (sp, State.regs[REG_D0 + 3]);
3374 store_word (sp, State.regs[REG_A0 + 2]);
3380 store_word (sp, State.regs[REG_A0 + 3]);
3386 store_word (sp, State.regs[REG_D0]);
3388 store_word (sp, State.regs[REG_D0 + 1]);
3390 store_word (sp, State.regs[REG_A0]);
3392 store_word (sp, State.regs[REG_A0 + 1]);
3394 store_word (sp, State.regs[REG_MDR]);
3396 store_word (sp, State.regs[REG_LIR]);
3398 store_word (sp, State.regs[REG_LAR]);
3402 /* Update the stack pointer, note that the register saves to do not
3403 modify SP. The SP adjustment is derived totally from the imm8
3405 State.regs[REG_SP] -= IMM8;
3406 State.regs[REG_MDR] = next_pc;
3407 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
3412 // 1101 1111 regs.... imm8....; ret regs,imm8 (imm8 is zero-extended.)
3413 8.0xdf+8.REGS+8.IMM8:S2:::ret
3418 unsigned int sp, offset;
3422 State.regs[REG_SP] += IMM8;
3423 sp = State.regs[REG_SP];
3431 State.regs[REG_D0 + 2] = load_word (sp + offset);
3437 State.regs[REG_D0 + 3] = load_word (sp + offset);
3443 State.regs[REG_A0 + 2] = load_word (sp + offset);
3449 State.regs[REG_A0 + 3] = load_word (sp + offset);
3455 State.regs[REG_D0] = load_word (sp + offset);
3457 State.regs[REG_D0 + 1] = load_word (sp + offset);
3459 State.regs[REG_A0] = load_word (sp + offset);
3461 State.regs[REG_A0 + 1] = load_word (sp + offset);
3463 State.regs[REG_MDR] = load_word (sp + offset);
3465 State.regs[REG_LIR] = load_word (sp + offset);
3467 State.regs[REG_LAR] = load_word (sp + offset);
3471 /* Restore the PC value. */
3472 State.regs[REG_PC] = load_word(sp);
3477 // 1101 1110 regs.... imm8....; retf regs,imm8 (imm8 is zero-extended.)
3478 8.0xde+8.REGS+8.IMM8:S2:::retf
3483 unsigned int sp, offset;
3487 State.regs[REG_SP] += IMM8;
3488 sp = State.regs[REG_SP];
3489 State.regs[REG_PC] = State.regs[REG_MDR];
3497 State.regs[REG_D0 + 2] = load_word (sp + offset);
3503 State.regs[REG_D0 + 3] = load_word (sp + offset);
3509 State.regs[REG_A0 + 2] = load_word (sp + offset);
3515 State.regs[REG_A0 + 3] = load_word (sp + offset);
3521 State.regs[REG_D0] = load_word (sp + offset);
3523 State.regs[REG_D0 + 1] = load_word (sp + offset);
3525 State.regs[REG_A0] = load_word (sp + offset);
3527 State.regs[REG_A0 + 1] = load_word (sp + offset);
3529 State.regs[REG_MDR] = load_word (sp + offset);
3531 State.regs[REG_LIR] = load_word (sp + offset);
3533 State.regs[REG_LAR] = load_word (sp + offset);