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* mn10300.igen (OP_F0F4): Need to load contents of register AN0
[deliverable/binutils-gdb.git] / sim / mn10300 / mn10300.igen
1 // -*- C -*-
2 :option:::insn-bit-size:8
3 :option:::insn-specifying-widths:true
4 :option:::hi-bit-nr:7
5 :model:::mn10300:mn10300:
6 :model:::am33:am33:
7
8 // What do we do with an illegal instruction?
9 :internal::::illegal:
10 {
11 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
12 (unsigned long) cia);
13 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
14 }
15
16 // 1000 DnDn imm8....; mov imm8,Dn (imm8 is sign extended)
17 4.0x8,2.DM1,2.DN0=DM1+8.IMM8:S0i:::mov
18 "mov"
19 *mn10300
20 // start-sanitize-am33
21 *am33
22 // end-sanitize-am33
23 {
24 /* OP_8000 (); */
25 signed32 immed = EXTEND8 (IMM8);
26 State.regs[REG_D0+DN0] = immed;
27 PC = cia;
28 }
29
30 // 1000 DmDn; mov Dm,Dn (Dm != Dn, see above when Dm == Dn)
31 4.0x8,2.DM1,2.DN0!DM1:S0:::mov
32 "mov"
33 *mn10300
34 // start-sanitize-am33
35 *am33
36 // end-sanitize-am33
37 {
38 PC = cia;
39 /* OP_80 (); */
40 State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1];
41 }
42
43
44 // 1111 0001 1110 DmAn; mov Dm,An
45 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
46 "mov"
47 *mn10300
48 // start-sanitize-am33
49 *am33
50 // end-sanitize-am33
51 {
52 /* OP_F1E0 (); */
53 PC = cia;
54 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1];
55 }
56
57
58 // 1111 0001 1101 AmDn; mov Am,Dn
59 8.0xf1+1101,2.AM1,2.DN0:D0a:::mov
60 "mov"
61 *mn10300
62 // start-sanitize-am33
63 *am33
64 // end-sanitize-am33
65 {
66 /* OP_F1D0 (); */
67 PC = cia;
68 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1];
69 }
70
71
72 // 1001 AnAn imm8....; mov imm8,An (imm8 is zero-extended)
73 4.0x9,2.AM1,2.AN0=AM1+8.IMM8:S0ai:::mov
74 "mov"
75 *mn10300
76 // start-sanitize-am33
77 *am33
78 // end-sanitize-am33
79 {
80 PC = cia;
81 /* OP_9000 (); */
82 State.regs[REG_A0+AN0] = IMM8;
83 }
84
85
86 // 1001 AmAn; mov Am,An (Am != An, save above when Am == An)
87 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
88 "mov"
89 *mn10300
90 // start-sanitize-am33
91 *am33
92 // end-sanitize-am33
93 {
94 PC = cia;
95 /* OP_90 (); */
96 State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1];
97 }
98
99
100 // 0011 11An; mov SP,An
101 4.0x3,11,2.AN0:S0b:::mov
102 "mov"
103 *mn10300
104 // start-sanitize-am33
105 *am33
106 // end-sanitize-am33
107 {
108 /* OP_3C (); */
109 PC = cia;
110 State.regs[REG_A0 + AN0] = State.regs[REG_SP];
111 }
112
113
114 // 1111 0010 1111 Am00; mov Am,SP
115 8.0xf2+4.0xf,2.AM1,00:D0b:::mov
116 "mov"
117 *mn10300
118 // start-sanitize-am33
119 *am33
120 // end-sanitize-am33
121 {
122 /* OP_F2F0 (); */
123 PC = cia;
124 State.regs[REG_SP] = State.regs[REG_A0 + AM1];
125 }
126
127
128 // 1111 0010 1110 01Dn; mov PSW,Dn
129 8.0xf2+4.0xe,01,2.DN0:D0c:::mov
130 "mov"
131 *mn10300
132 // start-sanitize-am33
133 *am33
134 // end-sanitize-am33
135 {
136 /* OP_F2E4 (); */
137 PC = cia;
138 State.regs[REG_D0 + DN0] = PSW;
139 }
140
141
142 // 1111 0010 1111 Dm11; mov Dm,PSW
143 8.0xf2+4.0xf,2.DM1,11:D0d:::mov
144 "mov"
145 *mn10300
146 // start-sanitize-am33
147 *am33
148 // end-sanitize-am33
149 {
150 /* OP_F2F3 (); */
151 PC = cia;
152 PSW = State.regs[REG_D0 + DM1];
153 }
154
155
156 // 1111 0010 1110 00Dn; mov MDR,Dn
157 8.0xf2+4.0xe,00,2.DN0:D0e:::mov
158 "mov"
159 *mn10300
160 // start-sanitize-am33
161 *am33
162 // end-sanitize-am33
163 {
164 /* OP_F2E0 (); */
165 PC = cia;
166 State.regs[REG_D0 + DN0] = State.regs[REG_MDR];
167 }
168
169
170 // 1111 0010 1111 Dm10; mov Dm,MDR
171 8.0xf2+4.0xf,2.DM1,10:D0f:::mov
172 "mov"
173 *mn10300
174 // start-sanitize-am33
175 *am33
176 // end-sanitize-am33
177 {
178 /* OP_F2F2 (); */
179 PC = cia;
180 State.regs[REG_MDR] = State.regs[REG_D0 + DM1];
181 }
182
183
184 // 0111 DnAm; mov (Am),Dn
185 4.0x7,2.DN1,2.AM0:S0c:::mov
186 "mov"
187 *mn10300
188 // start-sanitize-am33
189 *am33
190 // end-sanitize-am33
191 {
192 /* OP_70 (); */
193 PC = cia;
194 State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]);
195 }
196
197
198 // 1111 1000 0000 DnAm d8......; mov (d8,Am),Dn (d8 is sign-extended)
199 8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
200 "mov"
201 *mn10300
202 // start-sanitize-am33
203 *am33
204 // end-sanitize-am33
205 {
206 /* OP_F80000 (); */
207 PC = cia;
208 State.regs[REG_D0 + DN1]
209 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
210 }
211
212
213 // 1111 1010 0000 DnAm d16.....; mov (d16,Am),Dn (d16 is sign-extended.)
214 8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
215 "mov"
216 *mn10300
217 // start-sanitize-am33
218 *am33
219 // end-sanitize-am33
220 {
221 /* OP_FA000000 (); */
222 PC = cia;
223 State.regs[REG_D0 + DN1]
224 = load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B))));
225 }
226
227
228 // 1111 1100 0000 DnAm d32.....; mov (d32,Am),Dn
229 8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
230 "mov"
231 *mn10300
232 // start-sanitize-am33
233 *am33
234 // end-sanitize-am33
235 {
236 /* OP_FC000000 (); */
237 PC = cia;
238 State.regs[REG_D0 + DN1]
239 = load_word ((State.regs[REG_A0 + AM0]
240 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
241 }
242
243
244 // 0101 10Dn d8......; mov (d8,SP),Dn (d8 is zero-extended)
245 4.0x5,10,2.DN0+8.D8:S1:::mov
246 "mov"
247 *mn10300
248 // start-sanitize-am33
249 *am33
250 // end-sanitize-am33
251 {
252 /* OP_5800 (); */
253 PC = cia;
254 State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8);
255 }
256
257
258 // 1111 1010 1011 01Dn d16.....; mov (d16,SP),Dn (d16 is zero-extended.)
259 8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
260 "mov"
261 *mn10300
262 // start-sanitize-am33
263 *am33
264 // end-sanitize-am33
265 {
266 /* OP_FAB40000 (); */
267 PC = cia;
268 State.regs[REG_D0 + DN0]
269 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
270 }
271
272
273 // 1111 1010 1011 01Dn d32.....; mov (d32,SP),Dn
274 8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
275 "mov"
276 *mn10300
277 // start-sanitize-am33
278 *am33
279 // end-sanitize-am33
280 {
281 /* OP_FCB40000 (); */
282 PC = cia;
283 State.regs[REG_D0 + DN0]
284 = load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
285 }
286
287
288 // 1111 0011 00Dn DiAm; mov (Di,Am),Dn
289 8.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov
290 "mov"
291 *mn10300
292 // start-sanitize-am33
293 *am33
294 // end-sanitize-am33
295 {
296 /* OP_F300 (); */
297 PC = cia;
298 State.regs[REG_D0 + DN2]
299 = load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
300 }
301
302
303 // 0011 00Dn abs16...; mov (abs16),Dn (abs16 is zero-extended)
304 4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
305 "mov"
306 *mn10300
307 // start-sanitize-am33
308 *am33
309 // end-sanitize-am33
310 {
311 /* OP_300000 (); */
312 PC = cia;
313 State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B));
314 }
315
316 // 1111 1100 1010 01Dn abs32...; mov (abs32),Dn
317 8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
318 "mov"
319 *mn10300
320 // start-sanitize-am33
321 *am33
322 // end-sanitize-am33
323 {
324 /* OP_FCA40000 (); */
325 PC = cia;
326 State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
327 }
328
329
330 // 1111 0000 0000 AnAm; mov (Am),An
331 8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
332 "mov"
333 *mn10300
334 // start-sanitize-am33
335 *am33
336 // end-sanitize-am33
337 {
338 /* OP_F000 (); */
339 PC = cia;
340 State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]);
341 }
342
343
344 // 1111 1000 0010 AnAm d8......; mov (d8,Am),An (d8 is sign-extended)
345 8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
346 "mov"
347 *mn10300
348 // start-sanitize-am33
349 *am33
350 // end-sanitize-am33
351 {
352 /* OP_F82000 (); */
353 PC = cia;
354 State.regs[REG_A0 + AN1]
355 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
356 }
357
358
359 // 1111 1010 0010 AnAm d16.....; mov (d16,Am),An (d16 is sign-extended.)
360 8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
361 "mov"
362 *mn10300
363 // start-sanitize-am33
364 *am33
365 // end-sanitize-am33
366 {
367 /* OP_FA200000 (); */
368 PC = cia;
369 State.regs[REG_A0 + AN1]
370 = load_word ((State.regs[REG_A0 + AM0]
371 + EXTEND16 (FETCH16(D16A, D16B))));
372 }
373
374
375 // 1111 1100 0010 AnAm d32.....; mov (d32,Am),An
376 8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
377 "mov"
378 *mn10300
379 // start-sanitize-am33
380 *am33
381 // end-sanitize-am33
382 {
383 /* OP_FC200000 (); */
384 PC = cia;
385 State.regs[REG_A0 + AN1]
386 = load_word ((State.regs[REG_A0 + AM0]
387 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
388 }
389
390
391 // 0101 11An d8......; mov (d8,SP),An (d8 is zero-extended)
392 4.0x5,11,2.AN0+8.D8:S1a:::mov
393 "mov"
394 *mn10300
395 // start-sanitize-am33
396 *am33
397 // end-sanitize-am33
398 {
399 /* OP_5C00 (); */
400 PC = cia;
401 State.regs[REG_A0 + AN0]
402 = load_word (State.regs[REG_SP] + D8);
403 }
404
405
406 // 1111 1010 1011 00An d16.....; mov (d16,SP),An (d16 is zero-extended.)
407 8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
408 "mov"
409 *mn10300
410 // start-sanitize-am33
411 *am33
412 // end-sanitize-am33
413 {
414 /* OP_FAB00000 (); */
415 PC = cia;
416 State.regs[REG_A0 + AN0]
417 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
418 }
419
420
421 // 1111 1100 1011 00An d32.....; mov (d32,SP),An
422 8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
423 "mov"
424 *mn10300
425 // start-sanitize-am33
426 *am33
427 // end-sanitize-am33
428 {
429 /* OP_FCB00000 (); */
430 PC = cia;
431 State.regs[REG_A0 + AN0]
432 = load_word (State.regs[REG_SP]
433 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
434 }
435
436
437 // 1111 0011 10An DiAm; mov (Di,Am),An
438 8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
439 "mov"
440 *mn10300
441 // start-sanitize-am33
442 *am33
443 // end-sanitize-am33
444 {
445 /* OP_F380 (); */
446 PC = cia;
447 State.regs[REG_A0 + AN2]
448 = load_word ((State.regs[REG_A0 + AM0]
449 + State.regs[REG_D0 + DI]));
450 }
451
452
453 // 1111 1010 1010 00An abs16...; mov (abs16),An (abs16 is zero-extended)
454 8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
455 "mov"
456 *mn10300
457 // start-sanitize-am33
458 *am33
459 // end-sanitize-am33
460 {
461 /* OP_FAA00000 (); */
462 PC = cia;
463 State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B));
464 }
465
466
467 // 1111 1100 1010 00An abs32...; mov (abs32),An
468 8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
469 "mov"
470 *mn10300
471 // start-sanitize-am33
472 *am33
473 // end-sanitize-am33
474 {
475 /* OP_FCA00000 (); */
476 PC = cia;
477 State.regs[REG_A0 + AN0]
478 = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
479 }
480
481
482 // 1111 1000 1111 00Am d8......; mov (d8,Am),SP (d8 is sign-extended)
483 8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
484 "mov"
485 *mn10300
486 // start-sanitize-am33
487 *am33
488 // end-sanitize-am33
489 {
490 /* OP_F8F000 (); */
491 PC = cia;
492 State.regs[REG_SP]
493 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
494 }
495
496
497 // 0110 DmAn; mov Dm,(An)
498 4.0x6,2.DM1,2.AN0:S0d:::mov
499 "mov"
500 *mn10300
501 // start-sanitize-am33
502 *am33
503 // end-sanitize-am33
504 {
505 /* OP_60 (); */
506 PC = cia;
507 store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
508 }
509
510
511 // 1111 1000 0001 DmAn d8......; mov Dm,(d8,An) (d8 is sign-extended)
512 8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
513 "mov"
514 *mn10300
515 // start-sanitize-am33
516 *am33
517 // end-sanitize-am33
518 {
519 /* OP_F81000 (); */
520 PC = cia;
521 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
522 State.regs[REG_D0 + DM1]);
523 }
524
525
526 // 1111 1010 0001 DmAn d16.....; mov Dm,(d16,An) (d16 is sign-extended.)
527 8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
528 "mov"
529 *mn10300
530 // start-sanitize-am33
531 *am33
532 // end-sanitize-am33
533 {
534 /* OP_FA100000 (); */
535 PC = cia;
536 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
537 State.regs[REG_D0 + DM1]);
538 }
539
540
541 // 1111 1100 0001 DmAn d32.....; mov Dm,(d32,An)
542 8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
543 "mov"
544 *mn10300
545 // start-sanitize-am33
546 *am33
547 // end-sanitize-am33
548 {
549 /* OP_FC100000 (); */
550 PC = cia;
551 store_word ((State.regs[REG_A0 + AN0]
552 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
553 State.regs[REG_D0 + DM1]);
554 }
555
556
557 // 0100 Dm10 d8......; mov Dm,(d8,SP) (d8 is zero-extended)
558 4.0x4,2.DM1,10+8.D8:S1b:::mov
559 "mov"
560 *mn10300
561 // start-sanitize-am33
562 *am33
563 // end-sanitize-am33
564 {
565 /* OP_4200 (); */
566 PC = cia;
567 store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]);
568 }
569
570
571 // 1111 1010 1001 Dm01 d16.....; mov Dm,(d16,SP) (d16 is zero-extended.)
572 8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
573 "mov"
574 *mn10300
575 // start-sanitize-am33
576 *am33
577 // end-sanitize-am33
578 {
579 /* OP_FA910000 (); */
580 PC = cia;
581 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
582 State.regs[REG_D0 + DM1]);
583 }
584
585
586 // 1111 1100 1001 Dm01 d32.....; mov Dm,(d32,SP)
587 8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
588 "mov"
589 *mn10300
590 // start-sanitize-am33
591 *am33
592 // end-sanitize-am33
593 {
594 /* OP_FC910000 (); */
595 PC = cia;
596 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
597 State.regs[REG_D0 + DM1]);
598 }
599
600
601 // 1111 0011 01Dm DiAn; mov Dm,(Di,An)
602 8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
603 "mov"
604 *mn10300
605 // start-sanitize-am33
606 *am33
607 // end-sanitize-am33
608 {
609 /* OP_F340 (); */
610 PC = cia;
611 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
612 State.regs[REG_D0 + DM2]);
613 }
614
615
616 // 0000 Dm01 abs16..., mov Dm,(abs16) (abs16 is zero-extended).
617 4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
618 "mov"
619 *mn10300
620 // start-sanitize-am33
621 *am33
622 // end-sanitize-am33
623 {
624 /* OP_10000 (); */
625 PC = cia;
626 store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
627 }
628
629
630 // 1111 1100 1000 Dm01 abs32...; mov Dm,(abs32)
631 8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
632 "mov"
633 *mn10300
634 // start-sanitize-am33
635 *am33
636 // end-sanitize-am33
637 {
638 /* OP_FC810000 (); */
639 PC = cia;
640 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
641 State.regs[REG_D0 + DM1]);
642 }
643
644
645 // 1111 0000 0001 AmAn; mov Am,(An)
646 8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
647 "mov"
648 *mn10300
649 // start-sanitize-am33
650 *am33
651 // end-sanitize-am33
652 {
653 /* OP_F010 (); */
654 PC = cia;
655 store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]);
656 }
657
658
659 // 1111 1000 0011 AmAn d8......; mov Am,(d8,An) (d8 is sign-extended)
660 8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
661 "mov"
662 *mn10300
663 // start-sanitize-am33
664 *am33
665 // end-sanitize-am33
666 {
667 /* OP_F83000 (); */
668 PC = cia;
669 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
670 State.regs[REG_A0 + AM1]);
671 }
672
673
674 // 1111 1010 0011 AmAn d16.....; mov Am,(d16,An) (d16 is sign-extended.)
675 8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
676 "mov"
677 *mn10300
678 // start-sanitize-am33
679 *am33
680 // end-sanitize-am33
681 {
682 /* OP_FA300000 (); */
683 PC = cia;
684 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
685 State.regs[REG_A0 + AM1]);
686 }
687
688
689 // 1111 1100 0011 AmAn d32.....; mov Am,(d32,An)
690 8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
691 "mov"
692 *mn10300
693 // start-sanitize-am33
694 *am33
695 // end-sanitize-am33
696 {
697 /* OP_FC300000 (); */
698 PC = cia;
699 store_word ((State.regs[REG_A0 + AN0]
700 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
701 State.regs[REG_A0 + AM1]);
702 }
703
704
705 // 0100 Am11 d8......; mov Am,(d8,SP) (d8 is zero-extended)
706 4.0x4,2.AM1,11+8.D8:S1c:::mov
707 "mov"
708 *mn10300
709 // start-sanitize-am33
710 *am33
711 // end-sanitize-am33
712 {
713 /* OP_4300 (); */
714 PC = cia;
715 store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]);
716 }
717
718
719 // 1111 1010 1001 Am00 d16.....; mov Am,(d16,SP) (d16 is zero-extended.)
720 8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
721 "mov"
722 *mn10300
723 // start-sanitize-am33
724 *am33
725 // end-sanitize-am33
726 {
727 /* OP_FA900000 (); */
728 PC = cia;
729 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
730 State.regs[REG_A0 + AM1]);
731 }
732
733
734 // 1111 1100 1001 Am00 d32.....; mov Am,(d32,SP)
735 8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
736 "mov"
737 *mn10300
738 // start-sanitize-am33
739 *am33
740 // end-sanitize-am33
741 {
742 /* OP_FC900000 (); */
743 PC = cia;
744 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
745 State.regs[REG_A0 + AM1]);
746 }
747
748
749 // 1111 0011 11Am DiAn; mov Am,(Di,An)
750 8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
751 "mov"
752 *mn10300
753 // start-sanitize-am33
754 *am33
755 // end-sanitize-am33
756 {
757 /* OP_F3C0 (); */
758 PC = cia;
759 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
760 State.regs[REG_A0 + AM2]);
761 }
762
763
764 // 1111 1010 1000 Am00 abs16...; mov Am,(abs16) (abs16 is zero-extended)
765 8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
766 "mov"
767 *mn10300
768 // start-sanitize-am33
769 *am33
770 // end-sanitize-am33
771 {
772 /* OP_FA800000 (); */
773 PC = cia;
774 store_word (FETCH16(IMM16A, IMM16B),
775 State.regs[REG_A0 + AM1]);
776 }
777
778
779 // 1111 1100 1000 Am00 abs32...; mov Am,(abs32)
780 8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
781 "mov"
782 *mn10300
783 // start-sanitize-am33
784 *am33
785 // end-sanitize-am33
786 {
787 /* OP_FC800000 (); */
788 PC = cia;
789 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
790 State.regs[REG_A0 + AM1]);
791 }
792
793
794 // 1111 1000 1111 01An d8......; mov SP,(d8,An) (d8 is sign-extended)
795 8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
796 "mov"
797 *mn10300
798 // start-sanitize-am33
799 *am33
800 // end-sanitize-am33
801 {
802 /* OP_F8F400 (); */
803 PC = cia;
804 store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8),
805 State.regs[REG_SP]);
806 }
807
808
809 // 0010 11Dn imm16...; mov imm16,Dn (imm16 is sign-extended)
810 4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
811 "mov"
812 *mn10300
813 // start-sanitize-am33
814 *am33
815 // end-sanitize-am33
816 {
817 /* OP_2C0000 (); */
818 unsigned long value;
819
820 PC = cia;
821 value = EXTEND16 (FETCH16(IMM16A, IMM16B));
822 State.regs[REG_D0 + DN0] = value;
823 }
824
825
826 // 1111 1100 1100 11Dn imm32...; mov imm32,Dn
827 8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
828 "mov"
829 *mn10300
830 // start-sanitize-am33
831 *am33
832 // end-sanitize-am33
833 {
834 /* OP_FCCC0000 (); */
835 unsigned long value;
836
837 PC = cia;
838 value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
839 State.regs[REG_D0 + DN0] = value;
840 }
841
842
843 // 0010 01An imm16...; mov imm16,An (imm16 is zero-extended)
844 4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
845 "mov"
846 *mn10300
847 // start-sanitize-am33
848 *am33
849 // end-sanitize-am33
850 {
851 /* OP_240000 (); */
852 unsigned long value;
853
854 PC = cia;
855 value = FETCH16(IMM16A, IMM16B);
856 State.regs[REG_A0 + AN0] = value;
857 }
858
859
860 // 1111 1100 1101 11An imm32...; mov imm32,An
861 8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
862 "mov"
863 *mn10300
864 // start-sanitize-am33
865 *am33
866 // end-sanitize-am33
867 {
868 /* OP_FCDC0000 (); */
869 PC = cia;
870 State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
871 }
872
873
874 // 1111 0000 0100 DnAm; movbu (Am),Dn
875 8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
876 "movbu"
877 *mn10300
878 // start-sanitize-am33
879 *am33
880 // end-sanitize-am33
881 {
882 /* OP_F040 (); */
883 PC = cia;
884 State.regs[REG_D0 + DN1]
885 = load_byte (State.regs[REG_A0 + AM0]);
886 }
887
888
889 // 1111 1000 0100 DnAm d8......; movbu (d8,Am),Dn (d8 is sign-extended)
890 8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
891 "movbu"
892 *mn10300
893 // start-sanitize-am33
894 *am33
895 // end-sanitize-am33
896 {
897 /* OP_F84000 (); */
898 PC = cia;
899 State.regs[REG_D0 + DN1]
900 = load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
901 }
902
903
904 // 1111 1010 0100 DnAm d16.....; movbu (d16,Am),Dn (d16 is sign-extended.)
905 8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
906 "movbu"
907 *mn10300
908 // start-sanitize-am33
909 *am33
910 // end-sanitize-am33
911 {
912 /* OP_FA400000 (); */
913 PC = cia;
914 State.regs[REG_D0 + DN1]
915 = load_byte ((State.regs[REG_A0 + AM0]
916 + EXTEND16 (FETCH16(D16A, D16B))));
917 }
918
919
920 // 1111 1100 0100 DnAm d32.....; movbu (d32,Am),Dn
921 8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
922 "movbu"
923 *mn10300
924 // start-sanitize-am33
925 *am33
926 // end-sanitize-am33
927 {
928 /* OP_FC400000 (); */
929 PC = cia;
930 State.regs[REG_D0 + DN1]
931 = load_byte ((State.regs[REG_A0 + AM0]
932 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
933 }
934
935
936 // 1111 1000 1011 10Dn d8......; movbu (d8,SP),Dn (d8 is zero-extended)
937 8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
938 "movbu"
939 *mn10300
940 // start-sanitize-am33
941 *am33
942 // end-sanitize-am33
943 {
944 /* OP_F8B800 (); */
945 PC = cia;
946 State.regs[REG_D0 + DN0]
947 = load_byte ((State.regs[REG_SP] + (D8)));
948 }
949
950
951 // 1111 1010 1011 10Dn d16.....; movbu (d16,SP),Dn (d16 is zero-extended.)
952 8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
953 "movbu"
954 *mn10300
955 // start-sanitize-am33
956 *am33
957 // end-sanitize-am33
958 {
959 /* OP_FAB80000 (); */
960 PC = cia;
961 State.regs[REG_D0 + DN0]
962 = load_byte ((State.regs[REG_SP]
963 + FETCH16(IMM16A, IMM16B)));
964 }
965
966
967 // 1111 1100 1011 10Dn d32.....; movbu (d32,SP),Dn
968 8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
969 "movbu"
970 *mn10300
971 // start-sanitize-am33
972 *am33
973 // end-sanitize-am33
974 {
975 /* OP_FCB80000 (); */
976 PC = cia;
977 State.regs[REG_D0 + DN0]
978 = load_byte (State.regs[REG_SP]
979 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
980 }
981
982
983 // 1111 0100 00Dn DiAm; movbu (Di,Am),Dn
984 8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
985 "movbu"
986 *mn10300
987 // start-sanitize-am33
988 *am33
989 // end-sanitize-am33
990 {
991 /* OP_F400 (); */
992 PC = cia;
993 State.regs[REG_D0 + DN2]
994 = load_byte ((State.regs[REG_A0 + AM0]
995 + State.regs[REG_D0 + DI]));
996 }
997
998
999 // 0011 01Dn abs16...; movbu (abs16),Dn (abs16 is zero-extended)
1000 4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
1001 "movbu"
1002 *mn10300
1003 // start-sanitize-am33
1004 *am33
1005 // end-sanitize-am33
1006 {
1007 /* OP_340000 (); */
1008 PC = cia;
1009 State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B));
1010 }
1011
1012
1013 // 1111 1100 1010 10Dn abs32...; movbu (abs32),Dn
1014 8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
1015 "movbu"
1016 *mn10300
1017 // start-sanitize-am33
1018 *am33
1019 // end-sanitize-am33
1020 {
1021 /* OP_FCA80000 (); */
1022 PC = cia;
1023 State.regs[REG_D0 + DN0]
1024 = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1025 }
1026
1027
1028 // 1111 0000 0101 DmAn; movbu Dm,(An)
1029 8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
1030 "movbu"
1031 *mn10300
1032 // start-sanitize-am33
1033 *am33
1034 // end-sanitize-am33
1035 {
1036 /* OP_F050 (); */
1037 PC = cia;
1038 store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
1039 }
1040
1041
1042 // 1111 1000 0101 DmAn d8......; movbu Dm,(d8,An) (d8 is sign-extended)
1043 8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
1044 "movbu"
1045 *mn10300
1046 // start-sanitize-am33
1047 *am33
1048 // end-sanitize-am33
1049 {
1050 /* OP_F85000 (); */
1051 PC = cia;
1052 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1053 State.regs[REG_D0 + DM1]);
1054 }
1055
1056
1057 // 1111 1010 0101 DmAn d16.....; movbu Dm,(d16,An) (d16 is sign-extended.)
1058 8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
1059 "movbu"
1060 *mn10300
1061 // start-sanitize-am33
1062 *am33
1063 // end-sanitize-am33
1064 {
1065 /* OP_FA500000 (); */
1066 PC = cia;
1067 store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1068 State.regs[REG_D0 + DM1]);
1069 }
1070
1071
1072 // 1111 1100 0101 DmAn d32.....; movbu Dm,(d32,An)
1073 8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
1074 "movbu"
1075 *mn10300
1076 // start-sanitize-am33
1077 *am33
1078 // end-sanitize-am33
1079 {
1080 /* OP_FC500000 (); */
1081 PC = cia;
1082 store_byte ((State.regs[REG_A0 + AN0]
1083 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1084 State.regs[REG_D0 + DM1]);
1085 }
1086
1087
1088 // 1111 1000 1001 Dm10 d8......; movbu Dm,(d8,SP) (d8 is zero-extended)
1089 8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
1090 "movbu"
1091 *mn10300
1092 // start-sanitize-am33
1093 *am33
1094 // end-sanitize-am33
1095 {
1096 /* OP_F89200 (); */
1097 PC = cia;
1098 store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]);
1099 }
1100
1101
1102 // 1111 1010 1001 Dm10 d16.....; movbu Dm,(d16,SP) (d16 is zero-extended.)
1103 8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
1104 "movbu"
1105 *mn10300
1106 // start-sanitize-am33
1107 *am33
1108 // end-sanitize-am33
1109 {
1110 /* OP_FA920000 (); */
1111 PC = cia;
1112 store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1113 State.regs[REG_D0 + DM1]);
1114 }
1115
1116
1117 // 1111 1100 1001 Dm10 d32.....; movbu Dm,(d32,SP)
1118 8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
1119 "movbu"
1120 *mn10300
1121 // start-sanitize-am33
1122 *am33
1123 // end-sanitize-am33
1124 {
1125 /* OP_FC920000 (); */
1126 PC = cia;
1127 store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1128 State.regs[REG_D0 + DM1]);
1129 }
1130
1131
1132 // 1111 0100 01Dm DiAn; movbu Dm,(Di,An)
1133 8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
1134 "movbu"
1135 *mn10300
1136 // start-sanitize-am33
1137 *am33
1138 // end-sanitize-am33
1139 {
1140 /* OP_F440 (); */
1141 PC = cia;
1142 store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1143 State.regs[REG_D0 + DM2]);
1144 }
1145
1146
1147 // 0000 Dm10 abs16...; movbu Dm,(abs16) (abs16 is zero-extended)
1148 4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
1149 "movbu"
1150 *mn10300
1151 // start-sanitize-am33
1152 *am33
1153 // end-sanitize-am33
1154 {
1155 /* OP_20000 (); */
1156 PC = cia;
1157 store_byte (FETCH16(IMM16A, IMM16B),
1158 State.regs[REG_D0 + DM1]);
1159 }
1160
1161
1162 // 1111 1100 1000 Dm10 abs32...; movbu Dm,(abs32)
1163 8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
1164 "movbu"
1165 *mn10300
1166 // start-sanitize-am33
1167 *am33
1168 // end-sanitize-am33
1169 {
1170 /* OP_FC820000 (); */
1171 PC = cia;
1172 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1173 State.regs[REG_D0 + DM1]);
1174 }
1175
1176
1177 // 1111 0000 0110 DnAm; movhu (Am),Dn
1178 8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
1179 "movhu"
1180 *mn10300
1181 // start-sanitize-am33
1182 *am33
1183 // end-sanitize-am33
1184 {
1185 /* OP_F060 (); */
1186 PC = cia;
1187 State.regs[REG_D0 + DN1]
1188 = load_half (State.regs[REG_A0 + AM0]);
1189 }
1190
1191
1192 // 1111 1000 0110 DnAm d8......; movhu (d8,Am),Dn (d8 is sign-extended)
1193 8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
1194 "movhu"
1195 *mn10300
1196 // start-sanitize-am33
1197 *am33
1198 // end-sanitize-am33
1199 {
1200 /* OP_F86000 (); */
1201 PC = cia;
1202 State.regs[REG_D0 + DN1]
1203 = load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
1204 }
1205
1206
1207 // 1111 1010 0110 DnAm d16.....; movhu (d16,Am),Dn (d16 is sign-extended.)
1208 8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
1209 "movhu"
1210 *mn10300
1211 // start-sanitize-am33
1212 *am33
1213 // end-sanitize-am33
1214 {
1215 /* OP_FA600000 (); */
1216 PC = cia;
1217 State.regs[REG_D0 + DN1]
1218 = load_half ((State.regs[REG_A0 + AM0]
1219 + EXTEND16 (FETCH16(D16A, D16B))));
1220 }
1221
1222
1223 // 1111 1100 0110 DnAm d32.....; movhu (d32,Am),Dn
1224 8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
1225 "movhu"
1226 *mn10300
1227 // start-sanitize-am33
1228 *am33
1229 // end-sanitize-am33
1230 {
1231 /* OP_FC600000 (); */
1232 PC = cia;
1233 State.regs[REG_D0 + DN1]
1234 = load_half ((State.regs[REG_A0 + AM0]
1235 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
1236 }
1237
1238
1239 // 1111 1000 1011 11Dn d8.....; movhu (d8,SP),Dn (d8 is zero-extended)
1240 8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
1241 "movhu"
1242 *mn10300
1243 // start-sanitize-am33
1244 *am33
1245 // end-sanitize-am33
1246 {
1247 /* OP_F8BC00 (); */
1248 PC = cia;
1249 State.regs[REG_D0 + DN0]
1250 = load_half ((State.regs[REG_SP] + (D8)));
1251 }
1252
1253
1254 // 1111 1010 1011 11Dn d16.....; movhu (d16,SP),Dn (d16 is zero-extended.)
1255 8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
1256 "movhu"
1257 *mn10300
1258 // start-sanitize-am33
1259 *am33
1260 // end-sanitize-am33
1261 {
1262 /* OP_FABC0000 (); */
1263 PC = cia;
1264 State.regs[REG_D0 + DN0]
1265 = load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)));
1266 }
1267
1268
1269 // 1111 1100 1011 11Dn d32.....; movhu (d32,SP),Dn
1270 8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
1271 "movhu"
1272 *mn10300
1273 // start-sanitize-am33
1274 *am33
1275 // end-sanitize-am33
1276 {
1277 /* OP_FCBC0000 (); */
1278 PC = cia;
1279 State.regs[REG_D0 + DN0]
1280 = load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1281 }
1282
1283
1284 // 1111 0100 10Dn DiAm; movhu (Di,Am),Dn
1285 8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
1286 "movhu"
1287 *mn10300
1288 // start-sanitize-am33
1289 *am33
1290 // end-sanitize-am33
1291 {
1292 /* OP_F480 (); */
1293 PC = cia;
1294 State.regs[REG_D0 + DN2]
1295 = load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
1296 }
1297
1298
1299 // 0011 10Dn abs16...; movhu (abs16),Dn (abs16 is zero-extended)
1300 4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
1301 "movhu"
1302 *mn10300
1303 // start-sanitize-am33
1304 *am33
1305 // end-sanitize-am33
1306 {
1307 /* OP_380000 (); */
1308 PC = cia;
1309 State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B));
1310 }
1311
1312
1313 // 1111 1100 1010 11Dn abs32...; movhu (abs32),Dn
1314 8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
1315 "movhu"
1316 *mn10300
1317 // start-sanitize-am33
1318 *am33
1319 // end-sanitize-am33
1320 {
1321 /* OP_FCAC0000 (); */
1322 PC = cia;
1323 State.regs[REG_D0 + DN0]
1324 = load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1325 }
1326
1327
1328 // 1111 0000 0111 DmAn; movhu Dm,(An)
1329 8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
1330 "movhu"
1331 *mn10300
1332 // start-sanitize-am33
1333 *am33
1334 // end-sanitize-am33
1335 {
1336 /* OP_F070 (); */
1337 PC = cia;
1338 store_half (State.regs[REG_A0 + AN0],
1339 State.regs[REG_D0 + DM1]);
1340 }
1341
1342
1343 // 1111 1000 0111 DmAn d8......; movhu Dm,(d8,An) (d8 is sign-extended)
1344 8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
1345 "movhu"
1346 *mn10300
1347 // start-sanitize-am33
1348 *am33
1349 // end-sanitize-am33
1350 {
1351 /* OP_F87000 (); */
1352 PC = cia;
1353 store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1354 State.regs[REG_D0 + DM1]);
1355 }
1356
1357
1358 // 1111 1010 0111 DnAm d16.....; movhu Dm,(d16,An) (d16 is sign-extended.)
1359 8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
1360 "movhu"
1361 *mn10300
1362 // start-sanitize-am33
1363 *am33
1364 // end-sanitize-am33
1365 {
1366 /* OP_FA700000 (); */
1367 PC = cia;
1368 store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1369 State.regs[REG_D0 + DM1]);
1370 }
1371
1372
1373 // 1111 1100 0111 DmAn d32.....; movhu Dm,(d32,An)
1374 8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
1375 "movhu"
1376 *mn10300
1377 // start-sanitize-am33
1378 *am33
1379 // end-sanitize-am33
1380 {
1381 /* OP_FC700000 (); */
1382 PC = cia;
1383 store_half ((State.regs[REG_A0 + AN0]
1384 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1385 State.regs[REG_D0 + DM1]);
1386 }
1387
1388
1389 // 1111 1000 1001 Dm11 d8....; movhu Dm,(d8,SP) (d8 is zero-extended)
1390 8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
1391 "movhu"
1392 *mn10300
1393 // start-sanitize-am33
1394 *am33
1395 // end-sanitize-am33
1396 {
1397 /* OP_F89300 (); */
1398 PC = cia;
1399 store_half (State.regs[REG_SP] + (D8),
1400 State.regs[REG_D0 + DM1]);
1401 }
1402
1403
1404 // 1111 1010 1001 Dm11 d16.....; movhu Dm,(d16,SP) (d16 is zero-extended.)
1405 8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
1406 "movhu"
1407 *mn10300
1408 // start-sanitize-am33
1409 *am33
1410 // end-sanitize-am33
1411 {
1412 /* OP_FA930000 (); */
1413 PC = cia;
1414 store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1415 State.regs[REG_D0 + DM1]);
1416 }
1417
1418
1419 // 1111 1100 1001 Dm11 d32.....; movhu Dm,(d32,SP)
1420 8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
1421 "movhu"
1422 *mn10300
1423 // start-sanitize-am33
1424 *am33
1425 // end-sanitize-am33
1426 {
1427 /* OP_FC930000 (); */
1428 PC = cia;
1429 store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1430 State.regs[REG_D0 + DM1]);
1431 }
1432
1433
1434 // 1111 0100 11Dm DiAn; movhu Dm,(Di,An)
1435 8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
1436 "movhu"
1437 *mn10300
1438 // start-sanitize-am33
1439 *am33
1440 // end-sanitize-am33
1441 {
1442 /* OP_F4C0 (); */
1443 PC = cia;
1444 store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1445 State.regs[REG_D0 + DM2]);
1446 }
1447
1448
1449 // 0000 Dm11 abs16...; movhu Dm,(abs16) (abs16 is zero-extended)
1450 4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
1451 "movhu"
1452 *mn10300
1453 // start-sanitize-am33
1454 *am33
1455 // end-sanitize-am33
1456 {
1457 /* OP_30000 (); */
1458 PC = cia;
1459 store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
1460 }
1461
1462
1463 // 1111 1100 1000 Dm11 abs32...; movhu Dm,(abs32)
1464 8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
1465 "movhu"
1466 *mn10300
1467 // start-sanitize-am33
1468 *am33
1469 // end-sanitize-am33
1470 {
1471 /* OP_FC830000 (); */
1472 PC = cia;
1473 store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1474 State.regs[REG_D0 + DM1]);
1475 }
1476
1477
1478 // 1111 0010 1101 00Dn; ext Dn
1479 8.0xf2+4.0xd,00,2.DN0:D0:::ext
1480 "ext"
1481 *mn10300
1482 // start-sanitize-am33
1483 *am33
1484 // end-sanitize-am33
1485 {
1486 /* OP_F2D0 (); */
1487 PC = cia;
1488 if (State.regs[REG_D0 + DN0] & 0x80000000)
1489 State.regs[REG_MDR] = -1;
1490 else
1491 State.regs[REG_MDR] = 0;
1492 }
1493
1494
1495 // 0001 00Dn; extb Dn
1496 4.0x1,00,2.DN0:S0:::extb
1497 "extb"
1498 *mn10300
1499 // start-sanitize-am33
1500 *am33
1501 // end-sanitize-am33
1502 {
1503 /* OP_10 (); */
1504 PC = cia;
1505 State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]);
1506 }
1507
1508
1509 // 0001 01Dn; extbu Dn
1510 4.0x1,01,2.DN0:S0:::extbu
1511 "extbu"
1512 *mn10300
1513 // start-sanitize-am33
1514 *am33
1515 // end-sanitize-am33
1516 {
1517 /* OP_14 (); */
1518 PC = cia;
1519 State.regs[REG_D0 + DN0] &= 0xff;
1520 }
1521
1522
1523 // 0001 10Dn; exth Dn
1524 4.0x1,10,2.DN0:S0:::exth
1525 "exth"
1526 *mn10300
1527 // start-sanitize-am33
1528 *am33
1529 // end-sanitize-am33
1530 {
1531 /* OP_18 (); */
1532 PC = cia;
1533 State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]);
1534 }
1535
1536
1537 // 0001 11Dn; exthu Dn
1538 4.0x1,11,2.DN0:S0:::exthu
1539 "exthu"
1540 *mn10300
1541 // start-sanitize-am33
1542 *am33
1543 // end-sanitize-am33
1544 {
1545 /* OP_1C (); */
1546 PC = cia;
1547 State.regs[REG_D0 + DN0] &= 0xffff;
1548 }
1549
1550
1551 // 0000 Dn00; clr Dn
1552 4.0x0,2.DN1,00:S0:::clr
1553 "clr"
1554 *mn10300
1555 // start-sanitize-am33
1556 *am33
1557 // end-sanitize-am33
1558 {
1559 /* OP_0 (); */
1560 PC = cia;
1561 State.regs[REG_D0 + DN1] = 0;
1562
1563 PSW |= PSW_Z;
1564 PSW &= ~(PSW_V | PSW_C | PSW_N);
1565 }
1566
1567
1568 // 1110 DmDn; add Dm,Dn
1569 4.0xe,2.DM1,2.DN0:S0:::add
1570 "add"
1571 *mn10300
1572 // start-sanitize-am33
1573 *am33
1574 // end-sanitize-am33
1575 {
1576 /* OP_E0 (); */
1577 PC = cia;
1578 genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1579 }
1580
1581 // 1111 0001 0110 DmAn; add Dm,An
1582 8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
1583 "add"
1584 *mn10300
1585 // start-sanitize-am33
1586 *am33
1587 // end-sanitize-am33
1588 {
1589 /* OP_F160 (); */
1590 PC = cia;
1591 genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1592 }
1593
1594
1595 // 1111 0001 0101 AmDn; add Am,Dn
1596 8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
1597 "add"
1598 *mn10300
1599 // start-sanitize-am33
1600 *am33
1601 // end-sanitize-am33
1602 {
1603 /* OP_F150 (); */
1604 PC = cia;
1605 genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1606 }
1607
1608
1609 // 1111 0001 0111 AmAn; add Am,An
1610 8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
1611 "add"
1612 *mn10300
1613 // start-sanitize-am33
1614 *am33
1615 // end-sanitize-am33
1616 {
1617 /* OP_F170 (); */
1618 PC = cia;
1619 genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1620 }
1621
1622
1623 // 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended)
1624 4.0x2,10,2.DN0+8.IMM8:S1:::add
1625 "add"
1626 *mn10300
1627 // start-sanitize-am33
1628 *am33
1629 // end-sanitize-am33
1630 {
1631 /* OP_2800 (); */
1632 PC = cia;
1633 genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
1634 }
1635
1636
1637 // 1111 1010 1100 00Dn imm16...; add imm16,Dn
1638 8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
1639 "add"
1640 *mn10300
1641 // start-sanitize-am33
1642 *am33
1643 // end-sanitize-am33
1644 {
1645 /* OP_FAC00000 (); */
1646 PC = cia;
1647 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
1648 }
1649
1650
1651 // 1111 1100 1100 00Dn imm32...; add imm32,Dn
1652 8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
1653 "add"
1654 *mn10300
1655 // start-sanitize-am33
1656 *am33
1657 // end-sanitize-am33
1658 {
1659 /* OP_FCC00000 (); */
1660 PC = cia;
1661 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1662 }
1663
1664
1665 // 0010 00An imm8....; add imm8,An (imm8 is sign-extended)
1666 4.0x2,00,2.AN0+8.IMM8:S1a:::add
1667 "add"
1668 *mn10300
1669 // start-sanitize-am33
1670 *am33
1671 // end-sanitize-am33
1672 {
1673 /* OP_2000 (); */
1674 PC = cia;
1675 genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
1676 }
1677
1678
1679 // 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.)
1680 8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
1681 "add"
1682 *mn10300
1683 // start-sanitize-am33
1684 *am33
1685 // end-sanitize-am33
1686 {
1687 /* OP_FAD00000 (); */
1688 PC = cia;
1689 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
1690 }
1691
1692
1693 // 1111 1100 1101 00An imm32...; add imm32,An
1694 8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
1695 "add"
1696 *mn10300
1697 // start-sanitize-am33
1698 *am33
1699 // end-sanitize-am33
1700 {
1701 /* OP_FCD00000 (); */
1702 PC = cia;
1703 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1704 }
1705
1706
1707 // 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.)
1708 8.0xf8+8.0xfe+8.IMM8:D1:::add
1709 "add"
1710 *mn10300
1711 // start-sanitize-am33
1712 *am33
1713 // end-sanitize-am33
1714 {
1715 /* OP_F8FE00 (); */
1716 unsigned long imm;
1717
1718 /* Note: no PSW changes. */
1719 PC = cia;
1720 imm = EXTEND8 (IMM8);
1721 State.regs[REG_SP] += imm;
1722 }
1723
1724
1725 // 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.)
1726 8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
1727 "add"
1728 *mn10300
1729 // start-sanitize-am33
1730 *am33
1731 // end-sanitize-am33
1732 {
1733 /* OP_FAFE0000 (); */
1734 unsigned long imm;
1735
1736 /* Note: no PSW changes. */
1737 PC = cia;
1738 imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
1739 State.regs[REG_SP] += imm;
1740 }
1741
1742
1743 // 1111 1100 1111 1110 imm32...; add imm32,SP
1744 8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
1745 "add"
1746 *mn10300
1747 // start-sanitize-am33
1748 *am33
1749 // end-sanitize-am33
1750 {
1751 /* OP_FCFE0000 (); */
1752 unsigned long imm;
1753
1754 /* Note: no PSW changes. */
1755 PC = cia;
1756 imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1757 State.regs[REG_SP] += imm;
1758 }
1759
1760
1761 // 1111 0001 0100 DmDn; addc Dm,Dn
1762 8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
1763 "addc"
1764 *mn10300
1765 // start-sanitize-am33
1766 *am33
1767 // end-sanitize-am33
1768 {
1769 /* OP_F140 (); */
1770 int z, c, n, v;
1771 unsigned long reg1, reg2, sum;
1772
1773 PC = cia;
1774 reg1 = State.regs[REG_D0 + DM1];
1775 reg2 = State.regs[REG_D0 + DN0];
1776 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
1777 State.regs[REG_D0 + DN0] = sum;
1778
1779 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1780 n = (sum & 0x80000000);
1781 c = (sum < reg1) || (sum < reg2);
1782 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1783 && (reg2 & 0x80000000) != (sum & 0x80000000));
1784
1785 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1786 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1787 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1788 }
1789
1790
1791 // 1111 0001 0000 DmDn; sub Dm,Dn
1792 8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
1793 "sub"
1794 *mn10300
1795 // start-sanitize-am33
1796 *am33
1797 // end-sanitize-am33
1798 {
1799 /* OP_F100 (); */
1800 PC = cia;
1801 genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1802 }
1803
1804 // 1111 0001 0010 DmAn; sub DmAn
1805 8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
1806 "sub"
1807 *mn10300
1808 // start-sanitize-am33
1809 *am33
1810 // end-sanitize-am33
1811 {
1812 /* OP_F120 (); */
1813 PC = cia;
1814 genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1815 }
1816
1817
1818 // 1111 0001 0001 AmDn; sub AmDn
1819 8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
1820 "sub"
1821 *mn10300
1822 // start-sanitize-am33
1823 *am33
1824 // end-sanitize-am33
1825 {
1826 /* OP_F110 (); */
1827 PC = cia;
1828 genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1829 }
1830
1831
1832 // 1111 0001 0011 AmAn; sub Am,An
1833 8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
1834 "sub"
1835 *mn10300
1836 // start-sanitize-am33
1837 *am33
1838 // end-sanitize-am33
1839 {
1840 /* OP_F130 (); */
1841 PC = cia;
1842 genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1843 }
1844
1845
1846 // 1111 1100 1100 01Dn imm32...; sub imm32,Dn
1847 8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
1848 "sub"
1849 *mn10300
1850 // start-sanitize-am33
1851 *am33
1852 // end-sanitize-am33
1853 {
1854 /* OP_FCC40000 (); */
1855 PC = cia;
1856 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1857 }
1858
1859
1860 // 1111 1100 1101 01An imm32...; sub imm32,An
1861 8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
1862 "sub"
1863 *mn10300
1864 // start-sanitize-am33
1865 *am33
1866 // end-sanitize-am33
1867 {
1868 /* OP_FCD40000 (); */
1869 PC = cia;
1870 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1871 }
1872
1873
1874 // 1111 0001 1000 DmDn; subc Dm,Dn
1875 8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
1876 "subc"
1877 *mn10300
1878 // start-sanitize-am33
1879 *am33
1880 // end-sanitize-am33
1881 {
1882 /* OP_F180 (); */
1883 int z, c, n, v;
1884 unsigned long reg1, reg2, difference;
1885
1886 PC = cia;
1887 reg1 = State.regs[REG_D0 + DM1];
1888 reg2 = State.regs[REG_D0 + DN0];
1889 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
1890 State.regs[REG_D0 + DN0] = difference;
1891
1892 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1893 n = (difference & 0x80000000);
1894 c = (reg1 > reg2);
1895 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1896 && (reg2 & 0x80000000) != (difference & 0x80000000));
1897
1898 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1899 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1900 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1901 }
1902
1903
1904 // 1111 0010 0100 DmDn; mul Dm,Dn
1905 8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
1906 "mul"
1907 *mn10300
1908 // start-sanitize-am33
1909 *am33
1910 // end-sanitize-am33
1911 {
1912 /* OP_F240 (); */
1913 unsigned long long temp;
1914 int n, z;
1915
1916 PC = cia;
1917 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
1918 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
1919 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1920 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1921 z = (State.regs[REG_D0 + DN0] == 0);
1922 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1923 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1924 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1925 }
1926
1927
1928 // 1111 0010 0101 DmDn; mulu Dm,Dn
1929 8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
1930 "mulu"
1931 *mn10300
1932 // start-sanitize-am33
1933 *am33
1934 // end-sanitize-am33
1935 {
1936 /* OP_F250 (); */
1937 unsigned long long temp;
1938 int n, z;
1939
1940 PC = cia;
1941 temp = ((unsigned64)State.regs[REG_D0 + DN0]
1942 * (unsigned64)State.regs[REG_D0 + DM1]);
1943 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1944 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1945 z = (State.regs[REG_D0 + DN0] == 0);
1946 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1947 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1948 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1949 }
1950
1951
1952 // 1111 0010 0110 DmDn; div Dm,Dn
1953 8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
1954 "div"
1955 *mn10300
1956 // start-sanitize-am33
1957 *am33
1958 // end-sanitize-am33
1959 {
1960 /* OP_F260 (); */
1961 signed64 temp;
1962 signed32 denom;
1963 int n, z, v;
1964
1965 PC = cia;
1966 denom = (signed32)State.regs[REG_D0 + DM1];
1967 /* still need to check for overflow */
1968 if ( !(v = (0 == denom)) )
1969 {
1970 temp = State.regs[REG_MDR];
1971 temp <<= 32;
1972 temp |= State.regs[REG_D0 + DN0];
1973 State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1];
1974 temp /= (signed32)State.regs[REG_D0 + DM1];
1975 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1976 z = (State.regs[REG_D0 + DN0] == 0);
1977 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1978 }
1979 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1980 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
1981 }
1982
1983
1984 // 1111 0010 0111 DmDn; divu Dm,Dn
1985 8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
1986 "divu"
1987 *mn10300
1988 // start-sanitize-am33
1989 *am33
1990 // end-sanitize-am33
1991 {
1992 /* OP_F270 (); */
1993 unsigned64 temp;
1994 unsigned32 denom;
1995 int n, z, v;
1996
1997 PC = cia;
1998 denom = (unsigned32)State.regs[REG_D0 + DM1];
1999 if ( !(v = (0 == denom)) )
2000 {
2001 temp = State.regs[REG_MDR];
2002 temp <<= 32;
2003 temp |= State.regs[REG_D0 + DN0];
2004 State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
2005 temp /= State.regs[REG_D0 + DM1];
2006 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2007 z = (State.regs[REG_D0 + DN0] == 0);
2008 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2009 }
2010 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2011 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
2012 }
2013
2014
2015 // 0100 Dn00; inc Dn
2016 4.0x4,2.DN1,00:S0:::inc
2017 "inc"
2018 *mn10300
2019 // start-sanitize-am33
2020 *am33
2021 // end-sanitize-am33
2022 {
2023 /* OP_40 (); */
2024 unsigned int imm;
2025
2026 PC = cia;
2027 imm = 1;
2028 genericAdd(imm, REG_D0 + DN1);
2029 }
2030
2031
2032 // 0100 An01
2033 4.0x4,2.AN1,01:S0a:::inc
2034 "inc"
2035 *mn10300
2036 // start-sanitize-am33
2037 *am33
2038 // end-sanitize-am33
2039 {
2040 /* OP_41 (); */
2041 PC = cia;
2042 State.regs[REG_A0 + AN1] += 1;
2043 }
2044
2045
2046 // 0101 00An; inc4 An
2047 4.0x5,00,2.AN0:S0:::inc4
2048 "inc4"
2049 *mn10300
2050 // start-sanitize-am33
2051 *am33
2052 // end-sanitize-am33
2053 {
2054 /* OP_50 (); */
2055 PC = cia;
2056 State.regs[REG_A0 + AN0] += 4;
2057 }
2058
2059
2060 // 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.)
2061 4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
2062 "cmp"
2063 *mn10300
2064 // start-sanitize-am33
2065 *am33
2066 // end-sanitize-am33
2067 {
2068 PC = cia;
2069 /* OP_A000 (); */
2070 genericCmp(EXTEND8 (IMM8), State.regs[REG_D0 + DN0]);
2071 }
2072
2073
2074 // 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn)
2075 4.0xa,2.DM1,2.DN0!DM1:S0:::cmp
2076 "cmp"
2077 *mn10300
2078 // start-sanitize-am33
2079 *am33
2080 // end-sanitize-am33
2081 {
2082 PC = cia;
2083 /* OP_A0 (); */
2084 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
2085 }
2086
2087
2088 // 1111 0001 1010 DmAn; cmp Dm,An
2089 8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
2090 "cmp"
2091 *mn10300
2092 // start-sanitize-am33
2093 *am33
2094 // end-sanitize-am33
2095 {
2096 /* OP_F1A0 (); */
2097 PC = cia;
2098 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
2099 }
2100
2101
2102 // 1111 0001 1001 AmDn; cmp Am,Dn
2103 8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
2104 "cmp"
2105 *mn10300
2106 // start-sanitize-am33
2107 *am33
2108 // end-sanitize-am33
2109 {
2110 /* OP_F190 (); */
2111 PC = cia;
2112 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
2113 }
2114
2115
2116 // 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.)
2117 4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
2118 "cmp"
2119 *mn10300
2120 // start-sanitize-am33
2121 *am33
2122 // end-sanitize-am33
2123 {
2124 PC = cia;
2125 /* OP_B000 (); */
2126 genericCmp(IMM8,
2127 State.regs[REG_A0 + AN0]);
2128 }
2129
2130
2131 // 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn)
2132 4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
2133 "cmp"
2134 *mn10300
2135 // start-sanitize-am33
2136 *am33
2137 // end-sanitize-am33
2138 {
2139 PC = cia;
2140 /* OP_B0 (); */
2141 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
2142 }
2143
2144
2145 // 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.)
2146 8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
2147 "cmp"
2148 *mn10300
2149 // start-sanitize-am33
2150 *am33
2151 // end-sanitize-am33
2152 {
2153 /* OP_FAC80000 (); */
2154 PC = cia;
2155 genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
2156 State.regs[REG_D0 + DN0]);
2157 }
2158
2159
2160 // 1111 1100 1100 10Dn imm32...; cmp imm32,Dn
2161 8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
2162 "cmp"
2163 *mn10300
2164 // start-sanitize-am33
2165 *am33
2166 // end-sanitize-am33
2167 {
2168 /* OP_FCC80000 (); */
2169 PC = cia;
2170 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2171 State.regs[REG_D0 + DN0]);
2172 }
2173
2174
2175 // 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.)
2176 8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
2177 "cmp"
2178 *mn10300
2179 // start-sanitize-am33
2180 *am33
2181 // end-sanitize-am33
2182 {
2183 /* OP_FAD80000 (); */
2184 PC = cia;
2185 genericCmp(FETCH16(IMM16A, IMM16B),
2186 State.regs[REG_A0 + AN0]);
2187 }
2188
2189
2190 // 1111 1100 1101 10An imm32...; cmp imm32,An
2191 8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
2192 "cmp"
2193 *mn10300
2194 // start-sanitize-am33
2195 *am33
2196 // end-sanitize-am33
2197 {
2198 /* OP_FCD80000 (); */
2199 PC = cia;
2200 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2201 State.regs[REG_A0 + AN0]);
2202 }
2203
2204
2205 // 1111 0010 0000 DmDn; and Dm,Dn
2206 8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
2207 "and"
2208 *mn10300
2209 // start-sanitize-am33
2210 *am33
2211 // end-sanitize-am33
2212 {
2213 /* OP_F200 (); */
2214 int n, z;
2215
2216 PC = cia;
2217 State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
2218 z = (State.regs[REG_D0 + DN0] == 0);
2219 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2220 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2221 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2222 }
2223
2224
2225 // 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.)
2226 8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
2227 "and"
2228 *mn10300
2229 // start-sanitize-am33
2230 *am33
2231 // end-sanitize-am33
2232 {
2233 /* OP_F8E000 (); */
2234 int n, z;
2235
2236 PC = cia;
2237 State.regs[REG_D0 + DN0] &= IMM8;
2238 z = (State.regs[REG_D0 + DN0] == 0);
2239 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2240 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2241 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2242 }
2243
2244
2245 // 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.)
2246 8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
2247 "and"
2248 *mn10300
2249 // start-sanitize-am33
2250 *am33
2251 // end-sanitize-am33
2252 {
2253 /* OP_FAE00000 (); */
2254 int n, z;
2255
2256 PC = cia;
2257 State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
2258 z = (State.regs[REG_D0 + DN0] == 0);
2259 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2260 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2261 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2262 }
2263
2264
2265 // 1111 1100 1110 00Dn imm32...; and imm32,Dn
2266 8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
2267 "and"
2268 *mn10300
2269 // start-sanitize-am33
2270 *am33
2271 // end-sanitize-am33
2272 {
2273 /* OP_FCE00000 (); */
2274 int n, z;
2275
2276 PC = cia;
2277 State.regs[REG_D0 + DN0]
2278 &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
2279 z = (State.regs[REG_D0 + DN0] == 0);
2280 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2281 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2282 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2283 }
2284
2285
2286 // 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.)
2287 8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
2288 "and"
2289 *mn10300
2290 // start-sanitize-am33
2291 *am33
2292 // end-sanitize-am33
2293 {
2294 /* OP_FAFC0000 (); */
2295 PC = cia;
2296 PSW &= FETCH16(IMM16A, IMM16B);
2297 }
2298
2299
2300
2301 // 1111 0010 0001 DmDn; or DmDn
2302 8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
2303 "or"
2304 *mn10300
2305 // start-sanitize-am33
2306 *am33
2307 // end-sanitize-am33
2308 {
2309 /* OP_F210 (); */
2310 PC = cia;
2311 genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2312 }
2313
2314
2315 // 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n
2316 8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
2317 "or"
2318 *mn10300
2319 // start-sanitize-am33
2320 *am33
2321 // end-sanitize-am33
2322 {
2323 /* OP_F8E400 (); */
2324 PC = cia;
2325 genericOr(IMM8, REG_D0 + DN0);
2326 }
2327
2328
2329 // 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.)
2330 8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
2331 "or"
2332 *mn10300
2333 // start-sanitize-am33
2334 *am33
2335 // end-sanitize-am33
2336 {
2337 /* OP_FAE40000 (); */
2338 PC = cia;
2339 genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2340 }
2341
2342
2343 // 1111 1100 1110 01Dn imm32...; or imm32,Dn
2344 8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
2345 "or"
2346 *mn10300
2347 // start-sanitize-am33
2348 *am33
2349 // end-sanitize-am33
2350 {
2351 /* OP_FCE40000 (); */
2352 PC = cia;
2353 genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2354 }
2355
2356
2357 // 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.)
2358 8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
2359 "or"
2360 *mn10300
2361 // start-sanitize-am33
2362 *am33
2363 // end-sanitize-am33
2364 {
2365 /* OP_FAFD0000 (); */
2366 PC = cia;
2367 PSW |= FETCH16(IMM16A, IMM16B);
2368 }
2369
2370
2371 // 1111 0010 0010 DmDn; xor Dm,Dn
2372 8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
2373 "xor"
2374 *mn10300
2375 // start-sanitize-am33
2376 *am33
2377 // end-sanitize-am33
2378 {
2379 /* OP_F220 (); */
2380 PC = cia;
2381 genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2382 }
2383
2384
2385 // 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.)
2386 8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
2387 "xor"
2388 *mn10300
2389 // start-sanitize-am33
2390 *am33
2391 // end-sanitize-am33
2392 {
2393 /* OP_FAE80000 (); */
2394 PC = cia;
2395 genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2396 }
2397
2398
2399 // 1111 1100 1110 10Dn imm32...; xor imm32,Dn
2400 8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
2401 "xor"
2402 *mn10300
2403 // start-sanitize-am33
2404 *am33
2405 // end-sanitize-am33
2406 {
2407 /* OP_FCE80000 (); */
2408 PC = cia;
2409 genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2410 }
2411
2412
2413 // 1111 0010 0011 00Dn; not Dn
2414 8.0xf2+4.0x3,00,2.DN0:D0:::not
2415 "not"
2416 *mn10300
2417 // start-sanitize-am33
2418 *am33
2419 // end-sanitize-am33
2420 {
2421 /* OP_F230 (); */
2422 int n, z;
2423
2424 PC = cia;
2425 State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
2426 z = (State.regs[REG_D0 + DN0] == 0);
2427 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2428 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2429 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2430 }
2431
2432
2433 // 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.)
2434 8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
2435 "btst"
2436 *mn10300
2437 // start-sanitize-am33
2438 *am33
2439 // end-sanitize-am33
2440 {
2441 /* OP_F8EC00 (); */
2442 PC = cia;
2443 genericBtst(IMM8, State.regs[REG_D0 + DN0]);
2444 }
2445
2446
2447 // 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.)
2448 8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
2449 "btst"
2450 *mn10300
2451 // start-sanitize-am33
2452 *am33
2453 // end-sanitize-am33
2454 {
2455 /* OP_FAEC0000 (); */
2456 PC = cia;
2457 genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
2458 }
2459
2460
2461 // 1111 1100 1110 11Dn imm32...; btst imm32,Dn
2462 8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
2463 "btst"
2464 *mn10300
2465 // start-sanitize-am33
2466 *am33
2467 // end-sanitize-am33
2468 {
2469 /* OP_FCEC0000 (); */
2470 PC = cia;
2471 genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2472 State.regs[REG_D0 + DN0]);
2473 }
2474
2475
2476 // 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2477 8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
2478 "btst"
2479 *mn10300
2480 // start-sanitize-am33
2481 *am33
2482 // end-sanitize-am33
2483 {
2484 /* OP_FE020000 (); */
2485 PC = cia;
2486 genericBtst(IMM8,
2487 load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
2488 }
2489
2490
2491 // 1111 1010 1111 10An d8...... imm8....;
2492 // btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte)
2493 8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
2494 "btst"
2495 *mn10300
2496 // start-sanitize-am33
2497 *am33
2498 // end-sanitize-am33
2499 {
2500 /* OP_FAF80000 (); */
2501 PC = cia;
2502 genericBtst(IMM8,
2503 load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
2504 }
2505
2506
2507 // 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte)
2508 8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
2509 "bset"
2510 *mn10300
2511 // start-sanitize-am33
2512 *am33
2513 // end-sanitize-am33
2514 {
2515 /* OP_F080 (); */
2516 unsigned long temp;
2517 int z;
2518
2519 PC = cia;
2520 temp = load_byte (State.regs[REG_A0 + AN0]);
2521 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2522 temp |= State.regs[REG_D0 + DM1];
2523 store_byte (State.regs[REG_A0 + AN0], temp);
2524 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2525 PSW |= (z ? PSW_Z : 0);
2526 }
2527
2528
2529 // 1111 1110 0000 0000 abs32... imm8....;
2530 // bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2531 8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
2532 "bset"
2533 *mn10300
2534 // start-sanitize-am33
2535 *am33
2536 // end-sanitize-am33
2537 {
2538 /* OP_FE000000 (); */
2539 unsigned long temp;
2540 int z;
2541
2542 PC = cia;
2543 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2544 z = (temp & IMM8) == 0;
2545 temp |= IMM8;
2546 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2547 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2548 PSW |= (z ? PSW_Z : 0);
2549 }
2550
2551
2552 // 1111 1010 1111 00AnAn d8...... imm8....;
2553 // bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2554 8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
2555 "bset"
2556 *mn10300
2557 // start-sanitize-am33
2558 *am33
2559 // end-sanitize-am33
2560 {
2561 /* OP_FAF00000 (); */
2562 unsigned long temp;
2563 int z;
2564
2565 PC = cia;
2566 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2567 z = (temp & (IMM8)) == 0;
2568 temp |= (IMM8);
2569 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2570 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2571 PSW |= (z ? PSW_Z : 0);
2572 }
2573
2574
2575 // 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte)
2576 8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
2577 "bclr"
2578 *mn10300
2579 // start-sanitize-am33
2580 *am33
2581 // end-sanitize-am33
2582 {
2583 /* OP_F090 (); */
2584 unsigned long temp;
2585 int z;
2586
2587 PC = cia;
2588 temp = load_byte (State.regs[REG_A0 + AN0]);
2589 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2590 temp = temp & ~State.regs[REG_D0 + DM1];
2591 store_byte (State.regs[REG_A0 + AN0], temp);
2592 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2593 PSW |= (z ? PSW_Z : 0);
2594 }
2595
2596
2597 // 1111 1110 0000 0001 abs32... imm8....;
2598 // bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2599 8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
2600 "bclr"
2601 *mn10300
2602 // start-sanitize-am33
2603 *am33
2604 // end-sanitize-am33
2605 {
2606 /* OP_FE010000 (); */
2607 unsigned long temp;
2608 int z;
2609
2610 PC = cia;
2611 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2612 z = (temp & IMM8) == 0;
2613 temp = temp & ~(IMM8);
2614 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2615 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2616 PSW |= (z ? PSW_Z : 0);
2617 }
2618
2619
2620 // 1111 1010 1111 01An d8...... imm8....;
2621 // bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2622 8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
2623 "bclr"
2624 *mn10300
2625 // start-sanitize-am33
2626 *am33
2627 // end-sanitize-am33
2628 {
2629 /* OP_FAF40000 (); */
2630 unsigned long temp;
2631 int z;
2632
2633 PC = cia;
2634 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2635 z = (temp & (IMM8)) == 0;
2636 temp = temp & ~(IMM8);
2637 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2638 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2639 PSW |= (z ? PSW_Z : 0);
2640 }
2641
2642
2643 // 1111 0010 1011 DmDn; asr Dm,Dn
2644 8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
2645 "asr"
2646 *mn10300
2647 // start-sanitize-am33
2648 *am33
2649 // end-sanitize-am33
2650 {
2651 /* OP_F2B0 (); */
2652 long temp;
2653 int z, n, c;
2654
2655 PC = cia;
2656 temp = State.regs[REG_D0 + DN0];
2657 c = temp & 1;
2658 temp >>= State.regs[REG_D0 + DM1];
2659 State.regs[REG_D0 + DN0] = temp;
2660 z = (State.regs[REG_D0 + DN0] == 0);
2661 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2662 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2663 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2664 }
2665
2666
2667 // 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.)
2668 8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
2669 "asr"
2670 *mn10300
2671 // start-sanitize-am33
2672 *am33
2673 // end-sanitize-am33
2674 {
2675 /* OP_F8C800 (); */
2676 long temp;
2677 int z, n, c;
2678
2679 PC = cia;
2680 temp = State.regs[REG_D0 + DN0];
2681 c = temp & 1;
2682 temp >>= IMM8;
2683 State.regs[REG_D0 + DN0] = temp;
2684 z = (State.regs[REG_D0 + DN0] == 0);
2685 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2686 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2687 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2688 }
2689
2690
2691 // 1111 0010 1010 DmDn; lsr Dm,Dn
2692 8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
2693 "lsr"
2694 *mn10300
2695 // start-sanitize-am33
2696 *am33
2697 // end-sanitize-am33
2698 {
2699 /* OP_F2A0 (); */
2700 int z, n, c;
2701
2702 PC = cia;
2703 c = State.regs[REG_D0 + DN0] & 1;
2704 State.regs[REG_D0 + DN0]
2705 >>= State.regs[REG_D0 + DM1];
2706 z = (State.regs[REG_D0 + DN0] == 0);
2707 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2708 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2709 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2710 }
2711
2712
2713 // 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.)
2714 8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
2715 "lsr"
2716 *mn10300
2717 // start-sanitize-am33
2718 *am33
2719 // end-sanitize-am33
2720 {
2721 /* OP_F8C400 (); */
2722 int z, n, c;
2723
2724 PC = cia;
2725 c = State.regs[REG_D0 + DN0] & 1;
2726 State.regs[REG_D0 + DN0] >>= IMM8;
2727 z = (State.regs[REG_D0 + DN0] == 0);
2728 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2729 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2730 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2731 }
2732
2733
2734 // 1111 0010 1001 DmDn; asl Dm,Dn
2735 8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
2736 "asl"
2737 *mn10300
2738 // start-sanitize-am33
2739 *am33
2740 // end-sanitize-am33
2741 {
2742 /* OP_F290 (); */
2743 int n, z;
2744
2745 PC = cia;
2746 State.regs[REG_D0 + DN0]
2747 <<= State.regs[REG_D0 + DM1];
2748 z = (State.regs[REG_D0 + DN0] == 0);
2749 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2750 PSW &= ~(PSW_Z | PSW_N);
2751 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2752 }
2753
2754
2755 // 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.)
2756 8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
2757 "asl"
2758 *mn10300
2759 // start-sanitize-am33
2760 *am33
2761 // end-sanitize-am33
2762 {
2763 /* OP_F8C000 (); */
2764 int n, z;
2765
2766 PC = cia;
2767 State.regs[REG_D0 + DN0] <<= IMM8;
2768 z = (State.regs[REG_D0 + DN0] == 0);
2769 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2770 PSW &= ~(PSW_Z | PSW_N);
2771 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2772 }
2773
2774
2775 // 0101 01Dn; als2 Dn
2776 4.0x5,01,2.DN0:S0:::asl2
2777 "asl2"
2778 *mn10300
2779 // start-sanitize-am33
2780 *am33
2781 // end-sanitize-am33
2782 {
2783 /* OP_54 (); */
2784 int n, z;
2785 PC = cia;
2786
2787 State.regs[REG_D0 + DN0] <<= 2;
2788 z = (State.regs[REG_D0 + DN0] == 0);
2789 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2790 PSW &= ~(PSW_Z | PSW_N);
2791 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2792 }
2793
2794
2795 // 1111 0010 1000 01Dn; ror Dn
2796 8.0xf2+4.0x8,01,2.DN0:D0:::ror
2797 "ror"
2798 *mn10300
2799 // start-sanitize-am33
2800 *am33
2801 // end-sanitize-am33
2802 {
2803 /* OP_F284 (); */
2804 unsigned long value;
2805 int c,n,z;
2806
2807 PC = cia;
2808 value = State.regs[REG_D0 + DN0];
2809 c = (value & 0x1);
2810
2811 value >>= 1;
2812 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2813 State.regs[REG_D0 + DN0] = value;
2814 z = (value == 0);
2815 n = (value & 0x80000000) != 0;
2816 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2817 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2818 }
2819
2820
2821 // 1111 0010 1000 00Dn; rol Dn
2822 8.0xf2+4.0x8,00,2.DN0:D0:::rol
2823 "rol"
2824 *mn10300
2825 // start-sanitize-am33
2826 *am33
2827 // end-sanitize-am33
2828 {
2829 /* OP_F280 (); */
2830 unsigned long value;
2831 int c,n,z;
2832
2833 PC = cia;
2834 value = State.regs[REG_D0 + DN0];
2835 c = (value & 0x80000000) ? 1 : 0;
2836
2837 value <<= 1;
2838 value |= ((PSW & PSW_C) != 0);
2839 State.regs[REG_D0 + DN0] = value;
2840 z = (value == 0);
2841 n = (value & 0x80000000) != 0;
2842 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2843 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2844 }
2845
2846
2847 // 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended)
2848 8.0xc8+8.D8:S1:::beq
2849 "beq"
2850 *mn10300
2851 // start-sanitize-am33
2852 *am33
2853 // end-sanitize-am33
2854 {
2855 /* OP_C800 (); */
2856 PC = cia;
2857 if ((PSW & PSW_Z))
2858 {
2859 State.regs[REG_PC] += EXTEND8 (D8);
2860 nia = PC;
2861 }
2862 }
2863
2864
2865 // 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended)
2866 8.0xc9+8.D8:S1:::bne
2867 "bne"
2868 *mn10300
2869 // start-sanitize-am33
2870 *am33
2871 // end-sanitize-am33
2872 {
2873 /* OP_C900 (); */
2874 PC = cia;
2875 if (!(PSW & PSW_Z))
2876 {
2877 State.regs[REG_PC] += EXTEND8 (D8);
2878 nia = PC;
2879 }
2880 }
2881
2882
2883 // 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended)
2884 8.0xc1+8.D8:S1:::bgt
2885 "bgt"
2886 *mn10300
2887 // start-sanitize-am33
2888 *am33
2889 // end-sanitize-am33
2890 {
2891 /* OP_C100 (); */
2892 PC = cia;
2893 if (!((PSW & PSW_Z)
2894 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2895 {
2896 State.regs[REG_PC] += EXTEND8 (D8);
2897 nia = PC;
2898 }
2899 }
2900
2901
2902 // 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended)
2903 8.0xc2+8.D8:S1:::bge
2904 "bge"
2905 *mn10300
2906 // start-sanitize-am33
2907 *am33
2908 // end-sanitize-am33
2909 {
2910 /* OP_C200 (); */
2911 PC = cia;
2912 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2913 {
2914 State.regs[REG_PC] += EXTEND8 (D8);
2915 nia = PC;
2916 }
2917 }
2918
2919
2920 // 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended)
2921 8.0xc3+8.D8:S1:::ble
2922 "ble"
2923 *mn10300
2924 // start-sanitize-am33
2925 *am33
2926 // end-sanitize-am33
2927 {
2928 /* OP_C300 (); */
2929 PC = cia;
2930 if ((PSW & PSW_Z)
2931 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2932 {
2933 State.regs[REG_PC] += EXTEND8 (D8);
2934 nia = PC;
2935 }
2936 }
2937
2938
2939 // 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended)
2940 8.0xc0+8.D8:S1:::blt
2941 "blt"
2942 *mn10300
2943 // start-sanitize-am33
2944 *am33
2945 // end-sanitize-am33
2946 {
2947 /* OP_C000 (); */
2948 PC = cia;
2949 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2950 {
2951 State.regs[REG_PC] += EXTEND8 (D8);
2952 nia = PC;
2953 }
2954 }
2955
2956
2957 // 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended)
2958 8.0xc5+8.D8:S1:::bhi
2959 "bhi"
2960 *mn10300
2961 // start-sanitize-am33
2962 *am33
2963 // end-sanitize-am33
2964 {
2965 /* OP_C500 (); */
2966 PC = cia;
2967 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2968 {
2969 State.regs[REG_PC] += EXTEND8 (D8);
2970 nia = PC;
2971 }
2972 }
2973
2974
2975 // 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended)
2976 8.0xc6+8.D8:S1:::bcc
2977 "bcc"
2978 *mn10300
2979 // start-sanitize-am33
2980 *am33
2981 // end-sanitize-am33
2982 {
2983 /* OP_C600 (); */
2984 PC = cia;
2985 if (!(PSW & PSW_C))
2986 {
2987 State.regs[REG_PC] += EXTEND8 (D8);
2988 nia = PC;
2989 }
2990 }
2991
2992
2993 // 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended)
2994 8.0xc7+8.D8:S1:::bls
2995 "bls"
2996 *mn10300
2997 // start-sanitize-am33
2998 *am33
2999 // end-sanitize-am33
3000 {
3001 /* OP_C700 (); */
3002 PC = cia;
3003 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
3004 {
3005 State.regs[REG_PC] += EXTEND8 (D8);
3006 nia = PC;
3007 }
3008 }
3009
3010
3011 // 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended)
3012 8.0xc4+8.D8:S1:::bcs
3013 "bcs"
3014 *mn10300
3015 // start-sanitize-am33
3016 *am33
3017 // end-sanitize-am33
3018 {
3019 /* OP_C400 (); */
3020 PC = cia;
3021 if (PSW & PSW_C)
3022 {
3023 State.regs[REG_PC] += EXTEND8 (D8);
3024 nia = PC;
3025 }
3026 }
3027
3028
3029 // 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended)
3030 8.0xf8+8.0xe8+8.D8:D1:::bvc
3031 "bvc"
3032 *mn10300
3033 // start-sanitize-am33
3034 *am33
3035 // end-sanitize-am33
3036 {
3037 /* OP_F8E800 (); */
3038 PC = cia;
3039 if (!(PSW & PSW_V))
3040 {
3041 State.regs[REG_PC] += EXTEND8 (D8);
3042 nia = PC;
3043 }
3044 }
3045
3046
3047 // 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended)
3048 8.0xf8+8.0xe9+8.D8:D1:::bvs
3049 "bvs"
3050 *mn10300
3051 // start-sanitize-am33
3052 *am33
3053 // end-sanitize-am33
3054 {
3055 /* OP_F8E900 (); */
3056 PC = cia;
3057 if (PSW & PSW_V)
3058 {
3059 State.regs[REG_PC] += EXTEND8 (D8);
3060 nia = PC;
3061 }
3062 }
3063
3064
3065 // 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended)
3066 8.0xf8+8.0xea+8.D8:D1:::bnc
3067 "bnc"
3068 *mn10300
3069 // start-sanitize-am33
3070 *am33
3071 // end-sanitize-am33
3072 {
3073 /* OP_F8EA00 (); */
3074 PC = cia;
3075 if (!(PSW & PSW_N))
3076 {
3077 State.regs[REG_PC] += EXTEND8 (D8);
3078 nia = PC;
3079 }
3080 }
3081
3082
3083 // 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended)
3084 8.0xf8+8.0xeb+8.D8:D1:::bns
3085 "bns"
3086 *mn10300
3087 // start-sanitize-am33
3088 *am33
3089 // end-sanitize-am33
3090 {
3091 /* OP_F8EB00 (); */
3092 PC = cia;
3093 if (PSW & PSW_N)
3094 {
3095 State.regs[REG_PC] += EXTEND8 (D8);
3096 nia = PC;
3097 }
3098 }
3099
3100
3101 // 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended)
3102 8.0xca+8.D8:S1:::bra
3103 "bra"
3104 *mn10300
3105 // start-sanitize-am33
3106 *am33
3107 // end-sanitize-am33
3108 {
3109 /* OP_CA00 (); */
3110 PC = cia;
3111 State.regs[REG_PC] += EXTEND8 (D8);
3112 nia = PC;
3113 }
3114
3115
3116 // 1101 1000; leq
3117 8.0xd8:S0:::leq
3118 "leq"
3119 *mn10300
3120 // start-sanitize-am33
3121 *am33
3122 // end-sanitize-am33
3123 {
3124 /* OP_D8 (); */
3125 PC = cia;
3126 if (PSW & PSW_Z)
3127 {
3128 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3129 nia = PC;
3130 }
3131 }
3132
3133
3134 // 1101 1001; lne
3135 8.0xd9:S0:::lne
3136 "lne"
3137 *mn10300
3138 // start-sanitize-am33
3139 *am33
3140 // end-sanitize-am33
3141 {
3142 /* OP_D9 (); */
3143 PC = cia;
3144 if (!(PSW & PSW_Z))
3145 {
3146 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3147 nia = PC;
3148 }
3149 }
3150
3151
3152 // 1101 0001; lgt
3153 8.0xd1:S0:::lgt
3154 "lgt"
3155 *mn10300
3156 // start-sanitize-am33
3157 *am33
3158 // end-sanitize-am33
3159 {
3160 /* OP_D1 (); */
3161 PC = cia;
3162 if (!((PSW & PSW_Z)
3163 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
3164 {
3165 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3166 nia = PC;
3167 }
3168 }
3169
3170
3171 // 1101 0010; lge
3172 8.0xd2:S0:::lge
3173 "lge"
3174 *mn10300
3175 // start-sanitize-am33
3176 *am33
3177 // end-sanitize-am33
3178 {
3179 /* OP_D2 (); */
3180 PC = cia;
3181 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3182 {
3183 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3184 nia = PC;
3185 }
3186 }
3187
3188
3189 // 1101 0011; lle
3190 8.0xd3:S0:::lle
3191 "lle"
3192 *mn10300
3193 // start-sanitize-am33
3194 *am33
3195 // end-sanitize-am33
3196 {
3197 /* OP_D3 (); */
3198 PC = cia;
3199 if ((PSW & PSW_Z)
3200 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3201 {
3202 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3203 nia = PC;
3204 }
3205 }
3206
3207
3208 // 1101 0000; llt
3209 8.0xd0:S0:::llt
3210 "llt"
3211 *mn10300
3212 // start-sanitize-am33
3213 *am33
3214 // end-sanitize-am33
3215 {
3216 /* OP_D0 (); */
3217 PC = cia;
3218 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
3219 {
3220 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3221 nia = PC;
3222 }
3223 }
3224
3225
3226 // 1101 0101; lhi
3227 8.0xd5:S0:::lhi
3228 "lhi"
3229 *mn10300
3230 // start-sanitize-am33
3231 *am33
3232 // end-sanitize-am33
3233 {
3234 /* OP_D5 (); */
3235 PC = cia;
3236 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
3237 {
3238 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3239 nia = PC;
3240 }
3241 }
3242
3243
3244 // 1101 0110; lcc
3245 8.0xd6:S0:::lcc
3246 "lcc"
3247 *mn10300
3248 // start-sanitize-am33
3249 *am33
3250 // end-sanitize-am33
3251 {
3252 /* OP_D6 (); */
3253 PC = cia;
3254 if (!(PSW & PSW_C))
3255 {
3256 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3257 nia = PC;
3258 }
3259 }
3260
3261
3262 // 1101 0111; lls
3263 8.0xd7:S0:::lls
3264 "lls"
3265 *mn10300
3266 // start-sanitize-am33
3267 *am33
3268 // end-sanitize-am33
3269 {
3270 /* OP_D7 (); */
3271 PC = cia;
3272 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
3273 {
3274 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3275 nia = PC;
3276 }
3277 }
3278
3279
3280 // 1101 0100; lcs
3281 8.0xd4:S0:::lcs
3282 "lcs"
3283 *mn10300
3284 // start-sanitize-am33
3285 *am33
3286 // end-sanitize-am33
3287 {
3288 /* OP_D4 (); */
3289 PC = cia;
3290 if (PSW & PSW_C)
3291 {
3292 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3293 nia = PC;
3294 }
3295 }
3296
3297
3298 // 1101 1010; lra
3299 8.0xda:S0:::lra
3300 "lra"
3301 *mn10300
3302 // start-sanitize-am33
3303 *am33
3304 // end-sanitize-am33
3305 {
3306 /* OP_DA (); */
3307 PC = cia;
3308 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3309 nia = PC;
3310 }
3311
3312
3313 // 1101 1010; setlb
3314 8.0xdb:S0:::setlb
3315 "setlb"
3316 *mn10300
3317 // start-sanitize-am33
3318 *am33
3319 // end-sanitize-am33
3320 {
3321 /* OP_DB (); */
3322 PC = cia;
3323 State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
3324 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
3325 }
3326
3327
3328 // 1111 0000 1111 01An; jmp (An)
3329 8.0xf0+4.0xf,01,2.AN0:D0:::jmp
3330 "jmp"
3331 *mn10300
3332 // start-sanitize-am33
3333 *am33
3334 // end-sanitize-am33
3335 {
3336 /* OP_F0F4 (); */
3337 PC = load_word (State.regs[REG_A0 + AN0]);
3338 nia = PC;
3339 }
3340
3341
3342 // 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.)
3343 8.0xcc+8.D16A+8.D16B:S2:::jmp
3344 "jmp"
3345 *mn10300
3346 // start-sanitize-am33
3347 *am33
3348 // end-sanitize-am33
3349 {
3350 /* OP_CC0000 (); */
3351 PC = cia + EXTEND16(FETCH16(D16A, D16B));
3352 nia = PC;
3353 }
3354
3355
3356 // 1101 1100 d32........; jmp (d32, PC)
3357 8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
3358 "jmp"
3359 *mn10300
3360 // start-sanitize-am33
3361 *am33
3362 // end-sanitize-am33
3363 {
3364 /* OP_DC000000 (); */
3365 PC = cia + FETCH32(D32A, D32B, D32C, D32D);
3366 nia = PC;
3367 }
3368
3369
3370 // 1111 0000 1111 00An; calls (An)
3371 8.0xf0+4.0xf,00,2.AN0:D0:::calls
3372 "calls"
3373 *mn10300
3374 // start-sanitize-am33
3375 *am33
3376 // end-sanitize-am33
3377 {
3378 /* OP_F0F0 (); */
3379 unsigned int next_pc, sp;
3380
3381 PC = cia;
3382 sp = State.regs[REG_SP];
3383 next_pc = State.regs[REG_PC] + 2;
3384 store_word(sp, next_pc);
3385 State.regs[REG_MDR] = next_pc;
3386 State.regs[REG_PC] = State.regs[REG_A0 + AN0];
3387 nia = PC;
3388 }
3389
3390
3391 // 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.)
3392 8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
3393 "calls"
3394 *mn10300
3395 // start-sanitize-am33
3396 *am33
3397 // end-sanitize-am33
3398 {
3399 /* OP_FAFF0000 (); */
3400 unsigned int next_pc, sp;
3401
3402 PC = cia;
3403 sp = State.regs[REG_SP];
3404 next_pc = State.regs[REG_PC] + 4;
3405 store_word(sp, next_pc);
3406 State.regs[REG_MDR] = next_pc;
3407 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
3408 nia = PC;
3409 }
3410
3411
3412 // 1111 1100 1111 1111 d32.....; calls (d32,PC)
3413 8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
3414 "calls"
3415 *mn10300
3416 // start-sanitize-am33
3417 *am33
3418 // end-sanitize-am33
3419 {
3420 /* OP_FCFF0000 (); */
3421 unsigned int next_pc, sp;
3422
3423 PC = cia;
3424 sp = State.regs[REG_SP];
3425 next_pc = State.regs[REG_PC] + 6;
3426 store_word(sp, next_pc);
3427 State.regs[REG_MDR] = next_pc;
3428 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
3429 nia = PC;
3430 }
3431
3432
3433 // 1111 0000 1111 1100; rets
3434 8.0xf0+8.0xfc:D0:::rets
3435 "rets"
3436 *mn10300
3437 // start-sanitize-am33
3438 *am33
3439 // end-sanitize-am33
3440 {
3441 /* OP_F0FC (); */
3442 unsigned int sp;
3443
3444 sp = State.regs[REG_SP];
3445 State.regs[REG_PC] = load_word(sp);
3446 nia = PC;
3447 }
3448
3449
3450 // 1111 0000 1111 1101; rti
3451 8.0xf0+8.0xfd:D0:::rti
3452 "rti"
3453 *mn10300
3454 // start-sanitize-am33
3455 *am33
3456 // end-sanitize-am33
3457 {
3458 /* OP_F0FD (); */
3459 unsigned int sp;
3460
3461 sp = State.regs[REG_SP];
3462 PSW = load_half(sp);
3463 State.regs[REG_PC] = load_word(sp+4);
3464 State.regs[REG_SP] +=8;
3465 nia = PC;
3466 }
3467
3468
3469 // 1111 0000 1111 1110; trap
3470 8.0xf0+8.0xfe:D0:::trap
3471 "trap"
3472 *mn10300
3473 // start-sanitize-am33
3474 *am33
3475 // end-sanitize-am33
3476 {
3477 /* OP_F0FE (); */
3478 unsigned int sp, next_pc;
3479
3480 PC = cia;
3481 sp = State.regs[REG_SP];
3482 next_pc = State.regs[REG_PC] + 2;
3483 store_word(sp, next_pc);
3484 nia = PC;
3485 }
3486
3487
3488 // 1111 0000 1111 1111; rtm
3489 8.0xf0+8.0xff:D0:::rtm
3490 "rtm"
3491 *mn10300
3492 // start-sanitize-am33
3493 *am33
3494 // end-sanitize-am33
3495 {
3496 /* OP_F0FF (); */
3497 PC = cia;
3498 abort ();
3499 }
3500
3501
3502 // 1100 1011; nop
3503 8.0xcb:S0:::nop
3504 "nop"
3505 *mn10300
3506 // start-sanitize-am33
3507 *am33
3508 // end-sanitize-am33
3509 {
3510 /* OP_CB (); */
3511 PC = cia;
3512 }
3513
3514
3515 // 1111 0101 0000 DmDn; udf20 Dm,Dm
3516 8.0xf5+4.0x0,2.DM1,2.DM0:D0:::putx
3517 "putx"
3518 *mn10300
3519 {
3520 /* OP_F500 (); */
3521 PC = cia;
3522 State.regs[REG_MDRQ] = State.regs[REG_D0 + DM0];
3523 }
3524
3525
3526 // 1111 0110 1111 DmDn; udf15 Dn,Dn
3527 8.0xf6+4.0xf,2.DN1,2.DN0:D0:::getx
3528 "getx"
3529 *mn10300
3530 // start-sanitize-am33
3531 *am33
3532 // end-sanitize-am33
3533 {
3534 /* OP_F6F0 (); */
3535 int z, n;
3536
3537 PC = cia;
3538 z = (State.regs[REG_MDRQ] == 0);
3539 n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
3540 State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];
3541
3542 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3543 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
3544 }
3545
3546
3547 // 1111 0110 0000 DmDn; udf00 Dm,Dn
3548 8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
3549 "mulq"
3550 *mn10300
3551 // start-sanitize-am33
3552 *am33
3553 // end-sanitize-am33
3554 {
3555 /* OP_F600 (); */
3556 unsigned long long temp;
3557 int n, z;
3558
3559 PC = cia;
3560 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3561 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
3562 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3563 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3564 z = (State.regs[REG_D0 + DN0] == 0);
3565 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3566 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3567 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3568 }
3569
3570
3571 // 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.)
3572 8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
3573 "mulq"
3574 *mn10300
3575 // start-sanitize-am33
3576 *am33
3577 // end-sanitize-am33
3578 {
3579 /* OP_F90000 (); */
3580 unsigned long long temp;
3581 int n, z;
3582
3583 PC = cia;
3584 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3585 * (signed64)(signed32)EXTEND8 (IMM8));
3586 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3587 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3588 z = (State.regs[REG_D0 + DN0] == 0);
3589 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3590 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3591 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3592 }
3593
3594
3595 // 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.)
3596 8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
3597 "mulq"
3598 *mn10300
3599 // start-sanitize-am33
3600 *am33
3601 // end-sanitize-am33
3602 {
3603 /* OP_FB000000 (); */
3604 unsigned long long temp;
3605 int n, z;
3606
3607 PC = cia;
3608 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3609 * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
3610 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3611 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3612 z = (State.regs[REG_D0 + DN0] == 0);
3613 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3614 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3615 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3616 }
3617
3618
3619 // 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn
3620 8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
3621 "mulq"
3622 *mn10300
3623 // start-sanitize-am33
3624 *am33
3625 // end-sanitize-am33
3626 {
3627 /* OP_FD000000 (); */
3628 unsigned long long temp;
3629 int n, z;
3630
3631 PC = cia;
3632 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3633 * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3634 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3635 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3636 z = (State.regs[REG_D0 + DN0] == 0);
3637 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3638 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3639 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3640 }
3641
3642
3643 // 1111 0110 0001 DmDn; udf01 Dm,Dn
3644 8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
3645 "mulqu"
3646 *mn10300
3647 // start-sanitize-am33
3648 *am33
3649 // end-sanitize-am33
3650 {
3651 /* OP_F610 (); */
3652 unsigned long long temp;
3653 int n, z;
3654
3655 PC = cia;
3656 temp = ((unsigned64) State.regs[REG_D0 + DN0]
3657 * (unsigned64) State.regs[REG_D0 + DM1]);
3658 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3659 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3660 z = (State.regs[REG_D0 + DN0] == 0);
3661 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3662 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3663 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3664 }
3665
3666
3667 // 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.)
3668 8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
3669 "mulqu"
3670 *mn10300
3671 // start-sanitize-am33
3672 *am33
3673 // end-sanitize-am33
3674 {
3675 /* OP_F91400 (); */
3676 unsigned long long temp;
3677 int n, z;
3678
3679 PC = cia;
3680 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3681 * (unsigned64)EXTEND8 (IMM8));
3682 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3683 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3684 z = (State.regs[REG_D0 + DN0] == 0);
3685 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3686 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3687 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3688 }
3689
3690
3691 // 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.)
3692 8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
3693 "mulqu"
3694 *mn10300
3695 // start-sanitize-am33
3696 *am33
3697 // end-sanitize-am33
3698 {
3699 /* OP_FB140000 (); */
3700 unsigned long long temp;
3701 int n, z;
3702
3703 PC = cia;
3704 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3705 * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
3706 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3707 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3708 z = (State.regs[REG_D0 + DN0] == 0);
3709 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3710 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3711 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3712 }
3713
3714
3715 // 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn
3716 8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
3717 "mulqu"
3718 *mn10300
3719 // start-sanitize-am33
3720 *am33
3721 // end-sanitize-am33
3722 {
3723 /* OP_FD140000 (); */
3724 unsigned long long temp;
3725 int n, z;
3726
3727 PC = cia;
3728 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3729 * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3730 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3731 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3732 z = (State.regs[REG_D0 + DN0] == 0);
3733 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3734 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3735 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3736 }
3737
3738
3739 // 1111 0110 0100 DmDn; udf04 Dm,Dn
3740 8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
3741 "sat16"
3742 *mn10300
3743 // start-sanitize-am33
3744 *am33
3745 // end-sanitize-am33
3746 {
3747 /* OP_F640 (); */
3748 int temp;
3749
3750 PC = cia;
3751 temp = State.regs[REG_D0 + DM1];
3752 temp = (temp > 0x7fff ? 0x7fff : temp);
3753 temp = (temp < -0x8000 ? -0x8000 : temp);
3754 State.regs[REG_D0 + DN0] = temp;
3755 }
3756
3757
3758 // 1111 0110 0101 DmDn; udf05 Dm,Dn
3759 8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
3760 "sat24"
3761 *mn10300
3762 // start-sanitize-am33
3763 *am33
3764 // end-sanitize-am33
3765 {
3766 /* OP_F650 (); */
3767 int temp;
3768
3769 PC = cia;
3770 temp = State.regs[REG_D0 + DM1];
3771 temp = (temp > 0x7fffff ? 0x7fffff : temp);
3772 temp = (temp < -0x800000 ? -0x800000 : temp);
3773 State.regs[REG_D0 + DN0] = temp;
3774 }
3775
3776
3777 // 1111 0110 0111 DmDn; udf07 Dm,Dn
3778 8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
3779 "bsch"
3780 *mn10300
3781 // start-sanitize-am33
3782 *am33
3783 // end-sanitize-am33
3784 {
3785 /* OP_F670 (); */
3786 int temp, c;
3787
3788 PC = cia;
3789 temp = State.regs[REG_D0 + DM1];
3790 temp <<= (State.regs[REG_D0 + DN0] & 0x1f);
3791 c = (temp != 0 ? 1 : 0);
3792 PSW &= ~(PSW_C);
3793 PSW |= (c ? PSW_C : 0);
3794 }
3795
3796
3797 // 1111 0000 1100 0000; syscall
3798 8.0xf0+8.0xc0:D0:::syscall
3799 "syscall"
3800 *mn10300
3801 // start-sanitize-am33
3802 *am33
3803 // end-sanitize-am33
3804 {
3805 /* OP_F0C0 (); */
3806 PC = cia;
3807 do_syscall ();
3808 }
3809
3810
3811 // 1111 1111; break
3812 8.0xff:S0:::break
3813 "break"
3814 *mn10300
3815 // start-sanitize-am33
3816 *am33
3817 // end-sanitize-am33
3818 {
3819 /* OP_FF (); */
3820 PC = cia;
3821 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
3822 PC -= 1;
3823 }
3824
3825 // 1100 1110 regs....; movm (SP),regs
3826 8.0xce+8.REGS:S1:::movm
3827 "movm"
3828 *mn10300
3829 // start-sanitize-am33
3830 *am33
3831 // end-sanitize-am33
3832 {
3833 /* OP_CE00 (); */
3834 unsigned long sp = State.regs[REG_SP];
3835 unsigned long mask;
3836
3837 PC = cia;
3838 mask = REGS;
3839
3840 if (mask & 0x8)
3841 {
3842 sp += 4;
3843 State.regs[REG_LAR] = load_word (sp);
3844 sp += 4;
3845 State.regs[REG_LIR] = load_word (sp);
3846 sp += 4;
3847 State.regs[REG_MDR] = load_word (sp);
3848 sp += 4;
3849 State.regs[REG_A0 + 1] = load_word (sp);
3850 sp += 4;
3851 State.regs[REG_A0] = load_word (sp);
3852 sp += 4;
3853 State.regs[REG_D0 + 1] = load_word (sp);
3854 sp += 4;
3855 State.regs[REG_D0] = load_word (sp);
3856 sp += 4;
3857 }
3858
3859 if (mask & 0x10)
3860 {
3861 State.regs[REG_A0 + 3] = load_word (sp);
3862 sp += 4;
3863 }
3864
3865 if (mask & 0x20)
3866 {
3867 State.regs[REG_A0 + 2] = load_word (sp);
3868 sp += 4;
3869 }
3870
3871 if (mask & 0x40)
3872 {
3873 State.regs[REG_D0 + 3] = load_word (sp);
3874 sp += 4;
3875 }
3876
3877 if (mask & 0x80)
3878 {
3879 State.regs[REG_D0 + 2] = load_word (sp);
3880 sp += 4;
3881 }
3882
3883 /* start-sanitize-am33 */
3884 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
3885 {
3886 if (mask & 0x1)
3887 {
3888 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
3889 sp += 16;
3890 State.regs[REG_E0 + 1] = load_word (sp);
3891 sp += 4;
3892 State.regs[REG_E0 + 0] = load_word (sp);
3893 sp += 4;
3894 }
3895
3896 if (mask & 0x2)
3897 {
3898 State.regs[REG_E0 + 7] = load_word (sp);
3899 sp += 4;
3900 State.regs[REG_E0 + 6] = load_word (sp);
3901 sp += 4;
3902 State.regs[REG_E0 + 5] = load_word (sp);
3903 sp += 4;
3904 State.regs[REG_E0 + 4] = load_word (sp);
3905 sp += 4;
3906 }
3907
3908 if (mask & 0x4)
3909 {
3910 State.regs[REG_E0 + 3] = load_word (sp);
3911 sp += 4;
3912 State.regs[REG_E0 + 2] = load_word (sp);
3913 sp += 4;
3914 }
3915 }
3916 /* end-sanitize-am33 */
3917
3918 /* And make sure to update the stack pointer. */
3919 State.regs[REG_SP] = sp;
3920 }
3921
3922
3923 // 1100 1111 regs....; movm regs,(SP)
3924 8.0xcf+8.REGS:S1a:::movm
3925 "movm"
3926 *mn10300
3927 // start-sanitize-am33
3928 *am33
3929 // end-sanitize-am33
3930 {
3931 /* OP_CF00 (); */
3932 unsigned long sp = State.regs[REG_SP];
3933 unsigned long mask;
3934
3935 PC = cia;
3936 mask = REGS;
3937
3938 /* start-sanitize-am33 */
3939 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
3940 {
3941 if (mask & 0x4)
3942 {
3943 sp -= 4;
3944 store_word (sp, State.regs[REG_E0 + 2]);
3945 sp -= 4;
3946 store_word (sp, State.regs[REG_E0 + 3]);
3947 }
3948
3949 if (mask & 0x2)
3950 {
3951 sp -= 4;
3952 store_word (sp, State.regs[REG_E0 + 4]);
3953 sp -= 4;
3954 store_word (sp, State.regs[REG_E0 + 5]);
3955 sp -= 4;
3956 store_word (sp, State.regs[REG_E0 + 6]);
3957 sp -= 4;
3958 store_word (sp, State.regs[REG_E0 + 7]);
3959 }
3960
3961 if (mask & 0x1)
3962 {
3963 sp -= 4;
3964 store_word (sp, State.regs[REG_E0 + 0]);
3965 sp -= 4;
3966 store_word (sp, State.regs[REG_E0 + 1]);
3967 sp -= 16;
3968 /* Need to save MDQR, MCRH, MCRL, and MCVF */
3969 }
3970 }
3971 /* end-sanitize-am33 */
3972
3973 if (mask & 0x80)
3974 {
3975 sp -= 4;
3976 store_word (sp, State.regs[REG_D0 + 2]);
3977 }
3978
3979 if (mask & 0x40)
3980 {
3981 sp -= 4;
3982 store_word (sp, State.regs[REG_D0 + 3]);
3983 }
3984
3985 if (mask & 0x20)
3986 {
3987 sp -= 4;
3988 store_word (sp, State.regs[REG_A0 + 2]);
3989 }
3990
3991 if (mask & 0x10)
3992 {
3993 sp -= 4;
3994 store_word (sp, State.regs[REG_A0 + 3]);
3995 }
3996
3997 if (mask & 0x8)
3998 {
3999 sp -= 4;
4000 store_word (sp, State.regs[REG_D0]);
4001 sp -= 4;
4002 store_word (sp, State.regs[REG_D0 + 1]);
4003 sp -= 4;
4004 store_word (sp, State.regs[REG_A0]);
4005 sp -= 4;
4006 store_word (sp, State.regs[REG_A0 + 1]);
4007 sp -= 4;
4008 store_word (sp, State.regs[REG_MDR]);
4009 sp -= 4;
4010 store_word (sp, State.regs[REG_LIR]);
4011 sp -= 4;
4012 store_word (sp, State.regs[REG_LAR]);
4013 sp -= 4;
4014 }
4015
4016 /* And make sure to update the stack pointer. */
4017 State.regs[REG_SP] = sp;
4018 }
4019
4020 // 1100 1101 d16..... regs.... imm8....;
4021 // call (d16,PC),regs,imm8 (d16 is sign-extended., imm8 is zero-extended.)
4022 8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
4023 "call"
4024 *mn10300
4025 // start-sanitize-am33
4026 *am33
4027 // end-sanitize-am33
4028 {
4029 /* OP_CD000000 (); */
4030 unsigned int next_pc, sp;
4031 unsigned long mask;
4032
4033 PC = cia;
4034 sp = State.regs[REG_SP];
4035 next_pc = PC + 5;
4036 store_word(sp, next_pc);
4037
4038 mask = REGS;
4039
4040 /* start-sanitize-am33 */
4041 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4042 {
4043 if (mask & 0x4)
4044 {
4045 sp -= 4;
4046 store_word (sp, State.regs[REG_E0 + 2]);
4047 sp -= 4;
4048 store_word (sp, State.regs[REG_E0 + 3]);
4049 }
4050
4051 if (mask & 0x2)
4052 {
4053 sp -= 4;
4054 store_word (sp, State.regs[REG_E0 + 4]);
4055 sp -= 4;
4056 store_word (sp, State.regs[REG_E0 + 5]);
4057 sp -= 4;
4058 store_word (sp, State.regs[REG_E0 + 6]);
4059 sp -= 4;
4060 store_word (sp, State.regs[REG_E0 + 7]);
4061 }
4062
4063 if (mask & 0x1)
4064 {
4065 sp -= 4;
4066 store_word (sp, State.regs[REG_E0 + 0]);
4067 sp -= 4;
4068 store_word (sp, State.regs[REG_E0 + 1]);
4069 sp -= 16;
4070 /* Need to save MDQR, MCRH, MCRL, and MCVF */
4071 }
4072 }
4073 /* end-sanitize-am33 */
4074
4075 if (mask & 0x80)
4076 {
4077 sp -= 4;
4078 store_word (sp, State.regs[REG_D0 + 2]);
4079 }
4080
4081 if (mask & 0x40)
4082 {
4083 sp -= 4;
4084 store_word (sp, State.regs[REG_D0 + 3]);
4085 }
4086
4087 if (mask & 0x20)
4088 {
4089 sp -= 4;
4090 store_word (sp, State.regs[REG_A0 + 2]);
4091 }
4092
4093 if (mask & 0x10)
4094 {
4095 sp -= 4;
4096 store_word (sp, State.regs[REG_A0 + 3]);
4097 }
4098
4099 if (mask & 0x8)
4100 {
4101 sp -= 4;
4102 store_word (sp, State.regs[REG_D0]);
4103 sp -= 4;
4104 store_word (sp, State.regs[REG_D0 + 1]);
4105 sp -= 4;
4106 store_word (sp, State.regs[REG_A0]);
4107 sp -= 4;
4108 store_word (sp, State.regs[REG_A0 + 1]);
4109 sp -= 4;
4110 store_word (sp, State.regs[REG_MDR]);
4111 sp -= 4;
4112 store_word (sp, State.regs[REG_LIR]);
4113 sp -= 4;
4114 store_word (sp, State.regs[REG_LAR]);
4115 sp -= 4;
4116 }
4117
4118 /* Update the stack pointer, note that the register saves to do not
4119 modify SP. The SP adjustment is derived totally from the imm8
4120 field. */
4121 State.regs[REG_SP] -= IMM8;
4122 State.regs[REG_MDR] = next_pc;
4123 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
4124 nia = PC;
4125 }
4126
4127
4128 // 1101 1101 d32..... regs.... imm8....;
4129 // call (d32,PC),regs,imm8 (imm8 is zero-extended.)
4130 8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
4131 "call"
4132 *mn10300
4133 // start-sanitize-am33
4134 *am33
4135 // end-sanitize-am33
4136 {
4137 /* OP_DD000000 (); */
4138 unsigned int next_pc, sp;
4139 unsigned long mask;
4140
4141 PC = cia;
4142 sp = State.regs[REG_SP];
4143 next_pc = State.regs[REG_PC] + 7;
4144 /* could assert that nia == next_pc here */
4145 store_word(sp, next_pc);
4146
4147 mask = REGS;
4148
4149 /* start-sanitize-am33 */
4150 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4151 {
4152 if (mask & 0x4)
4153 {
4154 sp -= 4;
4155 store_word (sp, State.regs[REG_E0 + 2]);
4156 sp -= 4;
4157 store_word (sp, State.regs[REG_E0 + 3]);
4158 }
4159
4160 if (mask & 0x2)
4161 {
4162 sp -= 4;
4163 store_word (sp, State.regs[REG_E0 + 4]);
4164 sp -= 4;
4165 store_word (sp, State.regs[REG_E0 + 5]);
4166 sp -= 4;
4167 store_word (sp, State.regs[REG_E0 + 6]);
4168 sp -= 4;
4169 store_word (sp, State.regs[REG_E0 + 7]);
4170 }
4171
4172 if (mask & 0x1)
4173 {
4174 sp -= 4;
4175 store_word (sp, State.regs[REG_E0 + 0]);
4176 sp -= 4;
4177 store_word (sp, State.regs[REG_E0 + 1]);
4178 sp -= 16;
4179 /* Need to save MDQR, MCRH, MCRL, and MCVF */
4180 }
4181 }
4182 /* end-sanitize-am33 */
4183
4184 if (mask & 0x80)
4185 {
4186 sp -= 4;
4187 store_word (sp, State.regs[REG_D0 + 2]);
4188 }
4189
4190 if (mask & 0x40)
4191 {
4192 sp -= 4;
4193 store_word (sp, State.regs[REG_D0 + 3]);
4194 }
4195
4196 if (mask & 0x20)
4197 {
4198 sp -= 4;
4199 store_word (sp, State.regs[REG_A0 + 2]);
4200 }
4201
4202 if (mask & 0x10)
4203 {
4204 sp -= 4;
4205 store_word (sp, State.regs[REG_A0 + 3]);
4206 }
4207
4208 if (mask & 0x8)
4209 {
4210 sp -= 4;
4211 store_word (sp, State.regs[REG_D0]);
4212 sp -= 4;
4213 store_word (sp, State.regs[REG_D0 + 1]);
4214 sp -= 4;
4215 store_word (sp, State.regs[REG_A0]);
4216 sp -= 4;
4217 store_word (sp, State.regs[REG_A0 + 1]);
4218 sp -= 4;
4219 store_word (sp, State.regs[REG_MDR]);
4220 sp -= 4;
4221 store_word (sp, State.regs[REG_LIR]);
4222 sp -= 4;
4223 store_word (sp, State.regs[REG_LAR]);
4224 sp -= 4;
4225 }
4226
4227 /* Update the stack pointer, note that the register saves to do not
4228 modify SP. The SP adjustment is derived totally from the imm8
4229 field. */
4230 State.regs[REG_SP] -= IMM8;
4231 State.regs[REG_MDR] = next_pc;
4232 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
4233 nia = PC;
4234 }
4235
4236
4237 // 1101 1111 regs.... imm8....; ret regs,imm8 (imm8 is zero-extended.)
4238 8.0xdf+8.REGS+8.IMM8:S2:::ret
4239 "ret"
4240 *mn10300
4241 // start-sanitize-am33
4242 *am33
4243 // end-sanitize-am33
4244 {
4245 /* OP_DF0000 (); */
4246 unsigned int sp, offset;
4247 unsigned long mask;
4248
4249 PC = cia;
4250 State.regs[REG_SP] += IMM8;
4251 sp = State.regs[REG_SP];
4252
4253 offset = -4;
4254 mask = REGS;
4255
4256 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4257 {
4258
4259 if (mask & 0x4)
4260 {
4261 State.regs[REG_E0 + 2] = load_word (sp + offset);
4262 offset -= 4;
4263 State.regs[REG_E0 + 3] = load_word (sp + offset);
4264 offset -= 4;
4265 }
4266
4267 if (mask & 0x2)
4268 {
4269 State.regs[REG_E0 + 4] = load_word (sp + offset);
4270 offset -= 4;
4271 State.regs[REG_E0 + 5] = load_word (sp + offset);
4272 offset -= 4;
4273 State.regs[REG_E0 + 6] = load_word (sp + offset);
4274 offset -= 4;
4275 State.regs[REG_E0 + 7] = load_word (sp + offset);
4276 offset -= 4;
4277 }
4278
4279 if (mask & 0x1)
4280 {
4281 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
4282 offset -= 16;
4283 State.regs[REG_E0 + 0] = load_word (sp + offset);
4284 offset -= 4;
4285 State.regs[REG_E0 + 1] = load_word (sp + offset);
4286 offset -= 4;
4287 }
4288
4289 }
4290
4291 if (mask & 0x80)
4292 {
4293 State.regs[REG_D0 + 2] = load_word (sp + offset);
4294 offset -= 4;
4295 }
4296
4297 if (mask & 0x40)
4298 {
4299 State.regs[REG_D0 + 3] = load_word (sp + offset);
4300 offset -= 4;
4301 }
4302
4303 if (mask & 0x20)
4304 {
4305 State.regs[REG_A0 + 2] = load_word (sp + offset);
4306 offset -= 4;
4307 }
4308
4309 if (mask & 0x10)
4310 {
4311 State.regs[REG_A0 + 3] = load_word (sp + offset);
4312 offset -= 4;
4313 }
4314
4315 if (mask & 0x8)
4316 {
4317 State.regs[REG_D0] = load_word (sp + offset);
4318 offset -= 4;
4319 State.regs[REG_D0 + 1] = load_word (sp + offset);
4320 offset -= 4;
4321 State.regs[REG_A0] = load_word (sp + offset);
4322 offset -= 4;
4323 State.regs[REG_A0 + 1] = load_word (sp + offset);
4324 offset -= 4;
4325 State.regs[REG_MDR] = load_word (sp + offset);
4326 offset -= 4;
4327 State.regs[REG_LIR] = load_word (sp + offset);
4328 offset -= 4;
4329 State.regs[REG_LAR] = load_word (sp + offset);
4330 offset -= 4;
4331 }
4332
4333 /* Restore the PC value. */
4334 State.regs[REG_PC] = load_word(sp);
4335 nia = PC;
4336 }
4337
4338
4339 // 1101 1110 regs.... imm8....; retf regs,imm8 (imm8 is zero-extended.)
4340 8.0xde+8.REGS+8.IMM8:S2:::retf
4341 "retf"
4342 *mn10300
4343 // start-sanitize-am33
4344 *am33
4345 // end-sanitize-am33
4346 {
4347 /* OP_DE0000 (); */
4348 unsigned int sp, offset;
4349 unsigned long mask;
4350
4351 PC = cia;
4352 State.regs[REG_SP] += IMM8;
4353 sp = State.regs[REG_SP];
4354 State.regs[REG_PC] = State.regs[REG_MDR] - 3;
4355
4356 offset = -4;
4357 mask = REGS;
4358
4359 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4360 {
4361
4362 if (mask & 0x4)
4363 {
4364 State.regs[REG_E0 + 2] = load_word (sp + offset);
4365 offset -= 4;
4366 State.regs[REG_E0 + 3] = load_word (sp + offset);
4367 offset -= 4;
4368 }
4369
4370 if (mask & 0x2)
4371 {
4372 State.regs[REG_E0 + 4] = load_word (sp + offset);
4373 offset -= 4;
4374 State.regs[REG_E0 + 5] = load_word (sp + offset);
4375 offset -= 4;
4376 State.regs[REG_E0 + 6] = load_word (sp + offset);
4377 offset -= 4;
4378 State.regs[REG_E0 + 7] = load_word (sp + offset);
4379 offset -= 4;
4380 }
4381
4382 if (mask & 0x1)
4383 {
4384 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
4385 offset -= 16;
4386 State.regs[REG_E0 + 0] = load_word (sp + offset);
4387 offset -= 4;
4388 State.regs[REG_E0 + 1] = load_word (sp + offset);
4389 offset -= 4;
4390 }
4391
4392 }
4393
4394 if (mask & 0x80)
4395 {
4396 State.regs[REG_D0 + 2] = load_word (sp + offset);
4397 offset -= 4;
4398 }
4399
4400 if (mask & 0x40)
4401 {
4402 State.regs[REG_D0 + 3] = load_word (sp + offset);
4403 offset -= 4;
4404 }
4405
4406 if (mask & 0x20)
4407 {
4408 State.regs[REG_A0 + 2] = load_word (sp + offset);
4409 offset -= 4;
4410 }
4411
4412 if (mask & 0x10)
4413 {
4414 State.regs[REG_A0 + 3] = load_word (sp + offset);
4415 offset -= 4;
4416 }
4417
4418 if (mask & 0x8)
4419 {
4420 State.regs[REG_D0] = load_word (sp + offset);
4421 offset -= 4;
4422 State.regs[REG_D0 + 1] = load_word (sp + offset);
4423 offset -= 4;
4424 State.regs[REG_A0] = load_word (sp + offset);
4425 offset -= 4;
4426 State.regs[REG_A0 + 1] = load_word (sp + offset);
4427 offset -= 4;
4428 State.regs[REG_MDR] = load_word (sp + offset);
4429 offset -= 4;
4430 State.regs[REG_LIR] = load_word (sp + offset);
4431 offset -= 4;
4432 State.regs[REG_LAR] = load_word (sp + offset);
4433 offset -= 4;
4434 }
4435 }
4436
4437 // start-sanitize-am33
4438 :include::am33:am33.igen
4439 // end-sanitize-am33
GDB Binutils - Deliverables
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