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[deliverable/binutils-gdb.git] / sim / mn10300 / mn10300.igen
1 :option:::insn-bit-size:8
2 :option:::insn-specifying-widths:true
3 :option:::hi-bit-nr:7
4 :model:::mn10300:mn10300:
5
6 // What do we do with an illegal instruction?
7 :internal::::illegal:
8 {
9 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
10 (unsigned long) cia);
11 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
12 }
13
14 // 1000 DnDn imm8....; mov imm8,Dn (imm8 is sign extended)
15 // 1000 DmDn; mov Dm,Dn (Dm != Dn, see above when Dm == Dn)
16 4.0x8,2.DM1,2.DN0:S0:::mov
17 "mov"
18 *mn10300
19 {
20 PC = cia;
21 if ( DM1 == DN0 )
22 {
23 // OP_8000 ();
24 signed32 immed = EXTEND8 (IMEM8_IMMED (cia, 1));
25 nia = cia + 2;
26 State.regs[REG_D0+DN0] = immed;
27 }
28 else
29 {
30 // OP_80 ();
31 State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1];
32 }
33 }
34
35
36 // 1111 0001 1110 DmAn; mov Dm,An
37 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
38 "mov"
39 *mn10300
40 {
41 // OP_F1E0 ();
42 PC = cia;
43 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1];
44 }
45
46
47 // 1111 0001 1101 AmDn; mov Am,Dn
48 8.0xf1+1101,2.AM1,2.DN0:D0a:::mov
49 "mov"
50 *mn10300
51 {
52 // OP_F1D0 ();
53 PC = cia;
54 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1];
55 }
56
57
58 // 1001 AnAn imm8....; mov imm8,An (imm8 is zero-extended)
59 // 1001 AmAn; mov Am,An (Am != An, save above when Am == An)
60 4.0x9,2.AM1,2.AN0:S0a:::mov
61 "mov"
62 *mn10300
63 {
64 PC = cia;
65 if ( AM1 == AN0 )
66 {
67 // OP_9000 ();
68 unsigned long immed = IMEM8_IMMED (cia, 1);
69 nia = cia + 2;
70 State.regs[REG_A0+AN0] = immed;
71 }
72 else
73 {
74 // OP_90 ();
75 State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1];
76 }
77 }
78
79
80 // 0011 11An; mov SP,An
81 4.0x3,11,2.AN0:S0b:::mov
82 "mov"
83 *mn10300
84 {
85 // OP_3C ();
86 PC = cia;
87 State.regs[REG_A0 + AN0] = State.regs[REG_SP];
88 }
89
90
91 // 1111 0010 1111 Am00; mov Am,SP
92 8.0xf2+4.0xf,2.AM1,00:D0b:::mov
93 "mov"
94 *mn10300
95 {
96 // OP_F2F0 ();
97 PC = cia;
98 State.regs[REG_SP] = State.regs[REG_A0 + AM1];
99 }
100
101
102 // 1111 0010 1110 01Dn; mov PSW,Dn
103 8.0xf2+4.0xe,01,2.DN0:D0c:::mov
104 "mov"
105 *mn10300
106 {
107 // OP_F2E4 ();
108 PC = cia;
109 State.regs[REG_D0 + DN0] = PSW;
110 }
111
112
113 // 1111 0010 1111 Dm11; mov Dm,PSW
114 8.0xf2+4.0xf,2.DM1,11:D0d:::mov
115 "mov"
116 *mn10300
117 {
118 // OP_F2F3 ();
119 PC = cia;
120 PSW = State.regs[REG_D0 + DM1];
121 }
122
123
124 // 1111 0010 1110 00Dn; mov MDR,Dn
125 8.0xf2+4.0xe,00,2.DN0:D0e:::mov
126 "mov"
127 *mn10300
128 {
129 // OP_F2E0 ();
130 PC = cia;
131 State.regs[REG_D0 + DN0] = State.regs[REG_MDR];
132 }
133
134
135 // 1111 0010 1111 Dm10; mov Dm,MDR
136 8.0xf2+4.0xf,2.DM1,10:D0f:::mov
137 "mov"
138 *mn10300
139 {
140 // OP_F2F2 ();
141 PC = cia;
142 State.regs[REG_MDR] = State.regs[REG_D0 + DM1];
143 }
144
145
146 // 0111 DnAm; mov (Am),Dn
147 4.0x7,2.DN1,2.AM0:S0c:::mov
148 "mov"
149 *mn10300
150 {
151 // OP_70 ();
152 PC = cia;
153 State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]);
154 }
155
156
157 // 1111 1000 0000 DnAm d8......; mov (d8,Am),Dn (d8 is sign-extended)
158 8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
159 "mov"
160 *mn10300
161 {
162 // OP_F80000 ();
163 PC = cia;
164 State.regs[REG_D0 + DN1]
165 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
166 }
167
168
169 // 1111 1010 0000 DnAm d16.....; mov (d16,Am),Dn (d16 is sign-extended.)
170 8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
171 "mov"
172 *mn10300
173 {
174 // OP_FA000000 ();
175 PC = cia;
176 State.regs[REG_D0 + DN1]
177 = load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B))));
178 }
179
180
181 // 1111 1100 0000 DnAm d32.....; mov (d32,Am),Dn
182 8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
183 "mov"
184 *mn10300
185 {
186 // OP_FC000000 ();
187 PC = cia;
188 State.regs[REG_D0 + DN1]
189 = load_word ((State.regs[REG_A0 + AM0]
190 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
191 }
192
193
194 // 0101 10Dn d8......; mov (d8,SP),Dn (d8 is zero-extended)
195 4.0x5,10,2.DN0+8.D8:S1:::mov
196 "mov"
197 *mn10300
198 {
199 // OP_5800 ();
200 PC = cia;
201 State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8);
202 }
203
204
205 // 1111 1010 1011 01Dn d16.....; mov (d16,SP),Dn (d16 is zero-extended.)
206 8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
207 "mov"
208 *mn10300
209 {
210 // OP_FAB40000 ();
211 PC = cia;
212 State.regs[REG_D0 + DN0]
213 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
214 }
215
216
217 // 1111 1010 1011 01Dn d32.....; mov (d32,SP),Dn
218 8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
219 "mov"
220 *mn10300
221 {
222 // OP_FCB40000 ();
223 PC = cia;
224 State.regs[REG_D0 + DN0]
225 = load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
226 }
227
228
229 // 1111 0011 00Dn DiAm; mov (Di,Am),Dn
230 8.0xf3+00,2.DI,2.AM0,2.DN2:D0g:::mov
231 "mov"
232 *mn10300
233 {
234 // OP_F300 ();
235 PC = cia;
236 State.regs[REG_D0 + DN2]
237 = load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
238 }
239
240
241 // 0011 00Dn abs16...; mov (abs16),Dn (abs16 is zero-extended)
242 4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
243 "mov"
244 *mn10300
245 {
246 // OP_300000 ();
247 PC = cia;
248 State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B));
249 }
250
251 // 1111 1100 1010 01Dn abs32...; mov (abs32),Dn
252 8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
253 "mov"
254 *mn10300
255 {
256 // OP_FCA40000 ();
257 PC = cia;
258 State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
259 }
260
261
262 // 1111 0000 0000 AnAm; mov (Am),An
263 8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
264 "mov"
265 *mn10300
266 {
267 // OP_F000 ();
268 PC = cia;
269 State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]);
270 }
271
272
273 // 1111 1000 0010 AnAm d8......; mov (d8,Am),An (d8 is sign-extended)
274 8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
275 "mov"
276 *mn10300
277 {
278 // OP_F82000 ();
279 PC = cia;
280 State.regs[REG_A0 + AN1]
281 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
282 }
283
284
285 // 1111 1010 0010 AnAm d16.....; mov (d16,Am),An (d16 is sign-extended.)
286 8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
287 "mov"
288 *mn10300
289 {
290 // OP_FA200000 ();
291 PC = cia;
292 State.regs[REG_A0 + AN1]
293 = load_word ((State.regs[REG_A0 + AM0]
294 + EXTEND16 (FETCH16(D16A, D16B))));
295 }
296
297
298 // 1111 1100 0010 AnAm d32.....; mov (d32,Am),An
299 8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
300 "mov"
301 *mn10300
302 {
303 // OP_FC200000 ();
304 PC = cia;
305 State.regs[REG_A0 + AN1]
306 = load_word ((State.regs[REG_A0 + AM0]
307 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
308 }
309
310
311 // 0101 11An d8......; mov (d8,SP),An (d8 is zero-extended)
312 4.0x5,11,2.AN0+8.D8:S1a:::mov
313 "mov"
314 *mn10300
315 {
316 // OP_5C00 ();
317 PC = cia;
318 State.regs[REG_A0 + AN0]
319 = load_word (State.regs[REG_SP] + D8);
320 }
321
322
323 // 1111 1010 1011 00An d16.....; mov (d16,SP),An (d16 is zero-extended.)
324 8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
325 "mov"
326 *mn10300
327 {
328 // OP_FAB00000 ();
329 PC = cia;
330 State.regs[REG_A0 + AN0]
331 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
332 }
333
334
335 // 1111 1100 1011 00An d32.....; mov (d32,SP),An
336 8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
337 "mov"
338 *mn10300
339 {
340 // OP_FCB00000 ();
341 PC = cia;
342 State.regs[REG_A0 + AN0]
343 = load_word (State.regs[REG_SP]
344 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
345 }
346
347
348 // 1111 0011 10An DiAm; mov (Di,Am),An
349 8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
350 "mov"
351 *mn10300
352 {
353 // OP_F380 ();
354 PC = cia;
355 State.regs[REG_A0 + AN2]
356 = load_word ((State.regs[REG_A0 + AM0]
357 + State.regs[REG_D0 + DI]));
358 }
359
360
361 // 1111 1010 1010 00An abs16...; mov (abs16),An (abs16 is zero-extended)
362 8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
363 "mov"
364 *mn10300
365 {
366 // OP_FAA00000 ();
367 PC = cia;
368 State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B));
369 }
370
371
372 // 1111 1100 1010 00An abs32...; mov (abs32),An
373 8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
374 "mov"
375 *mn10300
376 {
377 // OP_FCA00000 ();
378 PC = cia;
379 State.regs[REG_A0 + AN0]
380 = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
381 }
382
383
384 // 1111 1000 1111 00Am d8......; mov (d8,Am),SP (d8 is sign-extended)
385 8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
386 "mov"
387 *mn10300
388 {
389 // OP_F8F000 ();
390 PC = cia;
391 State.regs[REG_SP]
392 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
393 }
394
395
396 // 0110 DmAn; mov Dm,(An)
397 4.0x6,2.DM1,2.AN0:S0d:::mov
398 "mov"
399 *mn10300
400 {
401 // OP_60 ();
402 PC = cia;
403 store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
404 }
405
406
407 // 1111 1000 0001 DmAn d8......; mov Dm,(d8,An) (d8 is sign-extended)
408 8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
409 "mov"
410 *mn10300
411 {
412 // OP_F81000 ();
413 PC = cia;
414 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
415 State.regs[REG_D0 + DM1]);
416 }
417
418
419 // 1111 1010 0001 DmAn d16.....; mov Dm,(d16,An) (d16 is sign-extended.)
420 8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
421 "mov"
422 *mn10300
423 {
424 // OP_FA100000 ();
425 PC = cia;
426 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
427 State.regs[REG_D0 + DM1]);
428 }
429
430
431 // 1111 1100 0001 DmAn d32.....; mov Dm,(d32,An)
432 8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
433 "mov"
434 *mn10300
435 {
436 // OP_FC100000 ();
437 PC = cia;
438 store_word ((State.regs[REG_A0 + AN0]
439 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
440 State.regs[REG_D0 + DM1]);
441 }
442
443
444 // 0100 Dm10 d8......; mov Dm,(d8,SP) (d8 is zero-extended)
445 4.0x4,2.DM1,10+8.D8:S1b:::mov
446 "mov"
447 *mn10300
448 {
449 // OP_4200 ();
450 PC = cia;
451 store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]);
452 }
453
454
455 // 1111 1010 1001 Dm01 d16.....; mov Dm,(d16,SP) (d16 is zero-extended.)
456 8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
457 "mov"
458 *mn10300
459 {
460 // OP_FA910000 ();
461 PC = cia;
462 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
463 State.regs[REG_D0 + DM1]);
464 }
465
466
467 // 1111 1100 1001 Dm01 d32.....; mov Dm,(d32,SP)
468 8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
469 "mov"
470 *mn10300
471 {
472 // OP_FC910000 ();
473 PC = cia;
474 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
475 State.regs[REG_D0 + DM1]);
476 }
477
478
479 // 1111 0011 01Dm DiAn; mov Dm,(Di,An)
480 8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
481 "mov"
482 *mn10300
483 {
484 // OP_F340 ();
485 PC = cia;
486 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
487 State.regs[REG_D0 + DM2]);
488 }
489
490
491 // 0000 Dm01 abs16..., mov Dm,(abs16) (abs16 is zero-extended).
492 4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
493 "mov"
494 *mn10300
495 {
496 // OP_10000 ();
497 PC = cia;
498 store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
499 }
500
501
502 // 1111 1100 1000 Dm01 abs32...; mov Dm,(abs32)
503 8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
504 "mov"
505 *mn10300
506 {
507 // OP_FC810000 ();
508 PC = cia;
509 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
510 State.regs[REG_D0 + DM1]);
511 }
512
513
514 // 1111 0000 0001 AmAn; mov Am,(An)
515 8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
516 "mov"
517 *mn10300
518 {
519 // OP_F010 ();
520 PC = cia;
521 store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]);
522 }
523
524
525 // 1111 1000 0011 AmAn d8......; mov Am,(d8,An) (d8 is sign-extended)
526 8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
527 "mov"
528 *mn10300
529 {
530 // OP_F83000 ();
531 PC = cia;
532 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
533 State.regs[REG_A0 + AM1]);
534 }
535
536
537 // 1111 1010 0011 AmAn d16.....; mov Am,(d16,An) (d16 is sign-extended.)
538 8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
539 "mov"
540 *mn10300
541 {
542 // OP_FA300000 ();
543 PC = cia;
544 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
545 State.regs[REG_A0 + AM1]);
546 }
547
548
549 // 1111 1100 0011 AmAn d32.....; mov Am,(d32,An)
550 8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
551 "mov"
552 *mn10300
553 {
554 // OP_FC300000 ();
555 PC = cia;
556 store_word ((State.regs[REG_A0 + AN0]
557 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
558 State.regs[REG_A0 + AM1]);
559 }
560
561
562 // 0100 Am11 d8......; mov Am,(d8,SP) (d8 is zero-extended)
563 4.0x4,2.AM1,11+8.D8:S1c:::mov
564 "mov"
565 *mn10300
566 {
567 // OP_4300 ();
568 PC = cia;
569 store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]);
570 }
571
572
573 // 1111 1010 1001 Am00 d16.....; mov Am,(d16,SP) (d16 is zero-extended.)
574 8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
575 "mov"
576 *mn10300
577 {
578 // OP_FA900000 ();
579 PC = cia;
580 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
581 State.regs[REG_A0 + AM1]);
582 }
583
584
585 // 1111 1100 1001 Am00 d32.....; mov Am,(d32,SP)
586 8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
587 "mov"
588 *mn10300
589 {
590 // OP_FC900000 ();
591 PC = cia;
592 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
593 State.regs[REG_A0 + AM1]);
594 }
595
596
597 // 1111 0011 11Am DiAn; mov Am,(Di,An)
598 8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
599 "mov"
600 *mn10300
601 {
602 // OP_F3C0 ();
603 PC = cia;
604 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
605 State.regs[REG_A0 + AM2]);
606 }
607
608
609 // 1111 1010 1000 Am00 abs16...; mov Am,(abs16) (abs16 is zero-extended)
610 8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
611 "mov"
612 *mn10300
613 {
614 // OP_FA800000 ();
615 PC = cia;
616 store_word (FETCH16(IMM16A, IMM16B),
617 State.regs[REG_A0 + AM1]);
618 }
619
620
621 // 1111 1100 1000 Am00 abs32...; mov Am,(abs32)
622 8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
623 "mov"
624 *mn10300
625 {
626 // OP_FC800000 ();
627 PC = cia;
628 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
629 State.regs[REG_A0 + AM1]);
630 }
631
632
633 // 1111 1000 1111 01An d8......; mov SP,(d8,An) (d8 is sign-extended)
634 8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
635 "mov"
636 *mn10300
637 {
638 // OP_F8F400 ();
639 PC = cia;
640 store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8),
641 State.regs[REG_SP]);
642 }
643
644
645 // 0010 11Dn imm16...; mov imm16,Dn (imm16 is sign-extended)
646 4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
647 "mov"
648 *mn10300
649 {
650 // OP_2C0000 ();
651 unsigned long value;
652
653 PC = cia;
654 value = EXTEND16 (FETCH16(IMM16A, IMM16B));
655 State.regs[REG_D0 + DN0] = value;
656 }
657
658
659 // 1111 1100 1100 11Dn imm32...; mov imm32,Dn
660 8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
661 "mov"
662 *mn10300
663 {
664 // OP_FCCC0000 ();
665 unsigned long value;
666
667 PC = cia;
668 value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
669 State.regs[REG_D0 + DN0] = value;
670 }
671
672
673 // 0010 01An imm16...; mov imm16,An (imm16 is zero-extended)
674 4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
675 "mov"
676 *mn10300
677 {
678 // OP_240000 ();
679 unsigned long value;
680
681 PC = cia;
682 value = FETCH16(IMM16A, IMM16B);
683 State.regs[REG_A0 + AN0] = value;
684 }
685
686
687 // 1111 1100 1101 11An imm32...; mov imm32,An
688 8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
689 "mov"
690 *mn10300
691 {
692 // OP_FCDC0000 ();
693 PC = cia;
694 State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
695 }
696
697
698 // 1111 0000 0100 DnAm; movbu (Am),Dn
699 8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
700 "movbu"
701 *mn10300
702 {
703 // OP_F040 ();
704 PC = cia;
705 State.regs[REG_D0 + DN1]
706 = load_byte (State.regs[REG_A0 + AM0]);
707 }
708
709
710 // 1111 1000 0100 DnAm d8......; movbu (d8,Am),Dn (d8 is sign-extended)
711 8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
712 "movbu"
713 *mn10300
714 {
715 // OP_F84000 ();
716 PC = cia;
717 State.regs[REG_D0 + DN1]
718 = load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
719 }
720
721
722 // 1111 1010 0100 DnAm d16.....; movbu (d16,Am),Dn (d16 is sign-extended.)
723 8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
724 "movbu"
725 *mn10300
726 {
727 // OP_FA400000 ();
728 PC = cia;
729 State.regs[REG_D0 + DN1]
730 = load_byte ((State.regs[REG_A0 + AM0]
731 + EXTEND16 (FETCH16(D16A, D16B))));
732 }
733
734
735 // 1111 1100 0100 DnAm d32.....; movbu (d32,Am),Dn
736 8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
737 "movbu"
738 *mn10300
739 {
740 // OP_FC400000 ();
741 PC = cia;
742 State.regs[REG_D0 + DN1]
743 = load_byte ((State.regs[REG_A0 + AM0]
744 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
745 }
746
747
748 // 1111 1000 1011 10Dn d8......; movbu (d8,SP),Dn (d8 is zero-extended)
749 8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
750 "movbu"
751 *mn10300
752 {
753 // OP_F8B800 ();
754 PC = cia;
755 State.regs[REG_D0 + DN0]
756 = load_byte ((State.regs[REG_SP] + (D8)));
757 }
758
759
760 // 1111 1010 1011 10Dn d16.....; movbu (d16,SP),Dn (d16 is zero-extended.)
761 8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
762 "movbu"
763 *mn10300
764 {
765 // OP_FAB80000 ();
766 PC = cia;
767 State.regs[REG_D0 + DN0]
768 = load_byte ((State.regs[REG_SP]
769 + FETCH16(IMM16A, IMM16B)));
770 }
771
772
773 // 1111 1100 1011 10Dn d32.....; movbu (d32,SP),Dn
774 8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
775 "movbu"
776 *mn10300
777 {
778 // OP_FCB80000 ();
779 PC = cia;
780 State.regs[REG_D0 + DN0]
781 = load_byte (State.regs[REG_SP]
782 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
783 }
784
785
786 // 1111 0100 00Dn DiAm; movbu (Di,Am),Dn
787 8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
788 "movbu"
789 *mn10300
790 {
791 // OP_F400 ();
792 PC = cia;
793 State.regs[REG_D0 + DN2]
794 = load_byte ((State.regs[REG_A0 + AM0]
795 + State.regs[REG_D0 + DI]));
796 }
797
798
799 // 0011 01Dn abs16...; movbu (abs16),Dn (abs16 is zero-extended)
800 4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
801 "movbu"
802 *mn10300
803 {
804 // OP_340000 ();
805 PC = cia;
806 State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B));
807 }
808
809
810 // 1111 1100 1010 10Dn abs32...; movbu (abs32),Dn
811 8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
812 "movbu"
813 *mn10300
814 {
815 // OP_FCA80000 ();
816 PC = cia;
817 State.regs[REG_D0 + DN0]
818 = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
819 }
820
821
822 // 1111 0000 0101 DmAn; movbu Dm,(An)
823 8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
824 "movbu"
825 *mn10300
826 {
827 // OP_F050 ();
828 PC = cia;
829 store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
830 }
831
832
833 // 1111 1000 0101 DmAn d8......; movbu Dm,(d8,An) (d8 is sign-extended)
834 8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
835 "movbu"
836 *mn10300
837 {
838 // OP_F85000 ();
839 PC = cia;
840 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
841 State.regs[REG_D0 + DM1]);
842 }
843
844
845 // 1111 1010 0101 DmAn d16.....; movbu Dm,(d16,An) (d16 is sign-extended.)
846 8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
847 "movbu"
848 *mn10300
849 {
850 // OP_FA500000 ();
851 PC = cia;
852 store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
853 State.regs[REG_D0 + DM1]);
854 }
855
856
857 // 1111 1100 0101 DmAn d32.....; movbu Dm,(d32,An)
858 8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
859 "movbu"
860 *mn10300
861 {
862 // OP_FC500000 ();
863 PC = cia;
864 store_byte ((State.regs[REG_A0 + AN0]
865 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
866 State.regs[REG_D0 + DM1]);
867 }
868
869
870 // 1111 1000 1001 Dm10 d8......; movbu Dm,(d8,SP) (d8 is zero-extended)
871 8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
872 "movbu"
873 *mn10300
874 {
875 // OP_F89200 ();
876 PC = cia;
877 store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]);
878 }
879
880
881 // 1111 1010 1001 Dm10 d16.....; movbu Dm,(d16,SP) (d16 is zero-extended.)
882 8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
883 "movbu"
884 *mn10300
885 {
886 // OP_FA920000 ();
887 PC = cia;
888 store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
889 State.regs[REG_D0 + DM1]);
890 }
891
892
893 // 1111 1100 1001 Dm10 d32.....; movbu Dm,(d32,SP)
894 8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
895 "movbu"
896 *mn10300
897 {
898 // OP_FC920000 ();
899 PC = cia;
900 store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
901 State.regs[REG_D0 + DM1]);
902 }
903
904
905 // 1111 0100 01Dm DiAn; movbu Dm,(Di,An)
906 8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
907 "movbu"
908 *mn10300
909 {
910 // OP_F440 ();
911 PC = cia;
912 store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
913 State.regs[REG_D0 + DM2]);
914 }
915
916
917 // 0000 Dm10 abs16...; movbu Dm,(abs16) (abs16 is zero-extended)
918 4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
919 "movbu"
920 *mn10300
921 {
922 // OP_20000 ();
923 PC = cia;
924 store_byte (FETCH16(IMM16A, IMM16B),
925 State.regs[REG_D0 + DM1]);
926 }
927
928
929 // 1111 1100 1000 Dm10 abs32...; movbu Dm,(abs32)
930 8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
931 "movbu"
932 *mn10300
933 {
934 // OP_FC820000 ();
935 PC = cia;
936 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
937 State.regs[REG_D0 + DM1]);
938 }
939
940
941 // 1111 0000 0110 DnAm; movhu (Am),Dn
942 8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
943 "movhu"
944 *mn10300
945 {
946 // OP_F060 ();
947 PC = cia;
948 State.regs[REG_D0 + DN1]
949 = load_half (State.regs[REG_A0 + AM0]);
950 }
951
952
953 // 1111 1000 0110 DnAm d8......; movhu (d8,Am),Dn (d8 is sign-extended)
954 8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
955 "movhu"
956 *mn10300
957 {
958 // OP_F86000 ();
959 PC = cia;
960 State.regs[REG_D0 + DN1]
961 = load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
962 }
963
964
965 // 1111 1010 0110 DnAm d16.....; movhu (d16,Am),Dn (d16 is sign-extended.)
966 8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
967 "movhu"
968 *mn10300
969 {
970 // OP_FA600000 ();
971 PC = cia;
972 State.regs[REG_D0 + DN1]
973 = load_half ((State.regs[REG_A0 + AM0]
974 + EXTEND16 (FETCH16(D16A, D16B))));
975 }
976
977
978 // 1111 1100 0110 DnAm d32.....; movhu (d32,Am),Dn
979 8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
980 "movhu"
981 *mn10300
982 {
983 // OP_FC600000 ();
984 PC = cia;
985 State.regs[REG_D0 + DN1]
986 = load_half ((State.regs[REG_A0 + AM0]
987 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
988 }
989
990
991 // 1111 1000 1011 11Dn d8.....; movhu (d8,SP),Dn (d8 is zero-extended)
992 8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
993 "movhu"
994 *mn10300
995 {
996 // OP_F8BC00 ();
997 PC = cia;
998 State.regs[REG_D0 + DN0]
999 = load_half ((State.regs[REG_SP] + (D8)));
1000 }
1001
1002
1003 // 1111 1010 1011 11Dn d16.....; movhu (d16,SP),Dn (d16 is zero-extended.)
1004 8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
1005 "movhu"
1006 *mn10300
1007 {
1008 // OP_FABC0000 ();
1009 PC = cia;
1010 State.regs[REG_D0 + DN0]
1011 = load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)));
1012 }
1013
1014
1015 // 1111 1100 1011 11Dn d32.....; movhu (d32,SP),Dn
1016 8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
1017 "movhu"
1018 *mn10300
1019 {
1020 // OP_FCBC0000 ();
1021 PC = cia;
1022 State.regs[REG_D0 + DN0]
1023 = load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1024 }
1025
1026
1027 // 1111 0100 10Dn DiAm; movhu (Di,Am),Dn
1028 8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
1029 "movhu"
1030 *mn10300
1031 {
1032 // OP_F480 ();
1033 PC = cia;
1034 State.regs[REG_D0 + DN2]
1035 = load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
1036 }
1037
1038
1039 // 0011 10Dn abs16...; movhu (abs16),Dn (abs16 is zero-extended)
1040 4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
1041 "movhu"
1042 *mn10300
1043 {
1044 // OP_380000 ();
1045 PC = cia;
1046 State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B));
1047 }
1048
1049
1050 // 1111 1100 1010 11Dn abs32...; movhu (abs32),Dn
1051 8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
1052 "movhu"
1053 *mn10300
1054 {
1055 // OP_FCAC0000 ();
1056 PC = cia;
1057 State.regs[REG_D0 + DN0]
1058 = load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1059 }
1060
1061
1062 // 1111 0000 0111 DmAn; movhu Dm,(An)
1063 8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
1064 "movhu"
1065 *mn10300
1066 {
1067 // OP_F070 ();
1068 PC = cia;
1069 store_half (State.regs[REG_A0 + AN0],
1070 State.regs[REG_D0 + DM1]);
1071 }
1072
1073
1074 // 1111 1000 0111 DmAn d8......; movhu Dm,(d8,An) (d8 is sign-extended)
1075 8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
1076 "movhu"
1077 *mn10300
1078 {
1079 // OP_F87000 ();
1080 PC = cia;
1081 store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1082 State.regs[REG_D0 + DM1]);
1083 }
1084
1085
1086 // 1111 1010 0111 DnAm d16.....; movhu Dm,(d16,An) (d16 is sign-extended.)
1087 8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
1088 "movhu"
1089 *mn10300
1090 {
1091 // OP_FA700000 ();
1092 PC = cia;
1093 store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1094 State.regs[REG_D0 + DM1]);
1095 }
1096
1097
1098 // 1111 1100 0111 DmAn d32.....; movhu Dm,(d32,An)
1099 8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
1100 "movhu"
1101 *mn10300
1102 {
1103 // OP_FC700000 ();
1104 PC = cia;
1105 store_half ((State.regs[REG_A0 + AN0]
1106 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1107 State.regs[REG_D0 + DM1]);
1108 }
1109
1110
1111 // 1111 1000 1001 Dm11 d8....; movhu Dm,(d8,SP) (d8 is zero-extended)
1112 8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
1113 "movhu"
1114 *mn10300
1115 {
1116 // OP_F89300 ();
1117 PC = cia;
1118 store_half (State.regs[REG_SP] + (D8),
1119 State.regs[REG_D0 + DM1]);
1120 }
1121
1122
1123 // 1111 1010 1001 Dm11 d16.....; movhu Dm,(d16,SP) (d16 is zero-extended.)
1124 8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
1125 "movhu"
1126 *mn10300
1127 {
1128 // OP_FA930000 ();
1129 PC = cia;
1130 store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1131 State.regs[REG_D0 + DM1]);
1132 }
1133
1134
1135 // 1111 1100 1001 Dm11 d32.....; movhu Dm,(d32,SP)
1136 8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
1137 "movhu"
1138 *mn10300
1139 {
1140 // OP_FC930000 ();
1141 PC = cia;
1142 store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1143 State.regs[REG_D0 + DM1]);
1144 }
1145
1146
1147 // 1111 0100 11Dm DiAn; movhu Dm,(Di,An)
1148 8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
1149 "movhu"
1150 *mn10300
1151 {
1152 // OP_F4C0 ();
1153 PC = cia;
1154 store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1155 State.regs[REG_D0 + DM2]);
1156 }
1157
1158
1159 // 0000 Dm11 abs16...; movhu Dm,(abs16) (abs16 is zero-extended)
1160 4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
1161 "movhu"
1162 *mn10300
1163 {
1164 // OP_30000 ();
1165 PC = cia;
1166 store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
1167 }
1168
1169
1170 // 1111 1100 1000 Dm11 abs32...; movhu Dm,(abs32)
1171 8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
1172 "movhu"
1173 *mn10300
1174 {
1175 // OP_FC830000 ();
1176 PC = cia;
1177 store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1178 State.regs[REG_D0 + DM1]);
1179 }
1180
1181
1182 // 1111 0010 1101 00Dn; ext Dn
1183 8.0xf2+4.0xd,00,2.DN0:D0:::ext
1184 "ext"
1185 *mn10300
1186 {
1187 // OP_F2D0 ();
1188 PC = cia;
1189 if (State.regs[REG_D0 + DN0] & 0x80000000)
1190 State.regs[REG_MDR] = -1;
1191 else
1192 State.regs[REG_MDR] = 0;
1193 }
1194
1195
1196 // 0001 00Dn; extb Dn
1197 4.0x1,00,2.DN0:S0:::extb
1198 "extb"
1199 *mn10300
1200 {
1201 // OP_10 ();
1202 PC = cia;
1203 State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]);
1204 }
1205
1206
1207 // 0001 01Dn; extbu Dn
1208 4.0x1,01,2.DN0:S0:::extbu
1209 "extbu"
1210 *mn10300
1211 {
1212 // OP_14 ();
1213 PC = cia;
1214 State.regs[REG_D0 + DN0] &= 0xff;
1215 }
1216
1217
1218 // 0001 10Dn; exth Dn
1219 4.0x1,10,2.DN0:S0:::exth
1220 "exth"
1221 *mn10300
1222 {
1223 // OP_18 ();
1224 PC = cia;
1225 State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]);
1226 }
1227
1228
1229 // 0001 11Dn; exthu Dn
1230 4.0x1,11,2.DN0:S0:::exthu
1231 "exthu"
1232 *mn10300
1233 {
1234 // OP_1C ();
1235 PC = cia;
1236 State.regs[REG_D0 + DN0] &= 0xffff;
1237 }
1238
1239
1240 // 1100 1110 regs....; movm (SP),regs
1241 8.0xce+8.REGS:S1:::movm
1242 "movm"
1243 *mn10300
1244 {
1245 // OP_CE00 ();
1246 unsigned long sp = State.regs[REG_SP];
1247 unsigned long mask;
1248
1249 PC = cia;
1250 mask = REGS;
1251
1252 if (mask & 0x8)
1253 {
1254 sp += 4;
1255 State.regs[REG_LAR] = load_word (sp);
1256 sp += 4;
1257 State.regs[REG_LIR] = load_word (sp);
1258 sp += 4;
1259 State.regs[REG_MDR] = load_word (sp);
1260 sp += 4;
1261 State.regs[REG_A0 + 1] = load_word (sp);
1262 sp += 4;
1263 State.regs[REG_A0] = load_word (sp);
1264 sp += 4;
1265 State.regs[REG_D0 + 1] = load_word (sp);
1266 sp += 4;
1267 State.regs[REG_D0] = load_word (sp);
1268 sp += 4;
1269 }
1270
1271 if (mask & 0x10)
1272 {
1273 State.regs[REG_A0 + 3] = load_word (sp);
1274 sp += 4;
1275 }
1276
1277 if (mask & 0x20)
1278 {
1279 State.regs[REG_A0 + 2] = load_word (sp);
1280 sp += 4;
1281 }
1282
1283 if (mask & 0x40)
1284 {
1285 State.regs[REG_D0 + 3] = load_word (sp);
1286 sp += 4;
1287 }
1288
1289 if (mask & 0x80)
1290 {
1291 State.regs[REG_D0 + 2] = load_word (sp);
1292 sp += 4;
1293 }
1294
1295 /* And make sure to update the stack pointer. */
1296 State.regs[REG_SP] = sp;
1297 }
1298
1299
1300 // 1100 1111 regs....; movm regs,(SP)
1301 8.0xcf+8.REGS:S1a:::movm
1302 "movm"
1303 *mn10300
1304 {
1305 // OP_CF00 ();
1306 unsigned long sp = State.regs[REG_SP];
1307 unsigned long mask;
1308
1309 PC = cia;
1310 mask = REGS;
1311
1312 if (mask & 0x80)
1313 {
1314 sp -= 4;
1315 store_word (sp, State.regs[REG_D0 + 2]);
1316 }
1317
1318 if (mask & 0x40)
1319 {
1320 sp -= 4;
1321 store_word (sp, State.regs[REG_D0 + 3]);
1322 }
1323
1324 if (mask & 0x20)
1325 {
1326 sp -= 4;
1327 store_word (sp, State.regs[REG_A0 + 2]);
1328 }
1329
1330 if (mask & 0x10)
1331 {
1332 sp -= 4;
1333 store_word (sp, State.regs[REG_A0 + 3]);
1334 }
1335
1336 if (mask & 0x8)
1337 {
1338 sp -= 4;
1339 store_word (sp, State.regs[REG_D0]);
1340 sp -= 4;
1341 store_word (sp, State.regs[REG_D0 + 1]);
1342 sp -= 4;
1343 store_word (sp, State.regs[REG_A0]);
1344 sp -= 4;
1345 store_word (sp, State.regs[REG_A0 + 1]);
1346 sp -= 4;
1347 store_word (sp, State.regs[REG_MDR]);
1348 sp -= 4;
1349 store_word (sp, State.regs[REG_LIR]);
1350 sp -= 4;
1351 store_word (sp, State.regs[REG_LAR]);
1352 sp -= 4;
1353 }
1354
1355 /* And make sure to update the stack pointer. */
1356 State.regs[REG_SP] = sp;
1357 }
1358
1359
1360 // 0000 Dn00; clr Dn
1361 4.0x0,2.DN1,00:S0:::clr
1362 "clr"
1363 *mn10300
1364 {
1365 // OP_0 ();
1366 PC = cia;
1367 State.regs[REG_D0 + DN1] = 0;
1368
1369 PSW |= PSW_Z;
1370 PSW &= ~(PSW_V | PSW_C | PSW_N);
1371 }
1372
1373
1374 // 1110 DmDn; add Dm,Dn
1375 4.0xe,2.DM1,2.DN0:S0:::add
1376 "add"
1377 *mn10300
1378 {
1379 // OP_E0 ();
1380 PC = cia;
1381 genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1382 }
1383
1384 // 1111 0001 0110 DmAn; add Dm,An
1385 8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
1386 "add"
1387 *mn10300
1388 {
1389 // OP_F160 ();
1390 PC = cia;
1391 genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1392 }
1393
1394
1395 // 1111 0001 0101 AmDn; add Am,Dn
1396 8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
1397 "add"
1398 *mn10300
1399 {
1400 // OP_F150 ();
1401 PC = cia;
1402 genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1403 }
1404
1405
1406 // 1111 0001 0111 AmAn; add Am,An
1407 8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
1408 "add"
1409 *mn10300
1410 {
1411 // OP_F170 ();
1412 PC = cia;
1413 genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1414 }
1415
1416
1417 // 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended)
1418 4.0x2,10,2.DN0+8.IMM8:S1:::add
1419 "add"
1420 *mn10300
1421 {
1422 // OP_2800 ();
1423 PC = cia;
1424 genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
1425 }
1426
1427
1428 // 1111 1010 1100 00Dn imm16...; add imm16,Dn
1429 8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
1430 "add"
1431 *mn10300
1432 {
1433 // OP_FAC00000 ();
1434 PC = cia;
1435 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
1436 }
1437
1438
1439 // 1111 1100 1100 00Dn imm32...; add imm32,Dn
1440 8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
1441 "add"
1442 *mn10300
1443 {
1444 // OP_FCC00000 ();
1445 PC = cia;
1446 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1447 }
1448
1449
1450 // 0010 00An imm8....; add imm8,An (imm8 is sign-extended)
1451 4.0x2,00,2.AN0+8.IMM8:S1a:::add
1452 "add"
1453 *mn10300
1454 {
1455 // OP_2000 ();
1456 PC = cia;
1457 genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
1458 }
1459
1460
1461 // 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.)
1462 8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
1463 "add"
1464 *mn10300
1465 {
1466 // OP_FAD00000 ();
1467 PC = cia;
1468 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
1469 }
1470
1471
1472 // 1111 1100 1101 00An imm32...; add imm32,An
1473 8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
1474 "add"
1475 *mn10300
1476 {
1477 // OP_FCD00000 ();
1478 PC = cia;
1479 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1480 }
1481
1482
1483 // 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.)
1484 8.0xf8+8.0xfe+8.IMM8:D1:::add
1485 "add"
1486 *mn10300
1487 {
1488 // OP_F8FE00 ();
1489 unsigned long imm;
1490
1491 // Note: no PSW changes.
1492 PC = cia;
1493 imm = EXTEND8 (IMM8);
1494 State.regs[REG_SP] += imm;
1495 }
1496
1497
1498 // 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.)
1499 8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
1500 "add"
1501 *mn10300
1502 {
1503 // OP_FAFE0000 ();
1504 unsigned long imm;
1505
1506 // Note: no PSW changes.
1507 PC = cia;
1508 imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
1509 State.regs[REG_SP] += imm;
1510 }
1511
1512
1513 // 1111 1100 1111 1110 imm32...; add imm32,SP
1514 8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
1515 "add"
1516 *mn10300
1517 {
1518 // OP_FCFE0000 ();
1519 unsigned long imm;
1520
1521 // Note: no PSW changes.
1522 PC = cia;
1523 imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1524 State.regs[REG_SP] += imm;
1525 }
1526
1527
1528 // 1111 0001 0100 DmDn; addc Dm,Dn
1529 8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
1530 "addc"
1531 *mn10300
1532 {
1533 // OP_F140 ();
1534 int z, c, n, v;
1535 unsigned long reg1, reg2, sum;
1536
1537 PC = cia;
1538 reg1 = State.regs[REG_D0 + DM1];
1539 reg2 = State.regs[REG_D0 + DN0];
1540 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
1541 State.regs[REG_D0 + DN0] = sum;
1542
1543 z = (sum == 0);
1544 n = (sum & 0x80000000);
1545 c = (sum < reg1) || (sum < reg2);
1546 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1547 && (reg2 & 0x80000000) != (sum & 0x80000000));
1548
1549 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1550 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1551 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1552 }
1553
1554
1555 // 1111 0001 0000 DmDn; sub Dm,Dn
1556 8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
1557 "sub"
1558 *mn10300
1559 {
1560 // OP_F100 ();
1561 PC = cia;
1562 genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1563 }
1564
1565 // 1111 0001 0010 DmAn; sub DmAn
1566 8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
1567 "sub"
1568 *mn10300
1569 {
1570 // OP_F120 ();
1571 PC = cia;
1572 genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1573 }
1574
1575
1576 // 1111 0001 0001 AmDn; sub AmDn
1577 8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
1578 "sub"
1579 *mn10300
1580 {
1581 // OP_F110 ();
1582 PC = cia;
1583 genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1584 }
1585
1586
1587 // 1111 0001 0011 AmAn; sub Am,An
1588 8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
1589 "sub"
1590 *mn10300
1591 {
1592 // OP_F130 ();
1593 PC = cia;
1594 genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1595 }
1596
1597
1598 // 1111 1100 1100 01Dn imm32...; sub imm32,Dn
1599 8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
1600 "sub"
1601 *mn10300
1602 {
1603 // OP_FCC40000 ();
1604 PC = cia;
1605 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1606 }
1607
1608
1609 // 1111 1100 1101 01An imm32...; sub imm32,An
1610 8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
1611 "sub"
1612 *mn10300
1613 {
1614 // OP_FCD40000 ();
1615 PC = cia;
1616 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1617 }
1618
1619
1620 // 1111 0001 1000 DmDn; subc Dm,Dn
1621 8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
1622 "subc"
1623 *mn10300
1624 {
1625 // OP_F180 ();
1626 int z, c, n, v;
1627 unsigned long reg1, reg2, difference;
1628
1629 PC = cia;
1630 reg1 = State.regs[REG_D0 + DM1];
1631 reg2 = State.regs[REG_D0 + DN0];
1632 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
1633 State.regs[REG_D0 + DN0] = difference;
1634
1635 z = (difference == 0);
1636 n = (difference & 0x80000000);
1637 c = (reg1 > reg2);
1638 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1639 && (reg2 & 0x80000000) != (difference & 0x80000000));
1640
1641 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1642 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1643 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1644 }
1645
1646
1647 // 1111 0010 0100 DmDn; mul Dm,Dn
1648 8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
1649 "mul"
1650 *mn10300
1651 {
1652 // OP_F240 ();
1653 unsigned long long temp;
1654 int n, z;
1655
1656 PC = cia;
1657 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
1658 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
1659 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1660 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1661 z = (State.regs[REG_D0 + DN0] == 0);
1662 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1663 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1664 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1665 }
1666
1667
1668 // 1111 0010 0101 DmDn; mulu Dm,Dn
1669 8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
1670 "mulu"
1671 *mn10300
1672 {
1673 // OP_F250 ();
1674 unsigned long long temp;
1675 int n, z;
1676
1677 PC = cia;
1678 temp = ((unsigned64)State.regs[REG_D0 + DN0]
1679 * (unsigned64)State.regs[REG_D0 + DM1]);
1680 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1681 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1682 z = (State.regs[REG_D0 + DN0] == 0);
1683 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1684 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1685 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1686 }
1687
1688
1689 // 1111 0010 0110 DmDn; div Dm,Dn
1690 8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
1691 "div"
1692 *mn10300
1693 {
1694 // OP_F260 ();
1695 long long temp;
1696 int n, z;
1697
1698 PC = cia;
1699 temp = State.regs[REG_MDR];
1700 temp <<= 32;
1701 temp |= State.regs[REG_D0 + DN0];
1702 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + DM1];
1703 temp /= (long)State.regs[REG_D0 + DM1];
1704 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1705 z = (State.regs[REG_D0 + DN0] == 0);
1706 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1707 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1708 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1709 }
1710
1711
1712 // 1111 0010 0111 DmDn; divu Dm,Dn
1713 8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
1714 "divu"
1715 *mn10300
1716 {
1717 // OP_F270 ();
1718 unsigned long long temp;
1719 int n, z;
1720
1721 PC = cia;
1722 temp = State.regs[REG_MDR];
1723 temp <<= 32;
1724 temp |= State.regs[REG_D0 + DN0];
1725 State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
1726 temp /= State.regs[REG_D0 + DM1];
1727 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1728 z = (State.regs[REG_D0 + DN0] == 0);
1729 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1730 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1731 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1732 }
1733
1734
1735 // 0100 Dn00; inc Dn
1736 4.0x4,2.DN1,00:S0:::inc
1737 "inc"
1738 *mn10300
1739 {
1740 // OP_40 ();
1741 unsigned int imm;
1742
1743 PC = cia;
1744 imm = 1;
1745 genericAdd(imm, REG_D0 + DN1);
1746 }
1747
1748
1749 // 0100 An01
1750 4.0x4,2.AN1,01:S0a:::inc
1751 "inc"
1752 *mn10300
1753 {
1754 // OP_41 ();
1755 PC = cia;
1756 State.regs[REG_A0 + AN1] += 1;
1757 }
1758
1759
1760 // 0101 00An; inc4 An
1761 4.0x5,00,2.AN0:S0:::inc4
1762 "inc4"
1763 *mn10300
1764 {
1765 // OP_50 ();
1766 PC = cia;
1767 State.regs[REG_A0 + AN0] += 4;
1768 }
1769
1770
1771 // 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.)
1772 // 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn)
1773 4.0xa,2.DM1,2.DN0:S0:::cmp
1774 "cmp"
1775 *mn10300
1776 {
1777 PC = cia;
1778 if ( DM1 == DN0 )
1779 {
1780 signed32 immed = EXTEND8 (IMEM8_IMMED (cia, 1));
1781 nia = cia + 2;
1782 // OP_A000 ();
1783 genericCmp(immed, State.regs[REG_D0 + DN0]);
1784 }
1785 else
1786 {
1787 // OP_A0 ();
1788 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
1789 }
1790 }
1791
1792
1793 // 1111 0001 1010 DmAn; cmp Dm,An
1794 8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
1795 "cmp"
1796 *mn10300
1797 {
1798 // OP_F1A0 ();
1799 PC = cia;
1800 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
1801 }
1802
1803
1804 // 1111 0001 1001 AmDn; cmp Am,Dn
1805 8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
1806 "cmp"
1807 *mn10300
1808 {
1809 // OP_F190 ();
1810 PC = cia;
1811 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
1812 }
1813
1814
1815 // 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.)
1816 // 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn)
1817 4.0xb,2.AM1,2.AN0:S0a:::cmp
1818 "cmp"
1819 *mn10300
1820 {
1821 PC = cia;
1822 if ( AM1 == AN0 )
1823 {
1824 // op_B000 ();
1825 genericCmp(EXTEND8 (IMEM8_IMMED (cia, 1)),
1826 State.regs[REG_A0 + AN0]);
1827 nia = cia + 2;
1828 }
1829 else
1830 {
1831 // OP_B0 ();
1832 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
1833 }
1834 }
1835
1836
1837 // 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.)
1838 8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
1839 "cmp"
1840 *mn10300
1841 {
1842 // OP_FAC80000 ();
1843 PC = cia;
1844 genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
1845 State.regs[REG_D0 + DN0]);
1846 }
1847
1848
1849 // 1111 1100 1100 10Dn imm32...; cmp imm32,Dn
1850 8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
1851 "cmp"
1852 *mn10300
1853 {
1854 // OP_FCC80000 ();
1855 PC = cia;
1856 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1857 State.regs[REG_D0 + DN0]);
1858 }
1859
1860
1861 // 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.)
1862 8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
1863 "cmp"
1864 *mn10300
1865 {
1866 // OP_FAD80000 ();
1867 PC = cia;
1868 genericCmp(FETCH16(IMM16A, IMM16B),
1869 State.regs[REG_A0 + AN0]);
1870 }
1871
1872
1873 // 1111 1100 1101 10An imm32...; cmp imm32,An
1874 8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
1875 "cmp"
1876 *mn10300
1877 {
1878 // OP_FCD80000 ();
1879 PC = cia;
1880 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1881 State.regs[REG_A0 + AN0]);
1882 }
1883
1884
1885 // 1111 0010 0000 DmDn; and Dm,Dn
1886 8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
1887 "and"
1888 *mn10300
1889 {
1890 // OP_F200 ();
1891 int n, z;
1892
1893 PC = cia;
1894 State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
1895 z = (State.regs[REG_D0 + DN0] == 0);
1896 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1897 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1898 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1899 }
1900
1901
1902 // 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.)
1903 8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
1904 "and"
1905 *mn10300
1906 {
1907 // OP_F8E000 ();
1908 int n, z;
1909
1910 PC = cia;
1911 State.regs[REG_D0 + DN0] &= IMM8;
1912 z = (State.regs[REG_D0 + DN0] == 0);
1913 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1914 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1915 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1916 }
1917
1918
1919 // 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.)
1920 8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
1921 "and"
1922 *mn10300
1923 {
1924 // OP_FAE00000 ();
1925 int n, z;
1926
1927 PC = cia;
1928 State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
1929 z = (State.regs[REG_D0 + DN0] == 0);
1930 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1931 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1932 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1933 }
1934
1935
1936 // 1111 1100 1110 00Dn imm32...; and imm32,Dn
1937 8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
1938 "and"
1939 *mn10300
1940 {
1941 // OP_FCE00000 ();
1942 int n, z;
1943
1944 PC = cia;
1945 State.regs[REG_D0 + DN0]
1946 &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1947 z = (State.regs[REG_D0 + DN0] == 0);
1948 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1949 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1950 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1951 }
1952
1953
1954 // 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.)
1955 8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
1956 "and"
1957 *mn10300
1958 {
1959 // OP_FAFC0000 ();
1960 PC = cia;
1961 PSW &= FETCH16(IMM16A, IMM16B);
1962 }
1963
1964
1965
1966 // 1111 0010 0001 DmDn; or DmDn
1967 8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
1968 "or"
1969 *mn10300
1970 {
1971 // OP_F210 ();
1972 PC = cia;
1973 genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1974 }
1975
1976
1977 // 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n
1978 8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
1979 "or"
1980 *mn10300
1981 {
1982 // OP_F8E400 ();
1983 PC = cia;
1984 genericOr(IMM8, REG_D0 + DN0);
1985 }
1986
1987
1988 // 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.)
1989 8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
1990 "or"
1991 *mn10300
1992 {
1993 // OP_FAE40000 ();
1994 PC = cia;
1995 genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
1996 }
1997
1998
1999 // 1111 1100 1110 01Dn imm32...; or imm32,Dn
2000 8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
2001 "or"
2002 *mn10300
2003 {
2004 // OP_FCE40000 ();
2005 PC = cia;
2006 genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2007 }
2008
2009
2010 // 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.)
2011 8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
2012 "or"
2013 *mn10300
2014 {
2015 // OP_FAFD0000 ();
2016 PC = cia;
2017 PSW |= FETCH16(IMM16A, IMM16B);
2018 }
2019
2020
2021 // 1111 0010 0010 DmDn; xor Dm,Dn
2022 8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
2023 "xor"
2024 *mn10300
2025 {
2026 // OP_F220 ();
2027 PC = cia;
2028 genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2029 }
2030
2031
2032 // 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.)
2033 8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
2034 "xor"
2035 *mn10300
2036 {
2037 // OP_FAE80000 ();
2038 PC = cia;
2039 genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2040 }
2041
2042
2043 // 1111 1100 1110 10Dn imm32...; xor imm32,Dn
2044 8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
2045 "xor"
2046 *mn10300
2047 {
2048 // OP_FCE80000 ();
2049 PC = cia;
2050 genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2051 }
2052
2053
2054 // 1111 0010 0011 00Dn; not Dn
2055 8.0xf2+4.0x3,00,2.DN0:D0:::not
2056 "not"
2057 *mn10300
2058 {
2059 // OP_F230 ();
2060 int n, z;
2061
2062 PC = cia;
2063 State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
2064 z = (State.regs[REG_D0 + DN0] == 0);
2065 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2066 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2067 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2068 }
2069
2070
2071 // 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.)
2072 8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
2073 "btst"
2074 *mn10300
2075 {
2076 // OP_F8EC00 ();
2077 PC = cia;
2078 genericBtst(IMM8, State.regs[REG_D0 + DN0]);
2079 }
2080
2081
2082 // 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.)
2083 8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
2084 "btst"
2085 *mn10300
2086 {
2087 // OP_FAEC0000 ();
2088 PC = cia;
2089 genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
2090 }
2091
2092
2093 // 1111 1100 1110 11Dn imm32...; btst imm32,Dn
2094 8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
2095 "btst"
2096 *mn10300
2097 {
2098 // OP_FCEC0000 ();
2099 PC = cia;
2100 genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2101 State.regs[REG_D0 + DN0]);
2102 }
2103
2104
2105 // 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2106 8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
2107 "btst"
2108 *mn10300
2109 {
2110 // OP_FE020000 ();
2111 PC = cia;
2112 genericBtst(IMM8,
2113 load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
2114 }
2115
2116
2117 // 1111 1010 1111 10An d8...... imm8....;
2118 // btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte)
2119 8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
2120 "btst"
2121 *mn10300
2122 {
2123 // OP_FAF80000 ();
2124 PC = cia;
2125 genericBtst(IMM8,
2126 load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
2127 }
2128
2129
2130 // 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte)
2131 8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
2132 "bset"
2133 *mn10300
2134 {
2135 // OP_F080 ();
2136 unsigned long temp;
2137 int z;
2138
2139 PC = cia;
2140 temp = load_byte (State.regs[REG_A0 + AN0]);
2141 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2142 temp |= State.regs[REG_D0 + DM1];
2143 store_byte (State.regs[REG_A0 + AN0], temp);
2144 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2145 PSW |= (z ? PSW_Z : 0);
2146 }
2147
2148
2149 // 1111 1110 0000 0000 abs32... imm8....;
2150 // bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2151 8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
2152 "bset"
2153 *mn10300
2154 {
2155 // OP_FE000000 ();
2156 unsigned long temp;
2157 int z;
2158
2159 PC = cia;
2160 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2161 z = (temp & IMM8) == 0;
2162 temp |= IMM8;
2163 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2164 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2165 PSW |= (z ? PSW_Z : 0);
2166 }
2167
2168
2169 // 1111 1010 1111 00AnAn d8...... imm8....;
2170 // bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2171 8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
2172 "bset"
2173 *mn10300
2174 {
2175 // OP_FAF00000 ();
2176 unsigned long temp;
2177 int z;
2178
2179 PC = cia;
2180 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2181 z = (temp & (IMM8)) == 0;
2182 temp |= (IMM8);
2183 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2184 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2185 PSW |= (z ? PSW_Z : 0);
2186 }
2187
2188
2189 // 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte)
2190 8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
2191 "bclr"
2192 *mn10300
2193 {
2194 // OP_F090 ();
2195 unsigned long temp;
2196 int z;
2197
2198 PC = cia;
2199 temp = load_byte (State.regs[REG_A0 + AN0]);
2200 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2201 temp = temp & ~State.regs[REG_D0 + DM1];
2202 store_byte (State.regs[REG_A0 + AN0], temp);
2203 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2204 PSW |= (z ? PSW_Z : 0);
2205 }
2206
2207
2208 // 1111 1110 0000 0001 abs32... imm8....;
2209 // bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2210 8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
2211 "bclr"
2212 *mn10300
2213 {
2214 // OP_FE010000 ();
2215 unsigned long temp;
2216 int z;
2217
2218 PC = cia;
2219 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2220 z = (temp & IMM8) == 0;
2221 temp = temp & ~(IMM8);
2222 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2223 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2224 PSW |= (z ? PSW_Z : 0);
2225 }
2226
2227
2228 // 1111 1010 1111 01An d8...... imm8....;
2229 // bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2230 8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
2231 "bclr"
2232 *mn10300
2233 {
2234 // OP_FAF40000 ();
2235 unsigned long temp;
2236 int z;
2237
2238 PC = cia;
2239 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2240 z = (temp & (IMM8)) == 0;
2241 temp = temp & ~(IMM8);
2242 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2243 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2244 PSW |= (z ? PSW_Z : 0);
2245 }
2246
2247
2248 // 1111 0010 1011 DmDn; asr Dm,Dn
2249 8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
2250 "asr"
2251 *mn10300
2252 {
2253 // OP_F2B0 ();
2254 long temp;
2255 int z, n, c;
2256
2257 PC = cia;
2258 temp = State.regs[REG_D0 + DN0];
2259 c = temp & 1;
2260 temp >>= State.regs[REG_D0 + DM1];
2261 State.regs[REG_D0 + DN0] = temp;
2262 z = (State.regs[REG_D0 + DN0] == 0);
2263 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2264 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2265 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2266 }
2267
2268
2269 // 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.)
2270 8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
2271 "asr"
2272 *mn10300
2273 {
2274 // OP_F8C800 ();
2275 long temp;
2276 int z, n, c;
2277
2278 PC = cia;
2279 temp = State.regs[REG_D0 + DN0];
2280 c = temp & 1;
2281 temp >>= IMM8;
2282 State.regs[REG_D0 + DN0] = temp;
2283 z = (State.regs[REG_D0 + DN0] == 0);
2284 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2285 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2286 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2287 }
2288
2289
2290 // 1111 0010 1010 DmDn; lsr Dm,Dn
2291 8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
2292 "lsr"
2293 *mn10300
2294 {
2295 // OP_F2A0 ();
2296 int z, n, c;
2297
2298 PC = cia;
2299 c = State.regs[REG_D0 + DN0] & 1;
2300 State.regs[REG_D0 + DN0]
2301 >>= State.regs[REG_D0 + DM1];
2302 z = (State.regs[REG_D0 + DN0] == 0);
2303 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2304 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2305 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2306 }
2307
2308
2309 // 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.)
2310 8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
2311 "lsr"
2312 *mn10300
2313 {
2314 // OP_F8C400 ();
2315 int z, n, c;
2316
2317 PC = cia;
2318 c = State.regs[REG_D0 + DN0] & 1;
2319 State.regs[REG_D0 + DN0] >>= IMM8;
2320 z = (State.regs[REG_D0 + DN0] == 0);
2321 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2322 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2323 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2324 }
2325
2326
2327 // 1111 0010 1001 DmDn; asl Dm,Dn
2328 8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
2329 "asl"
2330 *mn10300
2331 {
2332 // OP_F290 ();
2333 int n, z;
2334
2335 PC = cia;
2336 State.regs[REG_D0 + DN0]
2337 <<= State.regs[REG_D0 + DM1];
2338 z = (State.regs[REG_D0 + DN0] == 0);
2339 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2340 PSW &= ~(PSW_Z | PSW_N);
2341 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2342 }
2343
2344
2345 // 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.)
2346 8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
2347 "asl"
2348 *mn10300
2349 {
2350 // OP_F8C000 ();
2351 int n, z;
2352
2353 PC = cia;
2354 State.regs[REG_D0 + DN0] <<= IMM8;
2355 z = (State.regs[REG_D0 + DN0] == 0);
2356 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2357 PSW &= ~(PSW_Z | PSW_N);
2358 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2359 }
2360
2361
2362 // 0101 01Dn; als2 Dn
2363 4.0x5,01,2.DN0:S0:::asl2
2364 "asl2"
2365 *mn10300
2366 {
2367 // OP_54 ();
2368 int n, z;
2369 PC = cia;
2370
2371 State.regs[REG_D0 + DN0] <<= 2;
2372 z = (State.regs[REG_D0 + DN0] == 0);
2373 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2374 PSW &= ~(PSW_Z | PSW_N);
2375 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2376 }
2377
2378
2379 // 1111 0010 1000 01Dn; ror Dn
2380 8.0xf2+4.0x8,01,2.DN0:D0:::ror
2381 "ror"
2382 *mn10300
2383 {
2384 // OP_F284 ();
2385 unsigned long value;
2386 int c,n,z;
2387
2388 PC = cia;
2389 value = State.regs[REG_D0 + DN0];
2390 c = (value & 0x1);
2391
2392 value >>= 1;
2393 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2394 State.regs[REG_D0 + DN0] = value;
2395 z = (value == 0);
2396 n = (value & 0x80000000) != 0;
2397 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2398 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2399 }
2400
2401
2402 // 1111 0010 1000 00Dn; rol Dn
2403 8.0xf2+4.0x8,00,2.DN0:D0:::rol
2404 "rol"
2405 *mn10300
2406 {
2407 // handle ror above, too.
2408 // OP_F280 ();
2409 unsigned long value;
2410 int c,n,z;
2411
2412 PC = cia;
2413 value = State.regs[REG_D0 + DN0];
2414 c = (value & 0x80000000) ? 1 : 0;
2415
2416 value <<= 1;
2417 value |= ((PSW & PSW_C) != 0);
2418 State.regs[REG_D0 + DN0] = value;
2419 z = (value == 0);
2420 n = (value & 0x80000000) != 0;
2421 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2422 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2423 }
2424
2425
2426 // 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended)
2427 8.0xc8+8.D8:S1:::beq
2428 "beq"
2429 *mn10300
2430 {
2431 // OP_C800 ();
2432 PC = cia;
2433 if ((PSW & PSW_Z))
2434 {
2435 State.regs[REG_PC] += EXTEND8 (D8);
2436 nia = PC;
2437 }
2438 }
2439
2440
2441 // 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended)
2442 8.0xc9+8.D8:S1:::bne
2443 "bne"
2444 *mn10300
2445 {
2446 // OP_C900 ();
2447 PC = cia;
2448 if (!(PSW & PSW_Z))
2449 {
2450 State.regs[REG_PC] += EXTEND8 (D8);
2451 nia = PC;
2452 }
2453 }
2454
2455
2456 // 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended)
2457 8.0xc1+8.D8:S1:::bgt
2458 "bgt"
2459 *mn10300
2460 {
2461 // OP_C100 ();
2462 PC = cia;
2463 if (!((PSW & PSW_Z)
2464 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2465 {
2466 State.regs[REG_PC] += EXTEND8 (D8);
2467 nia = PC;
2468 }
2469 }
2470
2471
2472 // 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended)
2473 8.0xc2+8.D8:S1:::bge
2474 "bge"
2475 *mn10300
2476 {
2477 // OP_C200 ();
2478 PC = cia;
2479 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2480 {
2481 State.regs[REG_PC] += EXTEND8 (D8);
2482 nia = PC;
2483 }
2484 }
2485
2486
2487 // 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended)
2488 8.0xc3+8.D8:S1:::ble
2489 "ble"
2490 *mn10300
2491 {
2492 // OP_C300 ();
2493 PC = cia;
2494 if ((PSW & PSW_Z)
2495 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2496 {
2497 State.regs[REG_PC] += EXTEND8 (D8);
2498 nia = PC;
2499 }
2500 }
2501
2502
2503 // 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended)
2504 8.0xc0+8.D8:S1:::blt
2505 "blt"
2506 *mn10300
2507 {
2508 // OP_C000 ();
2509 PC = cia;
2510 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2511 {
2512 State.regs[REG_PC] += EXTEND8 (D8);
2513 nia = PC;
2514 }
2515 }
2516
2517
2518 // 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended)
2519 8.0xc5+8.D8:S1:::bhi
2520 "bhi"
2521 *mn10300
2522 {
2523 // OP_C500 ();
2524 PC = cia;
2525 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2526 {
2527 State.regs[REG_PC] += EXTEND8 (D8);
2528 nia = PC;
2529 }
2530 }
2531
2532
2533 // 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended)
2534 8.0xc6+8.D8:S1:::bcc
2535 "bcc"
2536 *mn10300
2537 {
2538 // OP_C600 ();
2539 PC = cia;
2540 if (!(PSW & PSW_C))
2541 {
2542 State.regs[REG_PC] += EXTEND8 (D8);
2543 nia = PC;
2544 }
2545 }
2546
2547
2548 // 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended)
2549 8.0xc7+8.D8:S1:::bls
2550 "bls"
2551 *mn10300
2552 {
2553 // OP_C700 ();
2554 PC = cia;
2555 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2556 {
2557 State.regs[REG_PC] += EXTEND8 (D8);
2558 nia = PC;
2559 }
2560 }
2561
2562
2563 // 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended)
2564 8.0xc4+8.D8:S1:::bcs
2565 "bcs"
2566 *mn10300
2567 {
2568 // OP_C400 ();
2569 PC = cia;
2570 if (PSW & PSW_C)
2571 {
2572 State.regs[REG_PC] += EXTEND8 (D8);
2573 nia = PC;
2574 }
2575 }
2576
2577
2578 // 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended)
2579 8.0xf8+8.0xe8+8.D8:D1:::bvc
2580 "bvc"
2581 *mn10300
2582 {
2583 // OP_F8E800 ();
2584 PC = cia;
2585 if (!(PSW & PSW_V))
2586 {
2587 State.regs[REG_PC] += EXTEND8 (D8);
2588 nia = PC;
2589 }
2590 }
2591
2592
2593 // 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended)
2594 8.0xf8+8.0xe9+8.D8:D1:::bvs
2595 "bvs"
2596 *mn10300
2597 {
2598 // OP_F8E900 ();
2599 PC = cia;
2600 if (PSW & PSW_V)
2601 {
2602 State.regs[REG_PC] += EXTEND8 (D8);
2603 nia = PC;
2604 }
2605 }
2606
2607
2608 // 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended)
2609 8.0xf8+8.0xea+8.D8:D1:::bnc
2610 "bnc"
2611 *mn10300
2612 {
2613 // OP_F8EA00 ();
2614 PC = cia;
2615 if (!(PSW & PSW_N))
2616 {
2617 State.regs[REG_PC] += EXTEND8 (D8);
2618 nia = PC;
2619 }
2620 }
2621
2622
2623 // 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended)
2624 8.0xf8+8.0xeb+8.D8:D1:::bns
2625 "bns"
2626 *mn10300
2627 {
2628 // OP_F8EB00 ();
2629 PC = cia;
2630 if (PSW & PSW_N)
2631 {
2632 State.regs[REG_PC] += EXTEND8 (D8);
2633 nia = PC;
2634 }
2635 }
2636
2637
2638 // 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended)
2639 8.0xca+8.D8:S1:::bra
2640 "bra"
2641 *mn10300
2642 {
2643 // OP_CA00 ();
2644 PC = cia;
2645 State.regs[REG_PC] += EXTEND8 (D8);
2646 nia = PC;
2647 }
2648
2649
2650 // 1101 1000; leq
2651 8.0xd8:S0:::leq
2652 "leq"
2653 *mn10300
2654 {
2655 // OP_D8 ();
2656 PC = cia;
2657 if (PSW & PSW_Z)
2658 {
2659 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2660 nia = PC;
2661 }
2662 }
2663
2664
2665 // 1101 1001; lne
2666 8.0xd9:S0:::lne
2667 "lne"
2668 *mn10300
2669 {
2670 // OP_D9 ();
2671 PC = cia;
2672 if (!(PSW & PSW_Z))
2673 {
2674 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2675 nia = PC;
2676 }
2677 }
2678
2679
2680 // 1101 0001; lgt
2681 8.0xd1:S0:::lgt
2682 "lgt"
2683 *mn10300
2684 {
2685 // OP_D1 ();
2686 PC = cia;
2687 if (!((PSW & PSW_Z)
2688 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2689 {
2690 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2691 nia = PC;
2692 }
2693 }
2694
2695
2696 // 1101 0010; lge
2697 8.0xd2:S0:::lge
2698 "lge"
2699 *mn10300
2700 {
2701 // OP_D2 ();
2702 PC = cia;
2703 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2704 {
2705 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2706 nia = PC;
2707 }
2708 }
2709
2710
2711 // 1101 0011; lle
2712 8.0xd3:S0:::lle
2713 "lle"
2714 *mn10300
2715 {
2716 // OP_D3 ();
2717 PC = cia;
2718 if ((PSW & PSW_Z)
2719 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2720 {
2721 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2722 nia = PC;
2723 }
2724 }
2725
2726
2727 // 1101 0000; llt
2728 8.0xd0:S0:::llt
2729 "llt"
2730 *mn10300
2731 {
2732 // OP_D0 ();
2733 PC = cia;
2734 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2735 {
2736 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2737 nia = PC;
2738 }
2739 }
2740
2741
2742 // 1101 0101; lhi
2743 8.0xd5:S0:::lhi
2744 "lhi"
2745 *mn10300
2746 {
2747 // OP_D5 ();
2748 PC = cia;
2749 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2750 {
2751 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2752 nia = PC;
2753 }
2754 }
2755
2756
2757 // 1101 0110; lcc
2758 8.0xd6:S0:::lcc
2759 "lcc"
2760 *mn10300
2761 {
2762 // OP_D6 ();
2763 PC = cia;
2764 if (!(PSW & PSW_C))
2765 {
2766 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2767 nia = PC;
2768 }
2769 }
2770
2771
2772 // 1101 0111; lls
2773 8.0xd7:S0:::lls
2774 "lls"
2775 *mn10300
2776 {
2777 // OP_D7 ();
2778 PC = cia;
2779 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2780 {
2781 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2782 nia = PC;
2783 }
2784 }
2785
2786
2787 // 1101 0100; lcs
2788 8.0xd4:S0:::lcs
2789 "lcs"
2790 *mn10300
2791 {
2792 // OP_D4 ();
2793 PC = cia;
2794 if (PSW & PSW_C)
2795 {
2796 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2797 nia = PC;
2798 }
2799 }
2800
2801
2802 // 1101 1010; lra
2803 8.0xda:S0:::lra
2804 "lra"
2805 *mn10300
2806 {
2807 // OP_DA ();
2808 PC = cia;
2809 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2810 nia = PC;
2811 }
2812
2813
2814 // 1101 1010; setlb
2815 8.0xdb:S0:::setlb
2816 "setlb"
2817 *mn10300
2818 {
2819 // OP_DB ();
2820 PC = cia;
2821 State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
2822 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
2823 }
2824
2825
2826 // 1111 0000 1111 01An; jmp (An)
2827 8.0xf0+4.0xf,01,2.AN0:D0:::jmp
2828 "jmp"
2829 *mn10300
2830 {
2831 // OP_F0F4 ();
2832 PC = State.regs[REG_A0 + AN0];
2833 nia = PC;
2834 }
2835
2836
2837 // 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.)
2838 8.0xcc+8.D16A+8.D16B:S2:::jmp
2839 "jmp"
2840 *mn10300
2841 {
2842 // OP_CC0000 ();
2843 PC = cia + EXTEND16(FETCH16(D16A, D16B));
2844 nia = PC;
2845 }
2846
2847
2848 // 1101 1100 d32........; jmp (d32, PC)
2849 8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
2850 "jmp"
2851 *mn10300
2852 {
2853 // OP_DC000000 ();
2854 PC = cia + FETCH32(D32A, D32B, D32C, D32D);
2855 nia = PC;
2856 }
2857
2858
2859 // 1100 1101 d16..... regs.... imm8....;
2860 // call (d16,PC),regs,imm8 (d16 is sign-extended., imm8 is zero-extended.)
2861 8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
2862 "call"
2863 *mn10300
2864 {
2865 // OP_CD000000 ();
2866 unsigned int next_pc, sp;
2867 unsigned long mask;
2868
2869 PC = cia;
2870 sp = State.regs[REG_SP];
2871 next_pc = PC + 5;
2872 store_word(sp, next_pc);
2873
2874 mask = REGS;
2875
2876 if (mask & 0x80)
2877 {
2878 sp -= 4;
2879 store_word (sp, State.regs[REG_D0 + 2]);
2880 }
2881
2882 if (mask & 0x40)
2883 {
2884 sp -= 4;
2885 store_word (sp, State.regs[REG_D0 + 3]);
2886 }
2887
2888 if (mask & 0x20)
2889 {
2890 sp -= 4;
2891 store_word (sp, State.regs[REG_A0 + 2]);
2892 }
2893
2894 if (mask & 0x10)
2895 {
2896 sp -= 4;
2897 store_word (sp, State.regs[REG_A0 + 3]);
2898 }
2899
2900 if (mask & 0x8)
2901 {
2902 sp -= 4;
2903 store_word (sp, State.regs[REG_D0]);
2904 sp -= 4;
2905 store_word (sp, State.regs[REG_D0 + 1]);
2906 sp -= 4;
2907 store_word (sp, State.regs[REG_A0]);
2908 sp -= 4;
2909 store_word (sp, State.regs[REG_A0 + 1]);
2910 sp -= 4;
2911 store_word (sp, State.regs[REG_MDR]);
2912 sp -= 4;
2913 store_word (sp, State.regs[REG_LIR]);
2914 sp -= 4;
2915 store_word (sp, State.regs[REG_LAR]);
2916 sp -= 4;
2917 }
2918
2919 /* Update the stack pointer, note that the register saves to do not
2920 modify SP. The SP adjustment is derived totally from the imm8
2921 field. */
2922 State.regs[REG_SP] -= IMM8;
2923 State.regs[REG_MDR] = next_pc;
2924 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
2925 nia = PC;
2926 }
2927
2928
2929 // 1101 1101 d32..... regs.... imm8....;
2930 // call (d32,PC),regs,imm8 (imm8 is zero-extended.)
2931 8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
2932 "call"
2933 *mn10300
2934 {
2935 // op_DD000000();
2936 unsigned int next_pc, sp;
2937 unsigned long mask;
2938
2939 PC = cia;
2940 sp = State.regs[REG_SP];
2941 next_pc = State.regs[REG_PC] + 7;
2942 /* could assert that nia == next_pc here */
2943 store_word(sp, next_pc);
2944 // store_byte(sp, next_pc & 0xff);
2945 // store_byte(sp+1, (next_pc & 0xff00) >> 8 );
2946 // store_byte(sp+2, (next_pc & 0xff0000) >> 16 );
2947 // store_byte(sp+3, (next_pc & 0xff000000) >> 24);
2948
2949 mask = REGS;
2950
2951 if (mask & 0x80)
2952 {
2953 sp -= 4;
2954 store_word (sp, State.regs[REG_D0 + 2]);
2955 }
2956
2957 if (mask & 0x40)
2958 {
2959 sp -= 4;
2960 store_word (sp, State.regs[REG_D0 + 3]);
2961 }
2962
2963 if (mask & 0x20)
2964 {
2965 sp -= 4;
2966 store_word (sp, State.regs[REG_A0 + 2]);
2967 }
2968
2969 if (mask & 0x10)
2970 {
2971 sp -= 4;
2972 store_word (sp, State.regs[REG_A0 + 3]);
2973 }
2974
2975 if (mask & 0x8)
2976 {
2977 sp -= 4;
2978 store_word (sp, State.regs[REG_D0]);
2979 sp -= 4;
2980 store_word (sp, State.regs[REG_D0 + 1]);
2981 sp -= 4;
2982 store_word (sp, State.regs[REG_A0]);
2983 sp -= 4;
2984 store_word (sp, State.regs[REG_A0 + 1]);
2985 sp -= 4;
2986 store_word (sp, State.regs[REG_MDR]);
2987 sp -= 4;
2988 store_word (sp, State.regs[REG_LIR]);
2989 sp -= 4;
2990 store_word (sp, State.regs[REG_LAR]);
2991 sp -= 4;
2992 }
2993
2994 /* Update the stack pointer, note that the register saves to do not
2995 modify SP. The SP adjustment is derived totally from the imm8
2996 field. */
2997 State.regs[REG_SP] -= IMM8;
2998 State.regs[REG_MDR] = next_pc;
2999 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
3000 nia = PC;
3001 }
3002
3003
3004 // 1111 0000 1111 00An; calls (An)
3005 8.0xf0+4.0xf,00,2.AN0:D0:::calls
3006 "calls"
3007 *mn10300
3008 {
3009 // OP_F0F0 ();
3010 unsigned int next_pc, sp;
3011
3012 PC = cia;
3013 sp = State.regs[REG_SP];
3014 next_pc = State.regs[REG_PC] + 2;
3015 store_word(sp, next_pc);
3016 State.regs[REG_MDR] = next_pc;
3017 State.regs[REG_PC] = State.regs[REG_A0 + AN0];
3018 nia = PC;
3019 }
3020
3021
3022 // 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.)
3023 8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
3024 "calls"
3025 *mn10300
3026 {
3027 // OP_FAFF0000 ();
3028 unsigned int next_pc, sp;
3029
3030 PC = cia;
3031 sp = State.regs[REG_SP];
3032 next_pc = State.regs[REG_PC] + 4;
3033 store_word(sp, next_pc);
3034 State.regs[REG_MDR] = next_pc;
3035 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
3036 nia = PC;
3037 }
3038
3039
3040 // 1111 1100 1111 1111 d32.....; calls (d32,PC)
3041 8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
3042 "calls"
3043 *mn10300
3044 {
3045 // OP_FCFF0000 ();
3046 unsigned int next_pc, sp;
3047
3048 PC = cia;
3049 sp = State.regs[REG_SP];
3050 next_pc = State.regs[REG_PC] + 6;
3051 store_word(sp, next_pc);
3052 State.regs[REG_MDR] = next_pc;
3053 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
3054 nia = PC;
3055 }
3056
3057
3058 // 1101 1111 regs.... imm8....; ret regs,imm8 (imm8 is zero-extended.)
3059 8.0xdf+8.REGS+8.IMM8:S2:::ret
3060 "ret"
3061 *mn10300
3062 {
3063 // OP_DF0000 ();
3064 unsigned int sp, offset;
3065 unsigned long mask;
3066
3067 PC = cia;
3068 State.regs[REG_SP] += IMM8;
3069 sp = State.regs[REG_SP];
3070
3071 offset = -4;
3072 mask = REGS;
3073
3074 if (mask & 0x80)
3075 {
3076 State.regs[REG_D0 + 2] = load_word (sp + offset);
3077 offset -= 4;
3078 }
3079
3080 if (mask & 0x40)
3081 {
3082 State.regs[REG_D0 + 3] = load_word (sp + offset);
3083 offset -= 4;
3084 }
3085
3086 if (mask & 0x20)
3087 {
3088 State.regs[REG_A0 + 2] = load_word (sp + offset);
3089 offset -= 4;
3090 }
3091
3092 if (mask & 0x10)
3093 {
3094 State.regs[REG_A0 + 3] = load_word (sp + offset);
3095 offset -= 4;
3096 }
3097
3098 if (mask & 0x8)
3099 {
3100 State.regs[REG_D0] = load_word (sp + offset);
3101 offset -= 4;
3102 State.regs[REG_D0 + 1] = load_word (sp + offset);
3103 offset -= 4;
3104 State.regs[REG_A0] = load_word (sp + offset);
3105 offset -= 4;
3106 State.regs[REG_A0 + 1] = load_word (sp + offset);
3107 offset -= 4;
3108 State.regs[REG_MDR] = load_word (sp + offset);
3109 offset -= 4;
3110 State.regs[REG_LIR] = load_word (sp + offset);
3111 offset -= 4;
3112 State.regs[REG_LAR] = load_word (sp + offset);
3113 offset -= 4;
3114 }
3115
3116 /* Restore the PC value. */
3117 State.regs[REG_PC] = load_word(sp);
3118 nia = PC;
3119 }
3120
3121
3122 // 1101 1110 regs.... imm8....; retf regs,imm8 (imm8 is zero-extended.)
3123 8.0xde+8.REGS+8.IMM8:S2:::retf
3124 "retf"
3125 *mn10300
3126 {
3127 // OP_DE0000 ();
3128 unsigned int sp, offset;
3129 unsigned long mask;
3130
3131 PC = cia;
3132 State.regs[REG_SP] += IMM8;
3133 sp = State.regs[REG_SP];
3134 State.regs[REG_PC] = State.regs[REG_MDR] - 3;
3135
3136 offset = -4;
3137 mask = REGS;
3138
3139 if (mask & 0x80)
3140 {
3141 State.regs[REG_D0 + 2] = load_word (sp + offset);
3142 offset -= 4;
3143 }
3144
3145 if (mask & 0x40)
3146 {
3147 State.regs[REG_D0 + 3] = load_word (sp + offset);
3148 offset -= 4;
3149 }
3150
3151 if (mask & 0x20)
3152 {
3153 State.regs[REG_A0 + 2] = load_word (sp + offset);
3154 offset -= 4;
3155 }
3156
3157 if (mask & 0x10)
3158 {
3159 State.regs[REG_A0 + 3] = load_word (sp + offset);
3160 offset -= 4;
3161 }
3162
3163 if (mask & 0x8)
3164 {
3165 State.regs[REG_D0] = load_word (sp + offset);
3166 offset -= 4;
3167 State.regs[REG_D0 + 1] = load_word (sp + offset);
3168 offset -= 4;
3169 State.regs[REG_A0] = load_word (sp + offset);
3170 offset -= 4;
3171 State.regs[REG_A0 + 1] = load_word (sp + offset);
3172 offset -= 4;
3173 State.regs[REG_MDR] = load_word (sp + offset);
3174 offset -= 4;
3175 State.regs[REG_LIR] = load_word (sp + offset);
3176 offset -= 4;
3177 State.regs[REG_LAR] = load_word (sp + offset);
3178 offset -= 4;
3179 }
3180 }
3181
3182
3183 // 1111 0000 1111 1100; rets
3184 8.0xf0+8.0xfc:D0:::rets
3185 "rets"
3186 *mn10300
3187 {
3188 // OP_F0FC ();
3189 unsigned int sp;
3190
3191 sp = State.regs[REG_SP];
3192 State.regs[REG_PC] = load_word(sp);
3193 nia = PC;
3194 }
3195
3196
3197 // 1111 0000 1111 1101; rti
3198 8.0xf0+8.0xfd:D0:::rti
3199 "rti"
3200 *mn10300
3201 {
3202 // OP_F0FD ();
3203 unsigned int sp;
3204
3205 sp = State.regs[REG_SP];
3206 PSW = load_half(sp);
3207 State.regs[REG_PC] = load_word(sp+4);
3208 State.regs[REG_SP] +=8;
3209 nia = PC;
3210 }
3211
3212
3213 // 1111 0000 1111 1110; trap
3214 8.0xf0+8.0xfe:D0:::trap
3215 "trap"
3216 *mn10300
3217 {
3218 // OP_F0FE ();
3219 unsigned int sp, next_pc;
3220
3221 PC = cia;
3222 sp = State.regs[REG_SP];
3223 next_pc = State.regs[REG_PC] + 2;
3224 store_word(sp, next_pc);
3225 nia = PC;
3226 }
3227
3228
3229 // 1111 0000 1111 1111; rtm
3230 8.0xf0+8.0xff:D0:::rtm
3231 "rtm"
3232 *mn10300
3233 {
3234 // OP_F0FF ();
3235 PC = cia;
3236 abort ();
3237 }
3238
3239
3240 // 1100 1011; nop
3241 8.0xcb:S0:::nop
3242 "nop"
3243 *mn10300
3244 {
3245 // OP_CB ();
3246 PC = cia;
3247 }
3248
3249
3250 // 1111 0101 0000 DmDn; udf20 Dm,Dn
3251 8.0xf5+4.0x0,2.DN1,2.DN0:D0:::putx
3252 "putx"
3253 *mn10300
3254 {
3255 // OP_F500 ();
3256 PC = cia;
3257 State.regs[REG_MDRQ] = State.regs[REG_D0 + DN0];
3258 }
3259
3260
3261 // 1111 0110 1111 DmDn; udf15 Dm,Dn
3262 8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
3263 "getx"
3264 *mn10300
3265 {
3266 // OP_F6F0 ();
3267 int z, n;
3268
3269 PC = cia;
3270 z = (State.regs[REG_MDRQ] == 0);
3271 n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
3272 State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];
3273
3274 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3275 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
3276 }
3277
3278
3279 // 1111 0110 0000 DmDn; udf00 Dm,Dn
3280 8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
3281 "mulq"
3282 *mn10300
3283 {
3284 // OP_F600 ();
3285 unsigned long long temp;
3286 int n, z;
3287
3288 PC = cia;
3289 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3290 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
3291 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3292 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3293 z = (State.regs[REG_D0 + DN0] == 0);
3294 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3295 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3296 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3297 }
3298
3299
3300 // 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.)
3301 8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
3302 "mulq"
3303 *mn10300
3304 {
3305 // OP_F90000 ();
3306 unsigned long long temp;
3307 int n, z;
3308
3309 PC = cia;
3310 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3311 * (signed64)(signed32)EXTEND8 (IMM8));
3312 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3313 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3314 z = (State.regs[REG_D0 + DN0] == 0);
3315 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3316 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3317 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3318 }
3319
3320
3321 // 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.)
3322 8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
3323 "mulq"
3324 *mn10300
3325 {
3326 // OP_FB000000 ();
3327 unsigned long long temp;
3328 int n, z;
3329
3330 PC = cia;
3331 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3332 * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
3333 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3334 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3335 z = (State.regs[REG_D0 + DN0] == 0);
3336 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3337 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3338 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3339 }
3340
3341
3342 // 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn
3343 8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
3344 "mulq"
3345 *mn10300
3346 {
3347 // OP_FD000000 ();
3348 unsigned long long temp;
3349 int n, z;
3350
3351 PC = cia;
3352 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3353 * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3354 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3355 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3356 z = (State.regs[REG_D0 + DN0] == 0);
3357 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3358 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3359 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3360 }
3361
3362
3363 // 1111 0110 0001 DmDn; udf01 Dm,Dn
3364 8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
3365 "mulqu"
3366 *mn10300
3367 {
3368 // OP_F610 ();
3369 unsigned long long temp;
3370 int n, z;
3371
3372 PC = cia;
3373 temp = ((unsigned64) State.regs[REG_D0 + DN0]
3374 * (unsigned64) State.regs[REG_D0 + DM1]);
3375 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3376 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3377 z = (State.regs[REG_D0 + DN0] == 0);
3378 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3379 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3380 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3381 }
3382
3383
3384 // 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.)
3385 8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
3386 "mulqu"
3387 *mn10300
3388 {
3389 // OP_F91400 ();
3390 unsigned long long temp;
3391 int n, z;
3392
3393 PC = cia;
3394 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3395 * (unsigned64)EXTEND8 (IMM8));
3396 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3397 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3398 z = (State.regs[REG_D0 + DN0] == 0);
3399 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3400 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3401 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3402 }
3403
3404
3405 // 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.)
3406 8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
3407 "mulqu"
3408 *mn10300
3409 {
3410 // OP_FB140000 ();
3411 unsigned long long temp;
3412 int n, z;
3413
3414 PC = cia;
3415 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3416 * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
3417 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3418 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3419 z = (State.regs[REG_D0 + DN0] == 0);
3420 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3421 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3422 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3423 }
3424
3425
3426 // 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn
3427 8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
3428 "mulqu"
3429 *mn10300
3430 {
3431 // OP_FD140000 ();
3432 unsigned long long temp;
3433 int n, z;
3434
3435 PC = cia;
3436 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3437 * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3438 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3439 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3440 z = (State.regs[REG_D0 + DN0] == 0);
3441 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3442 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3443 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3444 }
3445
3446
3447 // 1111 0110 0100 DmDn; udf04 Dm,Dn
3448 8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
3449 "sat16"
3450 *mn10300
3451 {
3452 // OP_F640 ();
3453 int temp;
3454
3455 PC = cia;
3456 temp = State.regs[REG_D0 + DM1];
3457 temp = (temp > 0x7fff ? 0x7fff : temp);
3458 temp = (temp < -0x8000 ? -0x8000 : temp);
3459 State.regs[REG_D0 + DN0] = temp;
3460 }
3461
3462
3463 // 1111 0110 0101 DmDn; udf05 Dm,Dn
3464 8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
3465 "sat24"
3466 *mn10300
3467 {
3468 // OP_F650 ();
3469 int temp;
3470
3471 PC = cia;
3472 temp = State.regs[REG_D0 + DM1];
3473 temp = (temp > 0x7fffff ? 0x7fffff : temp);
3474 temp = (temp < -0x800000 ? -0x800000 : temp);
3475 State.regs[REG_D0 + DN0] = temp;
3476 }
3477
3478
3479 // 1111 0110 0111 DmDn; udf07 Dm,Dn
3480 8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
3481 "bsch"
3482 *mn10300
3483 {
3484 // OP_F670 ();
3485 int temp, c;
3486
3487 PC = cia;
3488 temp = State.regs[REG_D0 + DM1];
3489 temp <<= (State.regs[REG_D0 + DN0] & 0x1f);
3490 c = (temp != 0 ? 1 : 0);
3491 PSW &= ~(PSW_C);
3492 PSW |= (c ? PSW_C : 0);
3493 }
3494
3495
3496 // 1111 0000 0010 0000; syscall
3497 8.0xf0+8.0x20:D0:::syscall
3498 "syscall"
3499 *mn10300
3500 {
3501 // OP_F020 ();
3502 PC = cia;
3503 do_syscall ();
3504 }
3505
3506
3507 // 1111 1111; break
3508 8.0xff:S0:::break
3509 "break"
3510 *mn10300
3511 {
3512 // OP_FF ();
3513 PC = cia;
3514 // State.exception = SIGTRAP;
3515 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
3516 PC -= 1;
3517 }
GDB Binutils - Deliverables
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