4 #include "gdb/callback.h"
5 #include "opcode/mn10300.h"
7 #include "gdb/remote-sim.h"
19 extern host_callback
*mn10300_callback
;
20 extern SIM_DESC simulator
;
22 #define DEBUG_TRACE 0x00000001
23 #define DEBUG_VALUES 0x00000002
25 extern int mn10300_debug
;
28 typedef unsigned char uint8
;
29 typedef signed char int8
;
31 #error "Char is not an 8-bit type"
35 typedef unsigned short uint16
;
36 typedef signed short int16
;
38 #error "Short is not a 16-bit type"
41 #if INT_MAX == 2147483647
43 typedef unsigned int uint32
;
44 typedef signed int int32
;
47 # if LONG_MAX == 2147483647
49 typedef unsigned long uint32
;
50 typedef signed long int32
;
53 # error "Neither int nor long is a 32-bit type"
74 /* The current state of the processor; registers, memory, etc. */
78 reg_t regs
[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
79 lir, lar, mdrq, plus some room for processor
83 reg_t fs
[32]; /* FS0-31 */
84 dword fd
[16]; /* FD0,2,...,30 */
86 uint8
*mem
; /* main memory */
90 /* All internal state modified by signal_exception() that may need to be
91 rolled back for passing moment-of-exception image back to gdb. */
92 reg_t exc_trigger_regs
[32];
93 reg_t exc_suspend_regs
[32];
96 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
97 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
98 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
101 extern struct _state State
;
103 extern struct simops Simops
[];
105 #define PC (State.regs[REG_PC])
106 #define SP (State.regs[REG_SP])
108 #define PSW (State.regs[11])
113 #define PSW_IE LSBIT (11)
114 #define PSW_LM LSMASK (10, 8)
116 #define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
117 #define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
138 #define FPCR (State.regs[REG_FPCR])
140 #define FCC_MASK LSMASK (21, 18)
141 #define RM_MASK LSMASK (17, 16) /* Must always be zero. */
142 #define EC_MASK LSMASK (14, 10)
143 #define EE_MASK LSMASK ( 9, 5)
144 #define EF_MASK LSMASK ( 4, 0)
145 #define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
147 #define FCC_L LSBIT (21)
148 #define FCC_G LSBIT (20)
149 #define FCC_E LSBIT (19)
150 #define FCC_U LSBIT (18)
152 #define EC_V LSBIT (14)
153 #define EC_Z LSBIT (13)
154 #define EC_O LSBIT (12)
155 #define EC_U LSBIT (11)
156 #define EC_I LSBIT (10)
158 #define EE_V LSBIT (9)
159 #define EE_Z LSBIT (8)
160 #define EE_O LSBIT (7)
161 #define EE_U LSBIT (6)
162 #define EE_I LSBIT (5)
164 #define EF_V LSBIT (4)
165 #define EF_Z LSBIT (3)
166 #define EF_O LSBIT (2)
167 #define EF_U LSBIT (1)
168 #define EF_I LSBIT (0)
170 #define PSW_FE LSBIT(20)
171 #define FPU_DISABLED !(PSW & PSW_FE)
173 #define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
174 #define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
175 #define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
177 #define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
178 #define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
179 #define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
180 #define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
187 #define FETCH32(a,b,c,d) \
188 ((a)+((b)<<8)+((c)<<16)+((d)<<24))
190 #define FETCH24(a,b,c) \
191 ((a)+((b)<<8)+((c)<<16))
193 #define FETCH16(a,b) ((a)+((b)<<8))
195 #define load_byte(ADDR) \
196 sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
198 #define load_half(ADDR) \
199 sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
201 #define load_word(ADDR) \
202 sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
204 #define load_dword(ADDR) \
205 u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
206 PC, read_map, (ADDR)))
209 u642dw (unsigned64 dw
)
213 r
.low
= (unsigned32
)dw
;
214 r
.high
= (unsigned32
)(dw
>> 32);
218 #define store_byte(ADDR, DATA) \
219 sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
220 PC, write_map, (ADDR), (DATA))
223 #define store_half(ADDR, DATA) \
224 sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
225 PC, write_map, (ADDR), (DATA))
228 #define store_word(ADDR, DATA) \
229 sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
230 PC, write_map, (ADDR), (DATA))
231 #define store_dword(ADDR, DATA) \
232 sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
233 PC, write_map, (ADDR), dw2u64 (DATA))
235 static INLINE unsigned64
238 return data
.low
| (((unsigned64
)data
.high
) << 32);
241 /* Function declarations. */
243 uint32
get_word (uint8
*);
244 uint16
get_half (uint8
*);
245 uint8
get_byte (uint8
*);
246 void put_word (uint8
*, uint32
);
247 void put_half (uint8
*, uint16
);
248 void put_byte (uint8
*, uint8
);
250 extern uint8
*map (SIM_ADDR addr
);
252 INLINE_SIM_MAIN (void) genericAdd (unsigned32 source
, unsigned32 destReg
);
253 INLINE_SIM_MAIN (void) genericSub (unsigned32 source
, unsigned32 destReg
);
254 INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd
, unsigned32 rightOpnd
);
255 INLINE_SIM_MAIN (void) genericOr (unsigned32 source
, unsigned32 destReg
);
256 INLINE_SIM_MAIN (void) genericXor (unsigned32 source
, unsigned32 destReg
);
257 INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd
, unsigned32 rightOpnd
);
258 INLINE_SIM_MAIN (int) syscall_read_mem (host_callback
*cb
,
259 struct cb_syscall
*sc
,
263 INLINE_SIM_MAIN (int) syscall_write_mem (host_callback
*cb
,
264 struct cb_syscall
*sc
,
268 INLINE_SIM_MAIN (void) do_syscall (void);
269 void program_interrupt (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
, SIM_SIGNAL sig
);
271 void mn10300_cpu_exception_trigger(SIM_DESC sd
, sim_cpu
* cpu
, address_word pc
);
272 void mn10300_cpu_exception_suspend(SIM_DESC sd
, sim_cpu
* cpu
, int exception
);
273 void mn10300_cpu_exception_resume(SIM_DESC sd
, sim_cpu
* cpu
, int exception
);
275 void fpu_disabled_exception (SIM_DESC
, sim_cpu
*, address_word
);
276 void fpu_unimp_exception (SIM_DESC
, sim_cpu
*, address_word
);
277 void fpu_check_signal_exception (SIM_DESC
, sim_cpu
*, address_word
);
279 extern const struct fp_prec_t
281 void (* reg2val
) (const void *, sim_fpu
*);
282 int (* round
) (sim_fpu
*);
283 void (* val2reg
) (const sim_fpu
*, void *);
284 } fp_single_prec
, fp_double_prec
;
286 #define FP_SINGLE (&fp_single_prec)
287 #define FP_DOUBLE (&fp_double_prec)
289 void fpu_rsqrt (SIM_DESC
, sim_cpu
*, address_word
, const void *, void *, const struct fp_prec_t
*);
290 void fpu_sqrt (SIM_DESC
, sim_cpu
*, address_word
, const void *, void *, const struct fp_prec_t
*);
291 void fpu_cmp (SIM_DESC
, sim_cpu
*, address_word
, const void *, const void *, const struct fp_prec_t
*);
292 void fpu_add (SIM_DESC
, sim_cpu
*, address_word
, const void *, const void *, void *, const struct fp_prec_t
*);
293 void fpu_sub (SIM_DESC
, sim_cpu
*, address_word
, const void *, const void *, void *, const struct fp_prec_t
*);
294 void fpu_mul (SIM_DESC
, sim_cpu
*, address_word
, const void *, const void *, void *, const struct fp_prec_t
*);
295 void fpu_div (SIM_DESC
, sim_cpu
*, address_word
, const void *, const void *, void *, const struct fp_prec_t
*);
296 void fpu_fmadd (SIM_DESC
, sim_cpu
*, address_word
, const void *, const void *, const void *, void *, const struct fp_prec_t
*);
297 void fpu_fmsub (SIM_DESC
, sim_cpu
*, address_word
, const void *, const void *, const void *, void *, const struct fp_prec_t
*);
298 void fpu_fnmadd (SIM_DESC
, sim_cpu
*, address_word
, const void *, const void *, const void *, void *, const struct fp_prec_t
*);
299 void fpu_fnmsub (SIM_DESC
, sim_cpu
*, address_word
, const void *, const void *, const void *, void *, const struct fp_prec_t
*);
This page took 0.035325 seconds and 4 git commands to generate.