sim/mn10300/mn10300_sim.h

   1 #include <stdio.h>
   2 #include <ctype.h>
   3 #include "ansidecl.h"
   4 #include "callback.h"
   5 #include "opcode/mn10300.h"
   6 #include <limits.h>
   7 #include "remote-sim.h"
   8
   9 #ifndef INLINE
  10 #ifdef __GNUC__
  11 #define INLINE inline
  12 #else
  13 #define INLINE
  14 #endif
  15 #endif
  16
  17 extern host_callback *mn10300_callback;
  18 extern SIM_DESC simulator;
  19
  20 #define DEBUG_TRACE             0x00000001
  21 #define DEBUG_VALUES            0x00000002
  22
  23 extern int mn10300_debug;
  24
  25 #if UCHAR_MAX == 255
  26 typedef unsigned char uint8;
  27 typedef signed char int8;
  28 #else
  29 #error "Char is not an 8-bit type"
  30 #endif
  31
  32 #if SHRT_MAX == 32767
  33 typedef unsigned short uint16;
  34 typedef signed short int16;
  35 #else
  36 #error "Short is not a 16-bit type"
  37 #endif
  38
  39 #if INT_MAX == 2147483647
  40
  41 typedef unsigned int uint32;
  42 typedef signed int int32;
  43
  44 #else
  45 #  if LONG_MAX == 2147483647
  46
  47 typedef unsigned long uint32;
  48 typedef signed long int32;
  49
  50 #  else
  51 #  error "Neither int nor long is a 32-bit type"
  52 #  endif
  53 #endif
  54
  55 typedef uint32 reg_t;
  56
  57 struct simops
  58 {
  59   long opcode;
  60   long mask;
  61   void (*func)();
  62   int length;
  63   int format;
  64   int numops;
  65   int operands[16];
  66 };
  67
  68 /* The current state of the processor; registers, memory, etc.  */
  69
  70 struct _state
  71 {
  72   reg_t regs[15];               /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
  73                                    lir, lar, mdrq */
  74   uint8 *mem;                   /* main memory */
  75   int exception;
  76   int exited;
  77 } State;
  78
  79 extern uint32 OP[4];
  80 extern struct simops Simops[];
  81
  82 #define PC      (State.regs[9])
  83
  84 #define PSW (State.regs[11])
  85 #define PSW_Z 0x1
  86 #define PSW_N 0x2
  87 #define PSW_C 0x4
  88 #define PSW_V 0x8
  89
  90 #define REG_D0 0
  91 #define REG_A0 4
  92 #define REG_SP 8
  93 #define REG_PC 9
  94 #define REG_MDR 10
  95 #define REG_PSW 11
  96 #define REG_LIR 12
  97 #define REG_LAR 13
  98 #define REG_MDRQ 14
  99
 100 #if WITH_COMMON
 101 /* These definitions conflict with similar macros in common.  */
 102 #else
 103 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 104
 105 /* sign-extend a 4-bit number */
 106 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 107
 108 /* sign-extend a 5-bit number */
 109 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 110
 111 /* sign-extend an 8-bit number */
 112 #define SEXT8(x)        ((((x)&0xff)^(~0x7f))+0x80)
 113
 114 /* sign-extend a 9-bit number */
 115 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 116
 117 /* sign-extend a 16-bit number */
 118 #define SEXT16(x)       ((((x)&0xffff)^(~0x7fff))+0x8000)
 119
 120 /* sign-extend a 22-bit number */
 121 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 122
 123 #define MAX32   0x7fffffffLL
 124 #define MIN32   0xff80000000LL
 125 #define MASK32  0xffffffffLL
 126 #define MASK40  0xffffffffffLL
 127 #endif  /* not WITH_COMMON */
 128
 129 #ifdef _WIN32
 130 #define SIGTRAP 5
 131 #define SIGQUIT 3
 132 #endif
 133
 134 #if WITH_COMMON
 135
 136 #define FETCH32(a,b,c,d) \
 137  ((a)+((b)<<8)+((c)<<16)+((d)<<24))
 138
 139 #define FETCH16(a,b) ((a)+((b)<<8))
 140
 141 #define load_byte(ADDR) \
 142 sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 143
 144 #define load_half(ADDR) \
 145 sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 146
 147 #define load_word(ADDR) \
 148 sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 149
 150 #define store_byte(ADDR, DATA) \
 151 sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
 152                             PC, write_map, (ADDR), (DATA))
 153
 154
 155 #define store_half(ADDR, DATA) \
 156 sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
 157                             PC, write_map, (ADDR), (DATA))
 158
 159
 160 #define store_word(ADDR, DATA) \
 161 sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
 162                             PC, write_map, (ADDR), (DATA))
 163 #endif  /* WITH_COMMON */
 164
 165 #if WITH_COMMON
 166 #else
 167 #define load_mem_big(addr,len) \
 168   (len == 1 ? *((addr) + State.mem) : \
 169    len == 2 ? ((*((addr) + State.mem) << 8) \
 170                | *(((addr) + 1) + State.mem)) : \
 171    len == 3 ? ((*((addr) + State.mem) << 16) \
 172                | (*(((addr) + 1) + State.mem) << 8) \
 173                | *(((addr) + 2) + State.mem)) : \
 174               ((*((addr) + State.mem) << 24) \
 175                | (*(((addr) + 1) + State.mem) << 16) \
 176                | (*(((addr) + 2) + State.mem) << 8) \
 177                | *(((addr) + 3) + State.mem)))
 178
 179 static INLINE uint32
 180 load_byte (addr)
 181      SIM_ADDR addr;
 182 {
 183   uint8 *p = (addr & 0xffffff) + State.mem;
 184
 185 #ifdef CHECK_ADDR
 186   if ((addr & 0xffffff) > max_mem)
 187     abort ();
 188 #endif
 189
 190   return p[0];
 191 }
 192
 193 static INLINE uint32
 194 load_half (addr)
 195      SIM_ADDR addr;
 196 {
 197   uint8 *p = (addr & 0xffffff) + State.mem;
 198
 199 #ifdef CHECK_ADDR
 200   if ((addr & 0xffffff) > max_mem)
 201     abort ();
 202 #endif
 203
 204   return p[1] << 8 | p[0];
 205 }
 206
 207 static INLINE uint32
 208 load_3_byte (addr)
 209      SIM_ADDR addr;
 210 {
 211   uint8 *p = (addr & 0xffffff) + State.mem;
 212
 213 #ifdef CHECK_ADDR
 214   if ((addr & 0xffffff) > max_mem)
 215     abort ();
 216 #endif
 217
 218   return p[2] << 16 | p[1] << 8 | p[0];
 219 }
 220
 221 static INLINE uint32
 222 load_word (addr)
 223      SIM_ADDR addr;
 224 {
 225   uint8 *p = (addr & 0xffffff) + State.mem;
 226
 227 #ifdef CHECK_ADDR
 228   if ((addr & 0xffffff) > max_mem)
 229     abort ();
 230 #endif
 231
 232   return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
 233 }
 234
 235 static INLINE uint32
 236 load_mem (addr, len)
 237      SIM_ADDR addr;
 238      int len;
 239 {
 240   uint8 *p = (addr & 0xffffff) + State.mem;
 241
 242 #ifdef CHECK_ADDR
 243   if ((addr & 0xffffff) > max_mem)
 244     abort ();
 245 #endif
 246
 247   switch (len)
 248     {
 249     case 1:
 250       return p[0];
 251     case 2:
 252       return p[1] << 8 | p[0];
 253     case 3:
 254       return p[2] << 16 | p[1] << 8 | p[0];
 255     case 4:
 256       return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
 257     default:
 258       abort ();
 259     }
 260 }
 261
 262 static INLINE void
 263 store_byte (addr, data)
 264      SIM_ADDR addr;
 265      uint32 data;
 266 {
 267   uint8 *p = (addr & 0xffffff) + State.mem;
 268
 269 #ifdef CHECK_ADDR
 270   if ((addr & 0xffffff) > max_mem)
 271     abort ();
 272 #endif
 273
 274   p[0] = data;
 275 }
 276
 277 static INLINE void
 278 store_half (addr, data)
 279      SIM_ADDR addr;
 280      uint32 data;
 281 {
 282   uint8 *p = (addr & 0xffffff) + State.mem;
 283
 284 #ifdef CHECK_ADDR
 285   if ((addr & 0xffffff) > max_mem)
 286     abort ();
 287 #endif
 288
 289   p[0] = data;
 290   p[1] = data >> 8;
 291 }
 292
 293 static INLINE void
 294 store_3_byte (addr, data)
 295      SIM_ADDR addr;
 296      uint32 data;
 297 {
 298   uint8 *p = (addr & 0xffffff) + State.mem;
 299
 300 #ifdef CHECK_ADDR
 301   if ((addr & 0xffffff) > max_mem)
 302     abort ();
 303 #endif
 304
 305   p[0] = data;
 306   p[1] = data >> 8;
 307   p[2] = data >> 16;
 308 }
 309
 310 static INLINE void
 311 store_word (addr, data)
 312      SIM_ADDR addr;
 313      uint32 data;
 314 {
 315   uint8 *p = (addr & 0xffffff) + State.mem;
 316
 317 #ifdef CHECK_ADDR
 318   if ((addr & 0xffffff) > max_mem)
 319     abort ();
 320 #endif
 321
 322   p[0] = data;
 323   p[1] = data >> 8;
 324   p[2] = data >> 16;
 325   p[3] = data >> 24;
 326 }
 327 #endif  /* not WITH_COMMON */
 328
 329 /* Function declarations.  */
 330
 331 uint32 get_word PARAMS ((uint8 *));
 332 uint16 get_half PARAMS ((uint8 *));
 333 uint8 get_byte PARAMS ((uint8 *));
 334 void put_word PARAMS ((uint8 *, uint32));
 335 void put_half PARAMS ((uint8 *, uint16));
 336 void put_byte PARAMS ((uint8 *, uint8));
 337
 338 extern uint8 *map PARAMS ((SIM_ADDR addr));
 339
 340 void genericAdd PARAMS ((unsigned long source, unsigned long destReg));
 341 void genericSub PARAMS ((unsigned long source, unsigned long destReg));
 342 void genericCmp PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd));
 343 void genericOr PARAMS ((unsigned long source, unsigned long destReg));
 344 void genericXor PARAMS ((unsigned long source, unsigned long destReg));
 345 void genericBtst PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd));
 346 void do_syscall PARAMS ((void));