24 #include <sys/times.h>
29 #define REG0(X) ((X) & 0x3)
30 #define REG1(X) (((X) & 0xc) >> 2)
31 #define REG0_4(X) (((X) & 0x30) >> 4)
32 #define REG0_8(X) (((X) & 0x300) >> 8)
33 #define REG1_8(X) (((X) & 0xc00) >> 10)
34 #define REG0_16(X) (((X) & 0x30000) >> 16)
35 #define REG1_16(X) (((X) & 0xc0000) >> 18)
38 INLINE_SIM_MAIN (void)
39 genericAdd(unsigned32 source
, unsigned32 destReg
)
44 dest
= State
.regs
[destReg
];
46 State
.regs
[destReg
] = sum
;
49 n
= (sum
& 0x80000000);
50 c
= (sum
< source
) || (sum
< dest
);
51 v
= ((dest
& 0x80000000) == (source
& 0x80000000)
52 && (dest
& 0x80000000) != (sum
& 0x80000000));
54 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
55 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
56 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
62 INLINE_SIM_MAIN (void)
63 genericSub(unsigned32 source
, unsigned32 destReg
)
66 unsigned32 dest
, difference
;
68 dest
= State
.regs
[destReg
];
69 difference
= dest
- source
;
70 State
.regs
[destReg
] = difference
;
72 z
= (difference
== 0);
73 n
= (difference
& 0x80000000);
75 v
= ((dest
& 0x80000000) != (source
& 0x80000000)
76 && (dest
& 0x80000000) != (difference
& 0x80000000));
78 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
79 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
80 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
83 INLINE_SIM_MAIN (void)
84 genericCmp(unsigned32 leftOpnd
, unsigned32 rightOpnd
)
89 value
= rightOpnd
- leftOpnd
;
92 n
= (value
& 0x80000000);
93 c
= (leftOpnd
> rightOpnd
);
94 v
= ((rightOpnd
& 0x80000000) != (leftOpnd
& 0x80000000)
95 && (rightOpnd
& 0x80000000) != (value
& 0x80000000));
97 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
98 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
99 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
103 INLINE_SIM_MAIN (void)
104 genericOr(unsigned32 source
, unsigned32 destReg
)
108 State
.regs
[destReg
] |= source
;
109 z
= (State
.regs
[destReg
] == 0);
110 n
= (State
.regs
[destReg
] & 0x80000000) != 0;
111 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
112 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
116 INLINE_SIM_MAIN (void)
117 genericXor(unsigned32 source
, unsigned32 destReg
)
121 State
.regs
[destReg
] ^= source
;
122 z
= (State
.regs
[destReg
] == 0);
123 n
= (State
.regs
[destReg
] & 0x80000000) != 0;
124 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
125 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
129 INLINE_SIM_MAIN (void)
130 genericBtst(unsigned32 leftOpnd
, unsigned32 rightOpnd
)
137 n
= (temp
& 0x80000000) != 0;
139 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
140 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
143 /* Read/write functions for system call interface. */
144 INLINE_SIM_MAIN (int)
145 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
146 unsigned long taddr
, char *buf
, int bytes
)
148 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
149 sim_cpu
*cpu
= STATE_CPU(sd
, 0);
151 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
154 INLINE_SIM_MAIN (int)
155 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
156 unsigned long taddr
, const char *buf
, int bytes
)
158 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
159 sim_cpu
*cpu
= STATE_CPU(sd
, 0);
161 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
166 INLINE_SIM_MAIN (void)
170 /* We use this for simulated system calls; we may need to change
171 it to a reserved instruction if we conflict with uses at
173 int save_errno
= errno
;
176 /* Registers passed to trap 0 */
178 /* Function number. */
179 #define FUNC (State.regs[0])
182 #define PARM1 (State.regs[1])
183 #define PARM2 (load_word (State.regs[REG_SP] + 12))
184 #define PARM3 (load_word (State.regs[REG_SP] + 16))
186 /* Registers set by trap 0 */
188 #define RETVAL State.regs[0] /* return value */
189 #define RETERR State.regs[1] /* return error code */
191 /* Turn a pointer in a register into a pointer into real memory. */
192 #define MEMPTR(x) (State.mem + x)
194 if ( FUNC
== TARGET_SYS_exit
)
196 /* EXIT - caller can look in PARM1 to work out the reason */
198 State
.exception
= SIGABRT
;
201 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
203 State
.exception
= SIGQUIT
;
211 CB_SYSCALL_INIT (&syscall
);
212 syscall
.arg1
= PARM1
;
213 syscall
.arg2
= PARM2
;
214 syscall
.arg3
= PARM3
;
216 syscall
.p1
= (PTR
) simulator
;
217 syscall
.read_mem
= syscall_read_mem
;
218 syscall
.write_mem
= syscall_write_mem
;
219 cb_syscall (STATE_CALLBACK (simulator
), &syscall
);
220 RETERR
= syscall
.errcode
;
221 RETVAL
= syscall
.result
;
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