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* simops.c (multiply instructions): Cast input operands to a
[deliverable/binutils-gdb.git] / sim / mn10300 / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #ifdef HAVE_UNISTD_H
5 #include <unistd.h>
6 #endif
7 #include "mn10300_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10 #include "bfd.h"
11 #include <errno.h>
12 #include <sys/stat.h>
13 #include <sys/times.h>
14 #include <sys/time.h>
15
16 #define REG0(X) ((X) & 0x3)
17 #define REG1(X) (((X) & 0xc) >> 2)
18 #define REG0_4(X) (((X) & 0x30) >> 4)
19 #define REG0_8(X) (((X) & 0x300) >> 8)
20 #define REG1_8(X) (((X) & 0xc00) >> 10)
21 #define REG0_16(X) (((X) & 0x30000) >> 16)
22 #define REG1_16(X) (((X) & 0xc0000) >> 18)
23 \f
24 /* mov imm8, dn */
25 void OP_8000 (insn, extension)
26 unsigned long insn, extension;
27 {
28 State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff);
29 }
30
31 /* mov dm, dn */
32 void OP_80 (insn, extension)
33 unsigned long insn, extension;
34 {
35 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
36 }
37
38 /* mov dm, an */
39 void OP_F1E0 (insn, extension)
40 unsigned long insn, extension;
41 {
42 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
43 }
44
45 /* mov am, dn */
46 void OP_F1D0 (insn, extension)
47 unsigned long insn, extension;
48 {
49 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
50 }
51
52 /* mov imm8, an */
53 void OP_9000 (insn, extension)
54 unsigned long insn, extension;
55 {
56 State.regs[REG_A0 + REG0_8 (insn)] = insn & 0xff;
57 }
58
59 /* mov am, an */
60 void OP_90 (insn, extension)
61 unsigned long insn, extension;
62 {
63 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
64 }
65
66 /* mov sp, an */
67 void OP_3C (insn, extension)
68 unsigned long insn, extension;
69 {
70 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_SP];
71 }
72
73 /* mov am, sp */
74 void OP_F2F0 (insn, extension)
75 unsigned long insn, extension;
76 {
77 State.regs[REG_SP] = State.regs[REG_A0 + REG1 (insn)];
78 }
79
80 /* mov psw, dn */
81 void OP_F2E4 (insn, extension)
82 unsigned long insn, extension;
83 {
84 State.regs[REG_D0 + REG0 (insn)] = PSW;
85 }
86
87 /* mov dm, psw */
88 void OP_F2F3 (insn, extension)
89 unsigned long insn, extension;
90 {
91 PSW = State.regs[REG_D0 + REG1 (insn)];
92 }
93
94 /* mov mdr, dn */
95 void OP_F2E0 (insn, extension)
96 unsigned long insn, extension;
97 {
98 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDR];
99 }
100
101 /* mov dm, mdr */
102 void OP_F2F2 (insn, extension)
103 unsigned long insn, extension;
104 {
105 State.regs[REG_MDR] = State.regs[REG_D0 + REG1 (insn)];
106 }
107
108 /* mov (am), dn */
109 void OP_70 (insn, extension)
110 unsigned long insn, extension;
111 {
112 State.regs[REG_D0 + REG1 (insn)]
113 = load_word (State.regs[REG_A0 + REG0 (insn)]);
114 }
115
116 /* mov (d8,am), dn */
117 void OP_F80000 (insn, extension)
118 unsigned long insn, extension;
119 {
120 State.regs[REG_D0 + REG1_8 (insn)]
121 = load_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)));
122 }
123
124 /* mov (d16,am), dn */
125 void OP_FA000000 (insn, extension)
126 unsigned long insn, extension;
127 {
128 State.regs[REG_D0 + REG1_16 (insn)]
129 = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
130 + SEXT16 (insn & 0xffff)));
131 }
132
133 /* mov (d32,am), dn */
134 void OP_FC000000 (insn, extension)
135 unsigned long insn, extension;
136 {
137 State.regs[REG_D0 + REG1_16 (insn)]
138 = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
139 + ((insn & 0xffff) << 16) + extension));
140 }
141
142 /* mov (d8,sp), dn */
143 void OP_5800 (insn, extension)
144 unsigned long insn, extension;
145 {
146 State.regs[REG_D0 + REG0_8 (insn)]
147 = load_word (State.regs[REG_SP] + (insn & 0xff));
148 }
149
150 /* mov (d16,sp), dn */
151 void OP_FAB40000 (insn, extension)
152 unsigned long insn, extension;
153 {
154 State.regs[REG_D0 + REG0_16 (insn)]
155 = load_word (State.regs[REG_SP] + (insn & 0xffff));
156 }
157
158 /* mov (d32,sp), dn */
159 void OP_FCB40000 (insn, extension)
160 unsigned long insn, extension;
161 {
162 State.regs[REG_D0 + REG0_16 (insn)]
163 = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
164 }
165
166 /* mov (di,am), dn */
167 void OP_F300 (insn, extension)
168 unsigned long insn, extension;
169 {
170 State.regs[REG_D0 + REG0_4 (insn)]
171 = load_word ((State.regs[REG_A0 + REG0 (insn)]
172 + State.regs[REG_D0 + REG1 (insn)]));
173 }
174
175 /* mov (abs16), dn */
176 void OP_300000 (insn, extension)
177 unsigned long insn, extension;
178 {
179 State.regs[REG_D0 + REG0_16 (insn)] = load_word ((insn & 0xffff));
180 }
181
182 /* mov (abs32), dn */
183 void OP_FCA40000 (insn, extension)
184 unsigned long insn, extension;
185 {
186 State.regs[REG_D0 + REG0_16 (insn)]
187 = load_word ((((insn & 0xffff) << 16) + extension));
188 }
189
190 /* mov (am), an */
191 void OP_F000 (insn, extension)
192 unsigned long insn, extension;
193 {
194 State.regs[REG_A0 + REG1 (insn)]
195 = load_word (State.regs[REG_A0 + REG0 (insn)]);
196 }
197
198 /* mov (d8,am), an */
199 void OP_F82000 (insn, extension)
200 unsigned long insn, extension;
201 {
202 State.regs[REG_A0 + REG1_8 (insn)]
203 = load_word ((State.regs[REG_A0 + REG0_8 (insn)]
204 + SEXT8 (insn & 0xff)));
205 }
206
207 /* mov (d16,am), an */
208 void OP_FA200000 (insn, extension)
209 unsigned long insn, extension;
210 {
211 State.regs[REG_A0 + REG1_16 (insn)]
212 = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
213 + SEXT16 (insn & 0xffff)));
214 }
215
216 /* mov (d32,am), an */
217 void OP_FC200000 (insn, extension)
218 unsigned long insn, extension;
219 {
220 State.regs[REG_A0 + REG1_16 (insn)]
221 = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
222 + ((insn & 0xffff) << 16) + extension));
223 }
224
225 /* mov (d8,sp), an */
226 void OP_5C00 (insn, extension)
227 unsigned long insn, extension;
228 {
229 State.regs[REG_A0 + REG0_8 (insn)]
230 = load_word (State.regs[REG_SP] + (insn & 0xff));
231 }
232
233 /* mov (d16,sp), an */
234 void OP_FAB00000 (insn, extension)
235 unsigned long insn, extension;
236 {
237 State.regs[REG_A0 + REG0_16 (insn)]
238 = load_word (State.regs[REG_SP] + (insn & 0xffff));
239 }
240
241 /* mov (d32,sp), an */
242 void OP_FCB00000 (insn, extension)
243 unsigned long insn, extension;
244 {
245 State.regs[REG_A0 + REG0_16 (insn)]
246 = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
247 }
248
249 /* mov (di,am), an */
250 void OP_F380 (insn, extension)
251 unsigned long insn, extension;
252 {
253 State.regs[REG_A0 + REG0_4 (insn)]
254 = load_word ((State.regs[REG_A0 + REG0 (insn)]
255 + State.regs[REG_D0 + REG1 (insn)]));
256 }
257
258 /* mov (abs16), an */
259 void OP_FAA00000 (insn, extension)
260 unsigned long insn, extension;
261 {
262 State.regs[REG_A0 + REG0_16 (insn)] = load_word ((insn & 0xffff));
263 }
264
265 /* mov (abs32), an */
266 void OP_FCA00000 (insn, extension)
267 unsigned long insn, extension;
268 {
269 State.regs[REG_A0 + REG0_16 (insn)]
270 = load_word ((((insn & 0xffff) << 16) + extension));
271 }
272
273 /* mov (d8,am), sp */
274 void OP_F8F000 (insn, extension)
275 unsigned long insn, extension;
276 {
277 State.regs[REG_SP]
278 = load_word ((State.regs[REG_A0 + REG0_8 (insn)]
279 + SEXT8 (insn & 0xff)));
280 }
281
282 /* mov dm, (an) */
283 void OP_60 (insn, extension)
284 unsigned long insn, extension;
285 {
286 store_word (State.regs[REG_A0 + REG0 (insn)],
287 State.regs[REG_D0 + REG1 (insn)]);
288 }
289
290 /* mov dm, (d8,an) */
291 void OP_F81000 (insn, extension)
292 unsigned long insn, extension;
293 {
294 store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
295 State.regs[REG_D0 + REG1_8 (insn)]);
296 }
297
298 /* mov dm (d16,an) */
299 void OP_FA100000 (insn, extension)
300 unsigned long insn, extension;
301 {
302 store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
303 State.regs[REG_D0 + REG1_16 (insn)]);
304 }
305
306 /* mov dm (d32,an) */
307 void OP_FC100000 (insn, extension)
308 unsigned long insn, extension;
309 {
310 store_word ((State.regs[REG_A0 + REG0_16 (insn)]
311 + ((insn & 0xffff) << 16) + extension),
312 State.regs[REG_D0 + REG1_16 (insn)]);
313 }
314
315 /* mov dm, (d8,sp) */
316 void OP_4200 (insn, extension)
317 unsigned long insn, extension;
318 {
319 store_word (State.regs[REG_SP] + (insn & 0xff),
320 State.regs[REG_D0 + REG1_8 (insn)]);
321 }
322
323 /* mov dm, (d16,sp) */
324 void OP_FA910000 (insn, extension)
325 unsigned long insn, extension;
326 {
327 store_word (State.regs[REG_SP] + (insn & 0xffff),
328 State.regs[REG_D0 + REG1_16 (insn)]);
329 }
330
331 /* mov dm, (d32,sp) */
332 void OP_FC910000 (insn, extension)
333 unsigned long insn, extension;
334 {
335 store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
336 State.regs[REG_D0 + REG1_16 (insn)]);
337 }
338
339 /* mov dm, (di,an) */
340 void OP_F340 (insn, extension)
341 unsigned long insn, extension;
342 {
343 store_word ((State.regs[REG_A0 + REG0 (insn)]
344 + State.regs[REG_D0 + REG1 (insn)]),
345 State.regs[REG_D0 + REG0_4 (insn)]);
346 }
347
348 /* mov dm, (abs16) */
349 void OP_10000 (insn, extension)
350 unsigned long insn, extension;
351 {
352 store_word ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
353 }
354
355 /* mov dm, (abs32) */
356 void OP_FC810000 (insn, extension)
357 unsigned long insn, extension;
358 {
359 store_word ((((insn & 0xffff) << 16) + extension),
360 State.regs[REG_D0 + REG1_16 (insn)]);
361 }
362
363 /* mov am, (an) */
364 void OP_F010 (insn, extension)
365 unsigned long insn, extension;
366 {
367 store_word (State.regs[REG_A0 + REG0 (insn)],
368 State.regs[REG_A0 + REG1 (insn)]);
369 }
370
371 /* mov am, (d8,an) */
372 void OP_F83000 (insn, extension)
373 unsigned long insn, extension;
374 {
375 store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
376 State.regs[REG_A0 + REG1_8 (insn)]);
377 }
378
379 /* mov am, (d16,an) */
380 void OP_FA300000 (insn, extension)
381 unsigned long insn, extension;
382 {
383 store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
384 State.regs[REG_A0 + REG1_16 (insn)]);
385 }
386
387 /* mov am, (d32,an) */
388 void OP_FC300000 (insn, extension)
389 unsigned long insn, extension;
390 {
391 store_word ((State.regs[REG_A0 + REG0_16 (insn)]
392 + ((insn & 0xffff) << 16) + extension),
393 State.regs[REG_A0 + REG1_16 (insn)]);
394 }
395
396 /* mov am, (d8,sp) */
397 void OP_4300 (insn, extension)
398 unsigned long insn, extension;
399 {
400 store_word (State.regs[REG_SP] + (insn & 0xff),
401 State.regs[REG_A0 + REG1_8 (insn)]);
402 }
403
404 /* mov am, (d16,sp) */
405 void OP_FA900000 (insn, extension)
406 unsigned long insn, extension;
407 {
408 store_word (State.regs[REG_SP] + (insn & 0xffff),
409 State.regs[REG_A0 + REG1_16 (insn)]);
410 }
411
412 /* mov am, (d32,sp) */
413 void OP_FC900000 (insn, extension)
414 unsigned long insn, extension;
415 {
416 store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
417 State.regs[REG_A0 + REG1_16 (insn)]);
418 }
419
420 /* mov am, (di,an) */
421 void OP_F3C0 (insn, extension)
422 unsigned long insn, extension;
423 {
424 store_word ((State.regs[REG_A0 + REG0 (insn)]
425 + State.regs[REG_D0 + REG1 (insn)]),
426 State.regs[REG_A0 + REG0_4 (insn)]);
427 }
428
429 /* mov am, (abs16) */
430 void OP_FA800000 (insn, extension)
431 unsigned long insn, extension;
432 {
433 store_word ((insn & 0xffff), State.regs[REG_A0 + REG1_16 (insn)]);
434 }
435
436 /* mov am, (abs32) */
437 void OP_FC800000 (insn, extension)
438 unsigned long insn, extension;
439 {
440 store_word ((((insn & 0xffff) << 16) + extension), State.regs[REG_A0 + REG1_16 (insn)]);
441 }
442
443 /* mov sp, (d8,an) */
444 void OP_F8F400 (insn, extension)
445 unsigned long insn, extension;
446 {
447 store_word (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff),
448 State.regs[REG_SP]);
449 }
450
451 /* mov imm16, dn */
452 void OP_2C0000 (insn, extension)
453 unsigned long insn, extension;
454 {
455 unsigned long value;
456
457 value = SEXT16 (insn & 0xffff);
458 State.regs[REG_D0 + REG0_16 (insn)] = value;
459 }
460
461 /* mov imm32,dn */
462 void OP_FCCC0000 (insn, extension)
463 unsigned long insn, extension;
464 {
465 unsigned long value;
466
467 value = ((insn & 0xffff) << 16) + extension;
468 State.regs[REG_D0 + REG0_16 (insn)] = value;
469 }
470
471 /* mov imm16, an */
472 void OP_240000 (insn, extension)
473 unsigned long insn, extension;
474 {
475 unsigned long value;
476
477 value = insn & 0xffff;
478 State.regs[REG_A0 + REG0_16 (insn)] = value;
479 }
480
481 /* mov imm32, an */
482 void OP_FCDC0000 (insn, extension)
483 unsigned long insn, extension;
484 {
485 unsigned long value;
486
487 value = ((insn & 0xffff) << 16) + extension;
488 State.regs[REG_A0 + REG0_16 (insn)] = value;
489 }
490
491 /* movbu (am), dn */
492 void OP_F040 (insn, extension)
493 unsigned long insn, extension;
494 {
495 State.regs[REG_D0 + REG1 (insn)]
496 = load_byte (State.regs[REG_A0 + REG0 (insn)]);
497 }
498
499 /* movbu (d8,am), dn */
500 void OP_F84000 (insn, extension)
501 unsigned long insn, extension;
502 {
503 State.regs[REG_D0 + REG1_8 (insn)]
504 = load_byte ((State.regs[REG_A0 + REG0_8 (insn)]
505 + SEXT8 (insn & 0xff)));
506 }
507
508 /* movbu (d16,am), dn */
509 void OP_FA400000 (insn, extension)
510 unsigned long insn, extension;
511 {
512 State.regs[REG_D0 + REG1_16 (insn)]
513 = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
514 + SEXT16 (insn & 0xffff)));
515 }
516
517 /* movbu (d32,am), dn */
518 void OP_FC400000 (insn, extension)
519 unsigned long insn, extension;
520 {
521 State.regs[REG_D0 + REG1_16 (insn)]
522 = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
523 + ((insn & 0xffff) << 16) + extension));
524 }
525
526 /* movbu (d8,sp), dn */
527 void OP_F8B800 (insn, extension)
528 unsigned long insn, extension;
529 {
530 State.regs[REG_D0 + REG0_8 (insn)]
531 = load_byte ((State.regs[REG_SP] + (insn & 0xff)));
532 }
533
534 /* movbu (d16,sp), dn */
535 void OP_FAB80000 (insn, extension)
536 unsigned long insn, extension;
537 {
538 State.regs[REG_D0 + REG0_16 (insn)]
539 = load_byte ((State.regs[REG_SP] + (insn & 0xffff)));
540 }
541
542 /* movbu (d32,sp), dn */
543 void OP_FCB80000 (insn, extension)
544 unsigned long insn, extension;
545 {
546 State.regs[REG_D0 + REG0_16 (insn)]
547 = load_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
548 }
549
550 /* movbu (di,am), dn */
551 void OP_F400 (insn, extension)
552 unsigned long insn, extension;
553 {
554 State.regs[REG_D0 + REG0_4 (insn)]
555 = load_byte ((State.regs[REG_A0 + REG0 (insn)]
556 + State.regs[REG_D0 + REG1 (insn)]));
557 }
558
559 /* movbu (abs16), dn */
560 void OP_340000 (insn, extension)
561 unsigned long insn, extension;
562 {
563 State.regs[REG_D0 + REG0_16 (insn)] = load_byte ((insn & 0xffff));
564 }
565
566 /* movbu (abs32), dn */
567 void OP_FCA80000 (insn, extension)
568 unsigned long insn, extension;
569 {
570 State.regs[REG_D0 + REG0_16 (insn)]
571 = load_byte ((((insn & 0xffff) << 16) + extension));
572 }
573
574 /* movbu dm, (an) */
575 void OP_F050 (insn, extension)
576 unsigned long insn, extension;
577 {
578 store_byte (State.regs[REG_A0 + REG0 (insn)],
579 State.regs[REG_D0 + REG1 (insn)]);
580 }
581
582 /* movbu dm, (d8,an) */
583 void OP_F85000 (insn, extension)
584 unsigned long insn, extension;
585 {
586 store_byte ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
587 State.regs[REG_D0 + REG1_8 (insn)]);
588 }
589
590 /* movbu dm, (d16,an) */
591 void OP_FA500000 (insn, extension)
592 unsigned long insn, extension;
593 {
594 store_byte ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
595 State.regs[REG_D0 + REG1_16 (insn)]);
596 }
597
598 /* movbu dm, (d32,an) */
599 void OP_FC500000 (insn, extension)
600 unsigned long insn, extension;
601 {
602 store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
603 + ((insn & 0xffff) << 16) + extension),
604 State.regs[REG_D0 + REG1_16 (insn)]);
605 }
606
607 /* movbu dm, (d8,sp) */
608 void OP_F89200 (insn, extension)
609 unsigned long insn, extension;
610 {
611 store_byte (State.regs[REG_SP] + (insn & 0xff),
612 State.regs[REG_D0 + REG1_8 (insn)]);
613 }
614
615 /* movbu dm, (d16,sp) */
616 void OP_FA920000 (insn, extension)
617 unsigned long insn, extension;
618 {
619 store_byte (State.regs[REG_SP] + (insn & 0xffff),
620 State.regs[REG_D0 + REG1_16 (insn)]);
621 }
622
623 /* movbu dm (d32,sp) */
624 void OP_FC920000 (insn, extension)
625 unsigned long insn, extension;
626 {
627 store_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
628 State.regs[REG_D0 + REG1_16 (insn)]);
629 }
630
631 /* movbu dm, (di,an) */
632 void OP_F440 (insn, extension)
633 unsigned long insn, extension;
634 {
635 store_byte ((State.regs[REG_A0 + REG0 (insn)]
636 + State.regs[REG_D0 + REG1 (insn)]),
637 State.regs[REG_D0 + REG0_4 (insn)]);
638 }
639
640 /* movbu dm, (abs16) */
641 void OP_20000 (insn, extension)
642 unsigned long insn, extension;
643 {
644 store_byte ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
645 }
646
647 /* movbu dm, (abs32) */
648 void OP_FC820000 (insn, extension)
649 unsigned long insn, extension;
650 {
651 store_byte ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]);
652 }
653
654 /* movhu (am), dn */
655 void OP_F060 (insn, extension)
656 unsigned long insn, extension;
657 {
658 State.regs[REG_D0 + REG1 (insn)]
659 = load_half (State.regs[REG_A0 + REG0 (insn)]);
660 }
661
662 /* movhu (d8,am), dn */
663 void OP_F86000 (insn, extension)
664 unsigned long insn, extension;
665 {
666 State.regs[REG_D0 + REG1_8 (insn)]
667 = load_half ((State.regs[REG_A0 + REG0_8 (insn)]
668 + SEXT8 (insn & 0xff)));
669 }
670
671 /* movhu (d16,am), dn */
672 void OP_FA600000 (insn, extension)
673 unsigned long insn, extension;
674 {
675 State.regs[REG_D0 + REG1_16 (insn)]
676 = load_half ((State.regs[REG_A0 + REG0_16 (insn)]
677 + SEXT16 (insn & 0xffff)));
678 }
679
680 /* movhu (d32,am), dn */
681 void OP_FC600000 (insn, extension)
682 unsigned long insn, extension;
683 {
684 State.regs[REG_D0 + REG1_16 (insn)]
685 = load_half ((State.regs[REG_A0 + REG0_16 (insn)]
686 + ((insn & 0xffff) << 16) + extension));
687 }
688
689 /* movhu (d8,sp) dn */
690 void OP_F8BC00 (insn, extension)
691 unsigned long insn, extension;
692 {
693 State.regs[REG_D0 + REG0_8 (insn)]
694 = load_half ((State.regs[REG_SP] + (insn & 0xff)));
695 }
696
697 /* movhu (d16,sp), dn */
698 void OP_FABC0000 (insn, extension)
699 unsigned long insn, extension;
700 {
701 State.regs[REG_D0 + REG0_16 (insn)]
702 = load_half ((State.regs[REG_SP] + (insn & 0xffff)));
703 }
704
705 /* movhu (d32,sp), dn */
706 void OP_FCBC0000 (insn, extension)
707 unsigned long insn, extension;
708 {
709 State.regs[REG_D0 + REG0_16 (insn)]
710 = load_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
711 }
712
713 /* movhu (di,am), dn */
714 void OP_F480 (insn, extension)
715 unsigned long insn, extension;
716 {
717 State.regs[REG_D0 + REG0_4 (insn)]
718 = load_half ((State.regs[REG_A0 + REG0 (insn)]
719 + State.regs[REG_D0 + REG1 (insn)]));
720 }
721
722 /* movhu (abs16), dn */
723 void OP_380000 (insn, extension)
724 unsigned long insn, extension;
725 {
726 State.regs[REG_D0 + REG0_16 (insn)] = load_half ((insn & 0xffff));
727 }
728
729 /* movhu (abs32), dn */
730 void OP_FCAC0000 (insn, extension)
731 unsigned long insn, extension;
732 {
733 State.regs[REG_D0 + REG0_16 (insn)]
734 = load_half ((((insn & 0xffff) << 16) + extension));
735 }
736
737 /* movhu dm, (an) */
738 void OP_F070 (insn, extension)
739 unsigned long insn, extension;
740 {
741 store_half (State.regs[REG_A0 + REG0 (insn)],
742 State.regs[REG_D0 + REG1 (insn)]);
743 }
744
745 /* movhu dm, (d8,an) */
746 void OP_F87000 (insn, extension)
747 unsigned long insn, extension;
748 {
749 store_half ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
750 State.regs[REG_D0 + REG1_8 (insn)]);
751 }
752
753 /* movhu dm, (d16,an) */
754 void OP_FA700000 (insn, extension)
755 unsigned long insn, extension;
756 {
757 store_half ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
758 State.regs[REG_D0 + REG1_16 (insn)]);
759 }
760
761 /* movhu dm, (d32,an) */
762 void OP_FC700000 (insn, extension)
763 unsigned long insn, extension;
764 {
765 store_half ((State.regs[REG_A0 + REG0_16 (insn)]
766 + ((insn & 0xffff) << 16) + extension),
767 State.regs[REG_D0 + REG1_16 (insn)]);
768 }
769
770 /* movhu dm,(d8,sp) */
771 void OP_F89300 (insn, extension)
772 unsigned long insn, extension;
773 {
774 store_half (State.regs[REG_SP] + (insn & 0xff),
775 State.regs[REG_D0 + REG1_8 (insn)]);
776 }
777
778 /* movhu dm,(d16,sp) */
779 void OP_FA930000 (insn, extension)
780 unsigned long insn, extension;
781 {
782 store_half (State.regs[REG_SP] + (insn & 0xffff),
783 State.regs[REG_D0 + REG1_16 (insn)]);
784 }
785
786 /* movhu dm,(d32,sp) */
787 void OP_FC930000 (insn, extension)
788 unsigned long insn, extension;
789 {
790 store_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
791 State.regs[REG_D0 + REG1_16 (insn)]);
792 }
793
794 /* movhu dm, (di,an) */
795 void OP_F4C0 (insn, extension)
796 unsigned long insn, extension;
797 {
798 store_half ((State.regs[REG_A0 + REG0 (insn)]
799 + State.regs[REG_D0 + REG1 (insn)]),
800 State.regs[REG_D0 + REG0_4 (insn)]);
801 }
802
803 /* movhu dm, (abs16) */
804 void OP_30000 (insn, extension)
805 unsigned long insn, extension;
806 {
807 store_half ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
808 }
809
810 /* movhu dm, (abs32) */
811 void OP_FC830000 (insn, extension)
812 unsigned long insn, extension;
813 {
814 store_half ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]);
815 }
816
817 /* ext dn */
818 void OP_F2D0 (insn, extension)
819 unsigned long insn, extension;
820 {
821 if (State.regs[REG_D0 + REG0 (insn)] & 0x80000000)
822 State.regs[REG_MDR] = -1;
823 else
824 State.regs[REG_MDR] = 0;
825 }
826
827 /* extb dn */
828 void OP_10 (insn, extension)
829 unsigned long insn, extension;
830 {
831 State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]);
832 }
833
834 /* extbu dn */
835 void OP_14 (insn, extension)
836 unsigned long insn, extension;
837 {
838 State.regs[REG_D0 + REG0 (insn)] &= 0xff;
839 }
840
841 /* exth dn */
842 void OP_18 (insn, extension)
843 unsigned long insn, extension;
844 {
845 State.regs[REG_D0 + REG0 (insn)]
846 = SEXT16 (State.regs[REG_D0 + REG0 (insn)]);
847 }
848
849 /* exthu dn */
850 void OP_1C (insn, extension)
851 unsigned long insn, extension;
852 {
853 State.regs[REG_D0 + REG0 (insn)] &= 0xffff;
854 }
855
856 /* movm (sp), reg_list */
857 void OP_CE00 (insn, extension)
858 unsigned long insn, extension;
859 {
860 unsigned long sp = State.regs[REG_SP];
861 unsigned long mask;
862
863 mask = insn & 0xff;
864
865 if (mask & 0x8)
866 {
867 sp += 4;
868 State.regs[REG_LAR] = load_word (sp);
869 sp += 4;
870 State.regs[REG_LIR] = load_word (sp);
871 sp += 4;
872 State.regs[REG_MDR] = load_word (sp);
873 sp += 4;
874 State.regs[REG_A0 + 1] = load_word (sp);
875 sp += 4;
876 State.regs[REG_A0] = load_word (sp);
877 sp += 4;
878 State.regs[REG_D0 + 1] = load_word (sp);
879 sp += 4;
880 State.regs[REG_D0] = load_word (sp);
881 sp += 4;
882 }
883
884 if (mask & 0x10)
885 {
886 State.regs[REG_A0 + 3] = load_word (sp);
887 sp += 4;
888 }
889
890 if (mask & 0x20)
891 {
892 State.regs[REG_A0 + 2] = load_word (sp);
893 sp += 4;
894 }
895
896 if (mask & 0x40)
897 {
898 State.regs[REG_D0 + 3] = load_word (sp);
899 sp += 4;
900 }
901
902 if (mask & 0x80)
903 {
904 State.regs[REG_D0 + 2] = load_word (sp);
905 sp += 4;
906 }
907
908 /* And make sure to update the stack pointer. */
909 State.regs[REG_SP] = sp;
910 }
911
912 /* movm reg_list, (sp) */
913 void OP_CF00 (insn, extension)
914 unsigned long insn, extension;
915 {
916 unsigned long sp = State.regs[REG_SP];
917 unsigned long mask;
918
919 mask = insn & 0xff;
920
921 if (mask & 0x80)
922 {
923 sp -= 4;
924 store_word (sp, State.regs[REG_D0 + 2]);
925 }
926
927 if (mask & 0x40)
928 {
929 sp -= 4;
930 store_word (sp, State.regs[REG_D0 + 3]);
931 }
932
933 if (mask & 0x20)
934 {
935 sp -= 4;
936 store_word (sp, State.regs[REG_A0 + 2]);
937 }
938
939 if (mask & 0x10)
940 {
941 sp -= 4;
942 store_word (sp, State.regs[REG_A0 + 3]);
943 }
944
945 if (mask & 0x8)
946 {
947 sp -= 4;
948 store_word (sp, State.regs[REG_D0]);
949 sp -= 4;
950 store_word (sp, State.regs[REG_D0 + 1]);
951 sp -= 4;
952 store_word (sp, State.regs[REG_A0]);
953 sp -= 4;
954 store_word (sp, State.regs[REG_A0 + 1]);
955 sp -= 4;
956 store_word (sp, State.regs[REG_MDR]);
957 sp -= 4;
958 store_word (sp, State.regs[REG_LIR]);
959 sp -= 4;
960 store_word (sp, State.regs[REG_LAR]);
961 sp -= 4;
962 }
963
964 /* And make sure to update the stack pointer. */
965 State.regs[REG_SP] = sp;
966 }
967
968 /* clr dn */
969 void OP_0 (insn, extension)
970 unsigned long insn, extension;
971 {
972 State.regs[REG_D0 + REG1 (insn)] = 0;
973
974 PSW |= PSW_Z;
975 PSW &= ~(PSW_V | PSW_C | PSW_N);
976 }
977
978 /* add dm,dn */
979 void OP_E0 (insn, extension)
980 unsigned long insn, extension;
981 {
982 int z, c, n, v;
983 unsigned long reg1, reg2, value;
984
985 reg1 = State.regs[REG_D0 + REG1 (insn)];
986 reg2 = State.regs[REG_D0 + REG0 (insn)];
987 value = reg1 + reg2;
988 State.regs[REG_D0 + REG0 (insn)] = value;
989
990 z = (value == 0);
991 n = (value & 0x80000000);
992 c = (value < reg1) || (value < reg2);
993 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
994 && (reg2 & 0x80000000) != (value & 0x80000000));
995
996 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
997 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
998 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
999 }
1000
1001 /* add dm, an */
1002 void OP_F160 (insn, extension)
1003 unsigned long insn, extension;
1004 {
1005 int z, c, n, v;
1006 unsigned long reg1, reg2, value;
1007
1008 reg1 = State.regs[REG_D0 + REG1 (insn)];
1009 reg2 = State.regs[REG_A0 + REG0 (insn)];
1010 value = reg1 + reg2;
1011 State.regs[REG_A0 + REG0 (insn)] = value;
1012
1013 z = (value == 0);
1014 n = (value & 0x80000000);
1015 c = (value < reg1) || (value < reg2);
1016 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1017 && (reg2 & 0x80000000) != (value & 0x80000000));
1018
1019 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1020 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1021 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1022 }
1023
1024 /* add am, dn */
1025 void OP_F150 (insn, extension)
1026 unsigned long insn, extension;
1027 {
1028 int z, c, n, v;
1029 unsigned long reg1, reg2, value;
1030
1031 reg1 = State.regs[REG_A0 + REG1 (insn)];
1032 reg2 = State.regs[REG_D0 + REG0 (insn)];
1033 value = reg1 + reg2;
1034 State.regs[REG_D0 + REG0 (insn)] = value;
1035
1036 z = (value == 0);
1037 n = (value & 0x80000000);
1038 c = (value < reg1) || (value < reg2);
1039 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1040 && (reg2 & 0x80000000) != (value & 0x80000000));
1041
1042 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1043 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1044 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1045 }
1046
1047 /* add am,an */
1048 void OP_F170 (insn, extension)
1049 unsigned long insn, extension;
1050 {
1051 int z, c, n, v;
1052 unsigned long reg1, reg2, value;
1053
1054 reg1 = State.regs[REG_A0 + REG1 (insn)];
1055 reg2 = State.regs[REG_A0 + REG0 (insn)];
1056 value = reg1 + reg2;
1057 State.regs[REG_A0 + REG0 (insn)] = value;
1058
1059 z = (value == 0);
1060 n = (value & 0x80000000);
1061 c = (value < reg1) || (value < reg2);
1062 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1063 && (reg2 & 0x80000000) != (value & 0x80000000));
1064
1065 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1066 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1067 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1068 }
1069
1070 /* add imm8, dn */
1071 void OP_2800 (insn, extension)
1072 unsigned long insn, extension;
1073 {
1074 int z, c, n, v;
1075 unsigned long reg1, imm, value;
1076
1077 reg1 = State.regs[REG_D0 + REG0_8 (insn)];
1078 imm = SEXT8 (insn & 0xff);
1079 value = reg1 + imm;
1080 State.regs[REG_D0 + REG0_8 (insn)] = value;
1081
1082 z = (value == 0);
1083 n = (value & 0x80000000);
1084 c = (value < reg1) || (value < imm);
1085 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1086 && (reg1 & 0x80000000) != (value & 0x80000000));
1087
1088 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1089 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1090 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1091 }
1092
1093 /* add imm16, dn */
1094 void OP_FAC00000 (insn, extension)
1095 unsigned long insn, extension;
1096 {
1097 int z, c, n, v;
1098 unsigned long reg1, imm, value;
1099
1100 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1101 imm = SEXT16 (insn & 0xffff);
1102 value = reg1 + imm;
1103 State.regs[REG_D0 + REG0_16 (insn)] = value;
1104
1105 z = (value == 0);
1106 n = (value & 0x80000000);
1107 c = (value < reg1) || (value < imm);
1108 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1109 && (reg1 & 0x80000000) != (value & 0x80000000));
1110
1111 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1112 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1113 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1114 }
1115
1116 /* add imm32,dn */
1117 void OP_FCC00000 (insn, extension)
1118 unsigned long insn, extension;
1119 {
1120 int z, c, n, v;
1121 unsigned long reg1, imm, value;
1122
1123 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1124 imm = ((insn & 0xffff) << 16) + extension;
1125 value = reg1 + imm;
1126 State.regs[REG_D0 + REG0_16 (insn)] = value;
1127
1128 z = (value == 0);
1129 n = (value & 0x80000000);
1130 c = (value < reg1) || (value < imm);
1131 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1132 && (reg1 & 0x80000000) != (value & 0x80000000));
1133
1134 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1135 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1136 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1137 }
1138
1139 /* add imm8, an */
1140 void OP_2000 (insn, extension)
1141 unsigned long insn, extension;
1142 {
1143 int z, c, n, v;
1144 unsigned long reg1, imm, value;
1145
1146 reg1 = State.regs[REG_A0 + REG0_8 (insn)];
1147 imm = SEXT8 (insn & 0xff);
1148 value = reg1 + imm;
1149 State.regs[REG_A0 + REG0_8 (insn)] = value;
1150
1151 z = (value == 0);
1152 n = (value & 0x80000000);
1153 c = (value < reg1) || (value < imm);
1154 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1155 && (reg1 & 0x80000000) != (value & 0x80000000));
1156
1157 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1158 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1159 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1160 }
1161
1162 /* add imm16, an */
1163 void OP_FAD00000 (insn, extension)
1164 unsigned long insn, extension;
1165 {
1166 int z, c, n, v;
1167 unsigned long reg1, imm, value;
1168
1169 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1170 imm = SEXT16 (insn & 0xffff);
1171 value = reg1 + imm;
1172 State.regs[REG_A0 + REG0_16 (insn)] = value;
1173
1174 z = (value == 0);
1175 n = (value & 0x80000000);
1176 c = (value < reg1) || (value < imm);
1177 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1178 && (reg1 & 0x80000000) != (value & 0x80000000));
1179
1180 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1181 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1182 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1183 }
1184
1185 /* add imm32, an */
1186 void OP_FCD00000 (insn, extension)
1187 unsigned long insn, extension;
1188 {
1189 int z, c, n, v;
1190 unsigned long reg1, imm, value;
1191
1192 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1193 imm = ((insn & 0xffff) << 16) + extension;
1194 value = reg1 + imm;
1195 State.regs[REG_A0 + REG0_16 (insn)] = value;
1196
1197 z = (value == 0);
1198 n = (value & 0x80000000);
1199 c = (value < reg1) || (value < imm);
1200 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1201 && (reg1 & 0x80000000) != (value & 0x80000000));
1202
1203 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1204 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1205 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1206 }
1207
1208 /* add imm8, sp */
1209 void OP_F8FE00 (insn, extension)
1210 unsigned long insn, extension;
1211 {
1212 unsigned long reg1, imm, value;
1213
1214 reg1 = State.regs[REG_SP];
1215 imm = SEXT8 (insn & 0xff);
1216 value = reg1 + imm;
1217 State.regs[REG_SP] = value;
1218 }
1219
1220 /* add imm16,sp */
1221 void OP_FAFE0000 (insn, extension)
1222 unsigned long insn, extension;
1223 {
1224 unsigned long reg1, imm, value;
1225
1226 reg1 = State.regs[REG_SP];
1227 imm = SEXT16 (insn & 0xffff);
1228 value = reg1 + imm;
1229 State.regs[REG_SP] = value;
1230 }
1231
1232 /* add imm32, sp */
1233 void OP_FCFE0000 (insn, extension)
1234 unsigned long insn, extension;
1235 {
1236 unsigned long reg1, imm, value;
1237
1238 reg1 = State.regs[REG_SP];
1239 imm = ((insn & 0xffff) << 16) + extension;
1240 value = reg1 + imm;
1241 State.regs[REG_SP] = value;
1242 }
1243
1244 /* addc dm,dn */
1245 void OP_F140 (insn, extension)
1246 unsigned long insn, extension;
1247 {
1248 int z, c, n, v;
1249 unsigned long reg1, reg2, value;
1250
1251 reg1 = State.regs[REG_D0 + REG1 (insn)];
1252 reg2 = State.regs[REG_D0 + REG0 (insn)];
1253 value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1254 State.regs[REG_D0 + REG0 (insn)] = value;
1255
1256 z = (value == 0);
1257 n = (value & 0x80000000);
1258 c = (value < reg1) || (value < reg2);
1259 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1260 && (reg2 & 0x80000000) != (value & 0x80000000));
1261
1262 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1263 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1264 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1265 }
1266
1267 /* sub dm, dn */
1268 void OP_F100 (insn, extension)
1269 unsigned long insn, extension;
1270 {
1271 int z, c, n, v;
1272 unsigned long reg1, reg2, value;
1273
1274 reg1 = State.regs[REG_D0 + REG1 (insn)];
1275 reg2 = State.regs[REG_D0 + REG0 (insn)];
1276 value = reg2 - reg1;
1277 State.regs[REG_D0 + REG0 (insn)] = value;
1278
1279 z = (value == 0);
1280 n = (value & 0x80000000);
1281 c = (reg1 > reg2);
1282 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1283 && (reg2 & 0x80000000) != (value & 0x80000000));
1284
1285 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1286 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1287 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1288 }
1289
1290 /* sub dm, an */
1291 void OP_F120 (insn, extension)
1292 unsigned long insn, extension;
1293 {
1294 int z, c, n, v;
1295 unsigned long reg1, reg2, value;
1296
1297 reg1 = State.regs[REG_D0 + REG1 (insn)];
1298 reg2 = State.regs[REG_A0 + REG0 (insn)];
1299 value = reg2 - reg1;
1300 State.regs[REG_A0 + REG0 (insn)] = value;
1301
1302 z = (value == 0);
1303 n = (value & 0x80000000);
1304 c = (reg1 > reg2);
1305 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1306 && (reg2 & 0x80000000) != (value & 0x80000000));
1307
1308 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1309 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1310 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1311 }
1312
1313 /* sub am, dn */
1314 void OP_F110 (insn, extension)
1315 unsigned long insn, extension;
1316 {
1317 int z, c, n, v;
1318 unsigned long reg1, reg2, value;
1319
1320 reg1 = State.regs[REG_A0 + REG1 (insn)];
1321 reg2 = State.regs[REG_D0 + REG0 (insn)];
1322 value = reg2 - reg1;
1323 State.regs[REG_D0 + REG0 (insn)] = value;
1324
1325 z = (value == 0);
1326 n = (value & 0x80000000);
1327 c = (reg1 > reg2);
1328 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1329 && (reg2 & 0x80000000) != (value & 0x80000000));
1330
1331 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1332 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1333 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1334 }
1335
1336 /* sub am, an */
1337 void OP_F130 (insn, extension)
1338 unsigned long insn, extension;
1339 {
1340 int z, c, n, v;
1341 unsigned long reg1, reg2, value;
1342
1343 reg1 = State.regs[REG_A0 + REG1 (insn)];
1344 reg2 = State.regs[REG_A0 + REG0 (insn)];
1345 value = reg2 - reg1;
1346 State.regs[REG_A0 + REG0 (insn)] = value;
1347
1348 z = (value == 0);
1349 n = (value & 0x80000000);
1350 c = (reg1 > reg2);
1351 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1352 && (reg2 & 0x80000000) != (value & 0x80000000));
1353
1354 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1355 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1356 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1357 }
1358
1359 /* sub imm32, dn */
1360 void OP_FCC40000 (insn, extension)
1361 unsigned long insn, extension;
1362 {
1363 int z, c, n, v;
1364 unsigned long reg1, imm, value;
1365
1366 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1367 imm = ((insn & 0xffff) << 16) + extension;
1368 value = reg1 - imm;
1369 State.regs[REG_D0 + REG0_16 (insn)] = value;
1370
1371 z = (value == 0);
1372 n = (value & 0x80000000);
1373 c = (reg1 < imm);
1374 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1375 && (reg1 & 0x80000000) != (value & 0x80000000));
1376
1377 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1378 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1379 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1380 }
1381
1382 /* sub imm32, an */
1383 void OP_FCD40000 (insn, extension)
1384 unsigned long insn, extension;
1385 {
1386 int z, c, n, v;
1387 unsigned long reg1, imm, value;
1388
1389 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1390 imm = ((insn & 0xffff) << 16) + extension;
1391 value = reg1 - imm;
1392 State.regs[REG_A0 + REG0_16 (insn)] = value;
1393
1394 z = (value == 0);
1395 n = (value & 0x80000000);
1396 c = (reg1 < imm);
1397 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1398 && (reg1 & 0x80000000) != (value & 0x80000000));
1399
1400 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1401 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1402 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1403 }
1404
1405 /* subc dm, dn */
1406 void OP_F180 (insn, extension)
1407 unsigned long insn, extension;
1408 {
1409 int z, c, n, v;
1410 unsigned long reg1, reg2, value;
1411
1412 reg1 = State.regs[REG_D0 + REG1 (insn)];
1413 reg2 = State.regs[REG_D0 + REG0 (insn)];
1414 value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1415 State.regs[REG_D0 + REG0 (insn)] = value;
1416
1417 z = (value == 0);
1418 n = (value & 0x80000000);
1419 c = (reg1 > reg2);
1420 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1421 && (reg2 & 0x80000000) != (value & 0x80000000));
1422
1423 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1424 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1425 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1426 }
1427
1428 /* mul dm, dn */
1429 void OP_F240 (insn, extension)
1430 unsigned long insn, extension;
1431 {
1432 unsigned long long temp;
1433 int n, z;
1434
1435 temp = ((signed64)State.regs[REG_D0 + REG0 (insn)]
1436 * (signed64)State.regs[REG_D0 + REG1 (insn)]);
1437 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1438 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1439 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1440 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1441 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1442 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1443 }
1444
1445 /* mulu dm, dn */
1446 void OP_F250 (insn, extension)
1447 unsigned long insn, extension;
1448 {
1449 unsigned long long temp;
1450 int n, z;
1451
1452 temp = ((unsigned64)State.regs[REG_D0 + REG0 (insn)]
1453 * (unsigned64)State.regs[REG_D0 + REG1 (insn)]);
1454 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1455 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1456 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1457 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1458 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1459 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1460 }
1461
1462 /* div dm, dn */
1463 void OP_F260 (insn, extension)
1464 unsigned long insn, extension;
1465 {
1466 long long temp;
1467 int n, z;
1468
1469 temp = State.regs[REG_MDR];
1470 temp <<= 32;
1471 temp |= State.regs[REG_D0 + REG0 (insn)];
1472 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + REG1 (insn)];
1473 temp /= (long)State.regs[REG_D0 + REG1 (insn)];
1474 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1475 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1476 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1477 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1478 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1479 }
1480
1481 /* divu dm, dn */
1482 void OP_F270 (insn, extension)
1483 unsigned long insn, extension;
1484 {
1485 unsigned long long temp;
1486 int n, z;
1487
1488 temp = State.regs[REG_MDR];
1489 temp <<= 32;
1490 temp |= State.regs[REG_D0 + REG0 (insn)];
1491 State.regs[REG_MDR] = temp % State.regs[REG_D0 + REG1 (insn)];
1492 temp /= State.regs[REG_D0 + REG1 (insn)];
1493 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1494 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1495 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1496 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1497 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1498 }
1499
1500 /* inc dn */
1501 void OP_40 (insn, extension)
1502 unsigned long insn, extension;
1503 {
1504 int z,n,c,v;
1505 unsigned int value, imm, reg1;
1506
1507 reg1 = State.regs[REG_D0 + REG1 (insn)];
1508 imm = 1;
1509 value = reg1 + imm;
1510 State.regs[REG_D0 + REG1 (insn)] = value;
1511
1512 z = (value == 0);
1513 n = (value & 0x80000000);
1514 c = (reg1 < imm);
1515 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1516 && (reg1 & 0x80000000) != (value & 0x80000000));
1517
1518 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1519 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1520 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1521 }
1522
1523 /* inc an */
1524 void OP_41 (insn, extension)
1525 unsigned long insn, extension;
1526 {
1527 State.regs[REG_A0 + REG1 (insn)] += 1;
1528 }
1529
1530 /* inc4 an */
1531 void OP_50 (insn, extension)
1532 unsigned long insn, extension;
1533 {
1534 State.regs[REG_A0 + REG0 (insn)] += 4;
1535 }
1536
1537 /* cmp imm8, dn */
1538 void OP_A000 (insn, extension)
1539 unsigned long insn, extension;
1540 {
1541 int z, c, n, v;
1542 unsigned long reg1, imm, value;
1543
1544 reg1 = State.regs[REG_D0 + REG0_8 (insn)];
1545 imm = SEXT8 (insn & 0xff);
1546 value = reg1 - imm;
1547
1548 z = (value == 0);
1549 n = (value & 0x80000000);
1550 c = (reg1 < imm);
1551 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1552 && (reg1 & 0x80000000) != (value & 0x80000000));
1553
1554 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1555 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1556 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1557 }
1558
1559 /* cmp dm, dn */
1560 void OP_A0 (insn, extension)
1561 unsigned long insn, extension;
1562 {
1563 int z, c, n, v;
1564 unsigned long reg1, reg2, value;
1565
1566 reg1 = State.regs[REG_D0 + REG1 (insn)];
1567 reg2 = State.regs[REG_D0 + REG0 (insn)];
1568 value = reg2 - reg1;
1569
1570 z = (value == 0);
1571 n = (value & 0x80000000);
1572 c = (reg1 > reg2);
1573 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1574 && (reg2 & 0x80000000) != (value & 0x80000000));
1575
1576 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1577 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1578 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1579 }
1580
1581 /* cmp dm, an */
1582 void OP_F1A0 (insn, extension)
1583 unsigned long insn, extension;
1584 {
1585 int z, c, n, v;
1586 unsigned long reg1, reg2, value;
1587
1588 reg1 = State.regs[REG_D0 + REG1 (insn)];
1589 reg2 = State.regs[REG_A0 + REG0 (insn)];
1590 value = reg2 - reg1;
1591
1592 z = (value == 0);
1593 n = (value & 0x80000000);
1594 c = (reg1 > reg2);
1595 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1596 && (reg2 & 0x80000000) != (value & 0x80000000));
1597
1598 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1599 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1600 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1601 }
1602
1603 /* cmp am, dn */
1604 void OP_F190 (insn, extension)
1605 unsigned long insn, extension;
1606 {
1607 int z, c, n, v;
1608 unsigned long reg1, reg2, value;
1609
1610 reg1 = State.regs[REG_A0 + REG1 (insn)];
1611 reg2 = State.regs[REG_D0 + REG0 (insn)];
1612 value = reg2 - reg1;
1613
1614 z = (value == 0);
1615 n = (value & 0x80000000);
1616 c = (reg1 > reg2);
1617 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1618 && (reg2 & 0x80000000) != (value & 0x80000000));
1619
1620 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1621 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1622 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1623 }
1624
1625 /* cmp imm8, an */
1626 void OP_B000 (insn, extension)
1627 unsigned long insn, extension;
1628 {
1629 int z, c, n, v;
1630 unsigned long reg1, imm, value;
1631
1632 reg1 = State.regs[REG_A0 + REG0_8 (insn)];
1633 imm = insn & 0xff;
1634 value = reg1 - imm;
1635
1636 z = (value == 0);
1637 n = (value & 0x80000000);
1638 c = (reg1 < imm);
1639 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1640 && (reg1 & 0x80000000) != (value & 0x80000000));
1641
1642 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1643 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1644 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1645 }
1646
1647 /* cmp am, an */
1648 void OP_B0 (insn, extension)
1649 unsigned long insn, extension;
1650 {
1651 int z, c, n, v;
1652 unsigned long reg1, reg2, value;
1653
1654 reg1 = State.regs[REG_A0 + REG1 (insn)];
1655 reg2 = State.regs[REG_A0 + REG0 (insn)];
1656 value = reg2 - reg1;
1657
1658 z = (value == 0);
1659 n = (value & 0x80000000);
1660 c = (reg1 > reg2);
1661 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1662 && (reg2 & 0x80000000) != (value & 0x80000000));
1663
1664 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1665 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1666 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1667 }
1668
1669 /* cmp imm16, dn */
1670 void OP_FAC80000 (insn, extension)
1671 unsigned long insn, extension;
1672 {
1673 int z, c, n, v;
1674 unsigned long reg1, imm, value;
1675
1676 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1677 imm = SEXT16 (insn & 0xffff);
1678 value = reg1 - imm;
1679
1680 z = (value == 0);
1681 n = (value & 0x80000000);
1682 c = (reg1 < imm);
1683 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1684 && (reg1 & 0x80000000) != (value & 0x80000000));
1685
1686 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1687 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1688 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1689 }
1690
1691 /* cmp imm32, dn */
1692 void OP_FCC80000 (insn, extension)
1693 unsigned long insn, extension;
1694 {
1695 int z, c, n, v;
1696 unsigned long reg1, imm, value;
1697
1698 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1699 imm = ((insn & 0xffff) << 16) + extension;
1700 value = reg1 - imm;
1701
1702 z = (value == 0);
1703 n = (value & 0x80000000);
1704 c = (reg1 < imm);
1705 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1706 && (reg1 & 0x80000000) != (value & 0x80000000));
1707
1708 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1709 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1710 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1711 }
1712
1713 /* cmp imm16, an */
1714 void OP_FAD80000 (insn, extension)
1715 unsigned long insn, extension;
1716 {
1717 int z, c, n, v;
1718 unsigned long reg1, imm, value;
1719
1720 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1721 imm = insn & 0xffff;
1722 value = reg1 - imm;
1723
1724 z = (value == 0);
1725 n = (value & 0x80000000);
1726 c = (reg1 < imm);
1727 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1728 && (reg1 & 0x80000000) != (value & 0x80000000));
1729
1730 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1731 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1732 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1733 }
1734
1735 /* cmp imm32, an */
1736 void OP_FCD80000 (insn, extension)
1737 unsigned long insn, extension;
1738 {
1739 int z, c, n, v;
1740 unsigned long reg1, imm, value;
1741
1742 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1743 imm = ((insn & 0xffff) << 16) + extension;
1744 value = reg1 - imm;
1745
1746 z = (value == 0);
1747 n = (value & 0x80000000);
1748 c = (reg1 < imm);
1749 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1750 && (reg1 & 0x80000000) != (value & 0x80000000));
1751
1752 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1753 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1754 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1755 }
1756
1757 /* and dm, dn */
1758 void OP_F200 (insn, extension)
1759 unsigned long insn, extension;
1760 {
1761 int n, z;
1762
1763 State.regs[REG_D0 + REG0 (insn)] &= State.regs[REG_D0 + REG1 (insn)];
1764 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1765 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1766 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1767 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1768 }
1769
1770 /* and imm8, dn */
1771 void OP_F8E000 (insn, extension)
1772 unsigned long insn, extension;
1773 {
1774 int n, z;
1775
1776 State.regs[REG_D0 + REG0_8 (insn)] &= (insn & 0xff);
1777 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
1778 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
1779 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1780 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1781 }
1782
1783 /* and imm16, dn */
1784 void OP_FAE00000 (insn, extension)
1785 unsigned long insn, extension;
1786 {
1787 int n, z;
1788
1789 State.regs[REG_D0 + REG0_16 (insn)] &= (insn & 0xffff);
1790 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1791 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1792 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1793 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1794 }
1795
1796 /* and imm32, dn */
1797 void OP_FCE00000 (insn, extension)
1798 unsigned long insn, extension;
1799 {
1800 int n, z;
1801
1802 State.regs[REG_D0 + REG0_16 (insn)]
1803 &= ((insn & 0xffff) << 16) + extension;
1804 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1805 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1806 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1807 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1808 }
1809
1810 /* and imm16, psw */
1811 void OP_FAFC0000 (insn, extension)
1812 unsigned long insn, extension;
1813 {
1814 PSW &= (insn & 0xffff);
1815 }
1816
1817 /* or dm, dn*/
1818 void OP_F210 (insn, extension)
1819 unsigned long insn, extension;
1820 {
1821 int n, z;
1822
1823 State.regs[REG_D0 + REG0 (insn)] |= State.regs[REG_D0 + REG1 (insn)];
1824 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1825 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1826 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1827 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1828 }
1829
1830 /* or imm8, dn */
1831 void OP_F8E400 (insn, extension)
1832 unsigned long insn, extension;
1833 {
1834 int n, z;
1835
1836 State.regs[REG_D0 + REG0_8 (insn)] |= insn & 0xff;
1837 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
1838 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
1839 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1840 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1841 }
1842
1843 /* or imm16, dn*/
1844 void OP_FAE40000 (insn, extension)
1845 unsigned long insn, extension;
1846 {
1847 int n, z;
1848
1849 State.regs[REG_D0 + REG0_16 (insn)] |= insn & 0xffff;
1850 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1851 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1852 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1853 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1854 }
1855
1856 /* or imm32, dn */
1857 void OP_FCE40000 (insn, extension)
1858 unsigned long insn, extension;
1859 {
1860 int n, z;
1861
1862 State.regs[REG_D0 + REG0_16 (insn)]
1863 |= ((insn & 0xffff) << 16) + extension;
1864 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1865 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1866 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1867 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1868 }
1869
1870 /* or imm16,psw */
1871 void OP_FAFD0000 (insn, extension)
1872 unsigned long insn, extension;
1873 {
1874 PSW |= (insn & 0xffff);
1875 }
1876
1877 /* xor dm, dn */
1878 void OP_F220 (insn, extension)
1879 unsigned long insn, extension;
1880 {
1881 int n, z;
1882
1883 State.regs[REG_D0 + REG0 (insn)] ^= State.regs[REG_D0 + REG1 (insn)];
1884 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1885 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1886 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1887 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1888 }
1889
1890 /* xor imm16, dn */
1891 void OP_FAE80000 (insn, extension)
1892 unsigned long insn, extension;
1893 {
1894 int n, z;
1895
1896 State.regs[REG_D0 + REG0_16 (insn)] ^= insn & 0xffff;
1897 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1898 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1899 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1900 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1901 }
1902
1903 /* xor imm32, dn */
1904 void OP_FCE80000 (insn, extension)
1905 unsigned long insn, extension;
1906 {
1907 int n, z;
1908
1909 State.regs[REG_D0 + REG0_16 (insn)]
1910 ^= ((insn & 0xffff) << 16) + extension;
1911 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1912 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1913 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1914 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1915 }
1916
1917 /* not dn */
1918 void OP_F230 (insn, extension)
1919 unsigned long insn, extension;
1920 {
1921 int n, z;
1922
1923 State.regs[REG_D0 + REG0 (insn)] = ~State.regs[REG_D0 + REG0 (insn)];
1924 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1925 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1926 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1927 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1928 }
1929
1930 /* btst imm8, dn */
1931 void OP_F8EC00 (insn, extension)
1932 unsigned long insn, extension;
1933 {
1934 unsigned long temp;
1935 int z, n;
1936
1937 temp = State.regs[REG_D0 + REG0_8 (insn)];
1938 temp &= (insn & 0xff);
1939 n = (temp & 0x80000000) != 0;
1940 z = (temp == 0);
1941 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1942 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1943 }
1944
1945 /* btst imm16, dn */
1946 void OP_FAEC0000 (insn, extension)
1947 unsigned long insn, extension;
1948 {
1949 unsigned long temp;
1950 int z, n;
1951
1952 temp = State.regs[REG_D0 + REG0_16 (insn)];
1953 temp &= (insn & 0xffff);
1954 n = (temp & 0x80000000) != 0;
1955 z = (temp == 0);
1956 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1957 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1958 }
1959
1960 /* btst imm32, dn */
1961 void OP_FCEC0000 (insn, extension)
1962 unsigned long insn, extension;
1963 {
1964 unsigned long temp;
1965 int z, n;
1966
1967 temp = State.regs[REG_D0 + REG0_16 (insn)];
1968 temp &= ((insn & 0xffff) << 16) + extension;
1969 n = (temp & 0x80000000) != 0;
1970 z = (temp == 0);
1971 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1972 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1973 }
1974
1975 /* btst imm8,(abs32) */
1976 void OP_FE020000 (insn, extension)
1977 unsigned long insn, extension;
1978 {
1979 unsigned long temp;
1980 int n, z;
1981
1982 temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8));
1983 temp &= (extension & 0xff);
1984 n = (temp & 0x80000000) != 0;
1985 z = (temp == 0);
1986 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1987 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1988 }
1989
1990 /* btst imm8,(d8,an) */
1991 void OP_FAF80000 (insn, extension)
1992 unsigned long insn, extension;
1993 {
1994 unsigned long temp;
1995 int n, z;
1996
1997 temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
1998 + SEXT8 ((insn & 0xff00) >> 8)));
1999 temp &= (insn & 0xff);
2000 n = (temp & 0x80000000) != 0;
2001 z = (temp == 0);
2002 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2003 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2004 }
2005
2006 /* bset dm, (an) */
2007 void OP_F080 (insn, extension)
2008 unsigned long insn, extension;
2009 {
2010 unsigned long temp;
2011 int z;
2012
2013 temp = load_byte (State.regs[REG_A0 + REG0 (insn)]);
2014 z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
2015 temp |= State.regs[REG_D0 + REG1 (insn)];
2016 store_byte (State.regs[REG_A0 + REG0 (insn)], temp);
2017 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2018 PSW |= (z ? PSW_Z : 0);
2019 }
2020
2021 /* bset imm8, (abs32) */
2022 void OP_FE000000 (insn, extension)
2023 unsigned long insn, extension;
2024 {
2025 unsigned long temp;
2026 int z;
2027
2028 temp = load_byte (((insn & 0xffff) << 16 | (extension >> 8)));
2029 z = (temp & (extension & 0xff)) == 0;
2030 temp |= (extension & 0xff);
2031 store_byte ((((insn & 0xffff) << 16) | (extension >> 8)), temp);
2032 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2033 PSW |= (z ? PSW_Z : 0);
2034 }
2035
2036 /* bset imm8,(d8,an) */
2037 void OP_FAF00000 (insn, extension)
2038 unsigned long insn, extension;
2039 {
2040 unsigned long temp;
2041 int z;
2042
2043 temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
2044 + SEXT8 ((insn & 0xff00) >> 8)));
2045 z = (temp & (insn & 0xff)) == 0;
2046 temp |= (insn & 0xff);
2047 store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
2048 + SEXT8 ((insn & 0xff00) >> 8)), temp);
2049 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2050 PSW |= (z ? PSW_Z : 0);
2051 }
2052
2053 /* bclr dm, (an) */
2054 void OP_F090 (insn, extension)
2055 unsigned long insn, extension;
2056 {
2057 unsigned long temp;
2058 int z;
2059
2060 temp = load_byte (State.regs[REG_A0 + REG0 (insn)]);
2061 z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
2062 temp = temp & ~State.regs[REG_D0 + REG1 (insn)];
2063 store_byte (State.regs[REG_A0 + REG0 (insn)], temp);
2064 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2065 PSW |= (z ? PSW_Z : 0);
2066 }
2067
2068 /* bclr imm8, (abs32) */
2069 void OP_FE010000 (insn, extension)
2070 unsigned long insn, extension;
2071 {
2072 unsigned long temp;
2073 int z;
2074
2075 temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8));
2076 z = (temp & (extension & 0xff)) == 0;
2077 temp = temp & ~(extension & 0xff);
2078 store_byte (((insn & 0xffff) << 16) | (extension >> 8), temp);
2079 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2080 PSW |= (z ? PSW_Z : 0);
2081 }
2082
2083 /* bclr imm8,(d8,an) */
2084 void OP_FAF40000 (insn, extension)
2085 unsigned long insn, extension;
2086 {
2087 unsigned long temp;
2088 int z;
2089
2090 temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
2091 + SEXT8 ((insn & 0xff00) >> 8)));
2092 z = (temp & (insn & 0xff)) == 0;
2093 temp = temp & ~(insn & 0xff);
2094 store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
2095 + SEXT8 ((insn & 0xff00) >> 8)), temp);
2096 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2097 PSW |= (z ? PSW_Z : 0);
2098 }
2099
2100 /* asr dm, dn */
2101 void OP_F2B0 (insn, extension)
2102 unsigned long insn, extension;
2103 {
2104 long temp;
2105 int z, n, c;
2106
2107 temp = State.regs[REG_D0 + REG0 (insn)];
2108 c = temp & 1;
2109 temp >>= State.regs[REG_D0 + REG1 (insn)];
2110 State.regs[REG_D0 + REG0 (insn)] = temp;
2111 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2112 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2113 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2114 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2115 }
2116
2117 /* asr imm8, dn */
2118 void OP_F8C800 (insn, extension)
2119 unsigned long insn, extension;
2120 {
2121 long temp;
2122 int z, n, c;
2123
2124 temp = State.regs[REG_D0 + REG0_8 (insn)];
2125 c = temp & 1;
2126 temp >>= (insn & 0xff);
2127 State.regs[REG_D0 + REG0_8 (insn)] = temp;
2128 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2129 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2130 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2131 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2132 }
2133
2134 /* lsr dm, dn */
2135 void OP_F2A0 (insn, extension)
2136 unsigned long insn, extension;
2137 {
2138 int z, n, c;
2139
2140 c = State.regs[REG_D0 + REG0 (insn)] & 1;
2141 State.regs[REG_D0 + REG0 (insn)]
2142 >>= State.regs[REG_D0 + REG1 (insn)];
2143 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2144 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2145 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2146 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2147 }
2148
2149 /* lsr imm8, dn */
2150 void OP_F8C400 (insn, extension)
2151 unsigned long insn, extension;
2152 {
2153 int z, n, c;
2154
2155 c = State.regs[REG_D0 + REG0_8 (insn)] & 1;
2156 State.regs[REG_D0 + REG0_8 (insn)] >>= (insn & 0xff);
2157 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2158 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2159 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2160 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2161 }
2162
2163 /* asl dm, dn */
2164 void OP_F290 (insn, extension)
2165 unsigned long insn, extension;
2166 {
2167 int n, z;
2168
2169 State.regs[REG_D0 + REG0 (insn)]
2170 <<= State.regs[REG_D0 + REG1 (insn)];
2171 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2172 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2173 PSW &= ~(PSW_Z | PSW_N);
2174 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2175 }
2176
2177 /* asl imm8, dn */
2178 void OP_F8C000 (insn, extension)
2179 unsigned long insn, extension;
2180 {
2181 int n, z;
2182
2183 State.regs[REG_D0 + REG0_8 (insn)] <<= (insn & 0xff);
2184 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2185 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2186 PSW &= ~(PSW_Z | PSW_N);
2187 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2188 }
2189
2190 /* asl2 dn */
2191 void OP_54 (insn, extension)
2192 unsigned long insn, extension;
2193 {
2194 int n, z;
2195
2196 State.regs[REG_D0 + REG0 (insn)] <<= 2;
2197 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2198 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2199 PSW &= ~(PSW_Z | PSW_N);
2200 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2201 }
2202
2203 /* ror dn */
2204 void OP_F284 (insn, extension)
2205 unsigned long insn, extension;
2206 {
2207 unsigned long value;
2208 int c,n,z;
2209
2210 value = State.regs[REG_D0 + REG0 (insn)];
2211 c = (value & 0x1);
2212
2213 value >>= 1;
2214 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2215 State.regs[REG_D0 + REG0 (insn)] = value;
2216 z = (value == 0);
2217 n = (value & 0x80000000) != 0;
2218 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2219 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2220 }
2221
2222 /* rol dn */
2223 void OP_F280 (insn, extension)
2224 unsigned long insn, extension;
2225 {
2226 unsigned long value;
2227 int c,n,z;
2228
2229 value = State.regs[REG_D0 + REG0 (insn)];
2230 c = (value & 0x80000000) ? 1 : 0;
2231
2232 value <<= 1;
2233 value |= ((PSW & PSW_C) != 0);
2234 State.regs[REG_D0 + REG0 (insn)] = value;
2235 z = (value == 0);
2236 n = (value & 0x80000000) != 0;
2237 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2238 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2239 }
2240
2241 /* beq label:8 */
2242 void OP_C800 (insn, extension)
2243 unsigned long insn, extension;
2244 {
2245 /* The dispatching code will add 2 after we return, so
2246 we subtract two here to make things right. */
2247 if (PSW & PSW_Z)
2248 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2249 }
2250
2251 /* bne label:8 */
2252 void OP_C900 (insn, extension)
2253 unsigned long insn, extension;
2254 {
2255 /* The dispatching code will add 2 after we return, so
2256 we subtract two here to make things right. */
2257 if (!(PSW & PSW_Z))
2258 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2259 }
2260
2261 /* bgt label:8 */
2262 void OP_C100 (insn, extension)
2263 unsigned long insn, extension;
2264 {
2265 /* The dispatching code will add 2 after we return, so
2266 we subtract two here to make things right. */
2267 if (!((PSW & PSW_Z)
2268 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2269 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2270 }
2271
2272 /* bge label:8 */
2273 void OP_C200 (insn, extension)
2274 unsigned long insn, extension;
2275 {
2276 /* The dispatching code will add 2 after we return, so
2277 we subtract two here to make things right. */
2278 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2279 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2280 }
2281
2282 /* ble label:8 */
2283 void OP_C300 (insn, extension)
2284 unsigned long insn, extension;
2285 {
2286 /* The dispatching code will add 2 after we return, so
2287 we subtract two here to make things right. */
2288 if ((PSW & PSW_Z)
2289 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2290 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2291 }
2292
2293 /* blt label:8 */
2294 void OP_C000 (insn, extension)
2295 unsigned long insn, extension;
2296 {
2297 /* The dispatching code will add 2 after we return, so
2298 we subtract two here to make things right. */
2299 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2300 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2301 }
2302
2303 /* bhi label:8 */
2304 void OP_C500 (insn, extension)
2305 unsigned long insn, extension;
2306 {
2307 /* The dispatching code will add 2 after we return, so
2308 we subtract two here to make things right. */
2309 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2310 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2311 }
2312
2313 /* bcc label:8 */
2314 void OP_C600 (insn, extension)
2315 unsigned long insn, extension;
2316 {
2317 /* The dispatching code will add 2 after we return, so
2318 we subtract two here to make things right. */
2319 if (!(PSW & PSW_C))
2320 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2321 }
2322
2323 /* bls label:8 */
2324 void OP_C700 (insn, extension)
2325 unsigned long insn, extension;
2326 {
2327 /* The dispatching code will add 2 after we return, so
2328 we subtract two here to make things right. */
2329 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2330 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2331 }
2332
2333 /* bcs label:8 */
2334 void OP_C400 (insn, extension)
2335 unsigned long insn, extension;
2336 {
2337 /* The dispatching code will add 2 after we return, so
2338 we subtract two here to make things right. */
2339 if (PSW & PSW_C)
2340 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2341 }
2342
2343 /* bvc label:8 */
2344 void OP_F8E800 (insn, extension)
2345 unsigned long insn, extension;
2346 {
2347 /* The dispatching code will add 3 after we return, so
2348 we subtract two here to make things right. */
2349 if (!(PSW & PSW_V))
2350 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2351 }
2352
2353 /* bvs label:8 */
2354 void OP_F8E900 (insn, extension)
2355 unsigned long insn, extension;
2356 {
2357 /* The dispatching code will add 3 after we return, so
2358 we subtract two here to make things right. */
2359 if (PSW & PSW_V)
2360 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2361 }
2362
2363 /* bnc label:8 */
2364 void OP_F8EA00 (insn, extension)
2365 unsigned long insn, extension;
2366 {
2367 /* The dispatching code will add 3 after we return, so
2368 we subtract two here to make things right. */
2369 if (!(PSW & PSW_N))
2370 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2371 }
2372
2373 /* bns label:8 */
2374 void OP_F8EB00 (insn, extension)
2375 unsigned long insn, extension;
2376 {
2377 /* The dispatching code will add 3 after we return, so
2378 we subtract two here to make things right. */
2379 if (PSW & PSW_N)
2380 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2381 }
2382
2383 /* bra label:8 */
2384 void OP_CA00 (insn, extension)
2385 unsigned long insn, extension;
2386 {
2387 /* The dispatching code will add 2 after we return, so
2388 we subtract two here to make things right. */
2389 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2390 }
2391
2392 /* leq */
2393 void OP_D8 (insn, extension)
2394 unsigned long insn, extension;
2395 {
2396 /* The dispatching code will add 1 after we return, so
2397 we subtract one here to make things right. */
2398 if (PSW & PSW_Z)
2399 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2400 }
2401
2402 /* lne */
2403 void OP_D9 (insn, extension)
2404 unsigned long insn, extension;
2405 {
2406 /* The dispatching code will add 1 after we return, so
2407 we subtract one here to make things right. */
2408 if (!(PSW & PSW_Z))
2409 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2410 }
2411
2412 /* lgt */
2413 void OP_D1 (insn, extension)
2414 unsigned long insn, extension;
2415 {
2416 /* The dispatching code will add 1 after we return, so
2417 we subtract one here to make things right. */
2418 if (!((PSW & PSW_Z)
2419 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2420 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2421 }
2422
2423 /* lge */
2424 void OP_D2 (insn, extension)
2425 unsigned long insn, extension;
2426 {
2427 /* The dispatching code will add 1 after we return, so
2428 we subtract one here to make things right. */
2429 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2430 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2431 }
2432
2433 /* lle */
2434 void OP_D3 (insn, extension)
2435 unsigned long insn, extension;
2436 {
2437 /* The dispatching code will add 1 after we return, so
2438 we subtract one here to make things right. */
2439 if ((PSW & PSW_Z)
2440 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2441 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2442 }
2443
2444 /* llt */
2445 void OP_D0 (insn, extension)
2446 unsigned long insn, extension;
2447 {
2448 /* The dispatching code will add 1 after we return, so
2449 we subtract one here to make things right. */
2450 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2451 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2452 }
2453
2454 /* lhi */
2455 void OP_D5 (insn, extension)
2456 unsigned long insn, extension;
2457 {
2458 /* The dispatching code will add 1 after we return, so
2459 we subtract one here to make things right. */
2460 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2461 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2462 }
2463
2464 /* lcc */
2465 void OP_D6 (insn, extension)
2466 unsigned long insn, extension;
2467 {
2468 /* The dispatching code will add 1 after we return, so
2469 we subtract one here to make things right. */
2470 if (!(PSW & PSW_C))
2471 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2472 }
2473
2474 /* lls */
2475 void OP_D7 (insn, extension)
2476 unsigned long insn, extension;
2477 {
2478 /* The dispatching code will add 1 after we return, so
2479 we subtract one here to make things right. */
2480 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2481 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2482 }
2483
2484 /* lcs */
2485 void OP_D4 (insn, extension)
2486 unsigned long insn, extension;
2487 {
2488 /* The dispatching code will add 1 after we return, so
2489 we subtract one here to make things right. */
2490 if (PSW & PSW_C)
2491 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2492 }
2493
2494 /* lra */
2495 void OP_DA (insn, extension)
2496 unsigned long insn, extension;
2497 {
2498 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2499 }
2500
2501 /* setlb */
2502 void OP_DB (insn, extension)
2503 unsigned long insn, extension;
2504 {
2505 State.regs[REG_LIR] = load_mem_big (State.regs[REG_PC] + 1, 4);
2506 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
2507 }
2508
2509 /* jmp (an) */
2510 void OP_F0F4 (insn, extension)
2511 unsigned long insn, extension;
2512 {
2513 State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
2514 }
2515
2516 /* jmp label:16 */
2517 void OP_CC0000 (insn, extension)
2518 unsigned long insn, extension;
2519 {
2520 State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 3;
2521 }
2522
2523 /* jmp label:32 */
2524 void OP_DC000000 (insn, extension)
2525 unsigned long insn, extension;
2526 {
2527 State.regs[REG_PC] += (((insn & 0xffffff) << 8) + extension) - 5;
2528 }
2529
2530 /* call label:16,reg_list,imm8 */
2531 void OP_CD000000 (insn, extension)
2532 unsigned long insn, extension;
2533 {
2534 unsigned int next_pc, sp;
2535 unsigned long mask;
2536
2537 sp = State.regs[REG_SP];
2538 next_pc = State.regs[REG_PC] + 5;
2539 State.mem[sp] = next_pc & 0xff;
2540 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2541 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2542 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2543
2544 mask = insn & 0xff;
2545
2546 if (mask & 0x80)
2547 {
2548 sp -= 4;
2549 store_word (sp, State.regs[REG_D0 + 2]);
2550 }
2551
2552 if (mask & 0x40)
2553 {
2554 sp -= 4;
2555 store_word (sp, State.regs[REG_D0 + 3]);
2556 }
2557
2558 if (mask & 0x20)
2559 {
2560 sp -= 4;
2561 store_word (sp, State.regs[REG_A0 + 2]);
2562 }
2563
2564 if (mask & 0x10)
2565 {
2566 sp -= 4;
2567 store_word (sp, State.regs[REG_A0 + 3]);
2568 }
2569
2570 if (mask & 0x8)
2571 {
2572 sp -= 4;
2573 store_word (sp, State.regs[REG_D0]);
2574 sp -= 4;
2575 store_word (sp, State.regs[REG_D0 + 1]);
2576 sp -= 4;
2577 store_word (sp, State.regs[REG_A0]);
2578 sp -= 4;
2579 store_word (sp, State.regs[REG_A0 + 1]);
2580 sp -= 4;
2581 store_word (sp, State.regs[REG_MDR]);
2582 sp -= 4;
2583 store_word (sp, State.regs[REG_LIR]);
2584 sp -= 4;
2585 store_word (sp, State.regs[REG_LAR]);
2586 sp -= 4;
2587 }
2588
2589 /* Update the stack pointer, note that the register saves to do not
2590 modify SP. The SP adjustment is derived totally from the imm8
2591 field. */
2592 State.regs[REG_SP] -= extension;
2593 State.regs[REG_MDR] = next_pc;
2594 State.regs[REG_PC] += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2595 }
2596
2597 /* call label:32,reg_list,imm8*/
2598 void OP_DD000000 (insn, extension)
2599 unsigned long insn, extension;
2600 {
2601 unsigned int next_pc, sp, adjust;
2602 unsigned long mask;
2603
2604 sp = State.regs[REG_SP];
2605 next_pc = State.regs[REG_PC] + 7;
2606 State.mem[sp] = next_pc & 0xff;
2607 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2608 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2609 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2610
2611 mask = (extension & 0xff00) >> 8;
2612
2613 if (mask & 0x80)
2614 {
2615 sp -= 4;
2616 store_word (sp, State.regs[REG_D0 + 2]);
2617 }
2618
2619 if (mask & 0x40)
2620 {
2621 sp -= 4;
2622 store_word (sp, State.regs[REG_D0 + 3]);
2623 }
2624
2625 if (mask & 0x20)
2626 {
2627 sp -= 4;
2628 store_word (sp, State.regs[REG_A0 + 2]);
2629 }
2630
2631 if (mask & 0x10)
2632 {
2633 sp -= 4;
2634 store_word (sp, State.regs[REG_A0 + 3]);
2635 }
2636
2637 if (mask & 0x8)
2638 {
2639 sp -= 4;
2640 store_word (sp, State.regs[REG_D0]);
2641 sp -= 4;
2642 store_word (sp, State.regs[REG_D0 + 1]);
2643 sp -= 4;
2644 store_word (sp, State.regs[REG_A0]);
2645 sp -= 4;
2646 store_word (sp, State.regs[REG_A0 + 1]);
2647 sp -= 4;
2648 store_word (sp, State.regs[REG_MDR]);
2649 sp -= 4;
2650 store_word (sp, State.regs[REG_LIR]);
2651 sp -= 4;
2652 store_word (sp, State.regs[REG_LAR]);
2653 sp -= 4;
2654 }
2655
2656 /* Update the stack pointer, note that the register saves to do not
2657 modify SP. The SP adjustment is derived totally from the imm8
2658 field. */
2659 State.regs[REG_SP] -= (extension & 0xff);
2660 State.regs[REG_MDR] = next_pc;
2661 State.regs[REG_PC] += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2662 }
2663
2664 /* calls (an) */
2665 void OP_F0F0 (insn, extension)
2666 unsigned long insn, extension;
2667 {
2668 unsigned int next_pc, sp;
2669
2670 sp = State.regs[REG_SP];
2671 next_pc = State.regs[REG_PC] + 2;
2672 State.mem[sp] = next_pc & 0xff;
2673 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2674 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2675 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2676 State.regs[REG_MDR] = next_pc;
2677 State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
2678 }
2679
2680 /* calls label:16 */
2681 void OP_FAFF0000 (insn, extension)
2682 unsigned long insn, extension;
2683 {
2684 unsigned int next_pc, sp;
2685
2686 sp = State.regs[REG_SP];
2687 next_pc = State.regs[REG_PC] + 4;
2688 State.mem[sp] = next_pc & 0xff;
2689 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2690 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2691 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2692 State.regs[REG_MDR] = next_pc;
2693 State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 4;
2694 }
2695
2696 /* calls label:32 */
2697 void OP_FCFF0000 (insn, extension)
2698 unsigned long insn, extension;
2699 {
2700 unsigned int next_pc, sp;
2701
2702 sp = State.regs[REG_SP];
2703 next_pc = State.regs[REG_PC] + 6;
2704 State.mem[sp] = next_pc & 0xff;
2705 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2706 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2707 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2708 State.regs[REG_MDR] = next_pc;
2709 State.regs[REG_PC] += (((insn & 0xffff) << 16) + extension) - 6;
2710 }
2711
2712 /* ret reg_list, imm8 */
2713 void OP_DF0000 (insn, extension)
2714 unsigned long insn, extension;
2715 {
2716 unsigned int sp, offset;
2717 unsigned long mask;
2718
2719 State.regs[REG_SP] += insn & 0xff;
2720 sp = State.regs[REG_SP];
2721
2722 offset = -4;
2723 mask = (insn & 0xff00) >> 8;
2724
2725 if (mask & 0x80)
2726 {
2727 State.regs[REG_D0 + 2] = load_word (sp + offset);
2728 offset -= 4;
2729 }
2730
2731 if (mask & 0x40)
2732 {
2733 State.regs[REG_D0 + 3] = load_word (sp + offset);
2734 offset -= 4;
2735 }
2736
2737 if (mask & 0x20)
2738 {
2739 State.regs[REG_A0 + 2] = load_word (sp + offset);
2740 offset -= 4;
2741 }
2742
2743 if (mask & 0x10)
2744 {
2745 State.regs[REG_A0 + 3] = load_word (sp + offset);
2746 offset -= 4;
2747 }
2748
2749 if (mask & 0x8)
2750 {
2751 State.regs[REG_D0] = load_word (sp + offset);
2752 offset -= 4;
2753 State.regs[REG_D0 + 1] = load_word (sp + offset);
2754 offset -= 4;
2755 State.regs[REG_A0] = load_word (sp + offset);
2756 offset -= 4;
2757 State.regs[REG_A0 + 1] = load_word (sp + offset);
2758 offset -= 4;
2759 State.regs[REG_MDR] = load_word (sp + offset);
2760 offset -= 4;
2761 State.regs[REG_LIR] = load_word (sp + offset);
2762 offset -= 4;
2763 State.regs[REG_LAR] = load_word (sp + offset);
2764 offset -= 4;
2765 }
2766
2767 /* Restore the PC value. */
2768 State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
2769 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2770 State.regs[REG_PC] -= 3;
2771 }
2772
2773 /* retf reg_list,imm8 */
2774 void OP_DE0000 (insn, extension)
2775 unsigned long insn, extension;
2776 {
2777 unsigned int sp, offset;
2778 unsigned long mask;
2779
2780 State.regs[REG_SP] += (insn & 0xff);
2781 sp = State.regs[REG_SP];
2782 State.regs[REG_PC] = State.regs[REG_MDR] - 3;
2783
2784 offset = -4;
2785 mask = (insn & 0xff00) >> 8;
2786
2787 if (mask & 0x80)
2788 {
2789 State.regs[REG_D0 + 2] = load_word (sp + offset);
2790 offset -= 4;
2791 }
2792
2793 if (mask & 0x40)
2794 {
2795 State.regs[REG_D0 + 3] = load_word (sp + offset);
2796 offset -= 4;
2797 }
2798
2799 if (mask & 0x20)
2800 {
2801 State.regs[REG_A0 + 2] = load_word (sp + offset);
2802 offset -= 4;
2803 }
2804
2805 if (mask & 0x10)
2806 {
2807 State.regs[REG_A0 + 3] = load_word (sp + offset);
2808 offset -= 4;
2809 }
2810
2811 if (mask & 0x8)
2812 {
2813 State.regs[REG_D0] = load_word (sp + offset);
2814 offset -= 4;
2815 State.regs[REG_D0 + 1] = load_word (sp + offset);
2816 offset -= 4;
2817 State.regs[REG_A0] = load_word (sp + offset);
2818 offset -= 4;
2819 State.regs[REG_A0 + 1] = load_word (sp + offset);
2820 offset -= 4;
2821 State.regs[REG_MDR] = load_word (sp + offset);
2822 offset -= 4;
2823 State.regs[REG_LIR] = load_word (sp + offset);
2824 offset -= 4;
2825 State.regs[REG_LAR] = load_word (sp + offset);
2826 offset -= 4;
2827 }
2828 }
2829
2830 /* rets */
2831 void OP_F0FC (insn, extension)
2832 unsigned long insn, extension;
2833 {
2834 unsigned int sp;
2835
2836 sp = State.regs[REG_SP];
2837 State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
2838 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2839 State.regs[REG_PC] -= 2;
2840 }
2841
2842 /* rti */
2843 void OP_F0FD (insn, extension)
2844 unsigned long insn, extension;
2845 {
2846 unsigned int sp, next_pc;
2847
2848 PSW = State.mem[sp] | (State.mem[sp + 1] << 8);
2849 State.regs[REG_PC] = (State.mem[sp+4] | (State.mem[sp+5] << 8)
2850 | (State.mem[sp+6] << 16) | (State.mem[sp+7] << 24));
2851 State.regs[REG_SP] += 8;
2852 }
2853
2854 /* trap */
2855 void OP_F0FE (insn, extension)
2856 unsigned long insn, extension;
2857 {
2858 unsigned int sp, next_pc;
2859
2860 sp = State.regs[REG_SP];
2861 next_pc = State.regs[REG_PC] + 2;
2862 State.mem[sp] = next_pc & 0xff;
2863 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2864 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2865 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2866 State.regs[REG_PC] = 0x40000010 - 2;
2867 }
2868
2869 /* syscall */
2870 void OP_F020 (insn, extension)
2871 unsigned long insn, extension;
2872 {
2873 /* We use this for simulated system calls; we may need to change
2874 it to a reserved instruction if we conflict with uses at
2875 Matsushita. */
2876 int save_errno = errno;
2877 errno = 0;
2878
2879 /* Registers passed to trap 0 */
2880
2881 /* Function number. */
2882 #define FUNC (State.regs[0])
2883
2884 /* Parameters. */
2885 #define PARM1 (State.regs[1])
2886 #define PARM2 (load_word (State.regs[REG_SP] + 12))
2887 #define PARM3 (load_word (State.regs[REG_SP] + 16))
2888
2889 /* Registers set by trap 0 */
2890
2891 #define RETVAL State.regs[0] /* return value */
2892 #define RETERR State.regs[1] /* return error code */
2893
2894 /* Turn a pointer in a register into a pointer into real memory. */
2895
2896 #define MEMPTR(x) (State.mem + x)
2897
2898 switch (FUNC)
2899 {
2900 #if !defined(__GO32__) && !defined(_WIN32)
2901 case SYS_fork:
2902 RETVAL = fork ();
2903 break;
2904 case SYS_execve:
2905 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2906 (char **)MEMPTR (PARM3));
2907 break;
2908 #ifdef SYS_execv
2909 case SYS_execv:
2910 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2911 break;
2912 #endif
2913 #endif
2914
2915 case SYS_read:
2916 RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
2917 MEMPTR (PARM2), PARM3);
2918 break;
2919 case SYS_write:
2920 RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
2921 MEMPTR (PARM2), PARM3);
2922 break;
2923 case SYS_lseek:
2924 RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
2925 break;
2926 case SYS_close:
2927 RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
2928 break;
2929 case SYS_open:
2930 RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
2931 break;
2932 case SYS_exit:
2933 /* EXIT - caller can look in PARM1 to work out the
2934 reason */
2935 if (PARM1 == 0xdead)
2936 State.exception = SIGABRT;
2937 else
2938 State.exception = SIGQUIT;
2939 State.exited = 1;
2940 break;
2941
2942 case SYS_stat: /* added at hmsi */
2943 /* stat system call */
2944 {
2945 struct stat host_stat;
2946 reg_t buf;
2947
2948 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2949
2950 buf = PARM2;
2951
2952 /* Just wild-assed guesses. */
2953 store_half (buf, host_stat.st_dev);
2954 store_half (buf + 2, host_stat.st_ino);
2955 store_word (buf + 4, host_stat.st_mode);
2956 store_half (buf + 8, host_stat.st_nlink);
2957 store_half (buf + 10, host_stat.st_uid);
2958 store_half (buf + 12, host_stat.st_gid);
2959 store_half (buf + 14, host_stat.st_rdev);
2960 store_word (buf + 16, host_stat.st_size);
2961 store_word (buf + 20, host_stat.st_atime);
2962 store_word (buf + 28, host_stat.st_mtime);
2963 store_word (buf + 36, host_stat.st_ctime);
2964 }
2965 break;
2966
2967 case SYS_chown:
2968 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2969 break;
2970 case SYS_chmod:
2971 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2972 break;
2973 #ifdef SYS_time
2974 case SYS_time:
2975 RETVAL = time ((void*) MEMPTR (PARM1));
2976 break;
2977 #endif
2978 #ifdef SYS_times
2979 case SYS_times:
2980 {
2981 struct tms tms;
2982 RETVAL = times (&tms);
2983 store_word (PARM1, tms.tms_utime);
2984 store_word (PARM1 + 4, tms.tms_stime);
2985 store_word (PARM1 + 8, tms.tms_cutime);
2986 store_word (PARM1 + 12, tms.tms_cstime);
2987 break;
2988 }
2989 #endif
2990 case SYS_gettimeofday:
2991 {
2992 struct timeval t;
2993 struct timezone tz;
2994 RETVAL = gettimeofday (&t, &tz);
2995 store_word (PARM1, t.tv_sec);
2996 store_word (PARM1 + 4, t.tv_usec);
2997 store_word (PARM2, tz.tz_minuteswest);
2998 store_word (PARM2 + 4, tz.tz_dsttime);
2999 break;
3000 }
3001 #ifdef SYS_utime
3002 case SYS_utime:
3003 /* Cast the second argument to void *, to avoid type mismatch
3004 if a prototype is present. */
3005 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
3006 break;
3007 #endif
3008 default:
3009 abort ();
3010 }
3011 RETERR = errno;
3012 errno = save_errno;
3013 }
3014
3015 /* rtm */
3016 void OP_F0FF (insn, extension)
3017 unsigned long insn, extension;
3018 {
3019 abort ();
3020 }
3021
3022 /* nop */
3023 void OP_CB (insn, extension)
3024 unsigned long insn, extension;
3025 {
3026 }
3027
3028 /* putx dm,dm */
3029 void OP_F500 (insn, extension)
3030 unsigned long insn, extension;
3031 {
3032 State.regs[REG_MDRQ] = State.regs[REG_D0 + REG0 (insn)];
3033 }
3034
3035 /* getx dm,dm */
3036 void OP_F6F0 (insn, extension)
3037 unsigned long insn, extension;
3038 {
3039 int z, n;
3040 z = (State.regs[REG_MDRQ] == 0);
3041 n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
3042 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDRQ];
3043
3044 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3045 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
3046 }
3047
3048 /* mulq dm,dn */
3049 void OP_F600 (insn, extension)
3050 unsigned long insn, extension;
3051 {
3052 unsigned long long temp;
3053 int n, z;
3054
3055 temp = ((signed64)State.regs[REG_D0 + REG0 (insn)]
3056 * (signed64)State.regs[REG_D0 + REG1 (insn)]);
3057 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
3058 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3059 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
3060 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
3061 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3062 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3063 }
3064
3065 /* mulq imm8,dn */
3066 void OP_F90000 (insn, extension)
3067 unsigned long insn, extension;
3068 {
3069 unsigned long long temp;
3070 int n, z;
3071
3072 temp = ((signed64)State.regs[REG_D0 + REG0_8 (insn)]
3073 * (signed64)SEXT8 (insn & 0xff));
3074 State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff;
3075 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3076 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
3077 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
3078 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3079 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3080 }
3081
3082 /* mulq imm16,dn */
3083 void OP_FB000000 (insn, extension)
3084 unsigned long insn, extension;
3085 {
3086 unsigned long long temp;
3087 int n, z;
3088
3089 temp = ((signed64)State.regs[REG_D0 + REG0_16 (insn)]
3090 * (signed64)SEXT16 (insn & 0xffff));
3091 State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
3092 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3093 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
3094 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
3095 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3096 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3097 }
3098
3099 /* mulq imm32,dn */
3100 void OP_FD000000 (insn, extension)
3101 unsigned long insn, extension;
3102 {
3103 unsigned long long temp;
3104 int n, z;
3105
3106 temp = ((signed64)State.regs[REG_D0 + REG0_16 (insn)]
3107 * (signed64)(((insn & 0xffff) << 16) + extension));
3108 State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
3109 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3110 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
3111 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
3112 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3113 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3114 }
3115
3116 /* mulqu dm,dn */
3117 void OP_F610 (insn, extension)
3118 unsigned long insn, extension;
3119 {
3120 unsigned long long temp;
3121 int n, z;
3122
3123 temp = ((unsigned64) State.regs[REG_D0 + REG0 (insn)]
3124 * (unsigned64) State.regs[REG_D0 + REG1 (insn)]);
3125 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
3126 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3127 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
3128 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
3129 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3130 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3131 }
3132
3133 /* mulqu imm8,dn */
3134 void OP_F91400 (insn, extension)
3135 unsigned long insn, extension;
3136 {
3137 unsigned long long temp;
3138 int n, z;
3139
3140 temp = ((unsigned64)State.regs[REG_D0 + REG0_8 (insn)]
3141 * (unsigned64)SEXT8 (insn & 0xff));
3142 State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff;
3143 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3144 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
3145 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
3146 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3147 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3148 }
3149
3150 /* mulqu imm16,dn */
3151 void OP_FB140000 (insn, extension)
3152 unsigned long insn, extension;
3153 {
3154 unsigned long long temp;
3155 int n, z;
3156
3157 temp = ((unsigned64)State.regs[REG_D0 + REG0_16 (insn)]
3158 * (unsigned64) SEXT16 (insn & 0xffff));
3159 State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
3160 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3161 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
3162 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
3163 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3164 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3165 }
3166
3167 /* mulqu imm32,dn */
3168 void OP_FD140000 (insn, extension)
3169 unsigned long insn, extension;
3170 {
3171 unsigned long long temp;
3172 int n, z;
3173
3174 temp = ((unsigned64)State.regs[REG_D0 + REG0_16 (insn)]
3175 * (unsigned64)(((insn & 0xffff) << 16) + extension));
3176 State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
3177 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3178 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
3179 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
3180 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3181 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3182 }
3183
3184 /* sat16 dm,dn */
3185 void OP_F640 (insn, extension)
3186 unsigned long insn, extension;
3187 {
3188 int temp;
3189
3190 temp = State.regs[REG_D0 + REG1 (insn)];
3191 temp = (temp > 0x7fff ? 0x7fff : temp);
3192 temp = (temp < -0x8000 ? -0x8000 : temp);
3193 State.regs[REG_D0 + REG0 (insn)] = temp;
3194 }
3195
3196 /* sat24 dm,dn */
3197 void OP_F650 (insn, extension)
3198 unsigned long insn, extension;
3199 {
3200 int temp;
3201
3202 temp = State.regs[REG_D0 + REG1 (insn)];
3203 temp = (temp > 0x7fffff ? 0x7fffff : temp);
3204 temp = (temp < -0x800000 ? -0x800000 : temp);
3205 State.regs[REG_D0 + REG0 (insn)] = temp;
3206 }
3207
3208 /* bsch dm,dn */
3209 void OP_F670 (insn, extension)
3210 unsigned long insn, extension;
3211 {
3212 int temp, c;
3213
3214 temp = State.regs[REG_D0 + REG1 (insn)];
3215 temp <<= (State.regs[REG_D0 + REG0 (insn)] & 0x1f);
3216 c = (temp != 0 ? 1 : 0);
3217 PSW &= ~(PSW_C);
3218 PSW |= (c ? PSW_C : 0);
3219 }
3220
3221 /* breakpoint */
3222 void
3223 OP_FF (insn, extension)
3224 unsigned long insn, extension;
3225 {
3226 State.exception = SIGTRAP;
3227 PC -= 1;
3228 }
3229
GDB Binutils - Deliverables
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