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* simops.c: Fix thinkos in last change to "inc dn".
[deliverable/binutils-gdb.git] / sim / mn10300 / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #ifdef HAVE_UNISTD_H
5 #include <unistd.h>
6 #endif
7 #include "mn10300_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10 #include "bfd.h"
11 #include <errno.h>
12 #include <sys/stat.h>
13 #include <sys/times.h>
14 #include <sys/time.h>
15
16 enum op_types {
17 OP_UNKNOWN,
18 };
19
20 #ifdef DEBUG
21 static void trace_input PARAMS ((char *name, enum op_types type, int size));
22 static void trace_output PARAMS ((enum op_types result));
23 static int init_text_p = 0;
24 static asection *text;
25 static bfd_vma text_start;
26 static bfd_vma text_end;
27 extern bfd *exec_bfd;
28
29 #ifndef SIZE_INSTRUCTION
30 #define SIZE_INSTRUCTION 6
31 #endif
32
33 #ifndef SIZE_OPERANDS
34 #define SIZE_OPERANDS 16
35 #endif
36
37 #ifndef SIZE_VALUES
38 #define SIZE_VALUES 11
39 #endif
40
41 #ifndef SIZE_LOCATION
42 #define SIZE_LOCATION 40
43 #endif
44
45 static void
46 trace_input (name, type, size)
47 char *name;
48 enum op_types type;
49 int size;
50 {
51 }
52
53 static void
54 trace_output (result)
55 enum op_types result;
56 {
57 }
58
59 #else
60 #define trace_input(NAME, IN1, IN2)
61 #define trace_output(RESULT)
62 #endif
63
64 \f
65 /* mov imm8, dn */
66 void OP_8000 ()
67 {
68 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = SEXT8 (insn & 0xff);
69 }
70
71 /* mov dm, dn */
72 void OP_80 ()
73 {
74 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
75 }
76
77 /* mov dm, an */
78 void OP_F1E0 ()
79 {
80 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
81 }
82
83 /* mov am, dn */
84 void OP_F1D0 ()
85 {
86 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
87 }
88
89 /* mov imm8, an */
90 void OP_9000 ()
91 {
92 State.regs[REG_A0 + ((insn & 0x300) >> 8)] = insn & 0xff;
93 }
94
95 /* mov am, an */
96 void OP_90 ()
97 {
98 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
99 }
100
101 /* mov sp, an */
102 void OP_3C ()
103 {
104 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_SP];
105 }
106
107 /* mov am, sp */
108 void OP_F2F0 ()
109 {
110 State.regs[REG_SP] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
111 }
112
113 /* mov psw, dn */
114 void OP_F2E4 ()
115 {
116 State.regs[REG_D0 + (insn & 0x3)] = PSW;
117 }
118
119 /* mov dm, psw */
120 void OP_F2F3 ()
121 {
122 PSW = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
123 }
124
125 /* mov mdr, dn */
126 void OP_F2E0 ()
127 {
128 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_MDR];
129 }
130
131 /* mov dm, mdr */
132 void OP_F2F2 ()
133 {
134 State.regs[REG_MDR] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
135 }
136
137 /* mov (am), dn */
138 void OP_70 ()
139 {
140 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
141 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
142 }
143
144 /* mov (d8,am), dn */
145 void OP_F80000 ()
146 {
147 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
148 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
149 + SEXT8 (insn & 0xff)), 4);
150 }
151
152 /* mov (d16,am), dn */
153 void OP_FA000000 ()
154 {
155 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
156 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
157 + SEXT16 (insn & 0xffff)), 4);
158 }
159
160 /* mov (d32,am), dn */
161 void OP_FC000000 ()
162 {
163 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
164 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
165 + ((insn & 0xffff) << 16) | extension), 4);
166 }
167
168 /* mov (d8,sp), dn */
169 void OP_5800 ()
170 {
171 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
172 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
173 }
174
175 /* mov (d16,sp), dn */
176 void OP_FAB40000 ()
177 {
178 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
179 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
180 }
181
182 /* mov (d32,sp), dn */
183 void OP_FCB40000 ()
184 {
185 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
186 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
187 }
188
189 /* mov (di,am), dn */
190 void OP_F300 ()
191 {
192 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
193 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
194 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
195 }
196
197 /* mov (abs16), dn */
198 void OP_300000 ()
199 {
200 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
201 }
202
203 /* mov (abs32), dn */
204 void OP_FCA40000 ()
205 {
206 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
207 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
208 }
209
210 /* mov (am), an */
211 void OP_F000 ()
212 {
213 State.regs[REG_A0 + ((insn & 0xc) >> 2)]
214 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
215 }
216
217 /* mov (d8,am), an */
218 void OP_F82000 ()
219 {
220 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]
221 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
222 + SEXT8 (insn & 0xff)), 4);
223 }
224
225 /* mov (d16,am), an */
226 void OP_FA200000 ()
227 {
228 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
229 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
230 + SEXT16 (insn & 0xffff)), 4);
231 }
232
233 /* mov (d32,am), an */
234 void OP_FC200000 ()
235 {
236 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
237 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
238 + ((insn & 0xffff) << 16) + extension), 4);
239 }
240
241 /* mov (d8,sp), an */
242 void OP_5C00 ()
243 {
244 State.regs[REG_A0 + ((insn & 0x300) >> 8)]
245 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
246 }
247
248 /* mov (d16,sp), an */
249 void OP_FAB00000 ()
250 {
251 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
252 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
253 }
254
255 /* mov (d32,sp), an */
256 void OP_FCB00000 ()
257 {
258 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
259 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
260 }
261
262 /* mov (di,am), an */
263 void OP_F380 ()
264 {
265 State.regs[REG_A0 + ((insn & 0x300) >> 8)]
266 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
267 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
268 }
269
270 /* mov (abs16), an */
271 void OP_FAA00000 ()
272 {
273 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
274 }
275
276 /* mov (abs32), an */
277 void OP_FCA00000 ()
278 {
279 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
280 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
281 }
282
283 /* mov (d8,am), sp */
284 void OP_F8F000 ()
285 {
286 State.regs[REG_SP]
287 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
288 + SEXT8 (insn & 0xff)), 4);
289 }
290
291 /* mov dm, (an) */
292 void OP_60 ()
293 {
294 store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
295 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
296 }
297
298 /* mov dm, (d8,an) */
299 void OP_F81000 ()
300 {
301 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
302 + SEXT8 (insn & 0xff)), 4,
303 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
304 }
305
306 /* mov dm (d16,an) */
307 void OP_FA100000 ()
308 {
309 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
310 + SEXT16 (insn & 0xffff)), 4,
311 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
312 }
313
314 /* mov dm (d32,an) */
315 void OP_FC100000 ()
316 {
317 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
318 + ((insn & 0xffff) << 16) + extension), 4,
319 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
320 }
321
322 /* mov dm, (d8,sp) */
323 void OP_4200 ()
324 {
325 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
326 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
327 }
328
329 /* mov dm, (d16,sp) */
330 void OP_FA910000 ()
331 {
332 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
333 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
334 }
335
336 /* mov dm, (d32,sp) */
337 void OP_FC910000 ()
338 {
339 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
340 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
341 }
342
343 /* mov dm, (di,an) */
344 void OP_F340 ()
345 {
346 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
347 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
348 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
349 }
350
351 /* mov dm, (abs16) */
352 void OP_10000 ()
353 {
354 store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
355 }
356
357 /* mov dm, (abs32) */
358 void OP_FC810000 ()
359 {
360 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
361 }
362
363 /* mov am, (an) */
364 void OP_F010 ()
365 {
366 store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
367 State.regs[REG_A0 + ((insn & 0xc) >> 2)]);
368 }
369
370 /* mov am, (d8,an) */
371 void OP_F83000 ()
372 {
373 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
374 + SEXT8 (insn & 0xff)), 4,
375 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
376 }
377
378 /* mov am, (d16,an) */
379 void OP_FA300000 ()
380 {
381 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 17)]
382 + SEXT16 (insn & 0xffff)), 4,
383 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
384 }
385
386 /* mov am, (d32,an) */
387 void OP_FC300000 ()
388 {
389 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 17)]
390 + ((insn & 0xffff) << 16) + extension), 4,
391 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
392 }
393
394 /* mov am, (d8,sp) */
395 void OP_4300 ()
396 {
397 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
398 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
399 }
400
401 /* mov am, (d16,sp) */
402 void OP_FA900000 ()
403 {
404 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
405 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
406 }
407
408 /* mov am, (d32,sp) */
409 void OP_FC900000 ()
410 {
411 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
412 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
413 }
414
415 /* mov am, (di,an) */
416 void OP_F3C0 ()
417 {
418 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
419 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
420 State.regs[REG_A0 + ((insn & 0x300) >> 8)]);
421 }
422
423 /* mov am, (abs16) */
424 void OP_FA800000 ()
425 {
426 store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
427 }
428
429 /* mov am, (abs32) */
430 void OP_FC800000 ()
431 {
432 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
433 }
434
435 /* mov sp, (d8,an) */
436 void OP_F8F400 ()
437 {
438 store_mem (State.regs[REG_A0 + ((insn & 0x300) >> 8)] + SEXT8 (insn & 0xff),
439 4, State.regs[REG_SP]);
440 }
441
442 /* mov imm16, dn */
443 void OP_2C0000 ()
444 {
445 unsigned long value;
446
447 value = SEXT16 (insn & 0xffff);
448 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
449 }
450
451 /* mov imm32,dn */
452 void OP_FCCC0000 ()
453 {
454 unsigned long value;
455
456 value = (insn & 0xffff) << 16 | extension;
457 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
458 }
459
460 /* mov imm16, an */
461 void OP_240000 ()
462 {
463 unsigned long value;
464
465 value = insn & 0xffff;
466 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
467 }
468
469 /* mov imm32, an */
470 void OP_FCDC0000 ()
471 {
472 unsigned long value;
473
474 value = (insn & 0xffff) << 16 | extension;
475 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
476 }
477
478 /* movbu (am), dn */
479 void OP_F040 ()
480 {
481 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
482 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 1);
483 }
484
485 /* movbu (d8,am), dn */
486 void OP_F84000 ()
487 {
488 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
489 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
490 + SEXT8 (insn & 0xff)), 1);
491 }
492
493 /* movbu (d16,am), dn */
494 void OP_FA400000 ()
495 {
496 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
497 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
498 + SEXT16 (insn & 0xffff)), 1);
499 }
500
501 /* movbu (d32,am), dn */
502 void OP_FC400000 ()
503 {
504 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
505 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
506 + ((insn & 0xffff) << 16) + extension), 1);
507 }
508
509 /* movbu (d8,sp), dn */
510 void OP_F8B800 ()
511 {
512 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
513 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
514 }
515
516 /* movbu (d16,sp), dn */
517 void OP_FAB80000 ()
518 {
519 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
520 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
521 }
522
523 /* movbu (d32,sp), dn */
524 void OP_FCB80000 ()
525 {
526 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
527 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
528 }
529
530 /* movbu (di,am), dn */
531 void OP_F400 ()
532 {
533 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
534 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
535 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
536 }
537
538 /* movbu (abs16), dn */
539 void OP_340000 ()
540 {
541 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 1);
542 }
543
544 /* movbu (abs32), dn */
545 void OP_FCA80000 ()
546 {
547 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
548 = load_mem ((((insn & 0xffff) << 16) + extension), 1);
549 }
550
551 /* movbu dm, (an) */
552 void OP_F050 ()
553 {
554 store_mem (State.regs[REG_A0 + (insn & 0x3)], 1,
555 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
556 }
557
558 /* movbu dm, (d8,an) */
559 void OP_F85000 ()
560 {
561 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
562 + SEXT8 (insn & 0xff)), 1,
563 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
564 }
565
566 /* movbu dm, (d16,an) */
567 void OP_FA500000 ()
568 {
569 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
570 + SEXT16 (insn & 0xffff)), 1,
571 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
572 }
573
574 /* movbu dm, (d32,an) */
575 void OP_FC500000 ()
576 {
577 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
578 + ((insn & 0xffff) << 16) + extension), 1,
579 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
580 }
581
582 /* movbu dm, (d8,sp) */
583 void OP_F89200 ()
584 {
585 store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
586 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
587 }
588
589 /* movbu dm, (d16,sp) */
590 void OP_FA920000 ()
591 {
592 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
593 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
594 }
595
596 /* movbu dm (d32,sp) */
597 void OP_FC920000 ()
598 {
599 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
600 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
601 }
602
603 /* movbu dm, (di,an) */
604 void OP_F440 ()
605 {
606 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
607 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
608 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
609 }
610
611 /* movbu dm, (abs16) */
612 void OP_20000 ()
613 {
614 store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
615 }
616
617 /* movbu dm, (abs32) */
618 void OP_FC820000 ()
619 {
620 store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
621 }
622
623 /* movhu (am), dn */
624 void OP_F060 ()
625 {
626 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
627 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 2);
628 }
629
630 /* movhu (d8,am), dn */
631 void OP_F86000 ()
632 {
633 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
634 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
635 + SEXT8 (insn & 0xff)), 2);
636 }
637
638 /* movhu (d16,am), dn */
639 void OP_FA600000 ()
640 {
641 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
642 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
643 + SEXT16 (insn & 0xffff)), 2);
644 }
645
646 /* movhu (d32,am), dn */
647 void OP_FC600000 ()
648 {
649 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
650 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
651 + ((insn & 0xffff) << 16) + extension), 2);
652 }
653
654 /* movhu (d8,sp) dn */
655 void OP_F8BC00 ()
656 {
657 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
658 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
659 }
660
661 /* movhu (d16,sp), dn */
662 void OP_FABC0000 ()
663 {
664 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
665 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
666 }
667
668 /* movhu (d32,sp), dn */
669 void OP_FCBC0000 ()
670 {
671 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
672 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
673 }
674
675 /* movhu (di,am), dn */
676 void OP_F480 ()
677 {
678 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
679 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
680 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
681 }
682
683 /* movhu (abs16), dn */
684 void OP_380000 ()
685 {
686 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 2);
687 }
688
689 /* movhu (abs32), dn */
690 void OP_FCAC0000 ()
691 {
692 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
693 = load_mem ((((insn & 0xffff) << 16) + extension), 2);
694 }
695
696 /* movhu dm, (an) */
697 void OP_F070 ()
698 {
699 store_mem (State.regs[REG_A0 + (insn & 0x3)], 2,
700 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
701 }
702
703 /* movhu dm, (d8,an) */
704 void OP_F87000 ()
705 {
706 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
707 + SEXT8 (insn & 0xff)), 2,
708 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
709 }
710
711 /* movhu dm, (d16,an) */
712 void OP_FA700000 ()
713 {
714 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
715 + SEXT16 (insn & 0xffff)), 2,
716 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
717 }
718
719 /* movhu dm, (d32,an) */
720 void OP_FC700000 ()
721 {
722 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
723 + ((insn & 0xffff) << 16) + extension), 2,
724 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
725 }
726
727 /* movhu dm,(d8,sp) */
728 void OP_F89300 ()
729 {
730 store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
731 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
732 }
733
734 /* movhu dm,(d16,sp) */
735 void OP_FA930000 ()
736 {
737 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
738 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
739 }
740
741 /* movhu dm,(d32,sp) */
742 void OP_FC930000 ()
743 {
744 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
745 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
746 }
747
748 /* movhu dm, (di,an) */
749 void OP_F4C0 ()
750 {
751 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
752 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
753 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
754 }
755
756 /* movhu dm, (abs16) */
757 void OP_30000 ()
758 {
759 store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
760 }
761
762 /* movhu dm, (abs32) */
763 void OP_FC830000 ()
764 {
765 store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
766 }
767
768 /* ext dn */
769 void OP_F2D0 ()
770 {
771 if (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000)
772 State.regs[REG_MDR] = -1;
773 else
774 State.regs[REG_MDR] = 0;
775 }
776
777 /* extb dn */
778 void OP_10 ()
779 {
780 State.regs[REG_D0 + (insn & 0x3)] = SEXT8 (State.regs[REG_D0 + (insn & 0x3)]);
781 }
782
783 /* extbu dn */
784 void OP_14 ()
785 {
786 State.regs[REG_D0 + (insn & 0x3)] &= 0xff;
787 }
788
789 /* exth dn */
790 void OP_18 ()
791 {
792 State.regs[REG_D0 + (insn & 0x3)]
793 = SEXT16 (State.regs[REG_D0 + (insn & 0x3)]);
794 }
795
796 /* exthu dn */
797 void OP_1C ()
798 {
799 State.regs[REG_D0 + (insn & 0x3)] &= 0xffff;
800 }
801
802 /* movm (sp), reg_list */
803 void OP_CE00 ()
804 {
805 unsigned long sp = State.regs[REG_SP];
806 unsigned long mask;
807
808 mask = insn & 0xff;
809
810 if (mask & 0x8)
811 {
812 sp += 4;
813 State.regs[REG_LAR] = load_mem (sp, 4);
814 sp += 4;
815 State.regs[REG_LIR] = load_mem (sp, 4);
816 sp += 4;
817 State.regs[REG_MDR] = load_mem (sp, 4);
818 sp += 4;
819 State.regs[REG_A0 + 1] = load_mem (sp, 4);
820 sp += 4;
821 State.regs[REG_A0] = load_mem (sp, 4);
822 sp += 4;
823 State.regs[REG_D0 + 1] = load_mem (sp, 4);
824 sp += 4;
825 State.regs[REG_D0] = load_mem (sp, 4);
826 sp += 4;
827 }
828
829 if (mask & 0x10)
830 {
831 State.regs[REG_A0 + 3] = load_mem (sp, 4);
832 sp += 4;
833 }
834
835 if (mask & 0x20)
836 {
837 State.regs[REG_A0 + 2] = load_mem (sp, 4);
838 sp += 4;
839 }
840
841 if (mask & 0x40)
842 {
843 State.regs[REG_D0 + 3] = load_mem (sp, 4);
844 sp += 4;
845 }
846
847 if (mask & 0x80)
848 {
849 State.regs[REG_D0 + 2] = load_mem (sp, 4);
850 sp += 4;
851 }
852
853 /* And make sure to update the stack pointer. */
854 State.regs[REG_SP] = sp;
855 }
856
857 /* movm reg_list, (sp) */
858 void OP_CF00 ()
859 {
860 unsigned long sp = State.regs[REG_SP];
861 unsigned long mask;
862
863 mask = insn & 0xff;
864
865 if (mask & 0x80)
866 {
867 sp -= 4;
868 store_mem (sp, 4, State.regs[REG_D0 + 2]);
869 }
870
871 if (mask & 0x40)
872 {
873 sp -= 4;
874 store_mem (sp, 4, State.regs[REG_D0 + 3]);
875 }
876
877 if (mask & 0x20)
878 {
879 sp -= 4;
880 store_mem (sp, 4, State.regs[REG_A0 + 2]);
881 }
882
883 if (mask & 0x10)
884 {
885 sp -= 4;
886 store_mem (sp, 4, State.regs[REG_A0 + 3]);
887 }
888
889 if (mask & 0x8)
890 {
891 sp -= 4;
892 store_mem (sp, 4, State.regs[REG_D0]);
893 sp -= 4;
894 store_mem (sp, 4, State.regs[REG_D0 + 1]);
895 sp -= 4;
896 store_mem (sp, 4, State.regs[REG_A0]);
897 sp -= 4;
898 store_mem (sp, 4, State.regs[REG_A0 + 1]);
899 sp -= 4;
900 store_mem (sp, 4, State.regs[REG_MDR]);
901 sp -= 4;
902 store_mem (sp, 4, State.regs[REG_LIR]);
903 sp -= 4;
904 store_mem (sp, 4, State.regs[REG_LAR]);
905 sp -= 4;
906 }
907
908 /* And make sure to update the stack pointer. */
909 State.regs[REG_SP] = sp;
910 }
911
912 /* clr dn */
913 void OP_0 ()
914 {
915 State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
916
917 PSW |= PSW_Z;
918 PSW &= ~(PSW_V | PSW_C | PSW_N);
919 }
920
921 /* add dm,dn */
922 void OP_E0 ()
923 {
924 int z, c, n, v;
925 unsigned long reg1, reg2, value;
926
927 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
928 reg2 = State.regs[REG_D0 + (insn & 0x3)];
929 value = reg1 + reg2;
930 State.regs[REG_D0 + (insn & 0x3)] = value;
931
932 z = (value == 0);
933 n = (value & 0x80000000);
934 c = (reg1 < reg2);
935 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
936 && (reg2 & 0x80000000) != (value & 0x80000000));
937
938 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
939 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
940 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
941 }
942
943 /* add dm, an */
944 void OP_F160 ()
945 {
946 int z, c, n, v;
947 unsigned long reg1, reg2, value;
948
949 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
950 reg2 = State.regs[REG_A0 + (insn & 0x3)];
951 value = reg1 + reg2;
952 State.regs[REG_A0 + (insn & 0x3)] = value;
953
954 z = (value == 0);
955 n = (value & 0x80000000);
956 c = (reg1 < reg2);
957 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
958 && (reg2 & 0x80000000) != (value & 0x80000000));
959
960 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
961 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
962 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
963 }
964
965 /* add am, dn */
966 void OP_F150 ()
967 {
968 int z, c, n, v;
969 unsigned long reg1, reg2, value;
970
971 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
972 reg2 = State.regs[REG_D0 + (insn & 0x3)];
973 value = reg1 + reg2;
974 State.regs[REG_D0 + (insn & 0x3)] = value;
975
976 z = (value == 0);
977 n = (value & 0x80000000);
978 c = (reg1 < reg2);
979 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
980 && (reg2 & 0x80000000) != (value & 0x80000000));
981
982 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
983 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
984 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
985 }
986
987 /* add am,an */
988 void OP_F170 ()
989 {
990 int z, c, n, v;
991 unsigned long reg1, reg2, value;
992
993 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
994 reg2 = State.regs[REG_A0 + (insn & 0x3)];
995 value = reg1 + reg2;
996 State.regs[REG_A0 + (insn & 0x3)] = value;
997
998 z = (value == 0);
999 n = (value & 0x80000000);
1000 c = (reg1 < reg2);
1001 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1002 && (reg2 & 0x80000000) != (value & 0x80000000));
1003
1004 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1005 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1006 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1007 }
1008
1009 /* add imm8, dn */
1010 void OP_2800 ()
1011 {
1012 int z, c, n, v;
1013 unsigned long reg1, imm, value;
1014
1015 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1016 imm = SEXT8 (insn & 0xff);
1017 value = reg1 + imm;
1018 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = value;
1019
1020 z = (value == 0);
1021 n = (value & 0x80000000);
1022 c = (reg1 < imm);
1023 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1024 && (reg1 & 0x80000000) != (value & 0x80000000));
1025
1026 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1027 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1028 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1029 }
1030
1031 /* add imm16, dn */
1032 void OP_FAC00000 ()
1033 {
1034 int z, c, n, v;
1035 unsigned long reg1, imm, value;
1036
1037 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1038 imm = SEXT16 (insn & 0xffff);
1039 value = reg1 + imm;
1040 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1041
1042 z = (value == 0);
1043 n = (value & 0x80000000);
1044 c = (reg1 < imm);
1045 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1046 && (reg1 & 0x80000000) != (value & 0x80000000));
1047
1048 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1049 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1050 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1051 }
1052
1053 /* add imm32,dn */
1054 void OP_FCC00000 ()
1055 {
1056 int z, c, n, v;
1057 unsigned long reg1, imm, value;
1058
1059 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1060 imm = ((insn & 0xffff) << 16) | extension;
1061 value = reg1 + imm;
1062 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1063
1064 z = (value == 0);
1065 n = (value & 0x80000000);
1066 c = (reg1 < imm);
1067 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1068 && (reg1 & 0x80000000) != (value & 0x80000000));
1069
1070 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1071 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1072 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1073 }
1074
1075 /* add imm8, an */
1076 void OP_2000 ()
1077 {
1078 int z, c, n, v;
1079 unsigned long reg1, imm, value;
1080
1081 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1082 imm = SEXT8 (insn & 0xff);
1083 value = reg1 + imm;
1084 State.regs[REG_A0 + ((insn & 0x300) >> 8)] = value;
1085
1086 z = (value == 0);
1087 n = (value & 0x80000000);
1088 c = (reg1 < imm);
1089 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1090 && (reg1 & 0x80000000) != (value & 0x80000000));
1091
1092 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1093 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1094 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1095 }
1096
1097 /* add imm16, an */
1098 void OP_FAD00000 ()
1099 {
1100 int z, c, n, v;
1101 unsigned long reg1, imm, value;
1102
1103 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1104 imm = SEXT16 (insn & 0xffff);
1105 value = reg1 + imm;
1106 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1107
1108 z = (value == 0);
1109 n = (value & 0x80000000);
1110 c = (reg1 < imm);
1111 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1112 && (reg1 & 0x80000000) != (value & 0x80000000));
1113
1114 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1115 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1116 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1117 }
1118
1119 /* add imm32, an */
1120 void OP_FCD00000 ()
1121 {
1122 int z, c, n, v;
1123 unsigned long reg1, imm, value;
1124
1125 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1126 imm = ((insn & 0xffff) << 16) | extension;
1127 value = reg1 + imm;
1128 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1129
1130 z = (value == 0);
1131 n = (value & 0x80000000);
1132 c = (reg1 < imm);
1133 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1134 && (reg1 & 0x80000000) != (value & 0x80000000));
1135
1136 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1137 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1138 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1139 }
1140
1141 /* add imm8, sp */
1142 void OP_F8FE00 ()
1143 {
1144 int z, c, n, v;
1145 unsigned long reg1, imm, value;
1146
1147 reg1 = State.regs[REG_SP];
1148 imm = SEXT8 (insn & 0xff);
1149 value = reg1 + imm;
1150 State.regs[REG_SP] = value;
1151 }
1152
1153 /* add imm16,sp */
1154 void OP_FAFE0000 ()
1155 {
1156 int z, c, n, v;
1157 unsigned long reg1, imm, value;
1158
1159 reg1 = State.regs[REG_SP];
1160 imm = SEXT16 (insn & 0xffff);
1161 value = reg1 + imm;
1162 State.regs[REG_SP] = value;
1163 }
1164
1165 /* add imm32, sp */
1166 void OP_FCFE0000 ()
1167 {
1168 int z, c, n, v;
1169 unsigned long reg1, imm, value;
1170
1171 reg1 = State.regs[REG_SP];
1172 imm = ((insn & 0xffff) << 16) | extension;
1173 value = reg1 + imm;
1174 State.regs[REG_SP] = value;
1175 }
1176
1177 /* addc dm,dn */
1178 void OP_F140 ()
1179 {
1180 int z, c, n, v;
1181 unsigned long reg1, reg2, value;
1182
1183 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1184 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1185 value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1186 State.regs[REG_D0 + (insn & 0x3)] = value;
1187
1188 z = (value == 0);
1189 n = (value & 0x80000000);
1190 c = (reg1 < reg2);
1191 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1192 && (reg2 & 0x80000000) != (value & 0x80000000));
1193
1194 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1195 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1196 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1197 }
1198
1199 /* sub dm, dn */
1200 void OP_F100 ()
1201 {
1202 int z, c, n, v;
1203 unsigned long reg1, reg2, value;
1204
1205 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1206 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1207 value = reg2 - reg1;
1208
1209 z = (value == 0);
1210 n = (value & 0x80000000);
1211 c = (reg1 > reg2);
1212 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1213 && (reg2 & 0x80000000) != (value & 0x80000000));
1214
1215 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1216 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1217 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1218 State.regs[REG_D0 + (insn & 0x3)] = value;
1219 }
1220
1221 /* sub dm, an */
1222 void OP_F120 ()
1223 {
1224 int z, c, n, v;
1225 unsigned long reg1, reg2, value;
1226
1227 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1228 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1229 value = reg2 - reg1;
1230
1231 z = (value == 0);
1232 n = (value & 0x80000000);
1233 c = (reg1 > reg2);
1234 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1235 && (reg2 & 0x80000000) != (value & 0x80000000));
1236
1237 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1238 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1239 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1240 State.regs[REG_A0 + (insn & 0x3)] = value;
1241 }
1242
1243 /* sub am, dn */
1244 void OP_F110 ()
1245 {
1246 int z, c, n, v;
1247 unsigned long reg1, reg2, value;
1248
1249 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1250 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1251 value = reg2 - reg1;
1252
1253 z = (value == 0);
1254 n = (value & 0x80000000);
1255 c = (reg1 > reg2);
1256 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1257 && (reg2 & 0x80000000) != (value & 0x80000000));
1258
1259 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1260 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1261 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1262 State.regs[REG_D0 + (insn & 0x3)] = value;
1263 }
1264
1265 /* sub am, an */
1266 void OP_F130 ()
1267 {
1268 int z, c, n, v;
1269 unsigned long reg1, reg2, value;
1270
1271 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1272 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1273 value = reg2 - reg1;
1274
1275 z = (value == 0);
1276 n = (value & 0x80000000);
1277 c = (reg1 > reg2);
1278 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1279 && (reg2 & 0x80000000) != (value & 0x80000000));
1280
1281 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1282 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1283 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1284 State.regs[REG_A0 + (insn & 0x3)] = value;
1285 }
1286
1287 /* sub imm32, dn */
1288 void OP_FCC40000 ()
1289 {
1290 int z, c, n, v;
1291 unsigned long reg1, imm, value;
1292
1293 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1294 imm = ((insn & 0xffff) << 16) | extension;
1295 value = reg1 - imm;
1296
1297 z = (value == 0);
1298 n = (value & 0x80000000);
1299 c = (reg1 < imm);
1300 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1301 && (reg1 & 0x80000000) != (value & 0x80000000));
1302
1303 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1304 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1305 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1306 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1307 }
1308
1309 /* sub imm32, an */
1310 void OP_FCD40000 ()
1311 {
1312 int z, c, n, v;
1313 unsigned long reg1, imm, value;
1314
1315 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1316 imm = ((insn & 0xffff) << 16) | extension;
1317 value = reg1 - imm;
1318
1319 z = (value == 0);
1320 n = (value & 0x80000000);
1321 c = (reg1 < imm);
1322 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1323 && (reg1 & 0x80000000) != (value & 0x80000000));
1324
1325 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1326 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1327 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1328 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1329 }
1330
1331 /* subc dm, dn */
1332 void OP_F180 ()
1333 {
1334 int z, c, n, v;
1335 unsigned long reg1, reg2, value;
1336
1337 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1338 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1339 value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1340
1341 z = (value == 0);
1342 n = (value & 0x80000000);
1343 c = (reg1 > reg2);
1344 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1345 && (reg2 & 0x80000000) != (value & 0x80000000));
1346
1347 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1348 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1349 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1350 State.regs[REG_D0 + (insn & 0x3)] = value;
1351 }
1352
1353 /* mul dm, dn */
1354 void OP_F240 ()
1355 {
1356 unsigned long long temp;
1357 int n, z;
1358
1359 temp = (State.regs[REG_D0 + (insn & 0x3)]
1360 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1361 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1362 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1363 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1364 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1365 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1366 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1367 }
1368
1369 /* mulu dm, dn */
1370 void OP_F250 ()
1371 {
1372 unsigned long long temp;
1373 int n, z;
1374
1375 temp = (State.regs[REG_D0 + (insn & 0x3)]
1376 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1377 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1378 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1379 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1380 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1381 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1382 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1383 }
1384
1385 /* div dm, dn */
1386 void OP_F260 ()
1387 {
1388 long long temp;
1389 int n, z;
1390
1391 temp = State.regs[REG_MDR];
1392 temp <<= 32;
1393 temp |= State.regs[REG_D0 + (insn & 0x3)];
1394 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1395 temp /= (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1396 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1397 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1398 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1399 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1400 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1401 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1402 }
1403
1404 /* divu dm, dn */
1405 void OP_F270 ()
1406 {
1407 unsigned long long temp;
1408 int n, z;
1409
1410 temp = State.regs[REG_MDR];
1411 temp <<= 32;
1412 temp |= State.regs[REG_D0 + (insn & 0x3)];
1413 State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1414 temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1415 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1416 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1417 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1418 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1419 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1420 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1421 }
1422
1423 /* inc dn */
1424 void OP_40 ()
1425 {
1426 int z,n,c,v;
1427 unsigned int value, imm, reg1;
1428
1429 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1430 imm = 1;
1431 value = reg1 + imm;
1432 State.regs[REG_D0 + ((insn & 0xc) >> 2)] = value;
1433
1434 z = (value == 0);
1435 n = (value & 0x80000000);
1436 c = (reg1 < imm);
1437 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1438 && (reg1 & 0x80000000) != (value & 0x80000000));
1439
1440 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1441 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1442 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1443 }
1444
1445 /* inc an */
1446 void OP_41 ()
1447 {
1448 State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
1449 }
1450
1451 /* inc4 an */
1452 void OP_50 ()
1453 {
1454 State.regs[REG_A0 + (insn & 0x3)] += 4;
1455 }
1456
1457 /* cmp imm8, dn */
1458 void OP_A000 ()
1459 {
1460 int z, c, n, v;
1461 unsigned long reg1, imm, value;
1462
1463 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1464 imm = SEXT8 (insn & 0xff);
1465 value = reg1 - imm;
1466
1467 z = (value == 0);
1468 n = (value & 0x80000000);
1469 c = (reg1 < imm);
1470 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1471 && (reg1 & 0x80000000) != (value & 0x80000000));
1472
1473 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1474 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1475 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1476 }
1477
1478 /* cmp dm, dn */
1479 void OP_A0 ()
1480 {
1481 int z, c, n, v;
1482 unsigned long reg1, reg2, value;
1483
1484 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1485 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1486 value = reg2 - reg1;
1487
1488 z = (value == 0);
1489 n = (value & 0x80000000);
1490 c = (reg1 > reg2);
1491 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1492 && (reg2 & 0x80000000) != (value & 0x80000000));
1493
1494 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1495 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1496 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1497 }
1498
1499 /* cmp dm, an */
1500 void OP_F1A0 ()
1501 {
1502 int z, c, n, v;
1503 unsigned long reg1, reg2, value;
1504
1505 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1506 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1507 value = reg2 - reg1;
1508
1509 z = (value == 0);
1510 n = (value & 0x80000000);
1511 c = (reg1 > reg2);
1512 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1513 && (reg2 & 0x80000000) != (value & 0x80000000));
1514
1515 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1516 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1517 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1518 }
1519
1520 /* cmp am, dn */
1521 void OP_F190 ()
1522 {
1523 int z, c, n, v;
1524 unsigned long reg1, reg2, value;
1525
1526 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1527 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1528 value = reg2 - reg1;
1529
1530 z = (value == 0);
1531 n = (value & 0x80000000);
1532 c = (reg1 > reg2);
1533 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1534 && (reg2 & 0x80000000) != (value & 0x80000000));
1535
1536 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1537 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1538 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1539 }
1540
1541 /* cmp imm8, an */
1542 void OP_B000 ()
1543 {
1544 int z, c, n, v;
1545 unsigned long reg1, imm, value;
1546
1547 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1548 imm = insn & 0xff;
1549 value = reg1 - imm;
1550
1551 z = (value == 0);
1552 n = (value & 0x80000000);
1553 c = (reg1 < imm);
1554 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1555 && (reg1 & 0x80000000) != (value & 0x80000000));
1556
1557 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1558 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1559 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1560 }
1561
1562 /* cmp am, an */
1563 void OP_B0 ()
1564 {
1565 int z, c, n, v;
1566 unsigned long reg1, reg2, value;
1567
1568 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1569 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1570 value = reg2 - reg1;
1571
1572 z = (value == 0);
1573 n = (value & 0x80000000);
1574 c = (reg1 > reg2);
1575 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1576 && (reg2 & 0x80000000) != (value & 0x80000000));
1577
1578 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1579 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1580 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1581 }
1582
1583 /* cmp imm16, dn */
1584 void OP_FAC80000 ()
1585 {
1586 int z, c, n, v;
1587 unsigned long reg1, imm, value;
1588
1589 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1590 imm = SEXT16 (insn & 0xffff);
1591 value = reg1 - imm;
1592
1593 z = (value == 0);
1594 n = (value & 0x80000000);
1595 c = (reg1 < imm);
1596 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1597 && (reg1 & 0x80000000) != (value & 0x80000000));
1598
1599 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1600 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1601 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1602 }
1603
1604 /* cmp imm32, dn */
1605 void OP_FCC80000 ()
1606 {
1607 int z, c, n, v;
1608 unsigned long reg1, imm, value;
1609
1610 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1611 imm = ((insn & 0xffff) << 16) | extension;
1612 value = reg1 - imm;
1613
1614 z = (value == 0);
1615 n = (value & 0x80000000);
1616 c = (reg1 < imm);
1617 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1618 && (reg1 & 0x80000000) != (value & 0x80000000));
1619
1620 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1621 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1622 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1623 }
1624
1625 /* cmp imm16, an */
1626 void OP_FAD80000 ()
1627 {
1628 int z, c, n, v;
1629 unsigned long reg1, imm, value;
1630
1631 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1632 imm = insn & 0xffff;
1633 value = reg1 - imm;
1634
1635 z = (value == 0);
1636 n = (value & 0x80000000);
1637 c = (reg1 < imm);
1638 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1639 && (reg1 & 0x80000000) != (value & 0x80000000));
1640
1641 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1642 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1643 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1644 }
1645
1646 /* cmp imm32, an */
1647 void OP_FCD80000 ()
1648 {
1649 int z, c, n, v;
1650 unsigned long reg1, imm, value;
1651
1652 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1653 imm = ((insn & 0xffff) << 16) | extension;
1654 value = reg1 - imm;
1655
1656 z = (value == 0);
1657 n = (value & 0x80000000);
1658 c = (reg1 < imm);
1659 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1660 && (reg1 & 0x80000000) != (value & 0x80000000));
1661
1662 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1663 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1664 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1665 }
1666
1667 /* and dm, dn */
1668 void OP_F200 ()
1669 {
1670 int n, z;
1671
1672 State.regs[REG_D0 + (insn & 0x3)] &= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1673 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1674 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1675 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1676 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1677 }
1678
1679 /* and imm8, dn */
1680 void OP_F8E000 ()
1681 {
1682 int n, z;
1683
1684 State.regs[REG_D0 + ((insn & 0x300) >> 8)] &= (insn & 0xff);
1685 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1686 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
1687 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1688 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1689 }
1690
1691 /* and imm16, dn */
1692 void OP_FAE00000 ()
1693 {
1694 int n, z;
1695
1696 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] &= (insn & 0xffff);
1697 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1698 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1699 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1700 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1701 }
1702
1703 /* and imm32, dn */
1704 void OP_FCE00000 ()
1705 {
1706 int n, z;
1707
1708 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1709 &= ((insn & 0xffff) << 16 | extension);
1710 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1711 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1712 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1713 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1714 }
1715
1716 /* and imm16, psw */
1717 void OP_FAFC0000 ()
1718 {
1719 PSW &= (insn & 0xffff);
1720 }
1721
1722 /* or dm, dn*/
1723 void OP_F210 ()
1724 {
1725 int n, z;
1726
1727 State.regs[REG_D0 + (insn & 0x3)] |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1728 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1729 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1730 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1731 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1732 }
1733
1734 /* or imm8, dn */
1735 void OP_F8E400 ()
1736 {
1737 int n, z;
1738
1739 State.regs[REG_D0 + ((insn & 0x300) >> 8)] |= insn & 0xff;
1740 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1741 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
1742 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1743 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1744 }
1745
1746 /* or imm16, dn*/
1747 void OP_FAE40000 ()
1748 {
1749 int n, z;
1750
1751 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] |= insn & 0xffff;
1752 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1753 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1754 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1755 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1756 }
1757
1758 /* or imm32, dn */
1759 void OP_FCE40000 ()
1760 {
1761 int n, z;
1762
1763 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1764 |= ((insn & 0xffff) << 16 | extension);
1765 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1766 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1767 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1768 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1769 }
1770
1771 /* or imm16,psw */
1772 void OP_FAFD0000 ()
1773 {
1774 PSW |= (insn & 0xffff);
1775 }
1776
1777 /* xor dm, dn*/
1778 void OP_F220 ()
1779 {
1780 int n, z;
1781
1782 State.regs[REG_D0 + (insn & 0x3)] ^= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1783 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1784 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1785 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1786 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1787 }
1788
1789 /* xor imm16, dn */
1790 void OP_FAE80000 ()
1791 {
1792 int n, z;
1793
1794 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] ^= insn & 0xffff;
1795 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1796 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1797 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1798 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1799 }
1800
1801 /* xor imm32, dn */
1802 void OP_FCE80000 ()
1803 {
1804 int n, z;
1805
1806 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1807 ^= ((insn & 0xffff) << 16 | extension);
1808 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1809 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1810 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1811 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1812 }
1813
1814 /* not dn */
1815 void OP_F230 ()
1816 {
1817 int n, z;
1818
1819 State.regs[REG_D0 + (insn & 0x3)] = ~State.regs[REG_D0 + (insn & 0x3)];
1820 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1821 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1822 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1823 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1824 }
1825
1826 /* btst imm8, dn */
1827 void OP_F8EC00 ()
1828 {
1829 unsigned long temp;
1830 int z, n;
1831
1832 temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1833 temp &= (insn & 0xff);
1834 n = (temp & 0x80000000) != 0;
1835 z = (temp == 0);
1836 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1837 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1838 }
1839
1840 /* btst imm16, dn */
1841 void OP_FAEC0000 ()
1842 {
1843 unsigned long temp;
1844 int z, n;
1845
1846 temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1847 temp &= (insn & 0xffff);
1848 n = (temp & 0x80000000) != 0;
1849 z = (temp == 0);
1850 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1851 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1852 }
1853
1854 /* btst imm32, dn */
1855 void OP_FCEC0000 ()
1856 {
1857 unsigned long temp;
1858 int z, n;
1859
1860 temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1861 temp &= ((insn & 0xffff) << 16 | extension);
1862 n = (temp & 0x80000000) != 0;
1863 z = (temp == 0);
1864 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1865 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1866 }
1867
1868 /* btst imm8,(abs32) */
1869 void OP_FE020000 ()
1870 {
1871 unsigned long temp;
1872 int n, z;
1873
1874 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
1875 temp &= (extension & 0xff);
1876 n = (temp & 0x80000000) != 0;
1877 z = (temp == 0);
1878 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1879 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1880 }
1881
1882 /* btst imm8,(d8,an) */
1883 void OP_FAF80000 ()
1884 {
1885 unsigned long temp;
1886 int n, z;
1887
1888 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1889 + SEXT8 ((insn & 0xff00) >> 8)), 1);
1890 temp &= (insn & 0xff);
1891 n = (temp & 0x80000000) != 0;
1892 z = (temp == 0);
1893 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1894 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1895 }
1896
1897 /* bset dm, (an) */
1898 void OP_F080 ()
1899 {
1900 unsigned long temp;
1901 int z;
1902
1903 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1904 z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1905 temp |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1906 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1907 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1908 PSW |= (z ? PSW_Z : 0);
1909 }
1910
1911 /* bset imm8, (abs32) */
1912 void OP_FE000000 ()
1913 {
1914 unsigned long temp;
1915 int z;
1916
1917 temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
1918 z = (temp & (extension & 0xff)) == 0;
1919 temp |= (extension & 0xff);
1920 store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
1921 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1922 PSW |= (z ? PSW_Z : 0);
1923 }
1924
1925 /* bset imm8,(d8,an) */
1926 void OP_FAF00000 ()
1927 {
1928 unsigned long temp;
1929 int z;
1930
1931 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1932 + SEXT8 ((insn & 0xff00) >> 8)), 1);
1933 z = (temp & (insn & 0xff)) == 0;
1934 temp |= (insn & 0xff);
1935 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
1936 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1937 PSW |= (z ? PSW_Z : 0);
1938 }
1939
1940 /* bclr dm, (an) */
1941 void OP_F090 ()
1942 {
1943 unsigned long temp;
1944 int z;
1945
1946 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1947 z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1948 temp = ~temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1949 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1950 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1951 PSW |= (z ? PSW_Z : 0);
1952 }
1953
1954 /* bclr imm8, (abs32) */
1955 void OP_FE010000 ()
1956 {
1957 unsigned long temp;
1958 int z;
1959
1960 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
1961 z = (temp & (extension & 0xff)) == 0;
1962 temp = ~temp & (extension & 0xff);
1963 store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
1964 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1965 PSW |= (z ? PSW_Z : 0);
1966 }
1967
1968 /* bclr imm8,(d8,an) */
1969 void OP_FAF40000 ()
1970 {
1971 unsigned long temp;
1972 int z;
1973
1974 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1975 + SEXT8 ((insn & 0xff00) >> 8)), 1);
1976 z = (temp & (insn & 0xff)) == 0;
1977 temp = ~temp & (insn & 0xff);
1978 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
1979 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1980 PSW |= (z ? PSW_Z : 0);
1981 }
1982
1983 /* asr dm, dn */
1984 void OP_F2B0 ()
1985 {
1986 long temp;
1987 int z, n, c;
1988
1989 temp = State.regs[REG_D0 + (insn & 0x3)];
1990 c = temp & 1;
1991 temp >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1992 State.regs[REG_D0 + (insn & 0x3)] = temp;
1993 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1994 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1995 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1996 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1997 }
1998
1999 /* asr imm8, dn */
2000 void OP_F8C800 ()
2001 {
2002 long temp;
2003 int z, n, c;
2004
2005 temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
2006 c = temp & 1;
2007 temp >>= (insn & 0xff);
2008 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = temp;
2009 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
2010 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
2011 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2012 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2013 }
2014
2015 /* lsr dm, dn */
2016 void OP_F2A0 ()
2017 {
2018 int z, n, c;
2019
2020 c = State.regs[REG_D0 + (insn & 0x3)] & 1;
2021 State.regs[REG_D0 + (insn & 0x3)]
2022 >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2023 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2024 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2025 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2026 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2027 }
2028
2029 /* lsr dm, dn */
2030 void OP_F8C400 ()
2031 {
2032 int z, n, c;
2033
2034 c = State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 1;
2035 State.regs[REG_D0 + ((insn & 0x300) >> 8)] >>= (insn & 0xff);
2036 z = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] == 0);
2037 n = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] & 0x80000000) != 0;
2038 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2039 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2040 }
2041
2042 /* asl dm, dn */
2043 void OP_F290 ()
2044 {
2045 int n, z;
2046
2047 State.regs[REG_D0 + (insn & 0x3)]
2048 <<= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2049 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2050 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2051 PSW &= ~(PSW_Z | PSW_N);
2052 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2053 }
2054
2055 /* asl imm8, dn */
2056 void OP_F8C000 ()
2057 {
2058 int n, z;
2059
2060 State.regs[REG_D0 + ((insn & 0x300) >> 8)] <<= (insn & 0xff);
2061 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
2062 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
2063 PSW &= ~(PSW_Z | PSW_N);
2064 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2065 }
2066
2067 /* asl2 dn */
2068 void OP_54 ()
2069 {
2070 int n, z;
2071
2072 State.regs[REG_D0 + (insn & 0x3)] <<= 2;
2073 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2074 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2075 PSW &= ~(PSW_Z | PSW_N);
2076 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2077 }
2078
2079 /* ror dn */
2080 void OP_F284 ()
2081 {
2082 unsigned long value;
2083 int c,n,z;
2084
2085 value = State.regs[REG_D0 + (insn & 0x3)];
2086 if (value & 0x1)
2087 c = 1;
2088
2089 value >>= 1;
2090 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2091 State.regs[REG_D0 + (insn & 0x3)] = value;
2092 z = (value == 0);
2093 n = (value & 0x80000000) != 0;
2094 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2095 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2096 }
2097
2098 /* rol dn */
2099 void OP_F280 ()
2100 {
2101 unsigned long value;
2102 int c,n,z;
2103
2104 value = State.regs[REG_D0 + (insn & 0x3)];
2105 if (value & 0x80000000)
2106 c = 1;
2107
2108 value <<= 1;
2109 value |= ((PSW & PSW_C) != 0);
2110 State.regs[REG_D0 + (insn & 0x3)] = value;
2111 z = (value == 0);
2112 n = (value & 0x80000000) != 0;
2113 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2114 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2115 }
2116
2117 /* beq label:8 */
2118 void OP_C800 ()
2119 {
2120 /* The dispatching code will add 2 after we return, so
2121 we subtract two here to make things right. */
2122 if (PSW & PSW_Z)
2123 State.pc += SEXT8 (insn & 0xff) - 2;
2124 }
2125
2126 /* bne label:8 */
2127 void OP_C900 ()
2128 {
2129 /* The dispatching code will add 2 after we return, so
2130 we subtract two here to make things right. */
2131 if (!(PSW & PSW_Z))
2132 State.pc += SEXT8 (insn & 0xff) - 2;
2133 }
2134
2135 /* bgt label:8 */
2136 void OP_C100 ()
2137 {
2138 /* The dispatching code will add 2 after we return, so
2139 we subtract two here to make things right. */
2140 if (!((PSW & PSW_Z)
2141 || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)))
2142 State.pc += SEXT8 (insn & 0xff) - 2;
2143 }
2144
2145 /* bge label:8 */
2146 void OP_C200 ()
2147 {
2148 /* The dispatching code will add 2 after we return, so
2149 we subtract two here to make things right. */
2150 if (!(((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
2151 State.pc += SEXT8 (insn & 0xff) - 2;
2152 }
2153
2154 /* ble label:8 */
2155 void OP_C300 ()
2156 {
2157 /* The dispatching code will add 2 after we return, so
2158 we subtract two here to make things right. */
2159 if ((PSW & PSW_Z)
2160 || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
2161 State.pc += SEXT8 (insn & 0xff) - 2;
2162 }
2163
2164 /* blt label:8 */
2165 void OP_C000 ()
2166 {
2167 /* The dispatching code will add 2 after we return, so
2168 we subtract two here to make things right. */
2169 if (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)
2170 State.pc += SEXT8 (insn & 0xff) - 2;
2171 }
2172
2173 /* bhi label:8 */
2174 void OP_C500 ()
2175 {
2176 /* The dispatching code will add 2 after we return, so
2177 we subtract two here to make things right. */
2178 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2179 State.pc += SEXT8 (insn & 0xff) - 2;
2180 }
2181
2182 /* bcc label:8 */
2183 void OP_C600 ()
2184 {
2185 /* The dispatching code will add 2 after we return, so
2186 we subtract two here to make things right. */
2187 if (!(PSW & PSW_C))
2188 State.pc += SEXT8 (insn & 0xff) - 2;
2189 }
2190
2191 /* bls label:8 */
2192 void OP_C700 ()
2193 {
2194 /* The dispatching code will add 2 after we return, so
2195 we subtract two here to make things right. */
2196 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2197 State.pc += SEXT8 (insn & 0xff) - 2;
2198 }
2199
2200 /* bcs label:8 */
2201 void OP_C400 ()
2202 {
2203 /* The dispatching code will add 2 after we return, so
2204 we subtract two here to make things right. */
2205 if (PSW & PSW_C)
2206 State.pc += SEXT8 (insn & 0xff) - 2;
2207 }
2208
2209 /* bvc label:8 */
2210 void OP_F8E800 ()
2211 {
2212 /* The dispatching code will add 3 after we return, so
2213 we subtract two here to make things right. */
2214 if (!(PSW & PSW_V))
2215 State.pc += SEXT8 (insn & 0xff) - 3;
2216 }
2217
2218 /* bvs label:8 */
2219 void OP_F8E900 ()
2220 {
2221 /* The dispatching code will add 3 after we return, so
2222 we subtract two here to make things right. */
2223 if (PSW & PSW_V)
2224 State.pc += SEXT8 (insn & 0xff) - 3;
2225 }
2226
2227 /* bnc label:8 */
2228 void OP_F8EA00 ()
2229 {
2230 /* The dispatching code will add 3 after we return, so
2231 we subtract two here to make things right. */
2232 if (!(PSW & PSW_N))
2233 State.pc += SEXT8 (insn & 0xff) - 3;
2234 }
2235
2236 /* bns label:8 */
2237 void OP_F8EB00 ()
2238 {
2239 /* The dispatching code will add 3 after we return, so
2240 we subtract two here to make things right. */
2241 if (PSW & PSW_N)
2242 State.pc += SEXT8 (insn & 0xff) - 3;
2243 }
2244
2245 /* bra label:8 */
2246 void OP_CA00 ()
2247 {
2248 /* The dispatching code will add 2 after we return, so
2249 we subtract two here to make things right. */
2250 State.pc += SEXT8 (insn & 0xff) - 2;
2251 }
2252
2253 /* leq */
2254 void OP_D8 ()
2255 {
2256 abort ();
2257 }
2258
2259 /* lne */
2260 void OP_D9 ()
2261 {
2262 abort ();
2263 }
2264
2265 /* lgt */
2266 void OP_D1 ()
2267 {
2268 abort ();
2269 }
2270
2271 /* lge */
2272 void OP_D2 ()
2273 {
2274 abort ();
2275 }
2276
2277 /* lle */
2278 void OP_D3 ()
2279 {
2280 abort ();
2281 }
2282
2283 /* llt */
2284 void OP_D0 ()
2285 {
2286 abort ();
2287 }
2288
2289 /* lhi */
2290 void OP_D5 ()
2291 {
2292 abort ();
2293 }
2294
2295 /* lcc */
2296 void OP_D6 ()
2297 {
2298 abort ();
2299 }
2300
2301 /* lls */
2302 void OP_D7 ()
2303 {
2304 abort ();
2305 }
2306
2307 /* lcs */
2308 void OP_D4 ()
2309 {
2310 abort ();
2311 }
2312
2313 /* lra */
2314 void OP_DA ()
2315 {
2316 abort ();
2317 }
2318
2319 /* setlb */
2320 void OP_DB ()
2321 {
2322 abort ();
2323 }
2324
2325 /* jmp (an) */
2326 void OP_F0F4 ()
2327 {
2328 State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2329 }
2330
2331 /* jmp label:16 */
2332 void OP_CC0000 ()
2333 {
2334 State.pc += SEXT16 (insn & 0xffff) - 3;
2335 }
2336
2337 /* jmp label:32 */
2338 void OP_DC000000 ()
2339 {
2340 State.pc += (((insn & 0xffffff) << 8) | extension) - 5;
2341 }
2342
2343 /* call label:16,reg_list,imm8 */
2344 void OP_CD000000 ()
2345 {
2346 unsigned int next_pc, sp, adjust;
2347 unsigned long mask;
2348
2349 sp = State.regs[REG_SP];
2350 next_pc = State.pc + 2;
2351 State.mem[sp] = next_pc & 0xff;
2352 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2353 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2354 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2355
2356 mask = insn & 0xff;
2357
2358 adjust = 0;
2359 if (mask & 0x80)
2360 {
2361 adjust -= 4;
2362 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2363 }
2364
2365 if (mask & 0x40)
2366 {
2367 adjust -= 4;
2368 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2369 }
2370
2371 if (mask & 0x20)
2372 {
2373 adjust -= 4;
2374 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2375 }
2376
2377 if (mask & 0x10)
2378 {
2379 adjust -= 4;
2380 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2381 }
2382
2383 if (mask & 0x8)
2384 {
2385 adjust -= 4;
2386 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2387 adjust -= 4;
2388 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2389 adjust -= 4;
2390 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2391 adjust -= 4;
2392 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2393 adjust -= 4;
2394 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2395 adjust -= 4;
2396 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2397 adjust -= 4;
2398 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2399 adjust -= 4;
2400 }
2401
2402 /* And make sure to update the stack pointer. */
2403 State.regs[REG_SP] -= extension;
2404 State.regs[REG_MDR] = next_pc;
2405 State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2406 }
2407
2408 /* call label:32,reg_list,imm8*/
2409 void OP_DD000000 ()
2410 {
2411 unsigned int next_pc, sp, adjust;
2412 unsigned long mask;
2413
2414 sp = State.regs[REG_SP];
2415 next_pc = State.pc + 2;
2416 State.mem[sp] = next_pc & 0xff;
2417 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2418 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2419 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2420
2421 mask = (extension & 0xff00) >> 8;
2422
2423 adjust = 0;
2424 if (mask & 0x80)
2425 {
2426 adjust -= 4;
2427 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2428 }
2429
2430 if (mask & 0x40)
2431 {
2432 adjust -= 4;
2433 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2434 }
2435
2436 if (mask & 0x20)
2437 {
2438 adjust -= 4;
2439 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2440 }
2441
2442 if (mask & 0x10)
2443 {
2444 adjust -= 4;
2445 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2446 }
2447
2448 if (mask & 0x8)
2449 {
2450 adjust -= 4;
2451 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2452 adjust -= 4;
2453 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2454 adjust -= 4;
2455 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2456 adjust -= 4;
2457 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2458 adjust -= 4;
2459 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2460 adjust -= 4;
2461 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2462 adjust -= 4;
2463 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2464 adjust -= 4;
2465 }
2466
2467 /* And make sure to update the stack pointer. */
2468 State.regs[REG_SP] -= (extension & 0xff);
2469 State.regs[REG_MDR] = next_pc;
2470 State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2471 }
2472
2473 /* calls (an) */
2474 void OP_F0F0 ()
2475 {
2476 unsigned int next_pc, sp;
2477
2478 sp = State.regs[REG_SP];
2479 next_pc = State.pc + 2;
2480 State.mem[sp] = next_pc & 0xff;
2481 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2482 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2483 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2484 State.regs[REG_MDR] = next_pc;
2485 State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2486 }
2487
2488 /* calls label:16 */
2489 void OP_FAFF0000 ()
2490 {
2491 unsigned int next_pc, sp;
2492
2493 sp = State.regs[REG_SP];
2494 next_pc = State.pc + 4;
2495 State.mem[sp] = next_pc & 0xff;
2496 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2497 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2498 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2499 State.regs[REG_MDR] = next_pc;
2500 State.pc += SEXT16 (insn & 0xffff) - 4;
2501 }
2502
2503 /* calls label:32 */
2504 void OP_FCFF0000 ()
2505 {
2506 unsigned int next_pc, sp;
2507
2508 sp = State.regs[REG_SP];
2509 next_pc = State.pc + 6;
2510 State.mem[sp] = next_pc & 0xff;
2511 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2512 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2513 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2514 State.regs[REG_MDR] = next_pc;
2515 State.pc += (((insn & 0xffff) << 16) | extension) - 6;
2516 }
2517
2518 /* ret reg_list, imm8 */
2519 void OP_DF0000 ()
2520 {
2521 unsigned int sp;
2522 unsigned long mask;
2523
2524 State.regs[REG_SP] += insn & 0xff;
2525 State.pc = State.regs[REG_MDR] - 3;
2526 sp = State.regs[REG_SP];
2527
2528 mask = (insn & 0xff00) >> 8;
2529
2530 if (mask & 0x8)
2531 {
2532 sp += 4;
2533 State.regs[REG_LAR] = load_mem (sp, 4);
2534 sp += 4;
2535 State.regs[REG_LIR] = load_mem (sp, 4);
2536 sp += 4;
2537 State.regs[REG_MDR] = load_mem (sp, 4);
2538 sp += 4;
2539 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2540 sp += 4;
2541 State.regs[REG_A0] = load_mem (sp, 4);
2542 sp += 4;
2543 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2544 sp += 4;
2545 State.regs[REG_D0] = load_mem (sp, 4);
2546 sp += 4;
2547 }
2548
2549 if (mask & 0x10)
2550 {
2551 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2552 sp += 4;
2553 }
2554
2555 if (mask & 0x20)
2556 {
2557 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2558 sp += 4;
2559 }
2560
2561 if (mask & 0x40)
2562 {
2563 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2564 sp += 4;
2565 }
2566
2567 if (mask & 0x80)
2568 {
2569 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2570 sp += 4;
2571 }
2572 }
2573
2574 /* retf reg_list,imm8 */
2575 void OP_DE0000 ()
2576 {
2577 unsigned int sp;
2578 unsigned long mask;
2579
2580 State.regs[REG_SP] += insn & 0xff;
2581 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2582 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2583 State.pc -= 3;
2584
2585 sp = State.regs[REG_SP];
2586
2587 mask = (insn & 0xff00) >> 8;
2588
2589 if (mask & 0x8)
2590 {
2591 sp += 4;
2592 State.regs[REG_LAR] = load_mem (sp, 4);
2593 sp += 4;
2594 State.regs[REG_LIR] = load_mem (sp, 4);
2595 sp += 4;
2596 State.regs[REG_MDR] = load_mem (sp, 4);
2597 sp += 4;
2598 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2599 sp += 4;
2600 State.regs[REG_A0] = load_mem (sp, 4);
2601 sp += 4;
2602 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2603 sp += 4;
2604 State.regs[REG_D0] = load_mem (sp, 4);
2605 sp += 4;
2606 }
2607
2608 if (mask & 0x10)
2609 {
2610 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2611 sp += 4;
2612 }
2613
2614 if (mask & 0x20)
2615 {
2616 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2617 sp += 4;
2618 }
2619
2620 if (mask & 0x40)
2621 {
2622 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2623 sp += 4;
2624 }
2625
2626 if (mask & 0x80)
2627 {
2628 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2629 sp += 4;
2630 }
2631 }
2632
2633 /* rets */
2634 void OP_F0FC ()
2635 {
2636 unsigned int sp;
2637
2638 sp = State.regs[REG_SP];
2639 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2640 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2641 State.pc -= 2;
2642 }
2643
2644 /* rti */
2645 void OP_F0FD ()
2646 {
2647 abort ();
2648 }
2649
2650 /* trap */
2651 void OP_F0FE ()
2652 {
2653 /* We use this for simulated system calls; we may need to change
2654 it to a reserved instruction if we conflict with uses at
2655 Matsushita. */
2656 int save_errno = errno;
2657 errno = 0;
2658
2659 /* Registers passed to trap 0 */
2660
2661 /* Function number. */
2662 #define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
2663
2664 /* Parameters. */
2665 #define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
2666 #define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2667 #define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2668
2669 /* Registers set by trap 0 */
2670
2671 #define RETVAL State.regs[0] /* return value */
2672 #define RETERR State.regs[1] /* return error code */
2673
2674 /* Turn a pointer in a register into a pointer into real memory. */
2675
2676 #define MEMPTR(x) (State.mem + x)
2677
2678 switch (FUNC)
2679 {
2680 #if !defined(__GO32__) && !defined(_WIN32)
2681 case SYS_fork:
2682 RETVAL = fork ();
2683 break;
2684 case SYS_execve:
2685 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2686 (char **)MEMPTR (PARM3));
2687 break;
2688 case SYS_execv:
2689 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2690 break;
2691 #endif
2692
2693 case SYS_read:
2694 RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
2695 MEMPTR (PARM2), PARM3);
2696 break;
2697 case SYS_write:
2698 if (PARM1 == 1)
2699 RETVAL = (int)mn10300_callback->write_stdout (mn10300_callback,
2700 MEMPTR (PARM2), PARM3);
2701 else
2702 RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
2703 MEMPTR (PARM2), PARM3);
2704 break;
2705 case SYS_lseek:
2706 RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
2707 break;
2708 case SYS_close:
2709 RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
2710 break;
2711 case SYS_open:
2712 RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
2713 break;
2714 case SYS_exit:
2715 /* EXIT - caller can look in PARM1 to work out the
2716 reason */
2717 if (PARM1 == 0xdead || PARM1 == 0x1)
2718 State.exception = SIGABRT;
2719 else
2720 State.exception = SIGQUIT;
2721 break;
2722
2723 case SYS_stat: /* added at hmsi */
2724 /* stat system call */
2725 {
2726 struct stat host_stat;
2727 reg_t buf;
2728
2729 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2730
2731 buf = PARM2;
2732
2733 /* Just wild-assed guesses. */
2734 store_mem (buf, 2, host_stat.st_dev);
2735 store_mem (buf + 2, 2, host_stat.st_ino);
2736 store_mem (buf + 4, 4, host_stat.st_mode);
2737 store_mem (buf + 8, 2, host_stat.st_nlink);
2738 store_mem (buf + 10, 2, host_stat.st_uid);
2739 store_mem (buf + 12, 2, host_stat.st_gid);
2740 store_mem (buf + 14, 2, host_stat.st_rdev);
2741 store_mem (buf + 16, 4, host_stat.st_size);
2742 store_mem (buf + 20, 4, host_stat.st_atime);
2743 store_mem (buf + 28, 4, host_stat.st_mtime);
2744 store_mem (buf + 36, 4, host_stat.st_ctime);
2745 }
2746 break;
2747
2748 case SYS_chown:
2749 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2750 break;
2751 case SYS_chmod:
2752 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2753 break;
2754 case SYS_time:
2755 RETVAL = time (MEMPTR (PARM1));
2756 break;
2757 case SYS_times:
2758 {
2759 struct tms tms;
2760 RETVAL = times (&tms);
2761 store_mem (PARM1, 4, tms.tms_utime);
2762 store_mem (PARM1 + 4, 4, tms.tms_stime);
2763 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2764 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2765 break;
2766 }
2767 case SYS_gettimeofday:
2768 {
2769 struct timeval t;
2770 struct timezone tz;
2771 RETVAL = gettimeofday (&t, &tz);
2772 store_mem (PARM1, 4, t.tv_sec);
2773 store_mem (PARM1 + 4, 4, t.tv_usec);
2774 store_mem (PARM2, 4, tz.tz_minuteswest);
2775 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2776 break;
2777 }
2778 case SYS_utime:
2779 /* Cast the second argument to void *, to avoid type mismatch
2780 if a prototype is present. */
2781 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2782 break;
2783 default:
2784 abort ();
2785 }
2786 RETERR = errno;
2787 errno = save_errno;
2788 }
2789
2790 /* rtm */
2791 void OP_F0FF ()
2792 {
2793 abort ();
2794 }
2795
2796 /* nop */
2797 void OP_CB ()
2798 {
2799 }
2800
2801 /* putx */
2802 void OP_F500 ()
2803 {
2804 }
2805
2806 /* getx */
2807 void OP_F6F0 ()
2808 {
2809 }
2810
2811 /* mulq */
2812 void OP_F600 ()
2813 {
2814 }
2815
2816 /* mulq */
2817 void OP_F90000 ()
2818 {
2819 }
2820
2821 /* mulq */
2822 void OP_FB000000 ()
2823 {
2824 }
2825
2826 /* mulq */
2827 void OP_FD000000 ()
2828 {
2829 }
2830
2831 /* mulqu */
2832 void OP_F610 ()
2833 {
2834 }
2835
2836 /* mulqu */
2837 void OP_F91400 ()
2838 {
2839 }
2840
2841 /* mulqu */
2842 void OP_FB140000 ()
2843 {
2844 }
2845
2846 /* mulqu */
2847 void OP_FD140000 ()
2848 {
2849 }
2850
2851 /* sat16 */
2852 void OP_F640 ()
2853 {
2854 }
2855
2856 /* sat24 */
2857 void OP_F650 ()
2858 {
2859 }
2860
2861 /* bsch */
2862 void OP_F670 ()
2863 {
2864 }
GDB Binutils - Deliverables
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