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* simops.c (syscall): Handle new mn10300 calling conventions.
[deliverable/binutils-gdb.git] / sim / mn10300 / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #ifdef HAVE_UNISTD_H
5 #include <unistd.h>
6 #endif
7 #include "mn10300_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10 #include "bfd.h"
11 #include <errno.h>
12 #include <sys/stat.h>
13 #include <sys/times.h>
14 #include <sys/time.h>
15
16 #define REG0(X) ((X) & 0x3)
17 #define REG1(X) (((X) & 0xc) >> 2)
18 #define REG0_4(X) (((X) & 0x30) >> 4)
19 #define REG0_8(X) (((X) & 0x300) >> 8)
20 #define REG1_8(X) (((X) & 0xc00) >> 10)
21 #define REG0_16(X) (((X) & 0x30000) >> 16)
22 #define REG1_16(X) (((X) & 0xc0000) >> 18)
23 \f
24 /* mov imm8, dn */
25 void OP_8000 (insn, extension)
26 unsigned long insn, extension;
27 {
28 State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff);
29 }
30
31 /* mov dm, dn */
32 void OP_80 (insn, extension)
33 unsigned long insn, extension;
34 {
35 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
36 }
37
38 /* mov dm, an */
39 void OP_F1E0 (insn, extension)
40 unsigned long insn, extension;
41 {
42 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
43 }
44
45 /* mov am, dn */
46 void OP_F1D0 (insn, extension)
47 unsigned long insn, extension;
48 {
49 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
50 }
51
52 /* mov imm8, an */
53 void OP_9000 (insn, extension)
54 unsigned long insn, extension;
55 {
56 State.regs[REG_A0 + REG0_8 (insn)] = insn & 0xff;
57 }
58
59 /* mov am, an */
60 void OP_90 (insn, extension)
61 unsigned long insn, extension;
62 {
63 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
64 }
65
66 /* mov sp, an */
67 void OP_3C (insn, extension)
68 unsigned long insn, extension;
69 {
70 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_SP];
71 }
72
73 /* mov am, sp */
74 void OP_F2F0 (insn, extension)
75 unsigned long insn, extension;
76 {
77 State.regs[REG_SP] = State.regs[REG_A0 + REG1 (insn)];
78 }
79
80 /* mov psw, dn */
81 void OP_F2E4 (insn, extension)
82 unsigned long insn, extension;
83 {
84 State.regs[REG_D0 + REG0 (insn)] = PSW;
85 }
86
87 /* mov dm, psw */
88 void OP_F2F3 (insn, extension)
89 unsigned long insn, extension;
90 {
91 PSW = State.regs[REG_D0 + REG1 (insn)];
92 }
93
94 /* mov mdr, dn */
95 void OP_F2E0 (insn, extension)
96 unsigned long insn, extension;
97 {
98 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDR];
99 }
100
101 /* mov dm, mdr */
102 void OP_F2F2 (insn, extension)
103 unsigned long insn, extension;
104 {
105 State.regs[REG_MDR] = State.regs[REG_D0 + REG1 (insn)];
106 }
107
108 /* mov (am), dn */
109 void OP_70 (insn, extension)
110 unsigned long insn, extension;
111 {
112 State.regs[REG_D0 + REG1 (insn)]
113 = load_mem (State.regs[REG_A0 + REG0 (insn)], 4);
114 }
115
116 /* mov (d8,am), dn */
117 void OP_F80000 (insn, extension)
118 unsigned long insn, extension;
119 {
120 State.regs[REG_D0 + REG1_8 (insn)]
121 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
122 + SEXT8 (insn & 0xff)), 4);
123 }
124
125 /* mov (d16,am), dn */
126 void OP_FA000000 (insn, extension)
127 unsigned long insn, extension;
128 {
129 State.regs[REG_D0 + REG1_16 (insn)]
130 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
131 + SEXT16 (insn & 0xffff)), 4);
132 }
133
134 /* mov (d32,am), dn */
135 void OP_FC000000 (insn, extension)
136 unsigned long insn, extension;
137 {
138 State.regs[REG_D0 + REG1_16 (insn)]
139 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
140 + ((insn & 0xffff) << 16) + extension), 4);
141 }
142
143 /* mov (d8,sp), dn */
144 void OP_5800 (insn, extension)
145 unsigned long insn, extension;
146 {
147 State.regs[REG_D0 + REG0_8 (insn)]
148 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
149 }
150
151 /* mov (d16,sp), dn */
152 void OP_FAB40000 (insn, extension)
153 unsigned long insn, extension;
154 {
155 State.regs[REG_D0 + REG0_16 (insn)]
156 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
157 }
158
159 /* mov (d32,sp), dn */
160 void OP_FCB40000 (insn, extension)
161 unsigned long insn, extension;
162 {
163 State.regs[REG_D0 + REG0_16 (insn)]
164 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
165 }
166
167 /* mov (di,am), dn */
168 void OP_F300 (insn, extension)
169 unsigned long insn, extension;
170 {
171 State.regs[REG_D0 + REG0_4 (insn)]
172 = load_mem ((State.regs[REG_A0 + REG0 (insn)]
173 + State.regs[REG_D0 + REG1 (insn)]), 4);
174 }
175
176 /* mov (abs16), dn */
177 void OP_300000 (insn, extension)
178 unsigned long insn, extension;
179 {
180 State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 4);
181 }
182
183 /* mov (abs32), dn */
184 void OP_FCA40000 (insn, extension)
185 unsigned long insn, extension;
186 {
187 State.regs[REG_D0 + REG0_16 (insn)]
188 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
189 }
190
191 /* mov (am), an */
192 void OP_F000 (insn, extension)
193 unsigned long insn, extension;
194 {
195 State.regs[REG_A0 + REG1 (insn)]
196 = load_mem (State.regs[REG_A0 + REG0 (insn)], 4);
197 }
198
199 /* mov (d8,am), an */
200 void OP_F82000 (insn, extension)
201 unsigned long insn, extension;
202 {
203 State.regs[REG_A0 + REG1_8 (insn)]
204 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
205 + SEXT8 (insn & 0xff)), 4);
206 }
207
208 /* mov (d16,am), an */
209 void OP_FA200000 (insn, extension)
210 unsigned long insn, extension;
211 {
212 State.regs[REG_A0 + REG1_16 (insn)]
213 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
214 + SEXT16 (insn & 0xffff)), 4);
215 }
216
217 /* mov (d32,am), an */
218 void OP_FC200000 (insn, extension)
219 unsigned long insn, extension;
220 {
221 State.regs[REG_A0 + REG1_16 (insn)]
222 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
223 + ((insn & 0xffff) << 16) + extension), 4);
224 }
225
226 /* mov (d8,sp), an */
227 void OP_5C00 (insn, extension)
228 unsigned long insn, extension;
229 {
230 State.regs[REG_A0 + REG0_8 (insn)]
231 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
232 }
233
234 /* mov (d16,sp), an */
235 void OP_FAB00000 (insn, extension)
236 unsigned long insn, extension;
237 {
238 State.regs[REG_A0 + REG0_16 (insn)]
239 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
240 }
241
242 /* mov (d32,sp), an */
243 void OP_FCB00000 (insn, extension)
244 unsigned long insn, extension;
245 {
246 State.regs[REG_A0 + REG0_16 (insn)]
247 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
248 }
249
250 /* mov (di,am), an */
251 void OP_F380 (insn, extension)
252 unsigned long insn, extension;
253 {
254 State.regs[REG_A0 + REG0_4 (insn)]
255 = load_mem ((State.regs[REG_A0 + REG0 (insn)]
256 + State.regs[REG_D0 + REG1 (insn)]), 4);
257 }
258
259 /* mov (abs16), an */
260 void OP_FAA00000 (insn, extension)
261 unsigned long insn, extension;
262 {
263 State.regs[REG_A0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 4);
264 }
265
266 /* mov (abs32), an */
267 void OP_FCA00000 (insn, extension)
268 unsigned long insn, extension;
269 {
270 State.regs[REG_A0 + REG0_16 (insn)]
271 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
272 }
273
274 /* mov (d8,am), sp */
275 void OP_F8F000 (insn, extension)
276 unsigned long insn, extension;
277 {
278 State.regs[REG_SP]
279 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
280 + SEXT8 (insn & 0xff)), 4);
281 }
282
283 /* mov dm, (an) */
284 void OP_60 (insn, extension)
285 unsigned long insn, extension;
286 {
287 store_mem (State.regs[REG_A0 + REG0 (insn)], 4,
288 State.regs[REG_D0 + REG1 (insn)]);
289 }
290
291 /* mov dm, (d8,an) */
292 void OP_F81000 (insn, extension)
293 unsigned long insn, extension;
294 {
295 store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
296 + SEXT8 (insn & 0xff)), 4,
297 State.regs[REG_D0 + REG1_8 (insn)]);
298 }
299
300 /* mov dm (d16,an) */
301 void OP_FA100000 (insn, extension)
302 unsigned long insn, extension;
303 {
304 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
305 + SEXT16 (insn & 0xffff)), 4,
306 State.regs[REG_D0 + REG1_16 (insn)]);
307 }
308
309 /* mov dm (d32,an) */
310 void OP_FC100000 (insn, extension)
311 unsigned long insn, extension;
312 {
313 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
314 + ((insn & 0xffff) << 16) + extension), 4,
315 State.regs[REG_D0 + REG1_16 (insn)]);
316 }
317
318 /* mov dm, (d8,sp) */
319 void OP_4200 (insn, extension)
320 unsigned long insn, extension;
321 {
322 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
323 State.regs[REG_D0 + REG1_8 (insn)]);
324 }
325
326 /* mov dm, (d16,sp) */
327 void OP_FA910000 (insn, extension)
328 unsigned long insn, extension;
329 {
330 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
331 State.regs[REG_D0 + REG1_16 (insn)]);
332 }
333
334 /* mov dm, (d32,sp) */
335 void OP_FC910000 (insn, extension)
336 unsigned long insn, extension;
337 {
338 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
339 State.regs[REG_D0 + REG1_16 (insn)]);
340 }
341
342 /* mov dm, (di,an) */
343 void OP_F340 (insn, extension)
344 unsigned long insn, extension;
345 {
346 store_mem ((State.regs[REG_A0 + REG0 (insn)]
347 + State.regs[REG_D0 + REG1 (insn)]), 4,
348 State.regs[REG_D0 + REG0_4 (insn)]);
349 }
350
351 /* mov dm, (abs16) */
352 void OP_10000 (insn, extension)
353 unsigned long insn, extension;
354 {
355 store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + REG1_16 (insn)]);
356 }
357
358 /* mov dm, (abs32) */
359 void OP_FC810000 (insn, extension)
360 unsigned long insn, extension;
361 {
362 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + REG1_16 (insn)]);
363 }
364
365 /* mov am, (an) */
366 void OP_F010 (insn, extension)
367 unsigned long insn, extension;
368 {
369 store_mem (State.regs[REG_A0 + REG0 (insn)], 4,
370 State.regs[REG_A0 + REG1 (insn)]);
371 }
372
373 /* mov am, (d8,an) */
374 void OP_F83000 (insn, extension)
375 unsigned long insn, extension;
376 {
377 store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
378 + SEXT8 (insn & 0xff)), 4,
379 State.regs[REG_A0 + REG1_8 (insn)]);
380 }
381
382 /* mov am, (d16,an) */
383 void OP_FA300000 (insn, extension)
384 unsigned long insn, extension;
385 {
386 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
387 + SEXT16 (insn & 0xffff)), 4,
388 State.regs[REG_A0 + REG1_16 (insn)]);
389 }
390
391 /* mov am, (d32,an) */
392 void OP_FC300000 (insn, extension)
393 unsigned long insn, extension;
394 {
395 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
396 + ((insn & 0xffff) << 16) + extension), 4,
397 State.regs[REG_A0 + REG1_16 (insn)]);
398 }
399
400 /* mov am, (d8,sp) */
401 void OP_4300 (insn, extension)
402 unsigned long insn, extension;
403 {
404 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
405 State.regs[REG_A0 + REG1_8 (insn)]);
406 }
407
408 /* mov am, (d16,sp) */
409 void OP_FA900000 (insn, extension)
410 unsigned long insn, extension;
411 {
412 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
413 State.regs[REG_A0 + REG1_16 (insn)]);
414 }
415
416 /* mov am, (d32,sp) */
417 void OP_FC900000 (insn, extension)
418 unsigned long insn, extension;
419 {
420 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
421 State.regs[REG_A0 + REG1_16 (insn)]);
422 }
423
424 /* mov am, (di,an) */
425 void OP_F3C0 (insn, extension)
426 unsigned long insn, extension;
427 {
428 store_mem ((State.regs[REG_A0 + REG0 (insn)]
429 + State.regs[REG_D0 + REG1 (insn)]), 4,
430 State.regs[REG_A0 + REG0_4 (insn)]);
431 }
432
433 /* mov am, (abs16) */
434 void OP_FA800000 (insn, extension)
435 unsigned long insn, extension;
436 {
437 store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + REG1_16 (insn)]);
438 }
439
440 /* mov am, (abs32) */
441 void OP_FC800000 (insn, extension)
442 unsigned long insn, extension;
443 {
444 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + REG1_16 (insn)]);
445 }
446
447 /* mov sp, (d8,an) */
448 void OP_F8F400 (insn, extension)
449 unsigned long insn, extension;
450 {
451 store_mem (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff),
452 4, State.regs[REG_SP]);
453 }
454
455 /* mov imm16, dn */
456 void OP_2C0000 (insn, extension)
457 unsigned long insn, extension;
458 {
459 unsigned long value;
460
461 value = SEXT16 (insn & 0xffff);
462 State.regs[REG_D0 + REG0_16 (insn)] = value;
463 }
464
465 /* mov imm32,dn */
466 void OP_FCCC0000 (insn, extension)
467 unsigned long insn, extension;
468 {
469 unsigned long value;
470
471 value = ((insn & 0xffff) << 16) + extension;
472 State.regs[REG_D0 + REG0_16 (insn)] = value;
473 }
474
475 /* mov imm16, an */
476 void OP_240000 (insn, extension)
477 unsigned long insn, extension;
478 {
479 unsigned long value;
480
481 value = insn & 0xffff;
482 State.regs[REG_A0 + REG0_16 (insn)] = value;
483 }
484
485 /* mov imm32, an */
486 void OP_FCDC0000 (insn, extension)
487 unsigned long insn, extension;
488 {
489 unsigned long value;
490
491 value = ((insn & 0xffff) << 16) + extension;
492 State.regs[REG_A0 + REG0_16 (insn)] = value;
493 }
494
495 /* movbu (am), dn */
496 void OP_F040 (insn, extension)
497 unsigned long insn, extension;
498 {
499 State.regs[REG_D0 + REG1 (insn)]
500 = load_mem (State.regs[REG_A0 + REG0 (insn)], 1);
501 }
502
503 /* movbu (d8,am), dn */
504 void OP_F84000 (insn, extension)
505 unsigned long insn, extension;
506 {
507 State.regs[REG_D0 + REG1_8 (insn)]
508 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
509 + SEXT8 (insn & 0xff)), 1);
510 }
511
512 /* movbu (d16,am), dn */
513 void OP_FA400000 (insn, extension)
514 unsigned long insn, extension;
515 {
516 State.regs[REG_D0 + REG1_16 (insn)]
517 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
518 + SEXT16 (insn & 0xffff)), 1);
519 }
520
521 /* movbu (d32,am), dn */
522 void OP_FC400000 (insn, extension)
523 unsigned long insn, extension;
524 {
525 State.regs[REG_D0 + REG1_16 (insn)]
526 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
527 + ((insn & 0xffff) << 16) + extension), 1);
528 }
529
530 /* movbu (d8,sp), dn */
531 void OP_F8B800 (insn, extension)
532 unsigned long insn, extension;
533 {
534 State.regs[REG_D0 + REG0_8 (insn)]
535 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
536 }
537
538 /* movbu (d16,sp), dn */
539 void OP_FAB80000 (insn, extension)
540 unsigned long insn, extension;
541 {
542 State.regs[REG_D0 + REG0_16 (insn)]
543 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
544 }
545
546 /* movbu (d32,sp), dn */
547 void OP_FCB80000 (insn, extension)
548 unsigned long insn, extension;
549 {
550 State.regs[REG_D0 + REG0_16 (insn)]
551 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
552 }
553
554 /* movbu (di,am), dn */
555 void OP_F400 (insn, extension)
556 unsigned long insn, extension;
557 {
558 State.regs[REG_D0 + REG0_4 (insn)]
559 = load_mem ((State.regs[REG_A0 + REG0 (insn)]
560 + State.regs[REG_D0 + REG1 (insn)]), 1);
561 }
562
563 /* movbu (abs16), dn */
564 void OP_340000 (insn, extension)
565 unsigned long insn, extension;
566 {
567 State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 1);
568 }
569
570 /* movbu (abs32), dn */
571 void OP_FCA80000 (insn, extension)
572 unsigned long insn, extension;
573 {
574 State.regs[REG_D0 + REG0_16 (insn)]
575 = load_mem ((((insn & 0xffff) << 16) + extension), 1);
576 }
577
578 /* movbu dm, (an) */
579 void OP_F050 (insn, extension)
580 unsigned long insn, extension;
581 {
582 store_mem (State.regs[REG_A0 + REG0 (insn)], 1,
583 State.regs[REG_D0 + REG1 (insn)]);
584 }
585
586 /* movbu dm, (d8,an) */
587 void OP_F85000 (insn, extension)
588 unsigned long insn, extension;
589 {
590 store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
591 + SEXT8 (insn & 0xff)), 1,
592 State.regs[REG_D0 + REG1_8 (insn)]);
593 }
594
595 /* movbu dm, (d16,an) */
596 void OP_FA500000 (insn, extension)
597 unsigned long insn, extension;
598 {
599 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
600 + SEXT16 (insn & 0xffff)), 1,
601 State.regs[REG_D0 + REG1_16 (insn)]);
602 }
603
604 /* movbu dm, (d32,an) */
605 void OP_FC500000 (insn, extension)
606 unsigned long insn, extension;
607 {
608 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
609 + ((insn & 0xffff) << 16) + extension), 1,
610 State.regs[REG_D0 + REG1_16 (insn)]);
611 }
612
613 /* movbu dm, (d8,sp) */
614 void OP_F89200 (insn, extension)
615 unsigned long insn, extension;
616 {
617 store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
618 State.regs[REG_D0 + REG1_8 (insn)]);
619 }
620
621 /* movbu dm, (d16,sp) */
622 void OP_FA920000 (insn, extension)
623 unsigned long insn, extension;
624 {
625 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
626 State.regs[REG_D0 + REG1_16 (insn)]);
627 }
628
629 /* movbu dm (d32,sp) */
630 void OP_FC920000 (insn, extension)
631 unsigned long insn, extension;
632 {
633 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
634 State.regs[REG_D0 + REG1_16 (insn)]);
635 }
636
637 /* movbu dm, (di,an) */
638 void OP_F440 (insn, extension)
639 unsigned long insn, extension;
640 {
641 store_mem ((State.regs[REG_A0 + REG0 (insn)]
642 + State.regs[REG_D0 + REG1 (insn)]), 1,
643 State.regs[REG_D0 + REG0_4 (insn)]);
644 }
645
646 /* movbu dm, (abs16) */
647 void OP_20000 (insn, extension)
648 unsigned long insn, extension;
649 {
650 store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + REG1_16 (insn)]);
651 }
652
653 /* movbu dm, (abs32) */
654 void OP_FC820000 (insn, extension)
655 unsigned long insn, extension;
656 {
657 store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + REG1_16 (insn)]);
658 }
659
660 /* movhu (am), dn */
661 void OP_F060 (insn, extension)
662 unsigned long insn, extension;
663 {
664 State.regs[REG_D0 + REG1 (insn)]
665 = load_mem (State.regs[REG_A0 + REG0 (insn)], 2);
666 }
667
668 /* movhu (d8,am), dn */
669 void OP_F86000 (insn, extension)
670 unsigned long insn, extension;
671 {
672 State.regs[REG_D0 + REG1_8 (insn)]
673 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
674 + SEXT8 (insn & 0xff)), 2);
675 }
676
677 /* movhu (d16,am), dn */
678 void OP_FA600000 (insn, extension)
679 unsigned long insn, extension;
680 {
681 State.regs[REG_D0 + REG1_16 (insn)]
682 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
683 + SEXT16 (insn & 0xffff)), 2);
684 }
685
686 /* movhu (d32,am), dn */
687 void OP_FC600000 (insn, extension)
688 unsigned long insn, extension;
689 {
690 State.regs[REG_D0 + REG1_16 (insn)]
691 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
692 + ((insn & 0xffff) << 16) + extension), 2);
693 }
694
695 /* movhu (d8,sp) dn */
696 void OP_F8BC00 (insn, extension)
697 unsigned long insn, extension;
698 {
699 State.regs[REG_D0 + REG0_8 (insn)]
700 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
701 }
702
703 /* movhu (d16,sp), dn */
704 void OP_FABC0000 (insn, extension)
705 unsigned long insn, extension;
706 {
707 State.regs[REG_D0 + REG0_16 (insn)]
708 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
709 }
710
711 /* movhu (d32,sp), dn */
712 void OP_FCBC0000 (insn, extension)
713 unsigned long insn, extension;
714 {
715 State.regs[REG_D0 + REG0_16 (insn)]
716 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
717 }
718
719 /* movhu (di,am), dn */
720 void OP_F480 (insn, extension)
721 unsigned long insn, extension;
722 {
723 State.regs[REG_D0 + REG0_4 (insn)]
724 = load_mem ((State.regs[REG_A0 + REG0 (insn)]
725 + State.regs[REG_D0 + REG1 (insn)]), 2);
726 }
727
728 /* movhu (abs16), dn */
729 void OP_380000 (insn, extension)
730 unsigned long insn, extension;
731 {
732 State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 2);
733 }
734
735 /* movhu (abs32), dn */
736 void OP_FCAC0000 (insn, extension)
737 unsigned long insn, extension;
738 {
739 State.regs[REG_D0 + REG0_16 (insn)]
740 = load_mem ((((insn & 0xffff) << 16) + extension), 2);
741 }
742
743 /* movhu dm, (an) */
744 void OP_F070 (insn, extension)
745 unsigned long insn, extension;
746 {
747 store_mem (State.regs[REG_A0 + REG0 (insn)], 2,
748 State.regs[REG_D0 + REG1 (insn)]);
749 }
750
751 /* movhu dm, (d8,an) */
752 void OP_F87000 (insn, extension)
753 unsigned long insn, extension;
754 {
755 store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
756 + SEXT8 (insn & 0xff)), 2,
757 State.regs[REG_D0 + REG1_8 (insn)]);
758 }
759
760 /* movhu dm, (d16,an) */
761 void OP_FA700000 (insn, extension)
762 unsigned long insn, extension;
763 {
764 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
765 + SEXT16 (insn & 0xffff)), 2,
766 State.regs[REG_D0 + REG1_16 (insn)]);
767 }
768
769 /* movhu dm, (d32,an) */
770 void OP_FC700000 (insn, extension)
771 unsigned long insn, extension;
772 {
773 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
774 + ((insn & 0xffff) << 16) + extension), 2,
775 State.regs[REG_D0 + REG1_16 (insn)]);
776 }
777
778 /* movhu dm,(d8,sp) */
779 void OP_F89300 (insn, extension)
780 unsigned long insn, extension;
781 {
782 store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
783 State.regs[REG_D0 + REG1_8 (insn)]);
784 }
785
786 /* movhu dm,(d16,sp) */
787 void OP_FA930000 (insn, extension)
788 unsigned long insn, extension;
789 {
790 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
791 State.regs[REG_D0 + REG1_16 (insn)]);
792 }
793
794 /* movhu dm,(d32,sp) */
795 void OP_FC930000 (insn, extension)
796 unsigned long insn, extension;
797 {
798 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
799 State.regs[REG_D0 + REG1_16 (insn)]);
800 }
801
802 /* movhu dm, (di,an) */
803 void OP_F4C0 (insn, extension)
804 unsigned long insn, extension;
805 {
806 store_mem ((State.regs[REG_A0 + REG0 (insn)]
807 + State.regs[REG_D0 + REG1 (insn)]), 2,
808 State.regs[REG_D0 + REG0_4 (insn)]);
809 }
810
811 /* movhu dm, (abs16) */
812 void OP_30000 (insn, extension)
813 unsigned long insn, extension;
814 {
815 store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + REG1_16 (insn)]);
816 }
817
818 /* movhu dm, (abs32) */
819 void OP_FC830000 (insn, extension)
820 unsigned long insn, extension;
821 {
822 store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + REG1_16 (insn)]);
823 }
824
825 /* ext dn */
826 void OP_F2D0 (insn, extension)
827 unsigned long insn, extension;
828 {
829 if (State.regs[REG_D0 + REG0 (insn)] & 0x80000000)
830 State.regs[REG_MDR] = -1;
831 else
832 State.regs[REG_MDR] = 0;
833 }
834
835 /* extb dn */
836 void OP_10 (insn, extension)
837 unsigned long insn, extension;
838 {
839 State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]);
840 }
841
842 /* extbu dn */
843 void OP_14 (insn, extension)
844 unsigned long insn, extension;
845 {
846 State.regs[REG_D0 + REG0 (insn)] &= 0xff;
847 }
848
849 /* exth dn */
850 void OP_18 (insn, extension)
851 unsigned long insn, extension;
852 {
853 State.regs[REG_D0 + REG0 (insn)]
854 = SEXT16 (State.regs[REG_D0 + REG0 (insn)]);
855 }
856
857 /* exthu dn */
858 void OP_1C (insn, extension)
859 unsigned long insn, extension;
860 {
861 State.regs[REG_D0 + REG0 (insn)] &= 0xffff;
862 }
863
864 /* movm (sp), reg_list */
865 void OP_CE00 (insn, extension)
866 unsigned long insn, extension;
867 {
868 unsigned long sp = State.regs[REG_SP];
869 unsigned long mask;
870
871 mask = insn & 0xff;
872
873 if (mask & 0x8)
874 {
875 sp += 4;
876 State.regs[REG_LAR] = load_mem (sp, 4);
877 sp += 4;
878 State.regs[REG_LIR] = load_mem (sp, 4);
879 sp += 4;
880 State.regs[REG_MDR] = load_mem (sp, 4);
881 sp += 4;
882 State.regs[REG_A0 + 1] = load_mem (sp, 4);
883 sp += 4;
884 State.regs[REG_A0] = load_mem (sp, 4);
885 sp += 4;
886 State.regs[REG_D0 + 1] = load_mem (sp, 4);
887 sp += 4;
888 State.regs[REG_D0] = load_mem (sp, 4);
889 sp += 4;
890 }
891
892 if (mask & 0x10)
893 {
894 State.regs[REG_A0 + 3] = load_mem (sp, 4);
895 sp += 4;
896 }
897
898 if (mask & 0x20)
899 {
900 State.regs[REG_A0 + 2] = load_mem (sp, 4);
901 sp += 4;
902 }
903
904 if (mask & 0x40)
905 {
906 State.regs[REG_D0 + 3] = load_mem (sp, 4);
907 sp += 4;
908 }
909
910 if (mask & 0x80)
911 {
912 State.regs[REG_D0 + 2] = load_mem (sp, 4);
913 sp += 4;
914 }
915
916 /* And make sure to update the stack pointer. */
917 State.regs[REG_SP] = sp;
918 }
919
920 /* movm reg_list, (sp) */
921 void OP_CF00 (insn, extension)
922 unsigned long insn, extension;
923 {
924 unsigned long sp = State.regs[REG_SP];
925 unsigned long mask;
926
927 mask = insn & 0xff;
928
929 if (mask & 0x80)
930 {
931 sp -= 4;
932 store_mem (sp, 4, State.regs[REG_D0 + 2]);
933 }
934
935 if (mask & 0x40)
936 {
937 sp -= 4;
938 store_mem (sp, 4, State.regs[REG_D0 + 3]);
939 }
940
941 if (mask & 0x20)
942 {
943 sp -= 4;
944 store_mem (sp, 4, State.regs[REG_A0 + 2]);
945 }
946
947 if (mask & 0x10)
948 {
949 sp -= 4;
950 store_mem (sp, 4, State.regs[REG_A0 + 3]);
951 }
952
953 if (mask & 0x8)
954 {
955 sp -= 4;
956 store_mem (sp, 4, State.regs[REG_D0]);
957 sp -= 4;
958 store_mem (sp, 4, State.regs[REG_D0 + 1]);
959 sp -= 4;
960 store_mem (sp, 4, State.regs[REG_A0]);
961 sp -= 4;
962 store_mem (sp, 4, State.regs[REG_A0 + 1]);
963 sp -= 4;
964 store_mem (sp, 4, State.regs[REG_MDR]);
965 sp -= 4;
966 store_mem (sp, 4, State.regs[REG_LIR]);
967 sp -= 4;
968 store_mem (sp, 4, State.regs[REG_LAR]);
969 sp -= 4;
970 }
971
972 /* And make sure to update the stack pointer. */
973 State.regs[REG_SP] = sp;
974 }
975
976 /* clr dn */
977 void OP_0 (insn, extension)
978 unsigned long insn, extension;
979 {
980 State.regs[REG_D0 + REG1 (insn)] = 0;
981
982 PSW |= PSW_Z;
983 PSW &= ~(PSW_V | PSW_C | PSW_N);
984 }
985
986 /* add dm,dn */
987 void OP_E0 (insn, extension)
988 unsigned long insn, extension;
989 {
990 int z, c, n, v;
991 unsigned long reg1, reg2, value;
992
993 reg1 = State.regs[REG_D0 + REG1 (insn)];
994 reg2 = State.regs[REG_D0 + REG0 (insn)];
995 value = reg1 + reg2;
996 State.regs[REG_D0 + REG0 (insn)] = value;
997
998 z = (value == 0);
999 n = (value & 0x80000000);
1000 c = (value < reg1) || (value < reg2);
1001 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1002 && (reg2 & 0x80000000) != (value & 0x80000000));
1003
1004 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1005 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1006 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1007 }
1008
1009 /* add dm, an */
1010 void OP_F160 (insn, extension)
1011 unsigned long insn, extension;
1012 {
1013 int z, c, n, v;
1014 unsigned long reg1, reg2, value;
1015
1016 reg1 = State.regs[REG_D0 + REG1 (insn)];
1017 reg2 = State.regs[REG_A0 + REG0 (insn)];
1018 value = reg1 + reg2;
1019 State.regs[REG_A0 + REG0 (insn)] = value;
1020
1021 z = (value == 0);
1022 n = (value & 0x80000000);
1023 c = (value < reg1) || (value < reg2);
1024 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1025 && (reg2 & 0x80000000) != (value & 0x80000000));
1026
1027 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1028 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1029 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1030 }
1031
1032 /* add am, dn */
1033 void OP_F150 (insn, extension)
1034 unsigned long insn, extension;
1035 {
1036 int z, c, n, v;
1037 unsigned long reg1, reg2, value;
1038
1039 reg1 = State.regs[REG_A0 + REG1 (insn)];
1040 reg2 = State.regs[REG_D0 + REG0 (insn)];
1041 value = reg1 + reg2;
1042 State.regs[REG_D0 + REG0 (insn)] = value;
1043
1044 z = (value == 0);
1045 n = (value & 0x80000000);
1046 c = (value < reg1) || (value < reg2);
1047 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1048 && (reg2 & 0x80000000) != (value & 0x80000000));
1049
1050 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1051 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1052 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1053 }
1054
1055 /* add am,an */
1056 void OP_F170 (insn, extension)
1057 unsigned long insn, extension;
1058 {
1059 int z, c, n, v;
1060 unsigned long reg1, reg2, value;
1061
1062 reg1 = State.regs[REG_A0 + REG1 (insn)];
1063 reg2 = State.regs[REG_A0 + REG0 (insn)];
1064 value = reg1 + reg2;
1065 State.regs[REG_A0 + REG0 (insn)] = value;
1066
1067 z = (value == 0);
1068 n = (value & 0x80000000);
1069 c = (value < reg1) || (value < reg2);
1070 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1071 && (reg2 & 0x80000000) != (value & 0x80000000));
1072
1073 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1074 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1075 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1076 }
1077
1078 /* add imm8, dn */
1079 void OP_2800 (insn, extension)
1080 unsigned long insn, extension;
1081 {
1082 int z, c, n, v;
1083 unsigned long reg1, imm, value;
1084
1085 reg1 = State.regs[REG_D0 + REG0_8 (insn)];
1086 imm = SEXT8 (insn & 0xff);
1087 value = reg1 + imm;
1088 State.regs[REG_D0 + REG0_8 (insn)] = value;
1089
1090 z = (value == 0);
1091 n = (value & 0x80000000);
1092 c = (value < reg1) || (value < imm);
1093 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1094 && (reg1 & 0x80000000) != (value & 0x80000000));
1095
1096 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1097 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1098 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1099 }
1100
1101 /* add imm16, dn */
1102 void OP_FAC00000 (insn, extension)
1103 unsigned long insn, extension;
1104 {
1105 int z, c, n, v;
1106 unsigned long reg1, imm, value;
1107
1108 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1109 imm = SEXT16 (insn & 0xffff);
1110 value = reg1 + imm;
1111 State.regs[REG_D0 + REG0_16 (insn)] = value;
1112
1113 z = (value == 0);
1114 n = (value & 0x80000000);
1115 c = (value < reg1) || (value < imm);
1116 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1117 && (reg1 & 0x80000000) != (value & 0x80000000));
1118
1119 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1120 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1121 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1122 }
1123
1124 /* add imm32,dn */
1125 void OP_FCC00000 (insn, extension)
1126 unsigned long insn, extension;
1127 {
1128 int z, c, n, v;
1129 unsigned long reg1, imm, value;
1130
1131 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1132 imm = ((insn & 0xffff) << 16) + extension;
1133 value = reg1 + imm;
1134 State.regs[REG_D0 + REG0_16 (insn)] = value;
1135
1136 z = (value == 0);
1137 n = (value & 0x80000000);
1138 c = (value < reg1) || (value < imm);
1139 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1140 && (reg1 & 0x80000000) != (value & 0x80000000));
1141
1142 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1143 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1144 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1145 }
1146
1147 /* add imm8, an */
1148 void OP_2000 (insn, extension)
1149 unsigned long insn, extension;
1150 {
1151 int z, c, n, v;
1152 unsigned long reg1, imm, value;
1153
1154 reg1 = State.regs[REG_A0 + REG0_8 (insn)];
1155 imm = SEXT8 (insn & 0xff);
1156 value = reg1 + imm;
1157 State.regs[REG_A0 + REG0_8 (insn)] = value;
1158
1159 z = (value == 0);
1160 n = (value & 0x80000000);
1161 c = (value < reg1) || (value < imm);
1162 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1163 && (reg1 & 0x80000000) != (value & 0x80000000));
1164
1165 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1166 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1167 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1168 }
1169
1170 /* add imm16, an */
1171 void OP_FAD00000 (insn, extension)
1172 unsigned long insn, extension;
1173 {
1174 int z, c, n, v;
1175 unsigned long reg1, imm, value;
1176
1177 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1178 imm = SEXT16 (insn & 0xffff);
1179 value = reg1 + imm;
1180 State.regs[REG_A0 + REG0_16 (insn)] = value;
1181
1182 z = (value == 0);
1183 n = (value & 0x80000000);
1184 c = (value < reg1) || (value < imm);
1185 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1186 && (reg1 & 0x80000000) != (value & 0x80000000));
1187
1188 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1189 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1190 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1191 }
1192
1193 /* add imm32, an */
1194 void OP_FCD00000 (insn, extension)
1195 unsigned long insn, extension;
1196 {
1197 int z, c, n, v;
1198 unsigned long reg1, imm, value;
1199
1200 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1201 imm = ((insn & 0xffff) << 16) + extension;
1202 value = reg1 + imm;
1203 State.regs[REG_A0 + REG0_16 (insn)] = value;
1204
1205 z = (value == 0);
1206 n = (value & 0x80000000);
1207 c = (value < reg1) || (value < imm);
1208 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1209 && (reg1 & 0x80000000) != (value & 0x80000000));
1210
1211 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1212 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1213 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1214 }
1215
1216 /* add imm8, sp */
1217 void OP_F8FE00 (insn, extension)
1218 unsigned long insn, extension;
1219 {
1220 unsigned long reg1, imm, value;
1221
1222 reg1 = State.regs[REG_SP];
1223 imm = SEXT8 (insn & 0xff);
1224 value = reg1 + imm;
1225 State.regs[REG_SP] = value;
1226 }
1227
1228 /* add imm16,sp */
1229 void OP_FAFE0000 (insn, extension)
1230 unsigned long insn, extension;
1231 {
1232 unsigned long reg1, imm, value;
1233
1234 reg1 = State.regs[REG_SP];
1235 imm = SEXT16 (insn & 0xffff);
1236 value = reg1 + imm;
1237 State.regs[REG_SP] = value;
1238 }
1239
1240 /* add imm32, sp */
1241 void OP_FCFE0000 (insn, extension)
1242 unsigned long insn, extension;
1243 {
1244 unsigned long reg1, imm, value;
1245
1246 reg1 = State.regs[REG_SP];
1247 imm = ((insn & 0xffff) << 16) + extension;
1248 value = reg1 + imm;
1249 State.regs[REG_SP] = value;
1250 }
1251
1252 /* addc dm,dn */
1253 void OP_F140 (insn, extension)
1254 unsigned long insn, extension;
1255 {
1256 int z, c, n, v;
1257 unsigned long reg1, reg2, value;
1258
1259 reg1 = State.regs[REG_D0 + REG1 (insn)];
1260 reg2 = State.regs[REG_D0 + REG0 (insn)];
1261 value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1262 State.regs[REG_D0 + REG0 (insn)] = value;
1263
1264 z = (value == 0);
1265 n = (value & 0x80000000);
1266 c = (value < reg1) || (value < reg2);
1267 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1268 && (reg2 & 0x80000000) != (value & 0x80000000));
1269
1270 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1271 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1272 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1273 }
1274
1275 /* sub dm, dn */
1276 void OP_F100 (insn, extension)
1277 unsigned long insn, extension;
1278 {
1279 int z, c, n, v;
1280 unsigned long reg1, reg2, value;
1281
1282 reg1 = State.regs[REG_D0 + REG1 (insn)];
1283 reg2 = State.regs[REG_D0 + REG0 (insn)];
1284 value = reg2 - reg1;
1285 State.regs[REG_D0 + REG0 (insn)] = value;
1286
1287 z = (value == 0);
1288 n = (value & 0x80000000);
1289 c = (reg1 > reg2);
1290 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1291 && (reg2 & 0x80000000) != (value & 0x80000000));
1292
1293 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1294 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1295 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1296 }
1297
1298 /* sub dm, an */
1299 void OP_F120 (insn, extension)
1300 unsigned long insn, extension;
1301 {
1302 int z, c, n, v;
1303 unsigned long reg1, reg2, value;
1304
1305 reg1 = State.regs[REG_D0 + REG1 (insn)];
1306 reg2 = State.regs[REG_A0 + REG0 (insn)];
1307 value = reg2 - reg1;
1308 State.regs[REG_A0 + REG0 (insn)] = value;
1309
1310 z = (value == 0);
1311 n = (value & 0x80000000);
1312 c = (reg1 > reg2);
1313 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1314 && (reg2 & 0x80000000) != (value & 0x80000000));
1315
1316 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1317 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1318 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1319 }
1320
1321 /* sub am, dn */
1322 void OP_F110 (insn, extension)
1323 unsigned long insn, extension;
1324 {
1325 int z, c, n, v;
1326 unsigned long reg1, reg2, value;
1327
1328 reg1 = State.regs[REG_A0 + REG1 (insn)];
1329 reg2 = State.regs[REG_D0 + REG0 (insn)];
1330 value = reg2 - reg1;
1331 State.regs[REG_D0 + REG0 (insn)] = value;
1332
1333 z = (value == 0);
1334 n = (value & 0x80000000);
1335 c = (reg1 > reg2);
1336 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1337 && (reg2 & 0x80000000) != (value & 0x80000000));
1338
1339 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1340 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1341 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1342 }
1343
1344 /* sub am, an */
1345 void OP_F130 (insn, extension)
1346 unsigned long insn, extension;
1347 {
1348 int z, c, n, v;
1349 unsigned long reg1, reg2, value;
1350
1351 reg1 = State.regs[REG_A0 + REG1 (insn)];
1352 reg2 = State.regs[REG_A0 + REG0 (insn)];
1353 value = reg2 - reg1;
1354 State.regs[REG_A0 + REG0 (insn)] = value;
1355
1356 z = (value == 0);
1357 n = (value & 0x80000000);
1358 c = (reg1 > reg2);
1359 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1360 && (reg2 & 0x80000000) != (value & 0x80000000));
1361
1362 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1363 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1364 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1365 }
1366
1367 /* sub imm32, dn */
1368 void OP_FCC40000 (insn, extension)
1369 unsigned long insn, extension;
1370 {
1371 int z, c, n, v;
1372 unsigned long reg1, imm, value;
1373
1374 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1375 imm = ((insn & 0xffff) << 16) + extension;
1376 value = reg1 - imm;
1377 State.regs[REG_D0 + REG0_16 (insn)] = value;
1378
1379 z = (value == 0);
1380 n = (value & 0x80000000);
1381 c = (reg1 < imm);
1382 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1383 && (reg1 & 0x80000000) != (value & 0x80000000));
1384
1385 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1386 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1387 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1388 }
1389
1390 /* sub imm32, an */
1391 void OP_FCD40000 (insn, extension)
1392 unsigned long insn, extension;
1393 {
1394 int z, c, n, v;
1395 unsigned long reg1, imm, value;
1396
1397 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1398 imm = ((insn & 0xffff) << 16) + extension;
1399 value = reg1 - imm;
1400 State.regs[REG_A0 + REG0_16 (insn)] = value;
1401
1402 z = (value == 0);
1403 n = (value & 0x80000000);
1404 c = (reg1 < imm);
1405 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1406 && (reg1 & 0x80000000) != (value & 0x80000000));
1407
1408 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1409 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1410 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1411 }
1412
1413 /* subc dm, dn */
1414 void OP_F180 (insn, extension)
1415 unsigned long insn, extension;
1416 {
1417 int z, c, n, v;
1418 unsigned long reg1, reg2, value;
1419
1420 reg1 = State.regs[REG_D0 + REG1 (insn)];
1421 reg2 = State.regs[REG_D0 + REG0 (insn)];
1422 value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1423 State.regs[REG_D0 + REG0 (insn)] = value;
1424
1425 z = (value == 0);
1426 n = (value & 0x80000000);
1427 c = (reg1 > reg2);
1428 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1429 && (reg2 & 0x80000000) != (value & 0x80000000));
1430
1431 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1432 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1433 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1434 }
1435
1436 /* mul dm, dn */
1437 void OP_F240 (insn, extension)
1438 unsigned long insn, extension;
1439 {
1440 unsigned long long temp;
1441 int n, z;
1442
1443 temp = ((signed long)State.regs[REG_D0 + REG0 (insn)]
1444 * (signed long)State.regs[REG_D0 + REG1 (insn)]);
1445 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1446 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1447 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1448 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1449 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1450 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1451 }
1452
1453 /* mulu dm, dn */
1454 void OP_F250 (insn, extension)
1455 unsigned long insn, extension;
1456 {
1457 unsigned long long temp;
1458 int n, z;
1459
1460 temp = (State.regs[REG_D0 + REG0 (insn)]
1461 * State.regs[REG_D0 + REG1 (insn)]);
1462 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1463 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1464 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1465 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1466 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1467 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1468 }
1469
1470 /* div dm, dn */
1471 void OP_F260 (insn, extension)
1472 unsigned long insn, extension;
1473 {
1474 long long temp;
1475 int n, z;
1476
1477 temp = State.regs[REG_MDR];
1478 temp <<= 32;
1479 temp |= State.regs[REG_D0 + REG0 (insn)];
1480 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + REG1 (insn)];
1481 temp /= (long)State.regs[REG_D0 + REG1 (insn)];
1482 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1483 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1484 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1485 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1486 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1487 }
1488
1489 /* divu dm, dn */
1490 void OP_F270 (insn, extension)
1491 unsigned long insn, extension;
1492 {
1493 unsigned long long temp;
1494 int n, z;
1495
1496 temp = State.regs[REG_MDR];
1497 temp <<= 32;
1498 temp |= State.regs[REG_D0 + REG0 (insn)];
1499 State.regs[REG_MDR] = temp % State.regs[REG_D0 + REG1 (insn)];
1500 temp /= State.regs[REG_D0 + REG1 (insn)];
1501 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1502 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1503 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1504 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1505 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1506 }
1507
1508 /* inc dn */
1509 void OP_40 (insn, extension)
1510 unsigned long insn, extension;
1511 {
1512 int z,n,c,v;
1513 unsigned int value, imm, reg1;
1514
1515 reg1 = State.regs[REG_D0 + REG1 (insn)];
1516 imm = 1;
1517 value = reg1 + imm;
1518 State.regs[REG_D0 + REG1 (insn)] = value;
1519
1520 z = (value == 0);
1521 n = (value & 0x80000000);
1522 c = (reg1 < imm);
1523 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1524 && (reg1 & 0x80000000) != (value & 0x80000000));
1525
1526 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1527 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1528 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1529 }
1530
1531 /* inc an */
1532 void OP_41 (insn, extension)
1533 unsigned long insn, extension;
1534 {
1535 State.regs[REG_A0 + REG1 (insn)] += 1;
1536 }
1537
1538 /* inc4 an */
1539 void OP_50 (insn, extension)
1540 unsigned long insn, extension;
1541 {
1542 State.regs[REG_A0 + REG0 (insn)] += 4;
1543 }
1544
1545 /* cmp imm8, dn */
1546 void OP_A000 (insn, extension)
1547 unsigned long insn, extension;
1548 {
1549 int z, c, n, v;
1550 unsigned long reg1, imm, value;
1551
1552 reg1 = State.regs[REG_D0 + REG0_8 (insn)];
1553 imm = SEXT8 (insn & 0xff);
1554 value = reg1 - imm;
1555
1556 z = (value == 0);
1557 n = (value & 0x80000000);
1558 c = (reg1 < imm);
1559 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1560 && (reg1 & 0x80000000) != (value & 0x80000000));
1561
1562 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1563 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1564 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1565 }
1566
1567 /* cmp dm, dn */
1568 void OP_A0 (insn, extension)
1569 unsigned long insn, extension;
1570 {
1571 int z, c, n, v;
1572 unsigned long reg1, reg2, value;
1573
1574 reg1 = State.regs[REG_D0 + REG1 (insn)];
1575 reg2 = State.regs[REG_D0 + REG0 (insn)];
1576 value = reg2 - reg1;
1577
1578 z = (value == 0);
1579 n = (value & 0x80000000);
1580 c = (reg1 > reg2);
1581 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1582 && (reg2 & 0x80000000) != (value & 0x80000000));
1583
1584 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1585 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1586 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1587 }
1588
1589 /* cmp dm, an */
1590 void OP_F1A0 (insn, extension)
1591 unsigned long insn, extension;
1592 {
1593 int z, c, n, v;
1594 unsigned long reg1, reg2, value;
1595
1596 reg1 = State.regs[REG_D0 + REG1 (insn)];
1597 reg2 = State.regs[REG_A0 + REG0 (insn)];
1598 value = reg2 - reg1;
1599
1600 z = (value == 0);
1601 n = (value & 0x80000000);
1602 c = (reg1 > reg2);
1603 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1604 && (reg2 & 0x80000000) != (value & 0x80000000));
1605
1606 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1607 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1608 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1609 }
1610
1611 /* cmp am, dn */
1612 void OP_F190 (insn, extension)
1613 unsigned long insn, extension;
1614 {
1615 int z, c, n, v;
1616 unsigned long reg1, reg2, value;
1617
1618 reg1 = State.regs[REG_A0 + REG1 (insn)];
1619 reg2 = State.regs[REG_D0 + REG0 (insn)];
1620 value = reg2 - reg1;
1621
1622 z = (value == 0);
1623 n = (value & 0x80000000);
1624 c = (reg1 > reg2);
1625 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1626 && (reg2 & 0x80000000) != (value & 0x80000000));
1627
1628 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1629 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1630 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1631 }
1632
1633 /* cmp imm8, an */
1634 void OP_B000 (insn, extension)
1635 unsigned long insn, extension;
1636 {
1637 int z, c, n, v;
1638 unsigned long reg1, imm, value;
1639
1640 reg1 = State.regs[REG_A0 + REG0_8 (insn)];
1641 imm = insn & 0xff;
1642 value = reg1 - imm;
1643
1644 z = (value == 0);
1645 n = (value & 0x80000000);
1646 c = (reg1 < imm);
1647 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1648 && (reg1 & 0x80000000) != (value & 0x80000000));
1649
1650 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1651 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1652 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1653 }
1654
1655 /* cmp am, an */
1656 void OP_B0 (insn, extension)
1657 unsigned long insn, extension;
1658 {
1659 int z, c, n, v;
1660 unsigned long reg1, reg2, value;
1661
1662 reg1 = State.regs[REG_A0 + REG1 (insn)];
1663 reg2 = State.regs[REG_A0 + REG0 (insn)];
1664 value = reg2 - reg1;
1665
1666 z = (value == 0);
1667 n = (value & 0x80000000);
1668 c = (reg1 > reg2);
1669 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1670 && (reg2 & 0x80000000) != (value & 0x80000000));
1671
1672 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1673 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1674 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1675 }
1676
1677 /* cmp imm16, dn */
1678 void OP_FAC80000 (insn, extension)
1679 unsigned long insn, extension;
1680 {
1681 int z, c, n, v;
1682 unsigned long reg1, imm, value;
1683
1684 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1685 imm = SEXT16 (insn & 0xffff);
1686 value = reg1 - imm;
1687
1688 z = (value == 0);
1689 n = (value & 0x80000000);
1690 c = (reg1 < imm);
1691 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1692 && (reg1 & 0x80000000) != (value & 0x80000000));
1693
1694 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1695 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1696 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1697 }
1698
1699 /* cmp imm32, dn */
1700 void OP_FCC80000 (insn, extension)
1701 unsigned long insn, extension;
1702 {
1703 int z, c, n, v;
1704 unsigned long reg1, imm, value;
1705
1706 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1707 imm = ((insn & 0xffff) << 16) + extension;
1708 value = reg1 - imm;
1709
1710 z = (value == 0);
1711 n = (value & 0x80000000);
1712 c = (reg1 < imm);
1713 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1714 && (reg1 & 0x80000000) != (value & 0x80000000));
1715
1716 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1717 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1718 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1719 }
1720
1721 /* cmp imm16, an */
1722 void OP_FAD80000 (insn, extension)
1723 unsigned long insn, extension;
1724 {
1725 int z, c, n, v;
1726 unsigned long reg1, imm, value;
1727
1728 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1729 imm = insn & 0xffff;
1730 value = reg1 - imm;
1731
1732 z = (value == 0);
1733 n = (value & 0x80000000);
1734 c = (reg1 < imm);
1735 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1736 && (reg1 & 0x80000000) != (value & 0x80000000));
1737
1738 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1739 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1740 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1741 }
1742
1743 /* cmp imm32, an */
1744 void OP_FCD80000 (insn, extension)
1745 unsigned long insn, extension;
1746 {
1747 int z, c, n, v;
1748 unsigned long reg1, imm, value;
1749
1750 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1751 imm = ((insn & 0xffff) << 16) + extension;
1752 value = reg1 - imm;
1753
1754 z = (value == 0);
1755 n = (value & 0x80000000);
1756 c = (reg1 < imm);
1757 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1758 && (reg1 & 0x80000000) != (value & 0x80000000));
1759
1760 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1761 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1762 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1763 }
1764
1765 /* and dm, dn */
1766 void OP_F200 (insn, extension)
1767 unsigned long insn, extension;
1768 {
1769 int n, z;
1770
1771 State.regs[REG_D0 + REG0 (insn)] &= State.regs[REG_D0 + REG1 (insn)];
1772 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1773 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1774 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1775 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1776 }
1777
1778 /* and imm8, dn */
1779 void OP_F8E000 (insn, extension)
1780 unsigned long insn, extension;
1781 {
1782 int n, z;
1783
1784 State.regs[REG_D0 + REG0_8 (insn)] &= (insn & 0xff);
1785 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
1786 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
1787 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1788 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1789 }
1790
1791 /* and imm16, dn */
1792 void OP_FAE00000 (insn, extension)
1793 unsigned long insn, extension;
1794 {
1795 int n, z;
1796
1797 State.regs[REG_D0 + REG0_16 (insn)] &= (insn & 0xffff);
1798 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1799 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1800 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1801 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1802 }
1803
1804 /* and imm32, dn */
1805 void OP_FCE00000 (insn, extension)
1806 unsigned long insn, extension;
1807 {
1808 int n, z;
1809
1810 State.regs[REG_D0 + REG0_16 (insn)]
1811 &= ((insn & 0xffff) << 16) + extension;
1812 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1813 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1814 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1815 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1816 }
1817
1818 /* and imm16, psw */
1819 void OP_FAFC0000 (insn, extension)
1820 unsigned long insn, extension;
1821 {
1822 PSW &= (insn & 0xffff);
1823 }
1824
1825 /* or dm, dn*/
1826 void OP_F210 (insn, extension)
1827 unsigned long insn, extension;
1828 {
1829 int n, z;
1830
1831 State.regs[REG_D0 + REG0 (insn)] |= State.regs[REG_D0 + REG1 (insn)];
1832 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1833 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1834 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1835 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1836 }
1837
1838 /* or imm8, dn */
1839 void OP_F8E400 (insn, extension)
1840 unsigned long insn, extension;
1841 {
1842 int n, z;
1843
1844 State.regs[REG_D0 + REG0_8 (insn)] |= insn & 0xff;
1845 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
1846 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
1847 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1848 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1849 }
1850
1851 /* or imm16, dn*/
1852 void OP_FAE40000 (insn, extension)
1853 unsigned long insn, extension;
1854 {
1855 int n, z;
1856
1857 State.regs[REG_D0 + REG0_16 (insn)] |= insn & 0xffff;
1858 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1859 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1860 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1861 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1862 }
1863
1864 /* or imm32, dn */
1865 void OP_FCE40000 (insn, extension)
1866 unsigned long insn, extension;
1867 {
1868 int n, z;
1869
1870 State.regs[REG_D0 + REG0_16 (insn)]
1871 |= ((insn & 0xffff) << 16) + extension;
1872 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1873 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1874 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1875 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1876 }
1877
1878 /* or imm16,psw */
1879 void OP_FAFD0000 (insn, extension)
1880 unsigned long insn, extension;
1881 {
1882 PSW |= (insn & 0xffff);
1883 }
1884
1885 /* xor dm, dn */
1886 void OP_F220 (insn, extension)
1887 unsigned long insn, extension;
1888 {
1889 int n, z;
1890
1891 State.regs[REG_D0 + REG0 (insn)] ^= State.regs[REG_D0 + REG1 (insn)];
1892 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1893 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1894 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1895 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1896 }
1897
1898 /* xor imm16, dn */
1899 void OP_FAE80000 (insn, extension)
1900 unsigned long insn, extension;
1901 {
1902 int n, z;
1903
1904 State.regs[REG_D0 + REG0_16 (insn)] ^= insn & 0xffff;
1905 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1906 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1907 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1908 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1909 }
1910
1911 /* xor imm32, dn */
1912 void OP_FCE80000 (insn, extension)
1913 unsigned long insn, extension;
1914 {
1915 int n, z;
1916
1917 State.regs[REG_D0 + REG0_16 (insn)]
1918 ^= ((insn & 0xffff) << 16) + extension;
1919 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1920 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1921 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1922 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1923 }
1924
1925 /* not dn */
1926 void OP_F230 (insn, extension)
1927 unsigned long insn, extension;
1928 {
1929 int n, z;
1930
1931 State.regs[REG_D0 + REG0 (insn)] = ~State.regs[REG_D0 + REG0 (insn)];
1932 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1933 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1934 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1935 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1936 }
1937
1938 /* btst imm8, dn */
1939 void OP_F8EC00 (insn, extension)
1940 unsigned long insn, extension;
1941 {
1942 unsigned long temp;
1943 int z, n;
1944
1945 temp = State.regs[REG_D0 + REG0_8 (insn)];
1946 temp &= (insn & 0xff);
1947 n = (temp & 0x80000000) != 0;
1948 z = (temp == 0);
1949 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1950 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1951 }
1952
1953 /* btst imm16, dn */
1954 void OP_FAEC0000 (insn, extension)
1955 unsigned long insn, extension;
1956 {
1957 unsigned long temp;
1958 int z, n;
1959
1960 temp = State.regs[REG_D0 + REG0_16 (insn)];
1961 temp &= (insn & 0xffff);
1962 n = (temp & 0x80000000) != 0;
1963 z = (temp == 0);
1964 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1965 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1966 }
1967
1968 /* btst imm32, dn */
1969 void OP_FCEC0000 (insn, extension)
1970 unsigned long insn, extension;
1971 {
1972 unsigned long temp;
1973 int z, n;
1974
1975 temp = State.regs[REG_D0 + REG0_16 (insn)];
1976 temp &= ((insn & 0xffff) << 16) + extension;
1977 n = (temp & 0x80000000) != 0;
1978 z = (temp == 0);
1979 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1980 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1981 }
1982
1983 /* btst imm8,(abs32) */
1984 void OP_FE020000 (insn, extension)
1985 unsigned long insn, extension;
1986 {
1987 unsigned long temp;
1988 int n, z;
1989
1990 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
1991 temp &= (extension & 0xff);
1992 n = (temp & 0x80000000) != 0;
1993 z = (temp == 0);
1994 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1995 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1996 }
1997
1998 /* btst imm8,(d8,an) */
1999 void OP_FAF80000 (insn, extension)
2000 unsigned long insn, extension;
2001 {
2002 unsigned long temp;
2003 int n, z;
2004
2005 temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
2006 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2007 temp &= (insn & 0xff);
2008 n = (temp & 0x80000000) != 0;
2009 z = (temp == 0);
2010 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2011 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2012 }
2013
2014 /* bset dm, (an) */
2015 void OP_F080 (insn, extension)
2016 unsigned long insn, extension;
2017 {
2018 unsigned long temp;
2019 int z;
2020
2021 temp = load_mem (State.regs[REG_A0 + REG0 (insn)], 1);
2022 z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
2023 temp |= State.regs[REG_D0 + REG1 (insn)];
2024 store_mem (State.regs[REG_A0 + REG0 (insn)], 1, temp);
2025 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2026 PSW |= (z ? PSW_Z : 0);
2027 }
2028
2029 /* bset imm8, (abs32) */
2030 void OP_FE000000 (insn, extension)
2031 unsigned long insn, extension;
2032 {
2033 unsigned long temp;
2034 int z;
2035
2036 temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
2037 z = (temp & (extension & 0xff)) == 0;
2038 temp |= (extension & 0xff);
2039 store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
2040 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2041 PSW |= (z ? PSW_Z : 0);
2042 }
2043
2044 /* bset imm8,(d8,an) */
2045 void OP_FAF00000 (insn, extension)
2046 unsigned long insn, extension;
2047 {
2048 unsigned long temp;
2049 int z;
2050
2051 temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
2052 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2053 z = (temp & (insn & 0xff)) == 0;
2054 temp |= (insn & 0xff);
2055 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
2056 + SEXT8 ((insn & 0xff00) >> 8)), 1, temp);
2057 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2058 PSW |= (z ? PSW_Z : 0);
2059 }
2060
2061 /* bclr dm, (an) */
2062 void OP_F090 (insn, extension)
2063 unsigned long insn, extension;
2064 {
2065 unsigned long temp;
2066 int z;
2067
2068 temp = load_mem (State.regs[REG_A0 + REG0 (insn)], 1);
2069 z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
2070 temp = temp & ~State.regs[REG_D0 + REG1 (insn)];
2071 store_mem (State.regs[REG_A0 + REG0 (insn)], 1, temp);
2072 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2073 PSW |= (z ? PSW_Z : 0);
2074 }
2075
2076 /* bclr imm8, (abs32) */
2077 void OP_FE010000 (insn, extension)
2078 unsigned long insn, extension;
2079 {
2080 unsigned long temp;
2081 int z;
2082
2083 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
2084 z = (temp & (extension & 0xff)) == 0;
2085 temp = temp & ~(extension & 0xff);
2086 store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
2087 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2088 PSW |= (z ? PSW_Z : 0);
2089 }
2090
2091 /* bclr imm8,(d8,an) */
2092 void OP_FAF40000 (insn, extension)
2093 unsigned long insn, extension;
2094 {
2095 unsigned long temp;
2096 int z;
2097
2098 temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
2099 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2100 z = (temp & (insn & 0xff)) == 0;
2101 temp = temp & ~(insn & 0xff);
2102 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
2103 + SEXT8 ((insn & 0xff00) >> 8)), 1, temp);
2104 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2105 PSW |= (z ? PSW_Z : 0);
2106 }
2107
2108 /* asr dm, dn */
2109 void OP_F2B0 (insn, extension)
2110 unsigned long insn, extension;
2111 {
2112 long temp;
2113 int z, n, c;
2114
2115 temp = State.regs[REG_D0 + REG0 (insn)];
2116 c = temp & 1;
2117 temp >>= State.regs[REG_D0 + REG1 (insn)];
2118 State.regs[REG_D0 + REG0 (insn)] = temp;
2119 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2120 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2121 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2122 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2123 }
2124
2125 /* asr imm8, dn */
2126 void OP_F8C800 (insn, extension)
2127 unsigned long insn, extension;
2128 {
2129 long temp;
2130 int z, n, c;
2131
2132 temp = State.regs[REG_D0 + REG0_8 (insn)];
2133 c = temp & 1;
2134 temp >>= (insn & 0xff);
2135 State.regs[REG_D0 + REG0_8 (insn)] = temp;
2136 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2137 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2138 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2139 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2140 }
2141
2142 /* lsr dm, dn */
2143 void OP_F2A0 (insn, extension)
2144 unsigned long insn, extension;
2145 {
2146 int z, n, c;
2147
2148 c = State.regs[REG_D0 + REG0 (insn)] & 1;
2149 State.regs[REG_D0 + REG0 (insn)]
2150 >>= State.regs[REG_D0 + REG1 (insn)];
2151 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2152 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2153 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2154 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2155 }
2156
2157 /* lsr imm8, dn */
2158 void OP_F8C400 (insn, extension)
2159 unsigned long insn, extension;
2160 {
2161 int z, n, c;
2162
2163 c = State.regs[REG_D0 + REG0_8 (insn)] & 1;
2164 State.regs[REG_D0 + REG0_8 (insn)] >>= (insn & 0xff);
2165 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2166 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2167 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2168 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2169 }
2170
2171 /* asl dm, dn */
2172 void OP_F290 (insn, extension)
2173 unsigned long insn, extension;
2174 {
2175 int n, z;
2176
2177 State.regs[REG_D0 + REG0 (insn)]
2178 <<= State.regs[REG_D0 + REG1 (insn)];
2179 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2180 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2181 PSW &= ~(PSW_Z | PSW_N);
2182 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2183 }
2184
2185 /* asl imm8, dn */
2186 void OP_F8C000 (insn, extension)
2187 unsigned long insn, extension;
2188 {
2189 int n, z;
2190
2191 State.regs[REG_D0 + REG0_8 (insn)] <<= (insn & 0xff);
2192 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2193 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2194 PSW &= ~(PSW_Z | PSW_N);
2195 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2196 }
2197
2198 /* asl2 dn */
2199 void OP_54 (insn, extension)
2200 unsigned long insn, extension;
2201 {
2202 int n, z;
2203
2204 State.regs[REG_D0 + REG0 (insn)] <<= 2;
2205 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2206 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2207 PSW &= ~(PSW_Z | PSW_N);
2208 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2209 }
2210
2211 /* ror dn */
2212 void OP_F284 (insn, extension)
2213 unsigned long insn, extension;
2214 {
2215 unsigned long value;
2216 int c,n,z;
2217
2218 value = State.regs[REG_D0 + REG0 (insn)];
2219 c = (value & 0x1);
2220
2221 value >>= 1;
2222 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2223 State.regs[REG_D0 + REG0 (insn)] = value;
2224 z = (value == 0);
2225 n = (value & 0x80000000) != 0;
2226 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2227 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2228 }
2229
2230 /* rol dn */
2231 void OP_F280 (insn, extension)
2232 unsigned long insn, extension;
2233 {
2234 unsigned long value;
2235 int c,n,z;
2236
2237 value = State.regs[REG_D0 + REG0 (insn)];
2238 c = (value & 0x80000000) ? 1 : 0;
2239
2240 value <<= 1;
2241 value |= ((PSW & PSW_C) != 0);
2242 State.regs[REG_D0 + REG0 (insn)] = value;
2243 z = (value == 0);
2244 n = (value & 0x80000000) != 0;
2245 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2246 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2247 }
2248
2249 /* beq label:8 */
2250 void OP_C800 (insn, extension)
2251 unsigned long insn, extension;
2252 {
2253 /* The dispatching code will add 2 after we return, so
2254 we subtract two here to make things right. */
2255 if (PSW & PSW_Z)
2256 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2257 }
2258
2259 /* bne label:8 */
2260 void OP_C900 (insn, extension)
2261 unsigned long insn, extension;
2262 {
2263 /* The dispatching code will add 2 after we return, so
2264 we subtract two here to make things right. */
2265 if (!(PSW & PSW_Z))
2266 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2267 }
2268
2269 /* bgt label:8 */
2270 void OP_C100 (insn, extension)
2271 unsigned long insn, extension;
2272 {
2273 /* The dispatching code will add 2 after we return, so
2274 we subtract two here to make things right. */
2275 if (!((PSW & PSW_Z)
2276 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2277 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2278 }
2279
2280 /* bge label:8 */
2281 void OP_C200 (insn, extension)
2282 unsigned long insn, extension;
2283 {
2284 /* The dispatching code will add 2 after we return, so
2285 we subtract two here to make things right. */
2286 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2287 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2288 }
2289
2290 /* ble label:8 */
2291 void OP_C300 (insn, extension)
2292 unsigned long insn, extension;
2293 {
2294 /* The dispatching code will add 2 after we return, so
2295 we subtract two here to make things right. */
2296 if ((PSW & PSW_Z)
2297 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2298 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2299 }
2300
2301 /* blt label:8 */
2302 void OP_C000 (insn, extension)
2303 unsigned long insn, extension;
2304 {
2305 /* The dispatching code will add 2 after we return, so
2306 we subtract two here to make things right. */
2307 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2308 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2309 }
2310
2311 /* bhi label:8 */
2312 void OP_C500 (insn, extension)
2313 unsigned long insn, extension;
2314 {
2315 /* The dispatching code will add 2 after we return, so
2316 we subtract two here to make things right. */
2317 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2318 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2319 }
2320
2321 /* bcc label:8 */
2322 void OP_C600 (insn, extension)
2323 unsigned long insn, extension;
2324 {
2325 /* The dispatching code will add 2 after we return, so
2326 we subtract two here to make things right. */
2327 if (!(PSW & PSW_C))
2328 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2329 }
2330
2331 /* bls label:8 */
2332 void OP_C700 (insn, extension)
2333 unsigned long insn, extension;
2334 {
2335 /* The dispatching code will add 2 after we return, so
2336 we subtract two here to make things right. */
2337 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2338 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2339 }
2340
2341 /* bcs label:8 */
2342 void OP_C400 (insn, extension)
2343 unsigned long insn, extension;
2344 {
2345 /* The dispatching code will add 2 after we return, so
2346 we subtract two here to make things right. */
2347 if (PSW & PSW_C)
2348 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2349 }
2350
2351 /* bvc label:8 */
2352 void OP_F8E800 (insn, extension)
2353 unsigned long insn, extension;
2354 {
2355 /* The dispatching code will add 3 after we return, so
2356 we subtract two here to make things right. */
2357 if (!(PSW & PSW_V))
2358 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2359 }
2360
2361 /* bvs label:8 */
2362 void OP_F8E900 (insn, extension)
2363 unsigned long insn, extension;
2364 {
2365 /* The dispatching code will add 3 after we return, so
2366 we subtract two here to make things right. */
2367 if (PSW & PSW_V)
2368 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2369 }
2370
2371 /* bnc label:8 */
2372 void OP_F8EA00 (insn, extension)
2373 unsigned long insn, extension;
2374 {
2375 /* The dispatching code will add 3 after we return, so
2376 we subtract two here to make things right. */
2377 if (!(PSW & PSW_N))
2378 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2379 }
2380
2381 /* bns label:8 */
2382 void OP_F8EB00 (insn, extension)
2383 unsigned long insn, extension;
2384 {
2385 /* The dispatching code will add 3 after we return, so
2386 we subtract two here to make things right. */
2387 if (PSW & PSW_N)
2388 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2389 }
2390
2391 /* bra label:8 */
2392 void OP_CA00 (insn, extension)
2393 unsigned long insn, extension;
2394 {
2395 /* The dispatching code will add 2 after we return, so
2396 we subtract two here to make things right. */
2397 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2398 }
2399
2400 /* leq */
2401 void OP_D8 (insn, extension)
2402 unsigned long insn, extension;
2403 {
2404 /* The dispatching code will add 1 after we return, so
2405 we subtract one here to make things right. */
2406 if (PSW & PSW_Z)
2407 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2408 }
2409
2410 /* lne */
2411 void OP_D9 (insn, extension)
2412 unsigned long insn, extension;
2413 {
2414 /* The dispatching code will add 1 after we return, so
2415 we subtract one here to make things right. */
2416 if (!(PSW & PSW_Z))
2417 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2418 }
2419
2420 /* lgt */
2421 void OP_D1 (insn, extension)
2422 unsigned long insn, extension;
2423 {
2424 /* The dispatching code will add 1 after we return, so
2425 we subtract one here to make things right. */
2426 if (!((PSW & PSW_Z)
2427 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2428 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2429 }
2430
2431 /* lge */
2432 void OP_D2 (insn, extension)
2433 unsigned long insn, extension;
2434 {
2435 /* The dispatching code will add 1 after we return, so
2436 we subtract one here to make things right. */
2437 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2438 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2439 }
2440
2441 /* lle */
2442 void OP_D3 (insn, extension)
2443 unsigned long insn, extension;
2444 {
2445 /* The dispatching code will add 1 after we return, so
2446 we subtract one here to make things right. */
2447 if ((PSW & PSW_Z)
2448 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2449 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2450 }
2451
2452 /* llt */
2453 void OP_D0 (insn, extension)
2454 unsigned long insn, extension;
2455 {
2456 /* The dispatching code will add 1 after we return, so
2457 we subtract one here to make things right. */
2458 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2459 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2460 }
2461
2462 /* lhi */
2463 void OP_D5 (insn, extension)
2464 unsigned long insn, extension;
2465 {
2466 /* The dispatching code will add 1 after we return, so
2467 we subtract one here to make things right. */
2468 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2469 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2470 }
2471
2472 /* lcc */
2473 void OP_D6 (insn, extension)
2474 unsigned long insn, extension;
2475 {
2476 /* The dispatching code will add 1 after we return, so
2477 we subtract one here to make things right. */
2478 if (!(PSW & PSW_C))
2479 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2480 }
2481
2482 /* lls */
2483 void OP_D7 (insn, extension)
2484 unsigned long insn, extension;
2485 {
2486 /* The dispatching code will add 1 after we return, so
2487 we subtract one here to make things right. */
2488 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2489 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2490 }
2491
2492 /* lcs */
2493 void OP_D4 (insn, extension)
2494 unsigned long insn, extension;
2495 {
2496 /* The dispatching code will add 1 after we return, so
2497 we subtract one here to make things right. */
2498 if (PSW & PSW_C)
2499 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2500 }
2501
2502 /* lra */
2503 void OP_DA (insn, extension)
2504 unsigned long insn, extension;
2505 {
2506 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2507 }
2508
2509 /* setlb */
2510 void OP_DB (insn, extension)
2511 unsigned long insn, extension;
2512 {
2513 State.regs[REG_LIR] = load_mem_big (State.regs[REG_PC] + 1, 4);
2514 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
2515 }
2516
2517 /* jmp (an) */
2518 void OP_F0F4 (insn, extension)
2519 unsigned long insn, extension;
2520 {
2521 State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
2522 }
2523
2524 /* jmp label:16 */
2525 void OP_CC0000 (insn, extension)
2526 unsigned long insn, extension;
2527 {
2528 State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 3;
2529 }
2530
2531 /* jmp label:32 */
2532 void OP_DC000000 (insn, extension)
2533 unsigned long insn, extension;
2534 {
2535 State.regs[REG_PC] += (((insn & 0xffffff) << 8) + extension) - 5;
2536 }
2537
2538 /* call label:16,reg_list,imm8 */
2539 void OP_CD000000 (insn, extension)
2540 unsigned long insn, extension;
2541 {
2542 unsigned int next_pc, sp, adjust;
2543 unsigned long mask;
2544
2545 sp = State.regs[REG_SP];
2546 next_pc = State.regs[REG_PC] + 2;
2547 State.mem[sp] = next_pc & 0xff;
2548 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2549 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2550 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2551
2552 mask = insn & 0xff;
2553
2554 adjust = 0;
2555 if (mask & 0x80)
2556 {
2557 adjust -= 4;
2558 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2559 }
2560
2561 if (mask & 0x40)
2562 {
2563 adjust -= 4;
2564 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2565 }
2566
2567 if (mask & 0x20)
2568 {
2569 adjust -= 4;
2570 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2571 }
2572
2573 if (mask & 0x10)
2574 {
2575 adjust -= 4;
2576 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2577 }
2578
2579 if (mask & 0x8)
2580 {
2581 adjust -= 4;
2582 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2583 adjust -= 4;
2584 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2585 adjust -= 4;
2586 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2587 adjust -= 4;
2588 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2589 adjust -= 4;
2590 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2591 adjust -= 4;
2592 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2593 adjust -= 4;
2594 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2595 adjust -= 4;
2596 }
2597
2598 /* And make sure to update the stack pointer. */
2599 State.regs[REG_SP] -= extension;
2600 State.regs[REG_MDR] = next_pc;
2601 State.regs[REG_PC] += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2602 }
2603
2604 /* call label:32,reg_list,imm8*/
2605 void OP_DD000000 (insn, extension)
2606 unsigned long insn, extension;
2607 {
2608 unsigned int next_pc, sp, adjust;
2609 unsigned long mask;
2610
2611 sp = State.regs[REG_SP];
2612 next_pc = State.regs[REG_PC] + 2;
2613 State.mem[sp] = next_pc & 0xff;
2614 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2615 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2616 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2617
2618 mask = (extension & 0xff00) >> 8;
2619
2620 adjust = 0;
2621 if (mask & 0x80)
2622 {
2623 adjust -= 4;
2624 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2625 }
2626
2627 if (mask & 0x40)
2628 {
2629 adjust -= 4;
2630 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2631 }
2632
2633 if (mask & 0x20)
2634 {
2635 adjust -= 4;
2636 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2637 }
2638
2639 if (mask & 0x10)
2640 {
2641 adjust -= 4;
2642 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2643 }
2644
2645 if (mask & 0x8)
2646 {
2647 adjust -= 4;
2648 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2649 adjust -= 4;
2650 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2651 adjust -= 4;
2652 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2653 adjust -= 4;
2654 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2655 adjust -= 4;
2656 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2657 adjust -= 4;
2658 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2659 adjust -= 4;
2660 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2661 adjust -= 4;
2662 }
2663
2664 /* And make sure to update the stack pointer. */
2665 State.regs[REG_SP] -= (extension & 0xff);
2666 State.regs[REG_MDR] = next_pc;
2667 State.regs[REG_PC] += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2668 }
2669
2670 /* calls (an) */
2671 void OP_F0F0 (insn, extension)
2672 unsigned long insn, extension;
2673 {
2674 unsigned int next_pc, sp;
2675
2676 sp = State.regs[REG_SP];
2677 next_pc = State.regs[REG_PC] + 2;
2678 State.mem[sp] = next_pc & 0xff;
2679 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2680 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2681 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2682 State.regs[REG_MDR] = next_pc;
2683 State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
2684 }
2685
2686 /* calls label:16 */
2687 void OP_FAFF0000 (insn, extension)
2688 unsigned long insn, extension;
2689 {
2690 unsigned int next_pc, sp;
2691
2692 sp = State.regs[REG_SP];
2693 next_pc = State.regs[REG_PC] + 4;
2694 State.mem[sp] = next_pc & 0xff;
2695 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2696 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2697 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2698 State.regs[REG_MDR] = next_pc;
2699 State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 4;
2700 }
2701
2702 /* calls label:32 */
2703 void OP_FCFF0000 (insn, extension)
2704 unsigned long insn, extension;
2705 {
2706 unsigned int next_pc, sp;
2707
2708 sp = State.regs[REG_SP];
2709 next_pc = State.regs[REG_PC] + 6;
2710 State.mem[sp] = next_pc & 0xff;
2711 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2712 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2713 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2714 State.regs[REG_MDR] = next_pc;
2715 State.regs[REG_PC] += (((insn & 0xffff) << 16) + extension) - 6;
2716 }
2717
2718 /* ret reg_list, imm8 */
2719 void OP_DF0000 (insn, extension)
2720 unsigned long insn, extension;
2721 {
2722 unsigned int sp;
2723 unsigned long mask;
2724
2725 State.regs[REG_SP] += insn & 0xff;
2726 sp = State.regs[REG_SP];
2727
2728 mask = (insn & 0xff00) >> 8;
2729
2730 if (mask & 0x8)
2731 {
2732 sp += 4;
2733 State.regs[REG_LAR] = load_mem (sp, 4);
2734 sp += 4;
2735 State.regs[REG_LIR] = load_mem (sp, 4);
2736 sp += 4;
2737 State.regs[REG_MDR] = load_mem (sp, 4);
2738 sp += 4;
2739 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2740 sp += 4;
2741 State.regs[REG_A0] = load_mem (sp, 4);
2742 sp += 4;
2743 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2744 sp += 4;
2745 State.regs[REG_D0] = load_mem (sp, 4);
2746 sp += 4;
2747 }
2748
2749 if (mask & 0x10)
2750 {
2751 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2752 sp += 4;
2753 }
2754
2755 if (mask & 0x20)
2756 {
2757 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2758 sp += 4;
2759 }
2760
2761 if (mask & 0x40)
2762 {
2763 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2764 sp += 4;
2765 }
2766
2767 if (mask & 0x80)
2768 {
2769 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2770 sp += 4;
2771 }
2772
2773 /* And make sure to update the stack pointer. */
2774 State.regs[REG_SP] = sp;
2775
2776 /* Restore the PC value. */
2777 State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
2778 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2779 State.regs[REG_PC] -= 3;
2780 }
2781
2782 /* retf reg_list,imm8 */
2783 void OP_DE0000 (insn, extension)
2784 unsigned long insn, extension;
2785 {
2786 unsigned int sp;
2787 unsigned long mask;
2788
2789 sp = State.regs[REG_SP] + (insn & 0xff);
2790 State.regs[REG_SP] = sp;
2791 State.regs[REG_PC] = State.regs[REG_MDR] - 3;
2792
2793 sp = State.regs[REG_SP];
2794
2795 mask = (insn & 0xff00) >> 8;
2796
2797 if (mask & 0x8)
2798 {
2799 sp += 4;
2800 State.regs[REG_LAR] = load_mem (sp, 4);
2801 sp += 4;
2802 State.regs[REG_LIR] = load_mem (sp, 4);
2803 sp += 4;
2804 State.regs[REG_MDR] = load_mem (sp, 4);
2805 sp += 4;
2806 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2807 sp += 4;
2808 State.regs[REG_A0] = load_mem (sp, 4);
2809 sp += 4;
2810 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2811 sp += 4;
2812 State.regs[REG_D0] = load_mem (sp, 4);
2813 sp += 4;
2814 }
2815
2816 if (mask & 0x10)
2817 {
2818 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2819 sp += 4;
2820 }
2821
2822 if (mask & 0x20)
2823 {
2824 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2825 sp += 4;
2826 }
2827
2828 if (mask & 0x40)
2829 {
2830 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2831 sp += 4;
2832 }
2833
2834 if (mask & 0x80)
2835 {
2836 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2837 sp += 4;
2838 }
2839
2840 /* And make sure to update the stack pointer. */
2841 State.regs[REG_SP] = sp;
2842 }
2843
2844 /* rets */
2845 void OP_F0FC (insn, extension)
2846 unsigned long insn, extension;
2847 {
2848 unsigned int sp;
2849
2850 sp = State.regs[REG_SP];
2851 State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
2852 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2853 State.regs[REG_PC] -= 2;
2854 }
2855
2856 /* rti */
2857 void OP_F0FD (insn, extension)
2858 unsigned long insn, extension;
2859 {
2860 unsigned int sp, next_pc;
2861
2862 PSW = State.mem[sp] | (State.mem[sp + 1] << 8);
2863 State.regs[REG_PC] = (State.mem[sp+4] | (State.mem[sp+5] << 8)
2864 | (State.mem[sp+6] << 16) | (State.mem[sp+7] << 24));
2865 State.regs[REG_SP] += 8;
2866 }
2867
2868 /* trap */
2869 void OP_F0FE (insn, extension)
2870 unsigned long insn, extension;
2871 {
2872 unsigned int sp, next_pc;
2873
2874 sp = State.regs[REG_SP];
2875 next_pc = State.regs[REG_PC] + 2;
2876 State.mem[sp] = next_pc & 0xff;
2877 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2878 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2879 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2880 State.regs[REG_PC] = 0x40000010 - 2;
2881 abort ();
2882 }
2883
2884 /* syscall */
2885 void OP_F020 (insn, extension)
2886 unsigned long insn, extension;
2887 {
2888 /* We use this for simulated system calls; we may need to change
2889 it to a reserved instruction if we conflict with uses at
2890 Matsushita. */
2891 int save_errno = errno;
2892 errno = 0;
2893
2894 /* Registers passed to trap 0 */
2895
2896 /* Function number. */
2897 #define FUNC (State.regs[0])
2898
2899 /* Parameters. */
2900 #define PARM1 (State.regs[1])
2901 #define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2902 #define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2903
2904 /* Registers set by trap 0 */
2905
2906 #define RETVAL State.regs[0] /* return value */
2907 #define RETERR State.regs[1] /* return error code */
2908
2909 /* Turn a pointer in a register into a pointer into real memory. */
2910
2911 #define MEMPTR(x) (State.mem + x)
2912
2913 switch (FUNC)
2914 {
2915 #if !defined(__GO32__) && !defined(_WIN32)
2916 case SYS_fork:
2917 RETVAL = fork ();
2918 break;
2919 case SYS_execve:
2920 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2921 (char **)MEMPTR (PARM3));
2922 break;
2923 case SYS_execv:
2924 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2925 break;
2926 #endif
2927
2928 case SYS_read:
2929 RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
2930 MEMPTR (PARM2), PARM3);
2931 break;
2932 case SYS_write:
2933 if (PARM1 == 1)
2934 RETVAL = (int)mn10300_callback->write_stdout (mn10300_callback,
2935 MEMPTR (PARM2), PARM3);
2936 else
2937 RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
2938 MEMPTR (PARM2), PARM3);
2939 break;
2940 case SYS_lseek:
2941 RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
2942 break;
2943 case SYS_close:
2944 RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
2945 break;
2946 case SYS_open:
2947 RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
2948 break;
2949 case SYS_exit:
2950 /* EXIT - caller can look in PARM1 to work out the
2951 reason */
2952 if (PARM1 == 0xdead || PARM1 == 0x1)
2953 State.exception = SIGABRT;
2954 else
2955 State.exception = SIGQUIT;
2956 break;
2957
2958 case SYS_stat: /* added at hmsi */
2959 /* stat system call */
2960 {
2961 struct stat host_stat;
2962 reg_t buf;
2963
2964 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2965
2966 buf = PARM2;
2967
2968 /* Just wild-assed guesses. */
2969 store_mem (buf, 2, host_stat.st_dev);
2970 store_mem (buf + 2, 2, host_stat.st_ino);
2971 store_mem (buf + 4, 4, host_stat.st_mode);
2972 store_mem (buf + 8, 2, host_stat.st_nlink);
2973 store_mem (buf + 10, 2, host_stat.st_uid);
2974 store_mem (buf + 12, 2, host_stat.st_gid);
2975 store_mem (buf + 14, 2, host_stat.st_rdev);
2976 store_mem (buf + 16, 4, host_stat.st_size);
2977 store_mem (buf + 20, 4, host_stat.st_atime);
2978 store_mem (buf + 28, 4, host_stat.st_mtime);
2979 store_mem (buf + 36, 4, host_stat.st_ctime);
2980 }
2981 break;
2982
2983 case SYS_chown:
2984 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2985 break;
2986 case SYS_chmod:
2987 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2988 break;
2989 case SYS_time:
2990 RETVAL = time (MEMPTR (PARM1));
2991 break;
2992 case SYS_times:
2993 {
2994 struct tms tms;
2995 RETVAL = times (&tms);
2996 store_mem (PARM1, 4, tms.tms_utime);
2997 store_mem (PARM1 + 4, 4, tms.tms_stime);
2998 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2999 store_mem (PARM1 + 12, 4, tms.tms_cstime);
3000 break;
3001 }
3002 case SYS_gettimeofday:
3003 {
3004 struct timeval t;
3005 struct timezone tz;
3006 RETVAL = gettimeofday (&t, &tz);
3007 store_mem (PARM1, 4, t.tv_sec);
3008 store_mem (PARM1 + 4, 4, t.tv_usec);
3009 store_mem (PARM2, 4, tz.tz_minuteswest);
3010 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
3011 break;
3012 }
3013 case SYS_utime:
3014 /* Cast the second argument to void *, to avoid type mismatch
3015 if a prototype is present. */
3016 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
3017 break;
3018 default:
3019 abort ();
3020 }
3021 RETERR = errno;
3022 errno = save_errno;
3023 }
3024
3025 /* rtm */
3026 void OP_F0FF (insn, extension)
3027 unsigned long insn, extension;
3028 {
3029 abort ();
3030 }
3031
3032 /* nop */
3033 void OP_CB (insn, extension)
3034 unsigned long insn, extension;
3035 {
3036 }
3037
3038 /* putx */
3039 void OP_F500 (insn, extension)
3040 unsigned long insn, extension;
3041 {
3042 abort ();
3043 }
3044
3045 /* getx */
3046 void OP_F6F0 (insn, extension)
3047 unsigned long insn, extension;
3048 {
3049 abort ();
3050 }
3051
3052 /* mulq */
3053 void OP_F600 (insn, extension)
3054 unsigned long insn, extension;
3055 {
3056 abort ();
3057 }
3058
3059 /* mulq */
3060 void OP_F90000 (insn, extension)
3061 unsigned long insn, extension;
3062 {
3063 abort ();
3064 }
3065
3066 /* mulq */
3067 void OP_FB000000 (insn, extension)
3068 unsigned long insn, extension;
3069 {
3070 abort ();
3071 }
3072
3073 /* mulq */
3074 void OP_FD000000 (insn, extension)
3075 unsigned long insn, extension;
3076 {
3077 abort ();
3078 }
3079
3080 /* mulqu */
3081 void OP_F610 (insn, extension)
3082 unsigned long insn, extension;
3083 {
3084 abort ();
3085 }
3086
3087 /* mulqu */
3088 void OP_F91400 (insn, extension)
3089 unsigned long insn, extension;
3090 {
3091 abort ();
3092 }
3093
3094 /* mulqu */
3095 void OP_FB140000 (insn, extension)
3096 unsigned long insn, extension;
3097 {
3098 abort ();
3099 }
3100
3101 /* mulqu */
3102 void OP_FD140000 (insn, extension)
3103 unsigned long insn, extension;
3104 {
3105 abort ();
3106 }
3107
3108 /* sat16 */
3109 void OP_F640 (insn, extension)
3110 unsigned long insn, extension;
3111 {
3112 abort ();
3113 }
3114
3115 /* sat24 */
3116 void OP_F650 (insn, extension)
3117 unsigned long insn, extension;
3118 {
3119 abort ();
3120 }
3121
3122 /* bsch */
3123 void OP_F670 (insn, extension)
3124 unsigned long insn, extension;
3125 {
3126 abort ();
3127 }
3128
3129 /* breakpoint */
3130 void
3131 OP_FF (insn, extension)
3132 unsigned long insn, extension;
3133 {
3134 State.exception = SIGTRAP;
3135 PC -= 1;
3136 }
3137
GDB Binutils - Deliverables
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