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* simops.c: Fix "movdm, an", "movbu dm, (an)", and "movhu dm, (an)".
[deliverable/binutils-gdb.git] / sim / mn10300 / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #ifdef HAVE_UNISTD_H
5 #include <unistd.h>
6 #endif
7 #include "mn10300_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10 #include "bfd.h"
11 #include <errno.h>
12 #include <sys/stat.h>
13 #include <sys/times.h>
14 #include <sys/time.h>
15
16 enum op_types {
17 OP_UNKNOWN,
18 };
19
20 #ifdef DEBUG
21 static void trace_input PARAMS ((char *name, enum op_types type, int size));
22 static void trace_output PARAMS ((enum op_types result));
23 static int init_text_p = 0;
24 static asection *text;
25 static bfd_vma text_start;
26 static bfd_vma text_end;
27 extern bfd *exec_bfd;
28
29 #ifndef SIZE_INSTRUCTION
30 #define SIZE_INSTRUCTION 6
31 #endif
32
33 #ifndef SIZE_OPERANDS
34 #define SIZE_OPERANDS 16
35 #endif
36
37 #ifndef SIZE_VALUES
38 #define SIZE_VALUES 11
39 #endif
40
41 #ifndef SIZE_LOCATION
42 #define SIZE_LOCATION 40
43 #endif
44
45 static void
46 trace_input (name, type, size)
47 char *name;
48 enum op_types type;
49 int size;
50 {
51 }
52
53 static void
54 trace_output (result)
55 enum op_types result;
56 {
57 }
58
59 #else
60 #define trace_input(NAME, IN1, IN2)
61 #define trace_output(RESULT)
62 #endif
63
64 \f
65 /* mov imm8, dn */
66 void OP_8000 ()
67 {
68 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = SEXT8 (insn & 0xff);
69 }
70
71 /* mov dm, dn */
72 void OP_80 ()
73 {
74 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
75 }
76
77 /* mov dm, an */
78 void OP_F1E0 ()
79 {
80 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
81 }
82
83 /* mov am, dn */
84 void OP_F1D0 ()
85 {
86 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
87 }
88
89 /* mov imm8, an */
90 void OP_9000 ()
91 {
92 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = insn & 0xff;
93 }
94
95 /* mov am, an */
96 void OP_90 ()
97 {
98 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
99 }
100
101 /* mov sp, an */
102 void OP_3C ()
103 {
104 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_SP];
105 }
106
107 /* mov am, sp */
108 void OP_F2F0 ()
109 {
110 State.regs[REG_SP] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
111 }
112
113 /* mov psw, dn */
114 void OP_F2E4 ()
115 {
116 State.regs[REG_D0 + (insn & 0x3)] = PSW;
117 }
118
119 /* mov dm, psw */
120 void OP_F2F3 ()
121 {
122 PSW = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
123 }
124
125 /* mov mdr, dn */
126 void OP_F2E0 ()
127 {
128 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_MDR];
129 }
130
131 /* mov dm, mdr */
132 void OP_F2F2 ()
133 {
134 State.regs[REG_MDR] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
135 }
136
137 /* mov (am), dn */
138 void OP_70 ()
139 {
140 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
141 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
142 }
143
144 /* mov (d8,am), dn */
145 void OP_F80000 ()
146 {
147 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
148 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
149 + SEXT8 (insn & 0xff)), 4);
150 }
151
152 /* mov (d16,am), dn */
153 void OP_FA000000 ()
154 {
155 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
156 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
157 + SEXT16 (insn & 0xffff)), 4);
158 }
159
160 /* mov (d32,am), dn */
161 void OP_FC000000 ()
162 {
163 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
164 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
165 + ((insn & 0xffff) << 16) | extension), 4);
166 }
167
168 /* mov (d8,sp), dn */
169 void OP_5800 ()
170 {
171 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
172 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
173 }
174
175 /* mov (d16,sp), dn */
176 void OP_FAB40000 ()
177 {
178 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
179 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
180 }
181
182 /* mov (d32,sp), dn */
183 void OP_FCB40000 ()
184 {
185 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
186 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
187 }
188
189 /* mov (di,am), dn */
190 void OP_F300 ()
191 {
192 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
193 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
194 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
195 }
196
197 /* mov (abs16), dn */
198 void OP_300000 ()
199 {
200 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
201 }
202
203 /* mov (abs32), dn */
204 void OP_FCA40000 ()
205 {
206 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
207 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
208 }
209
210 /* mov (am), an */
211 void OP_F000 ()
212 {
213 State.regs[REG_A0 + ((insn & 0xc) >> 2)]
214 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
215 }
216
217 /* mov (d8,am), an */
218 void OP_F82000 ()
219 {
220 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]
221 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
222 + SEXT8 (insn & 0xff)), 4);
223 }
224
225 /* mov (d16,am), an */
226 void OP_FA200000 ()
227 {
228 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
229 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
230 + SEXT16 (insn & 0xffff)), 4);
231 }
232
233 /* mov (d32,am), an */
234 void OP_FC200000 ()
235 {
236 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
237 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
238 + ((insn & 0xffff) << 16) + extension), 4);
239 }
240
241 /* mov (d8,sp), an */
242 void OP_5C00 ()
243 {
244 State.regs[REG_A0 + ((insn & 0x300) >> 8)]
245 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
246 }
247
248 /* mov (d16,sp), an */
249 void OP_FAB00000 ()
250 {
251 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
252 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
253 }
254
255 /* mov (d32,sp), an */
256 void OP_FCB00000 ()
257 {
258 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
259 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
260 }
261
262 /* mov (di,am), an */
263 void OP_F380 ()
264 {
265 State.regs[REG_A0 + ((insn & 0x300) >> 8)]
266 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
267 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
268 }
269
270 /* mov (abs16), an */
271 void OP_FAA00000 ()
272 {
273 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
274 }
275
276 /* mov (abs32), an */
277 void OP_FCA00000 ()
278 {
279 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
280 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
281 }
282
283 /* mov (d8,am), sp */
284 void OP_F8F000 ()
285 {
286 State.regs[REG_SP]
287 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
288 + SEXT8 (insn & 0xff)), 4);
289 }
290
291 /* mov dm, (an) */
292 void OP_60 ()
293 {
294 store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
295 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
296 }
297
298 /* mov dm, (d8,an) */
299 void OP_F81000 ()
300 {
301 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
302 + SEXT8 (insn & 0xff)), 4,
303 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
304 }
305
306 /* mov dm (d16,an) */
307 void OP_FA100000 ()
308 {
309 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
310 + SEXT16 (insn & 0xffff)), 4,
311 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
312 }
313
314 /* mov dm (d32,an) */
315 void OP_FC100000 ()
316 {
317 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
318 + ((insn & 0xffff) << 16) + extension), 4,
319 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
320 }
321
322 /* mov dm, (d8,sp) */
323 void OP_4200 ()
324 {
325 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
326 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
327 }
328
329 /* mov dm, (d16,sp) */
330 void OP_FA910000 ()
331 {
332 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
333 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
334 }
335
336 /* mov dm, (d32,sp) */
337 void OP_FC910000 ()
338 {
339 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
340 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
341 }
342
343 /* mov dm, (di,an) */
344 void OP_F340 ()
345 {
346 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
347 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
348 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
349 }
350
351 /* mov dm, (abs16) */
352 void OP_10000 ()
353 {
354 store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
355 }
356
357 /* mov dm, (abs32) */
358 void OP_FC810000 ()
359 {
360 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
361 }
362
363 /* mov am, (an) */
364 void OP_F010 ()
365 {
366 store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
367 State.regs[REG_A0 + ((insn & 0xc) >> 2)]);
368 }
369
370 /* mov am, (d8,an) */
371 void OP_F83000 ()
372 {
373 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
374 + SEXT8 (insn & 0xff)), 4,
375 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
376 }
377
378 /* mov am, (d16,an) */
379 void OP_FA300000 ()
380 {
381 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 17)]
382 + SEXT16 (insn & 0xffff)), 4,
383 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
384 }
385
386 /* mov am, (d32,an) */
387 void OP_FC300000 ()
388 {
389 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 17)]
390 + ((insn & 0xffff) << 16) + extension), 4,
391 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
392 }
393
394 /* mov am, (d8,sp) */
395 void OP_4300 ()
396 {
397 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
398 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
399 }
400
401 /* mov am, (d16,sp) */
402 void OP_FA900000 ()
403 {
404 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
405 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
406 }
407
408 /* mov am, (d32,sp) */
409 void OP_FC900000 ()
410 {
411 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
412 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
413 }
414
415 /* mov am, (di,an) */
416 void OP_F3C0 ()
417 {
418 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
419 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
420 State.regs[REG_A0 + ((insn & 0x300) >> 8)]);
421 }
422
423 /* mov am, (abs16) */
424 void OP_FA800000 ()
425 {
426 store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
427 }
428
429 /* mov am, (abs32) */
430 void OP_FC800000 ()
431 {
432 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
433 }
434
435 /* mov sp, (d8,an) */
436 void OP_F8F400 ()
437 {
438 store_mem (State.regs[REG_A0 + ((insn & 0x300) >> 8)] + SEXT8 (insn & 0xff),
439 4, State.regs[REG_SP]);
440 }
441
442 /* mov imm16, dn */
443 void OP_2C0000 ()
444 {
445 unsigned long value;
446
447 value = SEXT16 (insn & 0xffff);
448 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
449 }
450
451 /* mov imm32,dn */
452 void OP_FCCC0000 ()
453 {
454 unsigned long value;
455
456 value = (insn & 0xffff) << 16 | extension;
457 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
458 }
459
460 /* mov imm16, an */
461 void OP_240000 ()
462 {
463 unsigned long value;
464
465 value = insn & 0xffff;
466 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
467 }
468
469 /* mov imm32, an */
470 void OP_FCDC0000 ()
471 {
472 unsigned long value;
473
474 value = (insn & 0xffff) << 16 | extension;
475 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
476 }
477
478 /* movbu (am), dn */
479 void OP_F040 ()
480 {
481 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
482 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 1);
483 }
484
485 /* movbu (d8,am), dn */
486 void OP_F84000 ()
487 {
488 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
489 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
490 + SEXT8 (insn & 0xff)), 1);
491 }
492
493 /* movbu (d16,am), dn */
494 void OP_FA400000 ()
495 {
496 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
497 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
498 + SEXT16 (insn & 0xffff)), 1);
499 }
500
501 /* movbu (d32,am), dn */
502 void OP_FC400000 ()
503 {
504 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
505 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
506 + ((insn & 0xffff) << 16) + extension), 1);
507 }
508
509 /* movbu (d8,sp), dn */
510 void OP_F8B800 ()
511 {
512 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
513 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
514 }
515
516 /* movbu (d16,sp), dn */
517 void OP_FAB80000 ()
518 {
519 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
520 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
521 }
522
523 /* movbu (d32,sp), dn */
524 void OP_FCB80000 ()
525 {
526 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
527 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
528 }
529
530 /* movbu (di,am), dn */
531 void OP_F400 ()
532 {
533 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
534 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
535 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
536 }
537
538 /* movbu (abs16), dn */
539 void OP_340000 ()
540 {
541 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 1);
542 }
543
544 /* movbu (abs32), dn */
545 void OP_FCA80000 ()
546 {
547 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
548 = load_mem ((((insn & 0xffff) << 16) + extension), 1);
549 }
550
551 /* movbu dm, (an) */
552 void OP_F050 ()
553 {
554 store_mem (State.regs[REG_A0 + (insn & 0x3)], 1,
555 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
556 }
557
558 /* movbu dm, (d8,an) */
559 void OP_F85000 ()
560 {
561 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
562 + SEXT8 (insn & 0xff)), 1,
563 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
564 }
565
566 /* movbu dm, (d16,an) */
567 void OP_FA500000 ()
568 {
569 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
570 + SEXT16 (insn & 0xffff)), 1,
571 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
572 }
573
574 /* movbu dm, (d32,an) */
575 void OP_FC500000 ()
576 {
577 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
578 + ((insn & 0xffff) << 16) + extension), 1,
579 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
580 }
581
582 /* movbu dm, (d8,sp) */
583 void OP_F89200 ()
584 {
585 store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
586 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
587 }
588
589 /* movbu dm, (d16,sp) */
590 void OP_FA920000 ()
591 {
592 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
593 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
594 }
595
596 /* movbu dm (d32,sp) */
597 void OP_FC920000 ()
598 {
599 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
600 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
601 }
602
603 /* movbu dm, (di,an) */
604 void OP_F440 ()
605 {
606 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
607 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
608 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
609 }
610
611 /* movbu dm, (abs16) */
612 void OP_20000 ()
613 {
614 store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
615 }
616
617 /* movbu dm, (abs32) */
618 void OP_FC820000 ()
619 {
620 store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
621 }
622
623 /* movhu (am), dn */
624 void OP_F060 ()
625 {
626 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
627 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 2);
628 }
629
630 /* movhu (d8,am), dn */
631 void OP_F86000 ()
632 {
633 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
634 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
635 + SEXT8 (insn & 0xff)), 2);
636 }
637
638 /* movhu (d16,am), dn */
639 void OP_FA600000 ()
640 {
641 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
642 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
643 + SEXT16 (insn & 0xffff)), 2);
644 }
645
646 /* movhu (d32,am), dn */
647 void OP_FC600000 ()
648 {
649 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
650 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
651 + ((insn & 0xffff) << 16) + extension), 2);
652 }
653
654 /* movhu (d8,sp) dn */
655 void OP_F8BC00 ()
656 {
657 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
658 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
659 }
660
661 /* movhu (d16,sp), dn */
662 void OP_FABC0000 ()
663 {
664 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
665 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
666 }
667
668 /* movhu (d32,sp), dn */
669 void OP_FCBC0000 ()
670 {
671 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
672 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
673 }
674
675 /* movhu (di,am), dn */
676 void OP_F480 ()
677 {
678 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
679 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
680 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
681 }
682
683 /* movhu (abs16), dn */
684 void OP_380000 ()
685 {
686 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 2);
687 }
688
689 /* movhu (abs32), dn */
690 void OP_FCAC0000 ()
691 {
692 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
693 = load_mem ((((insn & 0xffff) << 16) + extension), 2);
694 }
695
696 /* movhu dm, (an) */
697 void OP_F070 ()
698 {
699 store_mem (State.regs[REG_A0 + (insn & 0x3)], 2,
700 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
701 }
702
703 /* movhu dm, (d8,an) */
704 void OP_F87000 ()
705 {
706 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
707 + SEXT8 (insn & 0xff)), 2,
708 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
709 }
710
711 /* movhu dm, (d16,an) */
712 void OP_FA700000 ()
713 {
714 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
715 + SEXT16 (insn & 0xffff)), 2,
716 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
717 }
718
719 /* movhu dm, (d32,an) */
720 void OP_FC700000 ()
721 {
722 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
723 + ((insn & 0xffff) << 16) + extension), 2,
724 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
725 }
726
727 /* movhu dm,(d8,sp) */
728 void OP_F89300 ()
729 {
730 store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
731 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
732 }
733
734 /* movhu dm,(d16,sp) */
735 void OP_FA930000 ()
736 {
737 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
738 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
739 }
740
741 /* movhu dm,(d32,sp) */
742 void OP_FC930000 ()
743 {
744 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
745 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
746 }
747
748 /* movhu dm, (di,an) */
749 void OP_F4C0 ()
750 {
751 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
752 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
753 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
754 }
755
756 /* movhu dm, (abs16) */
757 void OP_30000 ()
758 {
759 store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
760 }
761
762 /* movhu dm, (abs32) */
763 void OP_FC830000 ()
764 {
765 store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
766 }
767
768 /* ext dn */
769 void OP_F2D0 ()
770 {
771 if (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000)
772 State.regs[REG_MDR] = -1;
773 else
774 State.regs[REG_MDR] = 0;
775 }
776
777 /* extb dn */
778 void OP_10 ()
779 {
780 State.regs[REG_D0 + (insn & 0x3)] = SEXT8 (State.regs[REG_D0 + (insn & 0x3)]);
781 }
782
783 /* extbu dn */
784 void OP_14 ()
785 {
786 State.regs[REG_D0 + (insn & 0x3)] &= 0xff;
787 }
788
789 /* exth dn */
790 void OP_18 ()
791 {
792 State.regs[REG_D0 + (insn & 0x3)]
793 = SEXT16 (State.regs[REG_D0 + (insn & 0x3)]);
794 }
795
796 /* exthu dn */
797 void OP_1C ()
798 {
799 State.regs[REG_D0 + (insn & 0x3)] &= 0xffff;
800 }
801
802 /* movm (sp), reg_list */
803 void OP_CE00 ()
804 {
805 unsigned long sp = State.regs[REG_SP];
806 unsigned long mask;
807
808 mask = insn & 0xff;
809
810 if (mask & 0x8)
811 {
812 sp += 4;
813 State.regs[REG_LAR] = load_mem (sp, 4);
814 sp += 4;
815 State.regs[REG_LIR] = load_mem (sp, 4);
816 sp += 4;
817 State.regs[REG_MDR] = load_mem (sp, 4);
818 sp += 4;
819 State.regs[REG_A0 + 1] = load_mem (sp, 4);
820 sp += 4;
821 State.regs[REG_A0] = load_mem (sp, 4);
822 sp += 4;
823 State.regs[REG_D0 + 1] = load_mem (sp, 4);
824 sp += 4;
825 State.regs[REG_D0] = load_mem (sp, 4);
826 sp += 4;
827 }
828
829 if (mask & 0x10)
830 {
831 State.regs[REG_A0 + 3] = load_mem (sp, 4);
832 sp += 4;
833 }
834
835 if (mask & 0x20)
836 {
837 State.regs[REG_A0 + 2] = load_mem (sp, 4);
838 sp += 4;
839 }
840
841 if (mask & 0x40)
842 {
843 State.regs[REG_D0 + 3] = load_mem (sp, 4);
844 sp += 4;
845 }
846
847 if (mask & 0x80)
848 {
849 State.regs[REG_D0 + 2] = load_mem (sp, 4);
850 sp += 4;
851 }
852
853 /* And make sure to update the stack pointer. */
854 State.regs[REG_SP] = sp;
855 }
856
857 /* movm reg_list, (sp) */
858 void OP_CF00 ()
859 {
860 unsigned long sp = State.regs[REG_SP];
861 unsigned long mask;
862
863 mask = insn & 0xff;
864
865 if (mask & 0x80)
866 {
867 sp -= 4;
868 store_mem (sp, 4, State.regs[REG_D0 + 2]);
869 }
870
871 if (mask & 0x40)
872 {
873 sp -= 4;
874 store_mem (sp, 4, State.regs[REG_D0 + 3]);
875 }
876
877 if (mask & 0x20)
878 {
879 sp -= 4;
880 store_mem (sp, 4, State.regs[REG_A0 + 2]);
881 }
882
883 if (mask & 0x10)
884 {
885 sp -= 4;
886 store_mem (sp, 4, State.regs[REG_A0 + 3]);
887 }
888
889 if (mask & 0x8)
890 {
891 sp -= 4;
892 store_mem (sp, 4, State.regs[REG_D0]);
893 sp -= 4;
894 store_mem (sp, 4, State.regs[REG_D0 + 1]);
895 sp -= 4;
896 store_mem (sp, 4, State.regs[REG_A0]);
897 sp -= 4;
898 store_mem (sp, 4, State.regs[REG_A0 + 1]);
899 sp -= 4;
900 store_mem (sp, 4, State.regs[REG_MDR]);
901 sp -= 4;
902 store_mem (sp, 4, State.regs[REG_LIR]);
903 sp -= 4;
904 store_mem (sp, 4, State.regs[REG_LAR]);
905 sp -= 4;
906 }
907
908 /* And make sure to update the stack pointer. */
909 State.regs[REG_SP] = sp;
910 }
911
912 /* clr dn */
913 void OP_0 ()
914 {
915 State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
916
917 PSW |= PSW_Z;
918 PSW &= ~(PSW_V | PSW_C | PSW_N);
919 }
920
921 /* add dm,dn */
922 void OP_E0 ()
923 {
924 int z, c, n, v;
925 unsigned long reg1, reg2, value;
926
927 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
928 reg2 = State.regs[REG_D0 + (insn & 0x3)];
929 value = reg1 + reg2;
930 State.regs[REG_D0 + (insn & 0x3)] = value;
931
932 z = (value == 0);
933 n = (value & 0x80000000);
934 c = (reg1 < reg2);
935 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
936 && (reg2 & 0x8000000) != (value & 0x80000000));
937
938 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
939 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
940 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
941 }
942
943 /* add dm, an */
944 void OP_F160 ()
945 {
946 int z, c, n, v;
947 unsigned long reg1, reg2, value;
948
949 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
950 reg2 = State.regs[REG_A0 + (insn & 0x3)];
951 value = reg1 + reg2;
952 State.regs[REG_A0 + (insn & 0x3)] = value;
953
954 z = (value == 0);
955 n = (value & 0x80000000);
956 c = (reg1 < reg2);
957 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
958 && (reg2 & 0x8000000) != (value & 0x80000000));
959
960 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
961 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
962 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
963 }
964
965 /* add am, dn */
966 void OP_F150 ()
967 {
968 int z, c, n, v;
969 unsigned long reg1, reg2, value;
970
971 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
972 reg2 = State.regs[REG_D0 + (insn & 0x3)];
973 value = reg1 + reg2;
974 State.regs[REG_D0 + (insn & 0x3)] = value;
975
976 z = (value == 0);
977 n = (value & 0x80000000);
978 c = (reg1 < reg2);
979 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
980 && (reg2 & 0x8000000) != (value & 0x80000000));
981
982 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
983 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
984 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
985 }
986
987 /* add am,an */
988 void OP_F170 ()
989 {
990 int z, c, n, v;
991 unsigned long reg1, reg2, value;
992
993 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
994 reg2 = State.regs[REG_A0 + (insn & 0x3)];
995 value = reg1 + reg2;
996 State.regs[REG_A0 + (insn & 0x3)] = value;
997
998 z = (value == 0);
999 n = (value & 0x80000000);
1000 c = (reg1 < reg2);
1001 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1002 && (reg2 & 0x8000000) != (value & 0x80000000));
1003
1004 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1005 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1006 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1007 }
1008
1009 /* add imm8, dn */
1010 void OP_2800 ()
1011 {
1012 int z, c, n, v;
1013 unsigned long reg1, imm, value;
1014
1015 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1016 imm = SEXT8 (insn & 0xff);
1017 value = reg1 + imm;
1018 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = value;
1019
1020 z = (value == 0);
1021 n = (value & 0x80000000);
1022 c = (reg1 < imm);
1023 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1024 && (imm & 0x8000000) != (value & 0x80000000));
1025
1026 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1027 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1028 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1029 }
1030
1031 /* add imm16, dn */
1032 void OP_FAC00000 ()
1033 {
1034 int z, c, n, v;
1035 unsigned long reg1, imm, value;
1036
1037 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1038 imm = SEXT16 (insn & 0xffff);
1039 value = reg1 + imm;
1040 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1041
1042 z = (value == 0);
1043 n = (value & 0x80000000);
1044 c = (reg1 < imm);
1045 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1046 && (imm & 0x8000000) != (value & 0x80000000));
1047
1048 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1049 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1050 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1051 }
1052
1053 /* add imm32,dn */
1054 void OP_FCC00000 ()
1055 {
1056 int z, c, n, v;
1057 unsigned long reg1, imm, value;
1058
1059 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1060 imm = ((insn & 0xffff) << 16) | extension;
1061 value = reg1 + imm;
1062 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1063
1064 z = (value == 0);
1065 n = (value & 0x80000000);
1066 c = (reg1 < imm);
1067 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1068 && (imm & 0x8000000) != (value & 0x80000000));
1069
1070 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1071 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1072 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1073 }
1074
1075 /* add imm8, an */
1076 void OP_2000 ()
1077 {
1078 int z, c, n, v;
1079 unsigned long reg1, imm, value;
1080
1081 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1082 imm = SEXT8 (insn & 0xff);
1083 value = reg1 + imm;
1084 State.regs[REG_A0 + ((insn & 0x300) >> 8)] = value;
1085
1086 z = (value == 0);
1087 n = (value & 0x80000000);
1088 c = (reg1 < imm);
1089 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1090 && (imm & 0x8000000) != (value & 0x80000000));
1091
1092 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1093 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1094 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1095 }
1096
1097 /* add imm16, an */
1098 void OP_FAD00000 ()
1099 {
1100 int z, c, n, v;
1101 unsigned long reg1, imm, value;
1102
1103 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1104 imm = SEXT16 (insn & 0xffff);
1105 value = reg1 + imm;
1106 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1107
1108 z = (value == 0);
1109 n = (value & 0x80000000);
1110 c = (reg1 < imm);
1111 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1112 && (imm & 0x8000000) != (value & 0x80000000));
1113
1114 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1115 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1116 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1117 }
1118
1119 /* add imm32, an */
1120 void OP_FCD00000 ()
1121 {
1122 int z, c, n, v;
1123 unsigned long reg1, imm, value;
1124
1125 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1126 imm = ((insn & 0xffff) << 16) | extension;
1127 value = reg1 + imm;
1128 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1129
1130 z = (value == 0);
1131 n = (value & 0x80000000);
1132 c = (reg1 < imm);
1133 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1134 && (imm & 0x8000000) != (value & 0x80000000));
1135
1136 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1137 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1138 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1139 }
1140
1141 /* add imm8, sp */
1142 void OP_F8FE00 ()
1143 {
1144 int z, c, n, v;
1145 unsigned long reg1, imm, value;
1146
1147 reg1 = State.regs[REG_SP];
1148 imm = SEXT8 (insn & 0xff);
1149 value = reg1 + imm;
1150 State.regs[REG_SP] = value;
1151
1152 z = (value == 0);
1153 n = (value & 0x80000000);
1154 c = (reg1 < imm);
1155 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1156 && (imm & 0x8000000) != (value & 0x80000000));
1157
1158 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1159 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1160 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1161 }
1162
1163 /* add imm16,sp */
1164 void OP_FAFE0000 ()
1165 {
1166 int z, c, n, v;
1167 unsigned long reg1, imm, value;
1168
1169 reg1 = State.regs[REG_SP];
1170 imm = SEXT16 (insn & 0xffff);
1171 value = reg1 + imm;
1172 State.regs[REG_SP] = value;
1173
1174 z = (value == 0);
1175 n = (value & 0x80000000);
1176 c = (reg1 < imm);
1177 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1178 && (imm & 0x8000000) != (value & 0x80000000));
1179
1180 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1181 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1182 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1183 }
1184
1185 /* add imm32, sp */
1186 void OP_FCFE0000 ()
1187 {
1188 int z, c, n, v;
1189 unsigned long reg1, imm, value;
1190
1191 reg1 = State.regs[REG_SP];
1192 imm = ((insn & 0xffff) << 16) | extension;
1193 value = reg1 + imm;
1194 State.regs[REG_SP] = value;
1195
1196 z = (value == 0);
1197 n = (value & 0x80000000);
1198 c = (reg1 < imm);
1199 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1200 && (imm & 0x8000000) != (value & 0x80000000));
1201
1202 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1203 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1204 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1205 }
1206
1207 /* addc dm,dn */
1208 void OP_F140 ()
1209 {
1210 int z, c, n, v;
1211 unsigned long reg1, reg2, value;
1212
1213 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1214 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1215 value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1216 State.regs[REG_D0 + (insn & 0x3)] = value;
1217
1218 z = (value == 0);
1219 n = (value & 0x80000000);
1220 c = (reg1 < reg2);
1221 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1222 && (reg2 & 0x8000000) != (value & 0x80000000));
1223
1224 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1225 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1226 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1227 }
1228
1229 /* sub dm, dn */
1230 void OP_F100 ()
1231 {
1232 int z, c, n, v;
1233 unsigned long reg1, reg2, value;
1234
1235 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1236 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1237 value = reg2 - reg1;
1238
1239 z = (value == 0);
1240 n = (value & 0x80000000);
1241 c = (reg1 < reg2);
1242 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1243 && (reg2 & 0x8000000) != (value & 0x80000000));
1244
1245 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1246 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1247 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1248 State.regs[REG_D0 + (insn & 0x3)] = value;
1249 }
1250
1251 /* sub dm, an */
1252 void OP_F120 ()
1253 {
1254 int z, c, n, v;
1255 unsigned long reg1, reg2, value;
1256
1257 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1258 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1259 value = reg2 - reg1;
1260
1261 z = (value == 0);
1262 n = (value & 0x80000000);
1263 c = (reg1 < reg2);
1264 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1265 && (reg2 & 0x8000000) != (value & 0x80000000));
1266
1267 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1268 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1269 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1270 State.regs[REG_A0 + (insn & 0x3)] = value;
1271 }
1272
1273 /* sub am, dn */
1274 void OP_F110 ()
1275 {
1276 int z, c, n, v;
1277 unsigned long reg1, reg2, value;
1278
1279 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1280 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1281 value = reg2 - reg1;
1282
1283 z = (value == 0);
1284 n = (value & 0x80000000);
1285 c = (reg1 < reg2);
1286 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1287 && (reg2 & 0x8000000) != (value & 0x80000000));
1288
1289 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1290 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1291 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1292 State.regs[REG_D0 + (insn & 0x3)] = value;
1293 }
1294
1295 /* sub am, an */
1296 void OP_F130 ()
1297 {
1298 int z, c, n, v;
1299 unsigned long reg1, reg2, value;
1300
1301 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1302 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1303 value = reg2 - reg1;
1304
1305 z = (value == 0);
1306 n = (value & 0x80000000);
1307 c = (reg1 < reg2);
1308 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1309 && (reg2 & 0x8000000) != (value & 0x80000000));
1310
1311 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1312 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1313 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1314 State.regs[REG_A0 + (insn & 0x3)] = value;
1315 }
1316
1317 /* sub imm32, dn */
1318 void OP_FCC40000 ()
1319 {
1320 int z, c, n, v;
1321 unsigned long reg1, imm, value;
1322
1323 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1324 imm = ((insn & 0xffff) << 16) | extension;
1325 value = reg1 - imm;
1326
1327 z = (value == 0);
1328 n = (value & 0x80000000);
1329 c = (reg1 < imm);
1330 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1331 && (imm & 0x8000000) != (value & 0x80000000));
1332
1333 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1334 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1335 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1336 State.regs[REG_D0 + ((insn & 0x300) >> 16)] = value;
1337 }
1338
1339 /* sub imm32, an */
1340 void OP_FCD40000 ()
1341 {
1342 int z, c, n, v;
1343 unsigned long reg1, imm, value;
1344
1345 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1346 imm = ((insn & 0xffff) << 16) | extension;
1347 value = reg1 - imm;
1348
1349 z = (value == 0);
1350 n = (value & 0x80000000);
1351 c = (reg1 < imm);
1352 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1353 && (imm & 0x8000000) != (value & 0x80000000));
1354
1355 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1356 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1357 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1358 State.regs[REG_A0 + ((insn & 0x300) >> 16)] = value;
1359 }
1360
1361 /* subc dm, dn */
1362 void OP_F180 ()
1363 {
1364 int z, c, n, v;
1365 unsigned long reg1, reg2, value;
1366
1367 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1368 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1369 value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1370
1371 z = (value == 0);
1372 n = (value & 0x80000000);
1373 c = (reg1 < reg2);
1374 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1375 && (reg2 & 0x8000000) != (value & 0x80000000));
1376
1377 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1378 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1379 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1380 State.regs[REG_D0 + (insn & 0x3)] = value;
1381 }
1382
1383 /* mul dm, dn */
1384 void OP_F240 ()
1385 {
1386 unsigned long long temp;
1387 int n, z;
1388
1389 temp = (State.regs[REG_D0 + (insn & 0x3)]
1390 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1391 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1392 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1393 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1394 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1395 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1396 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1397 }
1398
1399 /* mulu dm, dn */
1400 void OP_F250 ()
1401 {
1402 unsigned long long temp;
1403 int n, z;
1404
1405 temp = (State.regs[REG_D0 + (insn & 0x3)]
1406 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1407 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1408 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1409 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1410 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1411 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1412 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1413 }
1414
1415 /* div dm, dn */
1416 void OP_F260 ()
1417 {
1418 long long temp;
1419 int n, z;
1420
1421 temp = State.regs[REG_MDR];
1422 temp <<= 32;
1423 temp |= State.regs[REG_D0 + (insn & 0x3)];
1424 State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1425 temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1426 temp = (State.regs[REG_D0 + (insn & 0x3)]
1427 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1428 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1429 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1430 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1431 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1432 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1433 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1434 }
1435
1436 /* divu dm, dn */
1437 void OP_F270 ()
1438 {
1439 unsigned long long temp;
1440 int n, z;
1441
1442 temp = State.regs[REG_MDR];
1443 temp <<= 32;
1444 temp |= State.regs[REG_D0 + (insn & 0x3)];
1445 State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1446 temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1447 temp = (State.regs[REG_D0 + (insn & 0x3)]
1448 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1449 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1450 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1451 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1452 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1453 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1454 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1455 }
1456
1457 /* inc dn */
1458 void OP_40 ()
1459 {
1460 State.regs[REG_D0 + ((insn & 0xc) >> 2)] += 1;
1461 }
1462
1463 /* inc an */
1464 void OP_41 ()
1465 {
1466 State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
1467 }
1468
1469 /* inc4 an */
1470 void OP_50 ()
1471 {
1472 State.regs[REG_A0 + (insn & 0x3)] += 4;
1473 }
1474
1475 /* cmp imm8, dn */
1476 void OP_A000 ()
1477 {
1478 int z, c, n, v;
1479 unsigned long reg1, imm, value;
1480
1481 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1482 imm = SEXT8 (insn & 0xff);
1483 value = reg1 - imm;
1484
1485 z = (value == 0);
1486 n = (value & 0x80000000);
1487 c = (reg1 < imm);
1488 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1489 && (imm & 0x8000000) != (value & 0x80000000));
1490
1491 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1492 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1493 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1494 }
1495
1496 /* cmp dm, dn */
1497 void OP_A0 ()
1498 {
1499 int z, c, n, v;
1500 unsigned long reg1, reg2, value;
1501
1502 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1503 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1504 value = reg2 - reg1;
1505
1506 z = (value == 0);
1507 n = (value & 0x80000000);
1508 c = (reg1 < reg2);
1509 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1510 && (reg2 & 0x8000000) != (value & 0x80000000));
1511
1512 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1513 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1514 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1515 }
1516
1517 /* cmp dm, an */
1518 void OP_F1A0 ()
1519 {
1520 int z, c, n, v;
1521 unsigned long reg1, reg2, value;
1522
1523 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1524 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1525 value = reg2 - reg1;
1526
1527 z = (value == 0);
1528 n = (value & 0x80000000);
1529 c = (reg1 < reg2);
1530 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1531 && (reg2 & 0x8000000) != (value & 0x80000000));
1532
1533 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1534 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1535 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1536 }
1537
1538 /* cmp am, dn */
1539 void OP_F190 ()
1540 {
1541 int z, c, n, v;
1542 unsigned long reg1, reg2, value;
1543
1544 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1545 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1546 value = reg2 - reg1;
1547
1548 z = (value == 0);
1549 n = (value & 0x80000000);
1550 c = (reg1 < reg2);
1551 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1552 && (reg2 & 0x8000000) != (value & 0x80000000));
1553
1554 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1555 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1556 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1557 }
1558
1559 /* cmp imm8, an */
1560 void OP_B000 ()
1561 {
1562 int z, c, n, v;
1563 unsigned long reg1, imm, value;
1564
1565 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1566 imm = insn & 0xff;
1567 value = reg1 - imm;
1568
1569 z = (value == 0);
1570 n = (value & 0x80000000);
1571 c = (reg1 < imm);
1572 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1573 && (imm & 0x8000000) != (value & 0x80000000));
1574
1575 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1576 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1577 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1578 }
1579
1580 /* cmp am, an */
1581 void OP_B0 ()
1582 {
1583 int z, c, n, v;
1584 unsigned long reg1, reg2, value;
1585
1586 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1587 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1588 value = reg2 - reg1;
1589
1590 z = (value == 0);
1591 n = (value & 0x80000000);
1592 c = (reg1 < reg2);
1593 v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1594 && (reg2 & 0x8000000) != (value & 0x80000000));
1595
1596 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1597 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1598 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1599 }
1600
1601 /* cmp imm16, dn */
1602 void OP_FAC80000 ()
1603 {
1604 int z, c, n, v;
1605 unsigned long reg1, imm, value;
1606
1607 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1608 imm = SEXT16 (insn & 0xffff);
1609 value = reg1 - imm;
1610
1611 z = (value == 0);
1612 n = (value & 0x80000000);
1613 c = (reg1 < imm);
1614 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1615 && (imm & 0x8000000) != (value & 0x80000000));
1616
1617 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1618 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1619 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1620 }
1621
1622 /* cmp imm32, dn */
1623 void OP_FCC80000 ()
1624 {
1625 int z, c, n, v;
1626 unsigned long reg1, imm, value;
1627
1628 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1629 imm = ((insn & 0xffff) << 16) | extension;
1630 value = reg1 - imm;
1631
1632 z = (value == 0);
1633 n = (value & 0x80000000);
1634 c = (reg1 < imm);
1635 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1636 && (imm & 0x8000000) != (value & 0x80000000));
1637
1638 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1639 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1640 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1641 }
1642
1643 /* cmp imm16, an */
1644 void OP_FAD80000 ()
1645 {
1646 int z, c, n, v;
1647 unsigned long reg1, imm, value;
1648
1649 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1650 imm = insn & 0xffff;
1651 value = reg1 - imm;
1652
1653 z = (value == 0);
1654 n = (value & 0x80000000);
1655 c = (reg1 < imm);
1656 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1657 && (imm & 0x8000000) != (value & 0x80000000));
1658
1659 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1660 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1661 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1662 }
1663
1664 /* cmp imm32, an */
1665 void OP_FCD80000 ()
1666 {
1667 int z, c, n, v;
1668 unsigned long reg1, imm, value;
1669
1670 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1671 imm = ((insn & 0xffff) << 16) | extension;
1672 value = reg1 - imm;
1673
1674 z = (value == 0);
1675 n = (value & 0x80000000);
1676 c = (reg1 < imm);
1677 v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1678 && (imm & 0x8000000) != (value & 0x80000000));
1679
1680 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1681 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1682 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1683 }
1684
1685 /* and dm, dn */
1686 void OP_F200 ()
1687 {
1688 int n, z;
1689
1690 State.regs[REG_D0 + (insn & 0x3)] &= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1691 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1692 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1693 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1694 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1695 }
1696
1697 /* and imm8, dn */
1698 void OP_F8E000 ()
1699 {
1700 int n, z;
1701
1702 State.regs[REG_D0 + ((insn & 0x300) >> 8)] &= (insn & 0xff);
1703 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1704 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
1705 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1706 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1707 }
1708
1709 /* and imm16, dn */
1710 void OP_FAE00000 ()
1711 {
1712 int n, z;
1713
1714 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] &= (insn & 0xffff);
1715 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1716 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x8000000) != 0;
1717 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1718 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1719 }
1720
1721 /* and imm32, dn */
1722 void OP_FCE00000 ()
1723 {
1724 int n, z;
1725
1726 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1727 &= ((insn & 0xffff) << 16 | extension);
1728 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1729 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x8000000) != 0;
1730 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1731 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1732 }
1733
1734 /* and imm16, psw */
1735 void OP_FAFC0000 ()
1736 {
1737 PSW &= (insn & 0xffff);
1738 }
1739
1740 /* or dm, dn*/
1741 void OP_F210 ()
1742 {
1743 int n, z;
1744
1745 State.regs[REG_D0 + (insn & 0x3)] |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1746 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1747 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1748 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1749 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1750 }
1751
1752 /* or imm8, dn */
1753 void OP_F8E400 ()
1754 {
1755 int n, z;
1756
1757 State.regs[REG_D0 + ((insn & 0x300) >> 8)] |= insn & 0xff;
1758 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1759 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
1760 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1761 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1762 }
1763
1764 /* or imm16, dn*/
1765 void OP_FAE40000 ()
1766 {
1767 int n, z;
1768
1769 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] |= insn & 0xffff;
1770 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1771 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x8000000) != 0;
1772 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1773 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1774 }
1775
1776 /* or imm32, dn */
1777 void OP_FCE40000 ()
1778 {
1779 int n, z;
1780
1781 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1782 |= ((insn & 0xffff) << 16 | extension);
1783 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1784 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x8000000) != 0;
1785 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1786 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1787 }
1788
1789 /* or imm16,psw */
1790 void OP_FAFD0000 ()
1791 {
1792 PSW |= (insn & 0xffff);
1793 }
1794
1795 /* xor dm, dn*/
1796 void OP_F220 ()
1797 {
1798 int n, z;
1799
1800 State.regs[REG_D0 + (insn & 0x3)] ^= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1801 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1802 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1803 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1804 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1805 }
1806
1807 /* xor imm16, dn */
1808 void OP_FAE80000 ()
1809 {
1810 int n, z;
1811
1812 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] ^= insn & 0xffff;
1813 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1814 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x8000000) != 0;
1815 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1816 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1817 }
1818
1819 /* xor imm32, dn */
1820 void OP_FCE80000 ()
1821 {
1822 int n, z;
1823
1824 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1825 ^= ((insn & 0xffff) << 16 | extension);
1826 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1827 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x8000000) != 0;
1828 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1829 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1830 }
1831
1832 /* not dn */
1833 void OP_F230 ()
1834 {
1835 int n, z;
1836
1837 State.regs[REG_D0 + (insn & 0x3)] = ~State.regs[REG_D0 + (insn & 0x3)];
1838 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1839 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1840 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1841 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1842 }
1843
1844 /* btst imm8, dn */
1845 void OP_F8EC00 ()
1846 {
1847 unsigned long temp;
1848 int z, n;
1849
1850 temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1851 temp &= (insn & 0xff);
1852 n = (temp & 0x80000000) != 0;
1853 z = (temp == 0);
1854 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1855 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1856 }
1857
1858 /* btst imm16, dn */
1859 void OP_FAEC0000 ()
1860 {
1861 unsigned long temp;
1862 int z, n;
1863
1864 temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1865 temp &= (insn & 0xffff);
1866 n = (temp & 0x80000000) != 0;
1867 z = (temp == 0);
1868 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1869 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1870 }
1871
1872 /* btst imm32, dn */
1873 void OP_FCEC0000 ()
1874 {
1875 unsigned long temp;
1876 int z, n;
1877
1878 temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1879 temp &= ((insn & 0xffff) << 16 | extension);
1880 n = (temp & 0x80000000) != 0;
1881 z = (temp == 0);
1882 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1883 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1884 }
1885
1886 /* btst imm8,(abs32) */
1887 void OP_FE020000 ()
1888 {
1889 unsigned long temp;
1890 int n, z;
1891
1892 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
1893 temp &= (extension & 0xff);
1894 n = (temp & 0x80000000) != 0;
1895 z = (temp == 0);
1896 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1897 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1898 }
1899
1900 /* btst imm8,(d8,an) */
1901 void OP_FAF80000 ()
1902 {
1903 unsigned long temp;
1904 int n, z;
1905
1906 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1907 + SEXT8 ((insn & 0xff00) >> 8)), 1);
1908 temp &= (insn & 0xff);
1909 n = (temp & 0x80000000) != 0;
1910 z = (temp == 0);
1911 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1912 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1913 }
1914
1915 /* bset dm, (an) */
1916 void OP_F080 ()
1917 {
1918 unsigned long temp;
1919 int z;
1920
1921 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1922 z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1923 temp |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1924 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1925 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1926 PSW |= (z ? PSW_Z : 0);
1927 }
1928
1929 /* bset imm8, (abs32) */
1930 void OP_FE000000 ()
1931 {
1932 unsigned long temp;
1933 int z;
1934
1935 temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
1936 z = (temp & (extension & 0xff)) == 0;
1937 temp |= (extension & 0xff);
1938 store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
1939 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1940 PSW |= (z ? PSW_Z : 0);
1941 }
1942
1943 /* bset imm8,(d8,an) */
1944 void OP_FAF00000 ()
1945 {
1946 unsigned long temp;
1947 int z;
1948
1949 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1950 + SEXT8 ((insn & 0xff00) >> 8)), 1);
1951 z = (temp & (insn & 0xff)) == 0;
1952 temp |= (insn & 0xff);
1953 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
1954 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1955 PSW |= (z ? PSW_Z : 0);
1956 }
1957
1958 /* bclr dm, (an) */
1959 void OP_F090 ()
1960 {
1961 unsigned long temp;
1962 int z;
1963
1964 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1965 z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1966 temp = ~temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1967 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1968 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1969 PSW |= (z ? PSW_Z : 0);
1970 }
1971
1972 /* bclr imm8, (abs32) */
1973 void OP_FE010000 ()
1974 {
1975 unsigned long temp;
1976 int z;
1977
1978 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
1979 z = (temp & (extension & 0xff)) == 0;
1980 temp = ~temp & (extension & 0xff);
1981 store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
1982 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1983 PSW |= (z ? PSW_Z : 0);
1984 }
1985
1986 /* bclr imm8,(d8,an) */
1987 void OP_FAF40000 ()
1988 {
1989 unsigned long temp;
1990 int z;
1991
1992 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1993 + SEXT8 ((insn & 0xff00) >> 8)), 1);
1994 z = (temp & (insn & 0xff)) == 0;
1995 temp = ~temp & (insn & 0xff);
1996 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
1997 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1998 PSW |= (z ? PSW_Z : 0);
1999 }
2000
2001 /* asr dm, dn */
2002 void OP_F2B0 ()
2003 {
2004 long temp;
2005 int z, n, c;
2006
2007 temp = State.regs[REG_D0 + (insn & 0x3)];
2008 c = temp & 1;
2009 temp >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2010 State.regs[REG_D0 + (insn & 0x3)] = temp;
2011 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2012 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
2013 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2014 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2015 }
2016
2017 /* asr imm8, dn */
2018 void OP_F8C800 ()
2019 {
2020 long temp;
2021 int z, n, c;
2022
2023 temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
2024 c = temp & 1;
2025 temp >>= (insn & 0xff);
2026 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = temp;
2027 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
2028 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
2029 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2030 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2031 }
2032
2033 /* lsr dm, dn */
2034 void OP_F2A0 ()
2035 {
2036 int z, n, c;
2037
2038 c = State.regs[REG_D0 + (insn & 0x3)] & 1;
2039 State.regs[REG_D0 + (insn & 0x3)]
2040 >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2041 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2042 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
2043 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2044 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2045 }
2046
2047 /* lsr dm, dn */
2048 void OP_F8C400 ()
2049 {
2050 int z, n, c;
2051
2052 c = State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 1;
2053 State.regs[REG_D0 + ((insn & 0x300) >> 8)] >>= (insn & 0xff);
2054 z = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] == 0);
2055 n = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] & 0x8000000) != 0;
2056 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2057 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2058 }
2059
2060 /* asl dm, dn */
2061 void OP_F290 ()
2062 {
2063 int n, z;
2064
2065 State.regs[REG_D0 + (insn & 0x3)]
2066 <<= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2067 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2068 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
2069 PSW &= ~(PSW_Z | PSW_N);
2070 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2071 }
2072
2073 /* asl imm8, dn */
2074 void OP_F8C000 ()
2075 {
2076 int n, z;
2077
2078 State.regs[REG_D0 + ((insn & 0x300) >> 8)] <<= (insn & 0xff);
2079 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
2080 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
2081 PSW &= ~(PSW_Z | PSW_N);
2082 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2083 }
2084
2085 /* asl2 dn */
2086 void OP_54 ()
2087 {
2088 int n, z;
2089
2090 State.regs[REG_D0 + (insn & 0x3)] <<= 2;
2091 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2092 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
2093 PSW &= ~(PSW_Z | PSW_N);
2094 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2095 }
2096
2097 /* ror dn */
2098 void OP_F284 ()
2099 {
2100 unsigned long value;
2101 int c,n,z;
2102
2103 value = State.regs[REG_D0 + (insn & 0x3)];
2104 if (value & 0x1)
2105 c = 1;
2106
2107 value >>= 1;
2108 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2109 State.regs[REG_D0 + (insn & 0x3)] = value;
2110 z = (value == 0);
2111 n = (value & 0x8000000) != 0;
2112 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2113 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2114 }
2115
2116 /* rol dn */
2117 void OP_F280 ()
2118 {
2119 unsigned long value;
2120 int c,n,z;
2121
2122 value = State.regs[REG_D0 + (insn & 0x3)];
2123 if (value & 0x80000000)
2124 c = 1;
2125
2126 value <<= 1;
2127 value |= ((PSW & PSW_C) != 0);
2128 State.regs[REG_D0 + (insn & 0x3)] = value;
2129 z = (value == 0);
2130 n = (value & 0x8000000) != 0;
2131 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2132 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2133 }
2134
2135 /* beq label:8 */
2136 void OP_C800 ()
2137 {
2138 /* The dispatching code will add 2 after we return, so
2139 we subtract two here to make things right. */
2140 if (PSW & PSW_Z)
2141 State.pc += SEXT8 (insn & 0xff) - 2;
2142 }
2143
2144 /* bne label:8 */
2145 void OP_C900 ()
2146 {
2147 /* The dispatching code will add 2 after we return, so
2148 we subtract two here to make things right. */
2149 if (!(PSW & PSW_Z))
2150 State.pc += SEXT8 (insn & 0xff) - 2;
2151 }
2152
2153 /* bgt label:8 */
2154 void OP_C100 ()
2155 {
2156 /* The dispatching code will add 2 after we return, so
2157 we subtract two here to make things right. */
2158 if (!((PSW & PSW_Z)
2159 || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)))
2160 State.pc += SEXT8 (insn & 0xff) - 2;
2161 }
2162
2163 /* bge label:8 */
2164 void OP_C200 ()
2165 {
2166 /* The dispatching code will add 2 after we return, so
2167 we subtract two here to make things right. */
2168 if (!(((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
2169 State.pc += SEXT8 (insn & 0xff) - 2;
2170 }
2171
2172 /* ble label:8 */
2173 void OP_C300 ()
2174 {
2175 /* The dispatching code will add 2 after we return, so
2176 we subtract two here to make things right. */
2177 if ((PSW & PSW_Z)
2178 || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
2179 State.pc += SEXT8 (insn & 0xff) - 2;
2180 }
2181
2182 /* blt label:8 */
2183 void OP_C000 ()
2184 {
2185 /* The dispatching code will add 2 after we return, so
2186 we subtract two here to make things right. */
2187 if (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)
2188 State.pc += SEXT8 (insn & 0xff) - 2;
2189 }
2190
2191 /* bhi label:8 */
2192 void OP_C500 ()
2193 {
2194 /* The dispatching code will add 2 after we return, so
2195 we subtract two here to make things right. */
2196 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2197 State.pc += SEXT8 (insn & 0xff) - 2;
2198 }
2199
2200 /* bcc label:8 */
2201 void OP_C600 ()
2202 {
2203 /* The dispatching code will add 2 after we return, so
2204 we subtract two here to make things right. */
2205 if (!(PSW & PSW_C))
2206 State.pc += SEXT8 (insn & 0xff) - 2;
2207 }
2208
2209 /* bls label:8 */
2210 void OP_C700 ()
2211 {
2212 /* The dispatching code will add 2 after we return, so
2213 we subtract two here to make things right. */
2214 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2215 State.pc += SEXT8 (insn & 0xff) - 2;
2216 }
2217
2218 /* bcs label:8 */
2219 void OP_C400 ()
2220 {
2221 /* The dispatching code will add 2 after we return, so
2222 we subtract two here to make things right. */
2223 if (PSW & PSW_C)
2224 State.pc += SEXT8 (insn & 0xff) - 2;
2225 }
2226
2227 /* bvc label:8 */
2228 void OP_F8E800 ()
2229 {
2230 /* The dispatching code will add 3 after we return, so
2231 we subtract two here to make things right. */
2232 if (!(PSW & PSW_V))
2233 State.pc += SEXT8 (insn & 0xff) - 3;
2234 }
2235
2236 /* bvs label:8 */
2237 void OP_F8E900 ()
2238 {
2239 /* The dispatching code will add 3 after we return, so
2240 we subtract two here to make things right. */
2241 if (PSW & PSW_V)
2242 State.pc += SEXT8 (insn & 0xff) - 3;
2243 }
2244
2245 /* bnc label:8 */
2246 void OP_F8EA00 ()
2247 {
2248 /* The dispatching code will add 3 after we return, so
2249 we subtract two here to make things right. */
2250 if (!(PSW & PSW_N))
2251 State.pc += SEXT8 (insn & 0xff) - 3;
2252 }
2253
2254 /* bns label:8 */
2255 void OP_F8EB00 ()
2256 {
2257 /* The dispatching code will add 3 after we return, so
2258 we subtract two here to make things right. */
2259 if (PSW & PSW_N)
2260 State.pc += SEXT8 (insn & 0xff) - 3;
2261 }
2262
2263 /* bra label:8 */
2264 void OP_CA00 ()
2265 {
2266 /* The dispatching code will add 2 after we return, so
2267 we subtract two here to make things right. */
2268 State.pc += SEXT8 (insn & 0xff) - 2;
2269 }
2270
2271 /* leq */
2272 void OP_D8 ()
2273 {
2274 abort ();
2275 }
2276
2277 /* lne */
2278 void OP_D9 ()
2279 {
2280 abort ();
2281 }
2282
2283 /* lgt */
2284 void OP_D1 ()
2285 {
2286 abort ();
2287 }
2288
2289 /* lge */
2290 void OP_D2 ()
2291 {
2292 abort ();
2293 }
2294
2295 /* lle */
2296 void OP_D3 ()
2297 {
2298 abort ();
2299 }
2300
2301 /* llt */
2302 void OP_D0 ()
2303 {
2304 abort ();
2305 }
2306
2307 /* lhi */
2308 void OP_D5 ()
2309 {
2310 abort ();
2311 }
2312
2313 /* lcc */
2314 void OP_D6 ()
2315 {
2316 abort ();
2317 }
2318
2319 /* lls */
2320 void OP_D7 ()
2321 {
2322 abort ();
2323 }
2324
2325 /* lcs */
2326 void OP_D4 ()
2327 {
2328 abort ();
2329 }
2330
2331 /* lra */
2332 void OP_DA ()
2333 {
2334 abort ();
2335 }
2336
2337 /* setlb */
2338 void OP_DB ()
2339 {
2340 abort ();
2341 }
2342
2343 /* jmp (an) */
2344 void OP_F0F4 ()
2345 {
2346 State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2347 }
2348
2349 /* jmp label:16 */
2350 void OP_CC0000 ()
2351 {
2352 State.pc += SEXT16 (insn & 0xffff) - 3;
2353 }
2354
2355 /* jmp label:32 */
2356 void OP_DC000000 ()
2357 {
2358 State.pc += (((insn & 0xffffff) << 8) | extension) - 5;
2359 }
2360
2361 /* call label:16,reg_list,imm8 */
2362 void OP_CD000000 ()
2363 {
2364 unsigned int next_pc, sp, adjust;
2365 unsigned long mask;
2366
2367 sp = State.regs[REG_SP];
2368 next_pc = State.pc + 2;
2369 State.mem[sp] = next_pc & 0xff;
2370 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2371 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2372 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2373
2374 mask = insn & 0xff;
2375
2376 adjust = 0;
2377 if (mask & 0x80)
2378 {
2379 adjust -= 4;
2380 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2381 }
2382
2383 if (mask & 0x40)
2384 {
2385 adjust -= 4;
2386 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2387 }
2388
2389 if (mask & 0x20)
2390 {
2391 adjust -= 4;
2392 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2393 }
2394
2395 if (mask & 0x10)
2396 {
2397 adjust -= 4;
2398 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2399 }
2400
2401 if (mask & 0x8)
2402 {
2403 adjust -= 4;
2404 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2405 adjust -= 4;
2406 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2407 adjust -= 4;
2408 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2409 adjust -= 4;
2410 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2411 adjust -= 4;
2412 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2413 adjust -= 4;
2414 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2415 adjust -= 4;
2416 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2417 adjust -= 4;
2418 }
2419
2420 /* And make sure to update the stack pointer. */
2421 State.regs[REG_SP] -= extension;
2422 State.regs[REG_MDR] = next_pc;
2423 State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2424 }
2425
2426 /* call label:32,reg_list,imm8*/
2427 void OP_DD000000 ()
2428 {
2429 unsigned int next_pc, sp, adjust;
2430 unsigned long mask;
2431
2432 sp = State.regs[REG_SP];
2433 next_pc = State.pc + 2;
2434 State.mem[sp] = next_pc & 0xff;
2435 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2436 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2437 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2438
2439 mask = (extension & 0xff00) >> 8;
2440
2441 adjust = 0;
2442 if (mask & 0x80)
2443 {
2444 adjust -= 4;
2445 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2446 }
2447
2448 if (mask & 0x40)
2449 {
2450 adjust -= 4;
2451 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2452 }
2453
2454 if (mask & 0x20)
2455 {
2456 adjust -= 4;
2457 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2458 }
2459
2460 if (mask & 0x10)
2461 {
2462 adjust -= 4;
2463 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2464 }
2465
2466 if (mask & 0x8)
2467 {
2468 adjust -= 4;
2469 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2470 adjust -= 4;
2471 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2472 adjust -= 4;
2473 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2474 adjust -= 4;
2475 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2476 adjust -= 4;
2477 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2478 adjust -= 4;
2479 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2480 adjust -= 4;
2481 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2482 adjust -= 4;
2483 }
2484
2485 /* And make sure to update the stack pointer. */
2486 State.regs[REG_SP] -= (extension & 0xff);
2487 State.regs[REG_MDR] = next_pc;
2488 State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2489 }
2490
2491 /* calls (an) */
2492 void OP_F0F0 ()
2493 {
2494 unsigned int next_pc, sp;
2495
2496 sp = State.regs[REG_SP];
2497 next_pc = State.pc + 2;
2498 State.mem[sp] = next_pc & 0xff;
2499 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2500 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2501 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2502 State.regs[REG_MDR] = next_pc;
2503 State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2504 }
2505
2506 /* calls label:16 */
2507 void OP_FAFF0000 ()
2508 {
2509 unsigned int next_pc, sp;
2510
2511 sp = State.regs[REG_SP];
2512 next_pc = State.pc + 4;
2513 State.mem[sp] = next_pc & 0xff;
2514 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2515 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2516 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2517 State.regs[REG_MDR] = next_pc;
2518 State.pc += SEXT16 (insn & 0xffff) - 4;
2519 }
2520
2521 /* calls label:32 */
2522 void OP_FCFF0000 ()
2523 {
2524 unsigned int next_pc, sp;
2525
2526 sp = State.regs[REG_SP];
2527 next_pc = State.pc + 6;
2528 State.mem[sp] = next_pc & 0xff;
2529 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2530 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2531 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2532 State.regs[REG_MDR] = next_pc;
2533 State.pc += (((insn & 0xffff) << 16) | extension) - 6;
2534 }
2535
2536 /* ret reg_list, imm8 */
2537 void OP_DF0000 ()
2538 {
2539 unsigned int sp;
2540 unsigned long mask;
2541
2542 State.regs[REG_SP] += insn & 0xff;
2543 State.pc = State.regs[REG_MDR] - 3;
2544 sp = State.regs[REG_SP];
2545
2546 mask = (insn & 0xff00) >> 8;
2547
2548 if (mask & 0x8)
2549 {
2550 sp += 4;
2551 State.regs[REG_LAR] = load_mem (sp, 4);
2552 sp += 4;
2553 State.regs[REG_LIR] = load_mem (sp, 4);
2554 sp += 4;
2555 State.regs[REG_MDR] = load_mem (sp, 4);
2556 sp += 4;
2557 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2558 sp += 4;
2559 State.regs[REG_A0] = load_mem (sp, 4);
2560 sp += 4;
2561 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2562 sp += 4;
2563 State.regs[REG_D0] = load_mem (sp, 4);
2564 sp += 4;
2565 }
2566
2567 if (mask & 0x10)
2568 {
2569 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2570 sp += 4;
2571 }
2572
2573 if (mask & 0x20)
2574 {
2575 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2576 sp += 4;
2577 }
2578
2579 if (mask & 0x40)
2580 {
2581 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2582 sp += 4;
2583 }
2584
2585 if (mask & 0x80)
2586 {
2587 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2588 sp += 4;
2589 }
2590 }
2591
2592 /* retf reg_list,imm8 */
2593 void OP_DE0000 ()
2594 {
2595 unsigned int sp;
2596 unsigned long mask;
2597
2598 State.regs[REG_SP] += insn & 0xff;
2599 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2600 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2601 State.pc -= 3;
2602
2603 sp = State.regs[REG_SP];
2604
2605 mask = (insn & 0xff00) >> 8;
2606
2607 if (mask & 0x8)
2608 {
2609 sp += 4;
2610 State.regs[REG_LAR] = load_mem (sp, 4);
2611 sp += 4;
2612 State.regs[REG_LIR] = load_mem (sp, 4);
2613 sp += 4;
2614 State.regs[REG_MDR] = load_mem (sp, 4);
2615 sp += 4;
2616 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2617 sp += 4;
2618 State.regs[REG_A0] = load_mem (sp, 4);
2619 sp += 4;
2620 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2621 sp += 4;
2622 State.regs[REG_D0] = load_mem (sp, 4);
2623 sp += 4;
2624 }
2625
2626 if (mask & 0x10)
2627 {
2628 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2629 sp += 4;
2630 }
2631
2632 if (mask & 0x20)
2633 {
2634 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2635 sp += 4;
2636 }
2637
2638 if (mask & 0x40)
2639 {
2640 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2641 sp += 4;
2642 }
2643
2644 if (mask & 0x80)
2645 {
2646 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2647 sp += 4;
2648 }
2649 }
2650
2651 /* rets */
2652 void OP_F0FC ()
2653 {
2654 unsigned int sp;
2655
2656 sp = State.regs[REG_SP];
2657 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2658 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2659 State.pc -= 2;
2660 }
2661
2662 /* rti */
2663 void OP_F0FD ()
2664 {
2665 abort ();
2666 }
2667
2668 /* trap */
2669 void OP_F0FE ()
2670 {
2671 /* We use this for simulated system calls; we may need to change
2672 it to a reserved instruction if we conflict with uses at
2673 Matsushita. */
2674 int save_errno = errno;
2675 errno = 0;
2676
2677 /* Registers passed to trap 0 */
2678
2679 /* Function number. */
2680 #define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
2681
2682 /* Parameters. */
2683 #define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
2684 #define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2685 #define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2686
2687 /* Registers set by trap 0 */
2688
2689 #define RETVAL State.regs[0] /* return value */
2690 #define RETERR State.regs[1] /* return error code */
2691
2692 /* Turn a pointer in a register into a pointer into real memory. */
2693
2694 #define MEMPTR(x) (State.mem + x)
2695
2696 switch (FUNC)
2697 {
2698 #if !defined(__GO32__) && !defined(_WIN32)
2699 case SYS_fork:
2700 RETVAL = fork ();
2701 break;
2702 case SYS_execve:
2703 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2704 (char **)MEMPTR (PARM3));
2705 break;
2706 case SYS_execv:
2707 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2708 break;
2709 #endif
2710
2711 case SYS_read:
2712 RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
2713 MEMPTR (PARM2), PARM3);
2714 break;
2715 case SYS_write:
2716 if (PARM1 == 1)
2717 RETVAL = (int)mn10300_callback->write_stdout (mn10300_callback,
2718 MEMPTR (PARM2), PARM3);
2719 else
2720 RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
2721 MEMPTR (PARM2), PARM3);
2722 break;
2723 case SYS_lseek:
2724 RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
2725 break;
2726 case SYS_close:
2727 RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
2728 break;
2729 case SYS_open:
2730 RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
2731 break;
2732 case SYS_exit:
2733 /* EXIT - caller can look in PARM1 to work out the
2734 reason */
2735 if (PARM1 == 0xdead || PARM1 == 0x1)
2736 State.exception = SIGABRT;
2737 else
2738 State.exception = SIGQUIT;
2739 break;
2740
2741 case SYS_stat: /* added at hmsi */
2742 /* stat system call */
2743 {
2744 struct stat host_stat;
2745 reg_t buf;
2746
2747 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2748
2749 buf = PARM2;
2750
2751 /* Just wild-assed guesses. */
2752 store_mem (buf, 2, host_stat.st_dev);
2753 store_mem (buf + 2, 2, host_stat.st_ino);
2754 store_mem (buf + 4, 4, host_stat.st_mode);
2755 store_mem (buf + 8, 2, host_stat.st_nlink);
2756 store_mem (buf + 10, 2, host_stat.st_uid);
2757 store_mem (buf + 12, 2, host_stat.st_gid);
2758 store_mem (buf + 14, 2, host_stat.st_rdev);
2759 store_mem (buf + 16, 4, host_stat.st_size);
2760 store_mem (buf + 20, 4, host_stat.st_atime);
2761 store_mem (buf + 28, 4, host_stat.st_mtime);
2762 store_mem (buf + 36, 4, host_stat.st_ctime);
2763 }
2764 break;
2765
2766 case SYS_chown:
2767 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2768 break;
2769 case SYS_chmod:
2770 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2771 break;
2772 case SYS_time:
2773 RETVAL = time (MEMPTR (PARM1));
2774 break;
2775 case SYS_times:
2776 {
2777 struct tms tms;
2778 RETVAL = times (&tms);
2779 store_mem (PARM1, 4, tms.tms_utime);
2780 store_mem (PARM1 + 4, 4, tms.tms_stime);
2781 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2782 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2783 break;
2784 }
2785 case SYS_gettimeofday:
2786 {
2787 struct timeval t;
2788 struct timezone tz;
2789 RETVAL = gettimeofday (&t, &tz);
2790 store_mem (PARM1, 4, t.tv_sec);
2791 store_mem (PARM1 + 4, 4, t.tv_usec);
2792 store_mem (PARM2, 4, tz.tz_minuteswest);
2793 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2794 break;
2795 }
2796 case SYS_utime:
2797 /* Cast the second argument to void *, to avoid type mismatch
2798 if a prototype is present. */
2799 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2800 break;
2801 default:
2802 abort ();
2803 }
2804 RETERR = errno;
2805 errno = save_errno;
2806 }
2807
2808 /* rtm */
2809 void OP_F0FF ()
2810 {
2811 abort ();
2812 }
2813
2814 /* nop */
2815 void OP_CB ()
2816 {
2817 }
2818
2819 /* putx */
2820 void OP_F500 ()
2821 {
2822 }
2823
2824 /* getx */
2825 void OP_F6F0 ()
2826 {
2827 }
2828
2829 /* mulq */
2830 void OP_F600 ()
2831 {
2832 }
2833
2834 /* mulq */
2835 void OP_F90000 ()
2836 {
2837 }
2838
2839 /* mulq */
2840 void OP_FB000000 ()
2841 {
2842 }
2843
2844 /* mulq */
2845 void OP_FD000000 ()
2846 {
2847 }
2848
2849 /* mulqu */
2850 void OP_F610 ()
2851 {
2852 }
2853
2854 /* mulqu */
2855 void OP_F91400 ()
2856 {
2857 }
2858
2859 /* mulqu */
2860 void OP_FB140000 ()
2861 {
2862 }
2863
2864 /* mulqu */
2865 void OP_FD140000 ()
2866 {
2867 }
2868
2869 /* sat16 */
2870 void OP_F640 ()
2871 {
2872 }
2873
2874 /* sat24 */
2875 void OP_F650 ()
2876 {
2877 }
2878
2879 /* bsch */
2880 void OP_F670 ()
2881 {
2882 }
GDB Binutils - Deliverables
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